./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4a390ef5 Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4a390ef-m [2024-10-25 00:40:25,427 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-25 00:40:25,487 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-25 00:40:25,492 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-25 00:40:25,493 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-25 00:40:25,513 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-25 00:40:25,515 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-25 00:40:25,515 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-25 00:40:25,516 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-25 00:40:25,516 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-25 00:40:25,517 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-25 00:40:25,517 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-25 00:40:25,517 INFO L153 SettingsManager]: * Use SBE=true [2024-10-25 00:40:25,518 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-25 00:40:25,519 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-25 00:40:25,519 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-25 00:40:25,520 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-25 00:40:25,520 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-25 00:40:25,520 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-25 00:40:25,520 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-25 00:40:25,520 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-25 00:40:25,521 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-25 00:40:25,523 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-25 00:40:25,523 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-25 00:40:25,524 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-25 00:40:25,524 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-25 00:40:25,524 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-25 00:40:25,524 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-25 00:40:25,524 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-25 00:40:25,524 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-25 00:40:25,524 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-25 00:40:25,524 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-25 00:40:25,524 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-25 00:40:25,525 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-25 00:40:25,525 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-25 00:40:25,525 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-25 00:40:25,525 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-25 00:40:25,525 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-25 00:40:25,525 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-25 00:40:25,526 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 [2024-10-25 00:40:25,722 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-25 00:40:25,742 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-25 00:40:25,745 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-25 00:40:25,746 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-25 00:40:25,746 INFO L274 PluginConnector]: CDTParser initialized [2024-10-25 00:40:25,747 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c [2024-10-25 00:40:26,943 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-25 00:40:27,125 INFO L384 CDTParser]: Found 1 translation units. [2024-10-25 00:40:27,126 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c [2024-10-25 00:40:27,143 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f83e4cd70/c66f6fd4c99646dea40e6a44793d87fc/FLAG5904b04bf [2024-10-25 00:40:27,506 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f83e4cd70/c66f6fd4c99646dea40e6a44793d87fc [2024-10-25 00:40:27,508 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-25 00:40:27,510 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-25 00:40:27,511 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-25 00:40:27,511 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-25 00:40:27,515 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-25 00:40:27,515 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:27,516 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7898d34d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27, skipping insertion in model container [2024-10-25 00:40:27,516 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:27,552 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-25 00:40:27,795 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-25 00:40:27,810 INFO L200 MainTranslator]: Completed pre-run [2024-10-25 00:40:27,859 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-25 00:40:27,883 INFO L204 MainTranslator]: Completed translation [2024-10-25 00:40:27,883 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27 WrapperNode [2024-10-25 00:40:27,883 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-25 00:40:27,884 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-25 00:40:27,884 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-25 00:40:27,884 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-25 00:40:27,889 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:27,898 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:27,973 INFO L138 Inliner]: procedures = 54, calls = 70, calls flagged for inlining = 65, calls inlined = 287, statements flattened = 4441 [2024-10-25 00:40:27,973 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-25 00:40:27,974 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-25 00:40:27,974 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-25 00:40:27,974 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-25 00:40:27,982 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:27,983 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:28,022 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:28,087 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-25 00:40:28,091 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:28,091 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:28,116 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:28,142 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:28,150 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:28,162 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:28,173 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-25 00:40:28,174 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-25 00:40:28,175 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-25 00:40:28,175 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-25 00:40:28,176 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (1/1) ... [2024-10-25 00:40:28,180 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-25 00:40:28,188 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-25 00:40:28,203 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-25 00:40:28,206 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-25 00:40:28,244 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-25 00:40:28,245 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-25 00:40:28,245 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-25 00:40:28,245 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-25 00:40:28,333 INFO L238 CfgBuilder]: Building ICFG [2024-10-25 00:40:28,335 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-25 00:40:30,443 INFO L? ?]: Removed 948 outVars from TransFormulas that were not future-live. [2024-10-25 00:40:30,443 INFO L287 CfgBuilder]: Performing block encoding [2024-10-25 00:40:30,490 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-25 00:40:30,491 INFO L314 CfgBuilder]: Removed 17 assume(true) statements. [2024-10-25 00:40:30,491 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.10 12:40:30 BoogieIcfgContainer [2024-10-25 00:40:30,491 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-25 00:40:30,492 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-25 00:40:30,492 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-25 00:40:30,495 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-25 00:40:30,496 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-25 00:40:30,496 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 25.10 12:40:27" (1/3) ... [2024-10-25 00:40:30,497 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@519d30c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.10 12:40:30, skipping insertion in model container [2024-10-25 00:40:30,497 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-25 00:40:30,497 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:27" (2/3) ... [2024-10-25 00:40:30,497 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@519d30c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.10 12:40:30, skipping insertion in model container [2024-10-25 00:40:30,497 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-25 00:40:30,497 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.10 12:40:30" (3/3) ... [2024-10-25 00:40:30,498 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.13.cil.c [2024-10-25 00:40:30,567 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-25 00:40:30,567 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-25 00:40:30,567 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-25 00:40:30,567 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-25 00:40:30,567 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-25 00:40:30,567 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-25 00:40:30,568 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-25 00:40:30,568 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-25 00:40:30,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1936 states, 1935 states have (on average 1.4945736434108527) internal successors, (2892), 1935 states have internal predecessors, (2892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:30,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1759 [2024-10-25 00:40:30,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:30,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:30,657 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:30,658 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:30,658 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-25 00:40:30,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1936 states, 1935 states have (on average 1.4945736434108527) internal successors, (2892), 1935 states have internal predecessors, (2892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:30,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1759 [2024-10-25 00:40:30,675 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:30,675 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:30,679 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:30,681 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:30,692 INFO L745 eck$LassoCheckResult]: Stem: 145#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1847#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 684#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1843#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1770#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1060#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1403#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 260#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1396#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 537#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 435#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 793#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 292#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 544#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 676#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 802#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 828#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 907#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 301#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1826#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1393#L1258-2true assume !(0 == ~T1_E~0); 484#L1263-1true assume !(0 == ~T2_E~0); 709#L1268-1true assume !(0 == ~T3_E~0); 1359#L1273-1true assume !(0 == ~T4_E~0); 1759#L1278-1true assume !(0 == ~T5_E~0); 1141#L1283-1true assume !(0 == ~T6_E~0); 1793#L1288-1true assume !(0 == ~T7_E~0); 1564#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1533#L1298-1true assume !(0 == ~T9_E~0); 1379#L1303-1true assume !(0 == ~T10_E~0); 195#L1308-1true assume !(0 == ~T11_E~0); 164#L1313-1true assume !(0 == ~T12_E~0); 1851#L1318-1true assume !(0 == ~T13_E~0); 167#L1323-1true assume !(0 == ~E_1~0); 265#L1328-1true assume !(0 == ~E_2~0); 1803#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 961#L1338-1true assume !(0 == ~E_4~0); 1101#L1343-1true assume !(0 == ~E_5~0); 1656#L1348-1true assume !(0 == ~E_6~0); 1672#L1353-1true assume !(0 == ~E_7~0); 725#L1358-1true assume !(0 == ~E_8~0); 990#L1363-1true assume !(0 == ~E_9~0); 1051#L1368-1true assume !(0 == ~E_10~0); 91#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 483#L1378-1true assume !(0 == ~E_12~0); 235#L1383-1true assume !(0 == ~E_13~0); 1089#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 727#L607true assume 1 == ~m_pc~0; 998#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1096#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 658#L1560true assume !(0 != activate_threads_~tmp~1#1); 1737#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 175#L626true assume !(1 == ~t1_pc~0); 1260#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 324#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 971#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1923#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 128#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1329#L645true assume 1 == ~t2_pc~0; 184#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1293#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1915#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 643#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1718#L664true assume 1 == ~t3_pc~0; 1636#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 952#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 410#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1411#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1629#L683true assume !(1 == ~t4_pc~0); 973#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 780#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1705#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 918#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 598#L702true assume 1 == ~t5_pc~0; 1694#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 910#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1561#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1386#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1229#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74#L721true assume !(1 == ~t6_pc~0); 65#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 141#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 418#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1517#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 856#L740true assume 1 == ~t7_pc~0; 100#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1867#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 760#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 375#L759true assume !(1 == ~t8_pc~0); 1370#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1856#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1508#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1067#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1678#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1562#L778true assume 1 == ~t9_pc~0; 1334#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1266#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 246#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 731#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 182#L797true assume !(1 == ~t10_pc~0); 252#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1300#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1299#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 481#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 694#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1385#L816true assume 1 == ~t11_pc~0; 47#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 574#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1423#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 422#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1503#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 801#L835true assume 1 == ~t12_pc~0; 704#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 132#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1797#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 518#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1435#L854true assume !(1 == ~t13_pc~0); 293#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 321#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1355#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 140#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1221#L1664-2true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1804#L1401true assume !(1 == ~M_E~0); 414#L1401-2true assume !(1 == ~T1_E~0); 1232#L1406-1true assume !(1 == ~T2_E~0); 848#L1411-1true assume !(1 == ~T3_E~0); 1613#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 580#L1421-1true assume !(1 == ~T5_E~0); 291#L1426-1true assume !(1 == ~T6_E~0); 1004#L1431-1true assume !(1 == ~T7_E~0); 64#L1436-1true assume !(1 == ~T8_E~0); 745#L1441-1true assume !(1 == ~T9_E~0); 477#L1446-1true assume !(1 == ~T10_E~0); 1784#L1451-1true assume !(1 == ~T11_E~0); 1095#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 743#L1461-1true assume !(1 == ~T13_E~0); 432#L1466-1true assume !(1 == ~E_1~0); 1777#L1471-1true assume !(1 == ~E_2~0); 1066#L1476-1true assume !(1 == ~E_3~0); 1306#L1481-1true assume !(1 == ~E_4~0); 1592#L1486-1true assume !(1 == ~E_5~0); 203#L1491-1true assume !(1 == ~E_6~0); 35#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 756#L1501-1true assume !(1 == ~E_8~0); 474#L1506-1true assume !(1 == ~E_9~0); 1027#L1511-1true assume !(1 == ~E_10~0); 447#L1516-1true assume !(1 == ~E_11~0); 12#L1521-1true assume !(1 == ~E_12~0); 34#L1526-1true assume !(1 == ~E_13~0); 305#L1531-1true assume { :end_inline_reset_delta_events } true; 1161#L1892-2true [2024-10-25 00:40:30,695 INFO L747 eck$LassoCheckResult]: Loop: 1161#L1892-2true assume !false; 1879#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1767#L1233-1true assume !true; 536#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 330#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1632#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1914#L1258-5true assume !(0 == ~T1_E~0); 135#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1603#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1622#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1921#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1623#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 254#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1802#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1158#L1298-3true assume !(0 == ~T9_E~0); 1704#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1420#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1157#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 649#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 136#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1294#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1681#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 210#L1338-3true assume !(0 == ~E_4~0); 1045#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1534#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1303#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1343#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 610#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 325#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1898#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 873#L1378-3true assume !(0 == ~E_12~0); 1452#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1087#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1776#L607-42true assume !(1 == ~m_pc~0); 898#L607-44true is_master_triggered_~__retres1~0#1 := 0; 503#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 405#is_master_triggered_returnLabel#15true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 337#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 695#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1211#L626-42true assume 1 == ~t1_pc~0; 390#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1463#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1761#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1118#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1569#L645-42true assume 1 == ~t2_pc~0; 1407#L646-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1706#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 266#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1666#L664-42true assume 1 == ~t3_pc~0; 451#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1626#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 940#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 827#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1005#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1801#L683-42true assume !(1 == ~t4_pc~0); 729#L683-44true is_transmit4_triggered_~__retres1~4#1 := 0; 833#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1008#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1404#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1919#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1152#L702-42true assume 1 == ~t5_pc~0; 634#L703-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 576#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 655#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1280#L1600-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98#L721-42true assume !(1 == ~t6_pc~0); 1577#L721-44true is_transmit6_triggered_~__retres1~6#1 := 0; 357#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1585#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 463#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 368#L740-42true assume 1 == ~t7_pc~0; 1310#L741-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 550#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 670#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 453#L1616-42true assume !(0 != activate_threads_~tmp___6~0#1); 638#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1911#L759-42true assume !(1 == ~t8_pc~0); 1348#L759-44true is_transmit8_triggered_~__retres1~8#1 := 0; 487#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 797#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 538#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 600#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1164#L778-42true assume !(1 == ~t9_pc~0); 603#L778-44true is_transmit9_triggered_~__retres1~9#1 := 0; 804#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1781#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 730#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1614#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 775#L797-42true assume !(1 == ~t10_pc~0); 1034#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 924#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 790#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1890#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 805#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1722#L816-42true assume 1 == ~t11_pc~0; 9#L817-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1865#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1483#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 479#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 314#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 573#L835-42true assume 1 == ~t12_pc~0; 837#L836-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1235#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 641#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1850#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1228#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 938#L854-42true assume 1 == ~t13_pc~0; 1794#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 475#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 364#is_transmit13_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 508#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 430#L1664-44true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1869#L1401-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1079#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 183#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 119#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1687#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 457#L1421-3true assume !(1 == ~T5_E~0); 1041#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 207#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 281#L1436-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 14#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1134#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1123#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 513#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 295#L1461-3true assume !(1 == ~T13_E~0); 1612#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1828#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 267#L1476-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1696#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 507#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 280#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1471#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 535#L1501-3true assume !(1 == ~E_8~0); 1594#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 869#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 861#L1516-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1730#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 613#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 957#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1854#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1893#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 194#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 489#L1911true assume !(0 == start_simulation_~tmp~3#1); 1297#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 892#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1016#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 94#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 511#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1325#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1339#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1161#L1892-2true [2024-10-25 00:40:30,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:30,703 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2024-10-25 00:40:30,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:30,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837514007] [2024-10-25 00:40:30,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:30,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:30,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:30,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:30,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:30,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837514007] [2024-10-25 00:40:30,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837514007] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:30,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:30,988 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:30,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856126055] [2024-10-25 00:40:30,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:30,992 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:30,994 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:30,994 INFO L85 PathProgramCache]: Analyzing trace with hash 1896097708, now seen corresponding path program 1 times [2024-10-25 00:40:30,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:30,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535184247] [2024-10-25 00:40:30,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:30,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:31,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:31,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:31,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:31,066 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535184247] [2024-10-25 00:40:31,066 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535184247] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:31,066 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:31,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:31,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466662465] [2024-10-25 00:40:31,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:31,068 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:31,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:31,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-10-25 00:40:31,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-10-25 00:40:31,096 INFO L87 Difference]: Start difference. First operand has 1936 states, 1935 states have (on average 1.4945736434108527) internal successors, (2892), 1935 states have internal predecessors, (2892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:31,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:31,145 INFO L93 Difference]: Finished difference Result 1934 states and 2855 transitions. [2024-10-25 00:40:31,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1934 states and 2855 transitions. [2024-10-25 00:40:31,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:31,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1934 states to 1928 states and 2849 transitions. [2024-10-25 00:40:31,177 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:31,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:31,180 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2849 transitions. [2024-10-25 00:40:31,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:31,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2849 transitions. [2024-10-25 00:40:31,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2849 transitions. [2024-10-25 00:40:31,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:31,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4776970954356847) internal successors, (2849), 1927 states have internal predecessors, (2849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:31,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2849 transitions. [2024-10-25 00:40:31,263 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2849 transitions. [2024-10-25 00:40:31,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-10-25 00:40:31,270 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2849 transitions. [2024-10-25 00:40:31,270 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-25 00:40:31,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2849 transitions. [2024-10-25 00:40:31,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:31,282 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:31,282 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:31,284 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:31,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:31,288 INFO L745 eck$LassoCheckResult]: Stem: 4170#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5070#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5071#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5796#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5467#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5468#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4391#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4392#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4869#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4706#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4707#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4455#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4456#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4877#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5061#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5229#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5262#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4471#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4472#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5687#L1258-2 assume !(0 == ~T1_E~0); 4789#L1263-1 assume !(0 == ~T2_E~0); 4790#L1268-1 assume !(0 == ~T3_E~0); 5107#L1273-1 assume !(0 == ~T4_E~0); 5666#L1278-1 assume !(0 == ~T5_E~0); 5524#L1283-1 assume !(0 == ~T6_E~0); 5525#L1288-1 assume !(0 == ~T7_E~0); 5762#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5751#L1298-1 assume !(0 == ~T9_E~0); 5682#L1303-1 assume !(0 == ~T10_E~0); 4269#L1308-1 assume !(0 == ~T11_E~0); 4209#L1313-1 assume !(0 == ~T12_E~0); 4210#L1318-1 assume !(0 == ~T13_E~0); 4215#L1323-1 assume !(0 == ~E_1~0); 4216#L1328-1 assume !(0 == ~E_2~0); 4401#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5395#L1338-1 assume !(0 == ~E_4~0); 5396#L1343-1 assume !(0 == ~E_5~0); 5501#L1348-1 assume !(0 == ~E_6~0); 5781#L1353-1 assume !(0 == ~E_7~0); 5130#L1358-1 assume !(0 == ~E_8~0); 5131#L1363-1 assume !(0 == ~E_9~0); 5417#L1368-1 assume !(0 == ~E_10~0); 4063#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4064#L1378-1 assume !(0 == ~E_12~0); 4344#L1383-1 assume !(0 == ~E_13~0); 4345#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5135#L607 assume 1 == ~m_pc~0; 5136#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4419#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4932#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4933#L1560 assume !(0 != activate_threads_~tmp~1#1); 5042#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4230#L626 assume !(1 == ~t1_pc~0); 4231#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4512#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4513#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5403#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4138#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4139#L645 assume 1 == ~t2_pc~0; 4246#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4203#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4312#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4313#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 5016#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5017#L664 assume 1 == ~t3_pc~0; 5779#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3997#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3998#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4661#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4662#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5695#L683 assume !(1 == ~t4_pc~0); 5246#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5200#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4021#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4022#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5353#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4956#L702 assume 1 == ~t5_pc~0; 4957#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4892#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5348#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5685#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5593#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4033#L721 assume !(1 == ~t6_pc~0); 4014#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4015#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4162#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4297#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4677#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5293#L740 assume 1 == ~t7_pc~0; 4079#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3914#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3915#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3904#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3905#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4601#L759 assume !(1 == ~t8_pc~0); 4602#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4633#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5739#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5478#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5479#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5761#L778 assume 1 == ~t9_pc~0; 5651#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4062#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4367#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3940#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3941#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4242#L797 assume !(1 == ~t10_pc~0); 4243#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4377#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5628#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4785#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4786#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5087#L816 assume 1 == ~t11_pc~0; 3975#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3976#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4921#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4683#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4684#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5228#L835 assume 1 == ~t12_pc~0; 5102#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4126#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3965#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3966#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4841#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4842#L854 assume !(1 == ~t13_pc~0); 4457#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4458#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4507#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4160#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4161#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5589#L1401 assume !(1 == ~M_E~0); 4670#L1401-2 assume !(1 == ~T1_E~0); 4671#L1406-1 assume !(1 == ~T2_E~0); 5282#L1411-1 assume !(1 == ~T3_E~0); 5283#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4931#L1421-1 assume !(1 == ~T5_E~0); 4453#L1426-1 assume !(1 == ~T6_E~0); 4454#L1431-1 assume !(1 == ~T7_E~0); 4012#L1436-1 assume !(1 == ~T8_E~0); 4013#L1441-1 assume !(1 == ~T9_E~0); 4778#L1446-1 assume !(1 == ~T10_E~0); 4779#L1451-1 assume !(1 == ~T11_E~0); 5497#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5155#L1461-1 assume !(1 == ~T13_E~0); 4699#L1466-1 assume !(1 == ~E_1~0); 4700#L1471-1 assume !(1 == ~E_2~0); 5476#L1476-1 assume !(1 == ~E_3~0); 5477#L1481-1 assume !(1 == ~E_4~0); 5634#L1486-1 assume !(1 == ~E_5~0); 4282#L1491-1 assume !(1 == ~E_6~0); 3950#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3951#L1501-1 assume !(1 == ~E_8~0); 4774#L1506-1 assume !(1 == ~E_9~0); 4775#L1511-1 assume !(1 == ~E_10~0); 4729#L1516-1 assume !(1 == ~E_11~0); 3902#L1521-1 assume !(1 == ~E_12~0); 3903#L1526-1 assume !(1 == ~E_13~0); 3949#L1531-1 assume { :end_inline_reset_delta_events } true; 4479#L1892-2 [2024-10-25 00:40:31,288 INFO L747 eck$LassoCheckResult]: Loop: 4479#L1892-2 assume !false; 5542#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5795#L1233-1 assume !false; 5722#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5043#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 5023#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5571#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3991#L1046 assume !(0 != eval_~tmp~0#1); 3993#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4524#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4525#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5778#L1258-5 assume !(0 == ~T1_E~0); 4150#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4151#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5770#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5774#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5775#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4382#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4383#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5539#L1298-3 assume !(0 == ~T9_E~0); 5540#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5702#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5538#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5027#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4152#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4153#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5626#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4293#L1338-3 assume !(0 == ~E_4~0); 4294#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5453#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5631#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5632#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4972#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4514#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4515#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5313#L1378-3 assume !(0 == ~E_12~0); 5314#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5494#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5495#L607-42 assume 1 == ~m_pc~0; 5112#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4822#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4654#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4534#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4535#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5088#L626-42 assume 1 == ~t1_pc~0; 4625#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4626#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5726#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5511#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4185#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4186#L645-42 assume !(1 == ~t2_pc~0); 5431#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5432#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4970#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4402#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3922#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3923#L664-42 assume !(1 == ~t3_pc~0); 4438#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4439#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5372#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5260#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5261#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5424#L683-42 assume !(1 == ~t4_pc~0); 5138#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 5139#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5267#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5427#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5692#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5533#L702-42 assume !(1 == ~t5_pc~0); 4615#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4616#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4924#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5037#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3934#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3935#L721-42 assume 1 == ~t6_pc~0; 4074#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4095#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4273#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4274#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4755#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4589#L740-42 assume !(1 == ~t7_pc~0); 4308#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4309#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4885#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4738#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 4739#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5010#L759-42 assume 1 == ~t8_pc~0; 4861#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4795#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4796#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4870#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4871#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4961#L778-42 assume 1 == ~t9_pc~0; 4807#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4809#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5232#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5140#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5141#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5195#L797-42 assume 1 == ~t10_pc~0; 4316#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4317#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5213#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5214#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5233#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5234#L816-42 assume 1 == ~t11_pc~0; 3894#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3895#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5732#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4782#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4493#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4494#L835-42 assume !(1 == ~t12_pc~0); 4818#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4819#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5013#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5014#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5592#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5370#L854-42 assume 1 == ~t13_pc~0; 5371#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4415#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4581#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4582#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4695#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4696#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5487#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4245#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4121#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4122#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4745#L1421-3 assume !(1 == ~T5_E~0); 4746#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4287#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4288#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3906#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3907#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5515#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4833#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4461#L1461-3 assume !(1 == ~T13_E~0); 4462#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5772#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4403#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4404#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4827#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4431#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4432#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4867#L1501-3 assume !(1 == ~E_8~0); 4868#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5309#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5297#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5298#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4975#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4976#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5391#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4220#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4267#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4268#L1911 assume !(0 == start_simulation_~tmp~3#1); 4799#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5330#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4358#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3944#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3945#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4068#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4831#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 5645#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4479#L1892-2 [2024-10-25 00:40:31,289 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:31,289 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2024-10-25 00:40:31,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:31,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838292082] [2024-10-25 00:40:31,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:31,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:31,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:31,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:31,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:31,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838292082] [2024-10-25 00:40:31,370 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838292082] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:31,370 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:31,371 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:31,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382785703] [2024-10-25 00:40:31,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:31,371 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:31,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:31,372 INFO L85 PathProgramCache]: Analyzing trace with hash -1414834051, now seen corresponding path program 1 times [2024-10-25 00:40:31,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:31,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280681785] [2024-10-25 00:40:31,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:31,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:31,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:31,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:31,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:31,513 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280681785] [2024-10-25 00:40:31,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280681785] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:31,514 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:31,514 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:31,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594267519] [2024-10-25 00:40:31,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:31,514 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:31,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:31,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:31,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:31,515 INFO L87 Difference]: Start difference. First operand 1928 states and 2849 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:31,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:31,560 INFO L93 Difference]: Finished difference Result 1928 states and 2848 transitions. [2024-10-25 00:40:31,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2848 transitions. [2024-10-25 00:40:31,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:31,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2848 transitions. [2024-10-25 00:40:31,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:31,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:31,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2848 transitions. [2024-10-25 00:40:31,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:31,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2848 transitions. [2024-10-25 00:40:31,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2848 transitions. [2024-10-25 00:40:31,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:31,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4771784232365146) internal successors, (2848), 1927 states have internal predecessors, (2848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:31,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2848 transitions. [2024-10-25 00:40:31,607 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2848 transitions. [2024-10-25 00:40:31,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:31,608 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2848 transitions. [2024-10-25 00:40:31,608 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-25 00:40:31,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2848 transitions. [2024-10-25 00:40:31,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:31,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:31,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:31,619 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:31,619 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:31,620 INFO L745 eck$LassoCheckResult]: Stem: 8033#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8034#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8933#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8934#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9659#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9330#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9331#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8254#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8255#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8732#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8569#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8570#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8318#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8319#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8740#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8924#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9092#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9125#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8334#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8335#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9550#L1258-2 assume !(0 == ~T1_E~0); 8652#L1263-1 assume !(0 == ~T2_E~0); 8653#L1268-1 assume !(0 == ~T3_E~0); 8970#L1273-1 assume !(0 == ~T4_E~0); 9529#L1278-1 assume !(0 == ~T5_E~0); 9387#L1283-1 assume !(0 == ~T6_E~0); 9388#L1288-1 assume !(0 == ~T7_E~0); 9625#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9614#L1298-1 assume !(0 == ~T9_E~0); 9545#L1303-1 assume !(0 == ~T10_E~0); 8132#L1308-1 assume !(0 == ~T11_E~0); 8072#L1313-1 assume !(0 == ~T12_E~0); 8073#L1318-1 assume !(0 == ~T13_E~0); 8078#L1323-1 assume !(0 == ~E_1~0); 8079#L1328-1 assume !(0 == ~E_2~0); 8264#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9258#L1338-1 assume !(0 == ~E_4~0); 9259#L1343-1 assume !(0 == ~E_5~0); 9364#L1348-1 assume !(0 == ~E_6~0); 9644#L1353-1 assume !(0 == ~E_7~0); 8993#L1358-1 assume !(0 == ~E_8~0); 8994#L1363-1 assume !(0 == ~E_9~0); 9280#L1368-1 assume !(0 == ~E_10~0); 7926#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7927#L1378-1 assume !(0 == ~E_12~0); 8207#L1383-1 assume !(0 == ~E_13~0); 8208#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8998#L607 assume 1 == ~m_pc~0; 8999#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8282#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8795#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8796#L1560 assume !(0 != activate_threads_~tmp~1#1); 8905#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8093#L626 assume !(1 == ~t1_pc~0); 8094#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8375#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8376#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9266#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 8001#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8002#L645 assume 1 == ~t2_pc~0; 8109#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8066#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8175#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8176#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8879#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8880#L664 assume 1 == ~t3_pc~0; 9642#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7860#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7861#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8524#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8525#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9558#L683 assume !(1 == ~t4_pc~0); 9109#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9063#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7884#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7885#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9216#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8819#L702 assume 1 == ~t5_pc~0; 8820#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8755#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9211#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9548#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9456#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7896#L721 assume !(1 == ~t6_pc~0); 7877#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7878#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8025#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8160#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8540#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9156#L740 assume 1 == ~t7_pc~0; 7942#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7777#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7778#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7767#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7768#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8464#L759 assume !(1 == ~t8_pc~0); 8465#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8496#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9602#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9341#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9342#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9624#L778 assume 1 == ~t9_pc~0; 9514#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7925#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8230#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7803#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7804#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8105#L797 assume !(1 == ~t10_pc~0); 8106#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8240#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9491#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8648#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8649#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8950#L816 assume 1 == ~t11_pc~0; 7838#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7839#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8784#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8546#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8547#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9091#L835 assume 1 == ~t12_pc~0; 8965#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7989#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7828#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7829#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8704#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8705#L854 assume !(1 == ~t13_pc~0); 8320#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8321#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8370#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8023#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8024#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9452#L1401 assume !(1 == ~M_E~0); 8533#L1401-2 assume !(1 == ~T1_E~0); 8534#L1406-1 assume !(1 == ~T2_E~0); 9145#L1411-1 assume !(1 == ~T3_E~0); 9146#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8794#L1421-1 assume !(1 == ~T5_E~0); 8316#L1426-1 assume !(1 == ~T6_E~0); 8317#L1431-1 assume !(1 == ~T7_E~0); 7875#L1436-1 assume !(1 == ~T8_E~0); 7876#L1441-1 assume !(1 == ~T9_E~0); 8641#L1446-1 assume !(1 == ~T10_E~0); 8642#L1451-1 assume !(1 == ~T11_E~0); 9360#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9018#L1461-1 assume !(1 == ~T13_E~0); 8562#L1466-1 assume !(1 == ~E_1~0); 8563#L1471-1 assume !(1 == ~E_2~0); 9339#L1476-1 assume !(1 == ~E_3~0); 9340#L1481-1 assume !(1 == ~E_4~0); 9497#L1486-1 assume !(1 == ~E_5~0); 8145#L1491-1 assume !(1 == ~E_6~0); 7813#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7814#L1501-1 assume !(1 == ~E_8~0); 8637#L1506-1 assume !(1 == ~E_9~0); 8638#L1511-1 assume !(1 == ~E_10~0); 8592#L1516-1 assume !(1 == ~E_11~0); 7765#L1521-1 assume !(1 == ~E_12~0); 7766#L1526-1 assume !(1 == ~E_13~0); 7812#L1531-1 assume { :end_inline_reset_delta_events } true; 8342#L1892-2 [2024-10-25 00:40:31,622 INFO L747 eck$LassoCheckResult]: Loop: 8342#L1892-2 assume !false; 9405#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9658#L1233-1 assume !false; 9585#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8906#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8886#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9434#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7854#L1046 assume !(0 != eval_~tmp~0#1); 7856#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8387#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8388#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9641#L1258-5 assume !(0 == ~T1_E~0); 8013#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8014#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9633#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9637#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9638#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8245#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8246#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9402#L1298-3 assume !(0 == ~T9_E~0); 9403#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9565#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9401#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8890#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8015#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8016#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9489#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8156#L1338-3 assume !(0 == ~E_4~0); 8157#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9316#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9494#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9495#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8835#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8377#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8378#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9176#L1378-3 assume !(0 == ~E_12~0); 9177#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9357#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9358#L607-42 assume !(1 == ~m_pc~0); 8976#L607-44 is_master_triggered_~__retres1~0#1 := 0; 8685#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8517#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8397#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8398#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8951#L626-42 assume 1 == ~t1_pc~0; 8488#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8489#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9589#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9374#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8048#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8049#L645-42 assume 1 == ~t2_pc~0; 9557#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9295#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8833#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8265#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7785#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7786#L664-42 assume 1 == ~t3_pc~0; 8598#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8302#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9235#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9123#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9124#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9287#L683-42 assume 1 == ~t4_pc~0; 9650#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9002#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9130#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9290#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9555#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9396#L702-42 assume 1 == ~t5_pc~0; 8867#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8479#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8787#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8900#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7797#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7798#L721-42 assume 1 == ~t6_pc~0; 7937#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7958#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8136#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8137#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8618#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8452#L740-42 assume 1 == ~t7_pc~0; 8453#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8172#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8748#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8601#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 8602#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8873#L759-42 assume 1 == ~t8_pc~0; 8724#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8658#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8659#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8733#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8734#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8824#L778-42 assume 1 == ~t9_pc~0; 8670#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8672#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9095#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9003#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9004#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9058#L797-42 assume 1 == ~t10_pc~0; 8179#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8180#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9076#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9077#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9096#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9097#L816-42 assume 1 == ~t11_pc~0; 7757#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7758#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9595#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8645#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8356#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8357#L835-42 assume !(1 == ~t12_pc~0); 8681#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 8682#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8876#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8877#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9455#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9233#L854-42 assume 1 == ~t13_pc~0; 9234#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8278#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8444#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8445#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8558#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8559#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9350#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8108#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7984#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7985#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8608#L1421-3 assume !(1 == ~T5_E~0); 8609#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8150#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8151#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7769#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7770#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9378#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8696#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8324#L1461-3 assume !(1 == ~T13_E~0); 8325#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9635#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8266#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8267#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8690#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8294#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8295#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8730#L1501-3 assume !(1 == ~E_8~0); 8731#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9172#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9160#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9161#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8838#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8839#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9254#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8083#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8130#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8131#L1911 assume !(0 == start_simulation_~tmp~3#1); 8662#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9193#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8221#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 7807#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7808#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7931#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8694#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 9508#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8342#L1892-2 [2024-10-25 00:40:31,622 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:31,622 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2024-10-25 00:40:31,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:31,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [231428040] [2024-10-25 00:40:31,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:31,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:31,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:31,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:31,697 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:31,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [231428040] [2024-10-25 00:40:31,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [231428040] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:31,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:31,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:31,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574601340] [2024-10-25 00:40:31,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:31,698 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:31,698 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:31,699 INFO L85 PathProgramCache]: Analyzing trace with hash 1581274049, now seen corresponding path program 1 times [2024-10-25 00:40:31,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:31,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005465509] [2024-10-25 00:40:31,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:31,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:31,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:31,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:31,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:31,767 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005465509] [2024-10-25 00:40:31,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1005465509] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:31,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:31,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:31,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523530421] [2024-10-25 00:40:31,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:31,768 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:31,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:31,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:31,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:31,769 INFO L87 Difference]: Start difference. First operand 1928 states and 2848 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:31,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:31,799 INFO L93 Difference]: Finished difference Result 1928 states and 2847 transitions. [2024-10-25 00:40:31,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2847 transitions. [2024-10-25 00:40:31,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:31,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2847 transitions. [2024-10-25 00:40:31,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:31,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:31,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2847 transitions. [2024-10-25 00:40:31,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:31,820 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2847 transitions. [2024-10-25 00:40:31,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2847 transitions. [2024-10-25 00:40:31,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:31,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4766597510373445) internal successors, (2847), 1927 states have internal predecessors, (2847), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:31,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2847 transitions. [2024-10-25 00:40:31,845 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2847 transitions. [2024-10-25 00:40:31,845 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:31,846 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2847 transitions. [2024-10-25 00:40:31,846 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-25 00:40:31,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2847 transitions. [2024-10-25 00:40:31,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:31,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:31,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:31,856 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:31,856 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:31,857 INFO L745 eck$LassoCheckResult]: Stem: 11896#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 11897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12796#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12797#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13522#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13193#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13194#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12117#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12118#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12595#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12432#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12433#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12181#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12182#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12603#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12787#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12955#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12988#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12197#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12198#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13413#L1258-2 assume !(0 == ~T1_E~0); 12515#L1263-1 assume !(0 == ~T2_E~0); 12516#L1268-1 assume !(0 == ~T3_E~0); 12833#L1273-1 assume !(0 == ~T4_E~0); 13392#L1278-1 assume !(0 == ~T5_E~0); 13250#L1283-1 assume !(0 == ~T6_E~0); 13251#L1288-1 assume !(0 == ~T7_E~0); 13488#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13477#L1298-1 assume !(0 == ~T9_E~0); 13408#L1303-1 assume !(0 == ~T10_E~0); 11995#L1308-1 assume !(0 == ~T11_E~0); 11935#L1313-1 assume !(0 == ~T12_E~0); 11936#L1318-1 assume !(0 == ~T13_E~0); 11941#L1323-1 assume !(0 == ~E_1~0); 11942#L1328-1 assume !(0 == ~E_2~0); 12127#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13121#L1338-1 assume !(0 == ~E_4~0); 13122#L1343-1 assume !(0 == ~E_5~0); 13227#L1348-1 assume !(0 == ~E_6~0); 13507#L1353-1 assume !(0 == ~E_7~0); 12856#L1358-1 assume !(0 == ~E_8~0); 12857#L1363-1 assume !(0 == ~E_9~0); 13143#L1368-1 assume !(0 == ~E_10~0); 11789#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11790#L1378-1 assume !(0 == ~E_12~0); 12070#L1383-1 assume !(0 == ~E_13~0); 12071#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12861#L607 assume 1 == ~m_pc~0; 12862#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12145#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12658#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12659#L1560 assume !(0 != activate_threads_~tmp~1#1); 12768#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11956#L626 assume !(1 == ~t1_pc~0); 11957#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12238#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12239#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13129#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11864#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11865#L645 assume 1 == ~t2_pc~0; 11972#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11929#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12038#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12039#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12742#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12743#L664 assume 1 == ~t3_pc~0; 13505#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11723#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11724#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12387#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12388#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13421#L683 assume !(1 == ~t4_pc~0); 12972#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12926#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11748#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13079#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12682#L702 assume 1 == ~t5_pc~0; 12683#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12618#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13074#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13411#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13319#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11759#L721 assume !(1 == ~t6_pc~0); 11740#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11741#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11888#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12023#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12403#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13019#L740 assume 1 == ~t7_pc~0; 11805#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11640#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11641#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11630#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11631#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12327#L759 assume !(1 == ~t8_pc~0); 12328#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12359#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13465#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13204#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13205#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13487#L778 assume 1 == ~t9_pc~0; 13377#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11788#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12093#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11666#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11667#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11968#L797 assume !(1 == ~t10_pc~0); 11969#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12103#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13354#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12511#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12512#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12813#L816 assume 1 == ~t11_pc~0; 11701#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11702#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12647#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12409#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12410#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12954#L835 assume 1 == ~t12_pc~0; 12828#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11852#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11691#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11692#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12567#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12568#L854 assume !(1 == ~t13_pc~0); 12183#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12184#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12233#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11886#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11887#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13315#L1401 assume !(1 == ~M_E~0); 12396#L1401-2 assume !(1 == ~T1_E~0); 12397#L1406-1 assume !(1 == ~T2_E~0); 13008#L1411-1 assume !(1 == ~T3_E~0); 13009#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12657#L1421-1 assume !(1 == ~T5_E~0); 12179#L1426-1 assume !(1 == ~T6_E~0); 12180#L1431-1 assume !(1 == ~T7_E~0); 11738#L1436-1 assume !(1 == ~T8_E~0); 11739#L1441-1 assume !(1 == ~T9_E~0); 12504#L1446-1 assume !(1 == ~T10_E~0); 12505#L1451-1 assume !(1 == ~T11_E~0); 13223#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12881#L1461-1 assume !(1 == ~T13_E~0); 12425#L1466-1 assume !(1 == ~E_1~0); 12426#L1471-1 assume !(1 == ~E_2~0); 13202#L1476-1 assume !(1 == ~E_3~0); 13203#L1481-1 assume !(1 == ~E_4~0); 13360#L1486-1 assume !(1 == ~E_5~0); 12008#L1491-1 assume !(1 == ~E_6~0); 11676#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11677#L1501-1 assume !(1 == ~E_8~0); 12500#L1506-1 assume !(1 == ~E_9~0); 12501#L1511-1 assume !(1 == ~E_10~0); 12455#L1516-1 assume !(1 == ~E_11~0); 11628#L1521-1 assume !(1 == ~E_12~0); 11629#L1526-1 assume !(1 == ~E_13~0); 11675#L1531-1 assume { :end_inline_reset_delta_events } true; 12205#L1892-2 [2024-10-25 00:40:31,857 INFO L747 eck$LassoCheckResult]: Loop: 12205#L1892-2 assume !false; 13268#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13521#L1233-1 assume !false; 13448#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12769#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12749#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13297#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11717#L1046 assume !(0 != eval_~tmp~0#1); 11719#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12250#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12251#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13504#L1258-5 assume !(0 == ~T1_E~0); 11876#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11877#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13496#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13500#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13501#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12108#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12109#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13265#L1298-3 assume !(0 == ~T9_E~0); 13266#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13428#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13264#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12753#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11878#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11879#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13352#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12019#L1338-3 assume !(0 == ~E_4~0); 12020#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13179#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13357#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13358#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12698#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12240#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12241#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13039#L1378-3 assume !(0 == ~E_12~0); 13040#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13220#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13221#L607-42 assume 1 == ~m_pc~0; 12838#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12548#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12380#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12260#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12261#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12814#L626-42 assume !(1 == ~t1_pc~0); 12353#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12352#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13452#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13237#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11911#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11912#L645-42 assume !(1 == ~t2_pc~0); 13157#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13158#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12696#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12128#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11648#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11649#L664-42 assume !(1 == ~t3_pc~0); 12164#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12165#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13098#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12986#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12987#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13150#L683-42 assume !(1 == ~t4_pc~0); 12864#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12865#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12993#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13153#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13418#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13259#L702-42 assume !(1 == ~t5_pc~0); 12341#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 12342#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12650#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12763#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11660#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11661#L721-42 assume 1 == ~t6_pc~0; 11800#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11821#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11999#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12000#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12481#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12315#L740-42 assume !(1 == ~t7_pc~0); 12034#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 12035#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12611#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12464#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 12465#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12736#L759-42 assume 1 == ~t8_pc~0; 12587#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12521#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12522#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12596#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12597#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12687#L778-42 assume 1 == ~t9_pc~0; 12533#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12535#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12958#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12866#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12867#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12921#L797-42 assume 1 == ~t10_pc~0; 12042#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12043#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12939#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12940#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12959#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12960#L816-42 assume 1 == ~t11_pc~0; 11620#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11621#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13458#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12508#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12219#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12220#L835-42 assume !(1 == ~t12_pc~0); 12544#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 12545#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12739#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12740#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13318#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13096#L854-42 assume 1 == ~t13_pc~0; 13097#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12141#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12307#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12308#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12421#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12422#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13213#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11971#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11847#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11848#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12471#L1421-3 assume !(1 == ~T5_E~0); 12472#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12013#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12014#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11632#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11633#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13241#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12559#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12187#L1461-3 assume !(1 == ~T13_E~0); 12188#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13498#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12129#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12130#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12553#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12157#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12158#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12593#L1501-3 assume !(1 == ~E_8~0); 12594#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13035#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13023#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13024#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12701#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12702#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13117#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11946#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11993#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11994#L1911 assume !(0 == start_simulation_~tmp~3#1); 12525#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13056#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12084#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11670#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11671#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11794#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12557#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 13371#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12205#L1892-2 [2024-10-25 00:40:31,858 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:31,859 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2024-10-25 00:40:31,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:31,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823073621] [2024-10-25 00:40:31,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:31,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:31,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:31,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:31,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:31,905 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [823073621] [2024-10-25 00:40:31,905 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [823073621] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:31,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:31,906 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:31,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [51435664] [2024-10-25 00:40:31,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:31,909 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:31,909 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:31,910 INFO L85 PathProgramCache]: Analyzing trace with hash 2002878428, now seen corresponding path program 1 times [2024-10-25 00:40:31,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:31,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [388147329] [2024-10-25 00:40:31,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:31,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:31,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [388147329] [2024-10-25 00:40:32,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [388147329] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769408643] [2024-10-25 00:40:32,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,010 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:32,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:32,010 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:32,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:32,011 INFO L87 Difference]: Start difference. First operand 1928 states and 2847 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:32,047 INFO L93 Difference]: Finished difference Result 1928 states and 2846 transitions. [2024-10-25 00:40:32,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2846 transitions. [2024-10-25 00:40:32,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2846 transitions. [2024-10-25 00:40:32,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:32,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:32,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2846 transitions. [2024-10-25 00:40:32,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:32,069 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2846 transitions. [2024-10-25 00:40:32,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2846 transitions. [2024-10-25 00:40:32,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:32,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4761410788381744) internal successors, (2846), 1927 states have internal predecessors, (2846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2846 transitions. [2024-10-25 00:40:32,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2846 transitions. [2024-10-25 00:40:32,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:32,099 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2846 transitions. [2024-10-25 00:40:32,099 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-25 00:40:32,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2846 transitions. [2024-10-25 00:40:32,107 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:32,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:32,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,109 INFO L745 eck$LassoCheckResult]: Stem: 15759#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 15760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16659#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16660#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17385#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 17056#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17057#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15980#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15981#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16458#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16295#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16296#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16044#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16045#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16466#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16650#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16818#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16851#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 16060#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16061#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17276#L1258-2 assume !(0 == ~T1_E~0); 16378#L1263-1 assume !(0 == ~T2_E~0); 16379#L1268-1 assume !(0 == ~T3_E~0); 16696#L1273-1 assume !(0 == ~T4_E~0); 17255#L1278-1 assume !(0 == ~T5_E~0); 17113#L1283-1 assume !(0 == ~T6_E~0); 17114#L1288-1 assume !(0 == ~T7_E~0); 17351#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17340#L1298-1 assume !(0 == ~T9_E~0); 17271#L1303-1 assume !(0 == ~T10_E~0); 15858#L1308-1 assume !(0 == ~T11_E~0); 15798#L1313-1 assume !(0 == ~T12_E~0); 15799#L1318-1 assume !(0 == ~T13_E~0); 15804#L1323-1 assume !(0 == ~E_1~0); 15805#L1328-1 assume !(0 == ~E_2~0); 15990#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16984#L1338-1 assume !(0 == ~E_4~0); 16985#L1343-1 assume !(0 == ~E_5~0); 17090#L1348-1 assume !(0 == ~E_6~0); 17370#L1353-1 assume !(0 == ~E_7~0); 16719#L1358-1 assume !(0 == ~E_8~0); 16720#L1363-1 assume !(0 == ~E_9~0); 17006#L1368-1 assume !(0 == ~E_10~0); 15652#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15653#L1378-1 assume !(0 == ~E_12~0); 15933#L1383-1 assume !(0 == ~E_13~0); 15934#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16724#L607 assume 1 == ~m_pc~0; 16725#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16008#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16521#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16522#L1560 assume !(0 != activate_threads_~tmp~1#1); 16631#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15819#L626 assume !(1 == ~t1_pc~0); 15820#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16101#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16992#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15727#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15728#L645 assume 1 == ~t2_pc~0; 15835#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15792#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15901#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15902#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16605#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16606#L664 assume 1 == ~t3_pc~0; 17368#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15586#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15587#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16250#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16251#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17284#L683 assume !(1 == ~t4_pc~0); 16835#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16789#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15610#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15611#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16942#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16545#L702 assume 1 == ~t5_pc~0; 16546#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16481#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16937#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17274#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17182#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15622#L721 assume !(1 == ~t6_pc~0); 15603#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15604#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15751#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15886#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16266#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16882#L740 assume 1 == ~t7_pc~0; 15668#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15503#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15504#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15493#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15494#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16190#L759 assume !(1 == ~t8_pc~0); 16191#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16222#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17328#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17067#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 17068#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17350#L778 assume 1 == ~t9_pc~0; 17240#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15651#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15956#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15529#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15530#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15831#L797 assume !(1 == ~t10_pc~0); 15832#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15966#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17217#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16374#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16375#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16676#L816 assume 1 == ~t11_pc~0; 15564#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15565#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16510#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16272#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16273#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16817#L835 assume 1 == ~t12_pc~0; 16691#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15715#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15554#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15555#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16430#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16431#L854 assume !(1 == ~t13_pc~0); 16046#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 16047#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16096#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15749#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15750#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17178#L1401 assume !(1 == ~M_E~0); 16259#L1401-2 assume !(1 == ~T1_E~0); 16260#L1406-1 assume !(1 == ~T2_E~0); 16871#L1411-1 assume !(1 == ~T3_E~0); 16872#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16520#L1421-1 assume !(1 == ~T5_E~0); 16042#L1426-1 assume !(1 == ~T6_E~0); 16043#L1431-1 assume !(1 == ~T7_E~0); 15601#L1436-1 assume !(1 == ~T8_E~0); 15602#L1441-1 assume !(1 == ~T9_E~0); 16367#L1446-1 assume !(1 == ~T10_E~0); 16368#L1451-1 assume !(1 == ~T11_E~0); 17086#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16744#L1461-1 assume !(1 == ~T13_E~0); 16288#L1466-1 assume !(1 == ~E_1~0); 16289#L1471-1 assume !(1 == ~E_2~0); 17065#L1476-1 assume !(1 == ~E_3~0); 17066#L1481-1 assume !(1 == ~E_4~0); 17223#L1486-1 assume !(1 == ~E_5~0); 15871#L1491-1 assume !(1 == ~E_6~0); 15539#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15540#L1501-1 assume !(1 == ~E_8~0); 16363#L1506-1 assume !(1 == ~E_9~0); 16364#L1511-1 assume !(1 == ~E_10~0); 16318#L1516-1 assume !(1 == ~E_11~0); 15491#L1521-1 assume !(1 == ~E_12~0); 15492#L1526-1 assume !(1 == ~E_13~0); 15538#L1531-1 assume { :end_inline_reset_delta_events } true; 16068#L1892-2 [2024-10-25 00:40:32,112 INFO L747 eck$LassoCheckResult]: Loop: 16068#L1892-2 assume !false; 17131#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17384#L1233-1 assume !false; 17311#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16632#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16612#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17160#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15580#L1046 assume !(0 != eval_~tmp~0#1); 15582#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16113#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16114#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17367#L1258-5 assume !(0 == ~T1_E~0); 15739#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15740#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17359#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17363#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17364#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15971#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15972#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17128#L1298-3 assume !(0 == ~T9_E~0); 17129#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17291#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17127#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16616#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15741#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15742#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17215#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15882#L1338-3 assume !(0 == ~E_4~0); 15883#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17042#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17220#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17221#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16561#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16103#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16104#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16902#L1378-3 assume !(0 == ~E_12~0); 16903#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17083#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17084#L607-42 assume 1 == ~m_pc~0; 16701#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16411#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16243#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16123#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16124#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16677#L626-42 assume 1 == ~t1_pc~0; 16214#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16215#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17315#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17100#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15774#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15775#L645-42 assume 1 == ~t2_pc~0; 17283#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17021#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16559#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15991#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15511#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15512#L664-42 assume 1 == ~t3_pc~0; 16324#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16028#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16961#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16849#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16850#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17013#L683-42 assume 1 == ~t4_pc~0; 17376#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16728#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16856#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17016#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17281#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17122#L702-42 assume 1 == ~t5_pc~0; 16593#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16205#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16513#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16626#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15523#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15524#L721-42 assume !(1 == ~t6_pc~0); 15664#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 15684#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15862#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15863#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16344#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16178#L740-42 assume 1 == ~t7_pc~0; 16179#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15898#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16474#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16327#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 16328#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16599#L759-42 assume 1 == ~t8_pc~0; 16450#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16384#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16385#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16459#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16460#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16550#L778-42 assume 1 == ~t9_pc~0; 16396#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16398#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16821#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16729#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16730#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16784#L797-42 assume 1 == ~t10_pc~0; 15905#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15906#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16802#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16803#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16822#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16823#L816-42 assume 1 == ~t11_pc~0; 15483#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15484#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17321#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16371#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16082#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16083#L835-42 assume !(1 == ~t12_pc~0); 16407#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16408#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16602#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16603#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17181#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16959#L854-42 assume 1 == ~t13_pc~0; 16960#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16004#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16170#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16171#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16284#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16285#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17076#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15834#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15710#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15711#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16334#L1421-3 assume !(1 == ~T5_E~0); 16335#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15876#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15877#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15495#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15496#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17104#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16422#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16050#L1461-3 assume !(1 == ~T13_E~0); 16051#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17361#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15992#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15993#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16416#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16020#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16021#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16456#L1501-3 assume !(1 == ~E_8~0); 16457#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16898#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16886#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16887#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16564#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16565#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16980#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15809#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15856#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15857#L1911 assume !(0 == start_simulation_~tmp~3#1); 16388#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16919#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15947#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15533#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15534#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15657#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16420#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 17234#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 16068#L1892-2 [2024-10-25 00:40:32,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,113 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2024-10-25 00:40:32,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361582009] [2024-10-25 00:40:32,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361582009] [2024-10-25 00:40:32,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [361582009] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,165 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196141446] [2024-10-25 00:40:32,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,166 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:32,166 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,166 INFO L85 PathProgramCache]: Analyzing trace with hash 1178302273, now seen corresponding path program 1 times [2024-10-25 00:40:32,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539198116] [2024-10-25 00:40:32,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539198116] [2024-10-25 00:40:32,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539198116] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,222 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864660203] [2024-10-25 00:40:32,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,222 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:32,222 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:32,222 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:32,222 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:32,223 INFO L87 Difference]: Start difference. First operand 1928 states and 2846 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:32,249 INFO L93 Difference]: Finished difference Result 1928 states and 2845 transitions. [2024-10-25 00:40:32,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2845 transitions. [2024-10-25 00:40:32,255 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2845 transitions. [2024-10-25 00:40:32,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:32,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:32,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2845 transitions. [2024-10-25 00:40:32,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:32,264 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2845 transitions. [2024-10-25 00:40:32,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2845 transitions. [2024-10-25 00:40:32,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:32,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4756224066390042) internal successors, (2845), 1927 states have internal predecessors, (2845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2845 transitions. [2024-10-25 00:40:32,287 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2845 transitions. [2024-10-25 00:40:32,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:32,288 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2845 transitions. [2024-10-25 00:40:32,288 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-25 00:40:32,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2845 transitions. [2024-10-25 00:40:32,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:32,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:32,297 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,297 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,297 INFO L745 eck$LassoCheckResult]: Stem: 19622#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 19623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20522#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20523#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21248#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20919#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20920#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19843#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19844#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20321#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20158#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20159#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19907#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19908#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20329#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20513#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20681#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20714#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19923#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19924#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 21139#L1258-2 assume !(0 == ~T1_E~0); 20241#L1263-1 assume !(0 == ~T2_E~0); 20242#L1268-1 assume !(0 == ~T3_E~0); 20559#L1273-1 assume !(0 == ~T4_E~0); 21118#L1278-1 assume !(0 == ~T5_E~0); 20976#L1283-1 assume !(0 == ~T6_E~0); 20977#L1288-1 assume !(0 == ~T7_E~0); 21214#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21203#L1298-1 assume !(0 == ~T9_E~0); 21134#L1303-1 assume !(0 == ~T10_E~0); 19721#L1308-1 assume !(0 == ~T11_E~0); 19661#L1313-1 assume !(0 == ~T12_E~0); 19662#L1318-1 assume !(0 == ~T13_E~0); 19667#L1323-1 assume !(0 == ~E_1~0); 19668#L1328-1 assume !(0 == ~E_2~0); 19853#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20847#L1338-1 assume !(0 == ~E_4~0); 20848#L1343-1 assume !(0 == ~E_5~0); 20953#L1348-1 assume !(0 == ~E_6~0); 21233#L1353-1 assume !(0 == ~E_7~0); 20582#L1358-1 assume !(0 == ~E_8~0); 20583#L1363-1 assume !(0 == ~E_9~0); 20869#L1368-1 assume !(0 == ~E_10~0); 19515#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19516#L1378-1 assume !(0 == ~E_12~0); 19796#L1383-1 assume !(0 == ~E_13~0); 19797#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20587#L607 assume 1 == ~m_pc~0; 20588#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19871#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20384#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20385#L1560 assume !(0 != activate_threads_~tmp~1#1); 20494#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19682#L626 assume !(1 == ~t1_pc~0); 19683#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19964#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19965#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20855#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19590#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19591#L645 assume 1 == ~t2_pc~0; 19698#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19655#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19764#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19765#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20468#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20469#L664 assume 1 == ~t3_pc~0; 21231#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19449#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19450#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20113#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 20114#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21147#L683 assume !(1 == ~t4_pc~0); 20698#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20652#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19473#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19474#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20805#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20408#L702 assume 1 == ~t5_pc~0; 20409#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20344#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20800#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21137#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 21045#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19485#L721 assume !(1 == ~t6_pc~0); 19466#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19467#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19614#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19749#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 20129#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20745#L740 assume 1 == ~t7_pc~0; 19531#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19366#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19367#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19356#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19357#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20053#L759 assume !(1 == ~t8_pc~0); 20054#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20085#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21191#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20930#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20931#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21213#L778 assume 1 == ~t9_pc~0; 21103#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19514#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19819#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19392#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19393#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19694#L797 assume !(1 == ~t10_pc~0); 19695#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19829#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21080#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20237#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20238#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20539#L816 assume 1 == ~t11_pc~0; 19427#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19428#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20373#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20135#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 20136#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20680#L835 assume 1 == ~t12_pc~0; 20554#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19578#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19417#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19418#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20293#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20294#L854 assume !(1 == ~t13_pc~0); 19909#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19910#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19959#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19612#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19613#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21041#L1401 assume !(1 == ~M_E~0); 20122#L1401-2 assume !(1 == ~T1_E~0); 20123#L1406-1 assume !(1 == ~T2_E~0); 20734#L1411-1 assume !(1 == ~T3_E~0); 20735#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20383#L1421-1 assume !(1 == ~T5_E~0); 19905#L1426-1 assume !(1 == ~T6_E~0); 19906#L1431-1 assume !(1 == ~T7_E~0); 19464#L1436-1 assume !(1 == ~T8_E~0); 19465#L1441-1 assume !(1 == ~T9_E~0); 20230#L1446-1 assume !(1 == ~T10_E~0); 20231#L1451-1 assume !(1 == ~T11_E~0); 20949#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20607#L1461-1 assume !(1 == ~T13_E~0); 20151#L1466-1 assume !(1 == ~E_1~0); 20152#L1471-1 assume !(1 == ~E_2~0); 20928#L1476-1 assume !(1 == ~E_3~0); 20929#L1481-1 assume !(1 == ~E_4~0); 21086#L1486-1 assume !(1 == ~E_5~0); 19734#L1491-1 assume !(1 == ~E_6~0); 19402#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19403#L1501-1 assume !(1 == ~E_8~0); 20226#L1506-1 assume !(1 == ~E_9~0); 20227#L1511-1 assume !(1 == ~E_10~0); 20181#L1516-1 assume !(1 == ~E_11~0); 19354#L1521-1 assume !(1 == ~E_12~0); 19355#L1526-1 assume !(1 == ~E_13~0); 19401#L1531-1 assume { :end_inline_reset_delta_events } true; 19931#L1892-2 [2024-10-25 00:40:32,298 INFO L747 eck$LassoCheckResult]: Loop: 19931#L1892-2 assume !false; 20994#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21247#L1233-1 assume !false; 21174#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20495#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20475#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21023#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19443#L1046 assume !(0 != eval_~tmp~0#1); 19445#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19976#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19977#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21230#L1258-5 assume !(0 == ~T1_E~0); 19602#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19603#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21222#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21226#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21227#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19834#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19835#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20991#L1298-3 assume !(0 == ~T9_E~0); 20992#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21154#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20990#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20479#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19604#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19605#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21078#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19745#L1338-3 assume !(0 == ~E_4~0); 19746#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20905#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21083#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21084#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20424#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19966#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19967#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20765#L1378-3 assume !(0 == ~E_12~0); 20766#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20946#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20947#L607-42 assume 1 == ~m_pc~0; 20564#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20274#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20106#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19986#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19987#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20540#L626-42 assume 1 == ~t1_pc~0; 20077#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20078#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21178#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20963#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19637#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19638#L645-42 assume !(1 == ~t2_pc~0); 20883#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20884#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20422#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19854#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19374#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19375#L664-42 assume !(1 == ~t3_pc~0); 19890#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19891#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20824#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20712#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20713#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20876#L683-42 assume 1 == ~t4_pc~0; 21239#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20591#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20719#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20879#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21144#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20985#L702-42 assume !(1 == ~t5_pc~0); 20067#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 20068#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20376#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20489#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19386#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19387#L721-42 assume 1 == ~t6_pc~0; 19526#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19547#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19725#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19726#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20207#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20041#L740-42 assume !(1 == ~t7_pc~0); 19760#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19761#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20337#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20190#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 20191#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20462#L759-42 assume 1 == ~t8_pc~0; 20313#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20247#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20248#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20322#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20323#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20413#L778-42 assume 1 == ~t9_pc~0; 20259#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20261#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20684#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20592#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20593#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20647#L797-42 assume 1 == ~t10_pc~0; 19768#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19769#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20665#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20666#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20685#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20686#L816-42 assume 1 == ~t11_pc~0; 19346#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19347#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21184#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20234#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19945#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19946#L835-42 assume 1 == ~t12_pc~0; 20372#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20271#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20465#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20466#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21044#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20822#L854-42 assume 1 == ~t13_pc~0; 20823#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 19867#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20033#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20034#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20147#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20148#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20939#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19697#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19573#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19574#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20197#L1421-3 assume !(1 == ~T5_E~0); 20198#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19739#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19740#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19358#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19359#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20967#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20285#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19913#L1461-3 assume !(1 == ~T13_E~0); 19914#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21224#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19855#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19856#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20279#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19883#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19884#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20319#L1501-3 assume !(1 == ~E_8~0); 20320#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20761#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20749#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20750#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20427#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20428#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20843#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19672#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19719#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19720#L1911 assume !(0 == start_simulation_~tmp~3#1); 20251#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20782#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19810#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19396#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19397#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19520#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20283#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21097#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19931#L1892-2 [2024-10-25 00:40:32,299 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,299 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2024-10-25 00:40:32,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850787949] [2024-10-25 00:40:32,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,361 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850787949] [2024-10-25 00:40:32,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [850787949] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,362 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,362 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893670932] [2024-10-25 00:40:32,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,362 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:32,363 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,363 INFO L85 PathProgramCache]: Analyzing trace with hash 289791039, now seen corresponding path program 1 times [2024-10-25 00:40:32,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,363 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138571564] [2024-10-25 00:40:32,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138571564] [2024-10-25 00:40:32,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1138571564] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2002696049] [2024-10-25 00:40:32,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,430 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:32,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:32,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:32,431 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:32,431 INFO L87 Difference]: Start difference. First operand 1928 states and 2845 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:32,462 INFO L93 Difference]: Finished difference Result 1928 states and 2844 transitions. [2024-10-25 00:40:32,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2844 transitions. [2024-10-25 00:40:32,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,476 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2844 transitions. [2024-10-25 00:40:32,477 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:32,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:32,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2844 transitions. [2024-10-25 00:40:32,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:32,480 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2844 transitions. [2024-10-25 00:40:32,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2844 transitions. [2024-10-25 00:40:32,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:32,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4751037344398341) internal successors, (2844), 1927 states have internal predecessors, (2844), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2844 transitions. [2024-10-25 00:40:32,508 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2844 transitions. [2024-10-25 00:40:32,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:32,509 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2844 transitions. [2024-10-25 00:40:32,509 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-25 00:40:32,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2844 transitions. [2024-10-25 00:40:32,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:32,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:32,518 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,518 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,519 INFO L745 eck$LassoCheckResult]: Stem: 23485#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23486#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25111#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24782#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24783#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23706#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23707#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24184#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24021#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 24022#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23770#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23771#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24192#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24376#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24544#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24577#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23786#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23787#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 25002#L1258-2 assume !(0 == ~T1_E~0); 24104#L1263-1 assume !(0 == ~T2_E~0); 24105#L1268-1 assume !(0 == ~T3_E~0); 24422#L1273-1 assume !(0 == ~T4_E~0); 24981#L1278-1 assume !(0 == ~T5_E~0); 24839#L1283-1 assume !(0 == ~T6_E~0); 24840#L1288-1 assume !(0 == ~T7_E~0); 25077#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25066#L1298-1 assume !(0 == ~T9_E~0); 24997#L1303-1 assume !(0 == ~T10_E~0); 23584#L1308-1 assume !(0 == ~T11_E~0); 23524#L1313-1 assume !(0 == ~T12_E~0); 23525#L1318-1 assume !(0 == ~T13_E~0); 23530#L1323-1 assume !(0 == ~E_1~0); 23531#L1328-1 assume !(0 == ~E_2~0); 23716#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24710#L1338-1 assume !(0 == ~E_4~0); 24711#L1343-1 assume !(0 == ~E_5~0); 24816#L1348-1 assume !(0 == ~E_6~0); 25096#L1353-1 assume !(0 == ~E_7~0); 24445#L1358-1 assume !(0 == ~E_8~0); 24446#L1363-1 assume !(0 == ~E_9~0); 24732#L1368-1 assume !(0 == ~E_10~0); 23378#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23379#L1378-1 assume !(0 == ~E_12~0); 23659#L1383-1 assume !(0 == ~E_13~0); 23660#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24450#L607 assume 1 == ~m_pc~0; 24451#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23734#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24247#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24248#L1560 assume !(0 != activate_threads_~tmp~1#1); 24357#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23545#L626 assume !(1 == ~t1_pc~0); 23546#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23827#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23828#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24718#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23453#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23454#L645 assume 1 == ~t2_pc~0; 23561#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23518#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23627#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23628#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24331#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24332#L664 assume 1 == ~t3_pc~0; 25094#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23312#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23313#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23976#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23977#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25010#L683 assume !(1 == ~t4_pc~0); 24561#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24515#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23336#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23337#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24668#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24271#L702 assume 1 == ~t5_pc~0; 24272#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24207#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24663#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25000#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24908#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23348#L721 assume !(1 == ~t6_pc~0); 23329#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23330#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23477#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23612#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23992#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24608#L740 assume 1 == ~t7_pc~0; 23394#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23229#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23230#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23219#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23220#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23916#L759 assume !(1 == ~t8_pc~0); 23917#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23948#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25054#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24793#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24794#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25076#L778 assume 1 == ~t9_pc~0; 24966#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23377#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23682#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23255#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23256#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23557#L797 assume !(1 == ~t10_pc~0); 23558#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23692#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24943#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24100#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 24101#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24402#L816 assume 1 == ~t11_pc~0; 23290#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23291#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24236#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23998#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23999#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24543#L835 assume 1 == ~t12_pc~0; 24417#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23441#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23280#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23281#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 24156#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24157#L854 assume !(1 == ~t13_pc~0); 23772#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23773#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23822#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23475#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23476#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24904#L1401 assume !(1 == ~M_E~0); 23985#L1401-2 assume !(1 == ~T1_E~0); 23986#L1406-1 assume !(1 == ~T2_E~0); 24597#L1411-1 assume !(1 == ~T3_E~0); 24598#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24246#L1421-1 assume !(1 == ~T5_E~0); 23768#L1426-1 assume !(1 == ~T6_E~0); 23769#L1431-1 assume !(1 == ~T7_E~0); 23327#L1436-1 assume !(1 == ~T8_E~0); 23328#L1441-1 assume !(1 == ~T9_E~0); 24093#L1446-1 assume !(1 == ~T10_E~0); 24094#L1451-1 assume !(1 == ~T11_E~0); 24812#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24470#L1461-1 assume !(1 == ~T13_E~0); 24014#L1466-1 assume !(1 == ~E_1~0); 24015#L1471-1 assume !(1 == ~E_2~0); 24791#L1476-1 assume !(1 == ~E_3~0); 24792#L1481-1 assume !(1 == ~E_4~0); 24949#L1486-1 assume !(1 == ~E_5~0); 23597#L1491-1 assume !(1 == ~E_6~0); 23265#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23266#L1501-1 assume !(1 == ~E_8~0); 24089#L1506-1 assume !(1 == ~E_9~0); 24090#L1511-1 assume !(1 == ~E_10~0); 24044#L1516-1 assume !(1 == ~E_11~0); 23217#L1521-1 assume !(1 == ~E_12~0); 23218#L1526-1 assume !(1 == ~E_13~0); 23264#L1531-1 assume { :end_inline_reset_delta_events } true; 23794#L1892-2 [2024-10-25 00:40:32,520 INFO L747 eck$LassoCheckResult]: Loop: 23794#L1892-2 assume !false; 24857#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25110#L1233-1 assume !false; 25037#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24358#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24338#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24886#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23306#L1046 assume !(0 != eval_~tmp~0#1); 23308#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23839#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23840#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25093#L1258-5 assume !(0 == ~T1_E~0); 23465#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23466#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25085#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25089#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25090#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23697#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23698#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24854#L1298-3 assume !(0 == ~T9_E~0); 24855#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25017#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24853#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24342#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23467#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23468#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24941#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23608#L1338-3 assume !(0 == ~E_4~0); 23609#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24768#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24946#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24947#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24287#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23829#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23830#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24628#L1378-3 assume !(0 == ~E_12~0); 24629#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24809#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24810#L607-42 assume 1 == ~m_pc~0; 24427#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24137#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23969#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23849#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23850#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24403#L626-42 assume 1 == ~t1_pc~0; 23940#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23941#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25041#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24826#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23500#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23501#L645-42 assume 1 == ~t2_pc~0; 25009#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24747#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24285#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23717#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23237#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23238#L664-42 assume 1 == ~t3_pc~0; 24050#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23754#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24687#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24575#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24576#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24739#L683-42 assume !(1 == ~t4_pc~0); 24453#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24454#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24582#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24742#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25007#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24848#L702-42 assume !(1 == ~t5_pc~0); 23930#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 23931#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24239#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24352#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23249#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23250#L721-42 assume 1 == ~t6_pc~0; 23389#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23410#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23588#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23589#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24070#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23904#L740-42 assume 1 == ~t7_pc~0; 23905#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23624#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24200#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24053#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 24054#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24325#L759-42 assume 1 == ~t8_pc~0; 24176#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24110#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24111#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24185#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24186#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24276#L778-42 assume 1 == ~t9_pc~0; 24122#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24124#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24547#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24455#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24456#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24510#L797-42 assume !(1 == ~t10_pc~0); 23633#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 23632#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24528#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24529#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24548#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24549#L816-42 assume 1 == ~t11_pc~0; 23209#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23210#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25047#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24097#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23808#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23809#L835-42 assume !(1 == ~t12_pc~0); 24133#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 24134#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24328#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24329#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24907#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24685#L854-42 assume !(1 == ~t13_pc~0); 23729#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 23730#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23896#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23897#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 24010#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24011#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24802#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23560#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23436#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23437#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24060#L1421-3 assume !(1 == ~T5_E~0); 24061#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23602#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23603#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23221#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23222#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24830#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24148#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23776#L1461-3 assume !(1 == ~T13_E~0); 23777#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25087#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23718#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23719#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24142#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23746#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23747#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24182#L1501-3 assume !(1 == ~E_8~0); 24183#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24624#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24612#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24613#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24290#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24291#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24706#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23535#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23582#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23583#L1911 assume !(0 == start_simulation_~tmp~3#1); 24114#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24645#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23673#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23259#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23260#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23383#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24146#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24960#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23794#L1892-2 [2024-10-25 00:40:32,521 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2024-10-25 00:40:32,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238783314] [2024-10-25 00:40:32,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,566 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238783314] [2024-10-25 00:40:32,566 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238783314] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,566 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,566 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699450706] [2024-10-25 00:40:32,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,567 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:32,567 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,567 INFO L85 PathProgramCache]: Analyzing trace with hash -1357039586, now seen corresponding path program 1 times [2024-10-25 00:40:32,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,567 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288158574] [2024-10-25 00:40:32,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288158574] [2024-10-25 00:40:32,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [288158574] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,616 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686827301] [2024-10-25 00:40:32,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,617 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:32,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:32,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:32,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:32,617 INFO L87 Difference]: Start difference. First operand 1928 states and 2844 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:32,643 INFO L93 Difference]: Finished difference Result 1928 states and 2843 transitions. [2024-10-25 00:40:32,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2843 transitions. [2024-10-25 00:40:32,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,654 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2843 transitions. [2024-10-25 00:40:32,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:32,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:32,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2843 transitions. [2024-10-25 00:40:32,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:32,657 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2843 transitions. [2024-10-25 00:40:32,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2843 transitions. [2024-10-25 00:40:32,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:32,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.474585062240664) internal successors, (2843), 1927 states have internal predecessors, (2843), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2843 transitions. [2024-10-25 00:40:32,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2843 transitions. [2024-10-25 00:40:32,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:32,681 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2843 transitions. [2024-10-25 00:40:32,681 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-25 00:40:32,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2843 transitions. [2024-10-25 00:40:32,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:32,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:32,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,688 INFO L745 eck$LassoCheckResult]: Stem: 27348#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28248#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28249#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28974#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28645#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28646#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27569#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27570#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28047#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27884#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27885#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27633#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27634#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28055#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28239#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28407#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28440#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27649#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27650#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28865#L1258-2 assume !(0 == ~T1_E~0); 27967#L1263-1 assume !(0 == ~T2_E~0); 27968#L1268-1 assume !(0 == ~T3_E~0); 28285#L1273-1 assume !(0 == ~T4_E~0); 28844#L1278-1 assume !(0 == ~T5_E~0); 28702#L1283-1 assume !(0 == ~T6_E~0); 28703#L1288-1 assume !(0 == ~T7_E~0); 28940#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28929#L1298-1 assume !(0 == ~T9_E~0); 28860#L1303-1 assume !(0 == ~T10_E~0); 27447#L1308-1 assume !(0 == ~T11_E~0); 27387#L1313-1 assume !(0 == ~T12_E~0); 27388#L1318-1 assume !(0 == ~T13_E~0); 27393#L1323-1 assume !(0 == ~E_1~0); 27394#L1328-1 assume !(0 == ~E_2~0); 27579#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28573#L1338-1 assume !(0 == ~E_4~0); 28574#L1343-1 assume !(0 == ~E_5~0); 28679#L1348-1 assume !(0 == ~E_6~0); 28959#L1353-1 assume !(0 == ~E_7~0); 28308#L1358-1 assume !(0 == ~E_8~0); 28309#L1363-1 assume !(0 == ~E_9~0); 28595#L1368-1 assume !(0 == ~E_10~0); 27241#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27242#L1378-1 assume !(0 == ~E_12~0); 27522#L1383-1 assume !(0 == ~E_13~0); 27523#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28313#L607 assume 1 == ~m_pc~0; 28314#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27597#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28110#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28111#L1560 assume !(0 != activate_threads_~tmp~1#1); 28220#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27408#L626 assume !(1 == ~t1_pc~0); 27409#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27690#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27691#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28581#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27316#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27317#L645 assume 1 == ~t2_pc~0; 27424#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27381#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27490#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27491#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 28194#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28195#L664 assume 1 == ~t3_pc~0; 28957#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27175#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27176#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27839#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27840#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28873#L683 assume !(1 == ~t4_pc~0); 28424#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28378#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27199#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27200#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28531#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28134#L702 assume 1 == ~t5_pc~0; 28135#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28070#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28526#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28863#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28771#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27211#L721 assume !(1 == ~t6_pc~0); 27192#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27193#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27475#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27855#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28471#L740 assume 1 == ~t7_pc~0; 27257#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27092#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27093#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27082#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 27083#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27779#L759 assume !(1 == ~t8_pc~0); 27780#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27811#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28917#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28656#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28657#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28939#L778 assume 1 == ~t9_pc~0; 28829#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27240#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27545#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27118#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 27119#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27420#L797 assume !(1 == ~t10_pc~0); 27421#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27555#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28806#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27963#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27964#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28265#L816 assume 1 == ~t11_pc~0; 27153#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27154#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28099#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27861#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27862#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28406#L835 assume 1 == ~t12_pc~0; 28280#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27304#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27143#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27144#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 28019#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28020#L854 assume !(1 == ~t13_pc~0); 27635#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27636#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27685#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27338#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27339#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28767#L1401 assume !(1 == ~M_E~0); 27848#L1401-2 assume !(1 == ~T1_E~0); 27849#L1406-1 assume !(1 == ~T2_E~0); 28460#L1411-1 assume !(1 == ~T3_E~0); 28461#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28109#L1421-1 assume !(1 == ~T5_E~0); 27631#L1426-1 assume !(1 == ~T6_E~0); 27632#L1431-1 assume !(1 == ~T7_E~0); 27190#L1436-1 assume !(1 == ~T8_E~0); 27191#L1441-1 assume !(1 == ~T9_E~0); 27956#L1446-1 assume !(1 == ~T10_E~0); 27957#L1451-1 assume !(1 == ~T11_E~0); 28675#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28333#L1461-1 assume !(1 == ~T13_E~0); 27877#L1466-1 assume !(1 == ~E_1~0); 27878#L1471-1 assume !(1 == ~E_2~0); 28654#L1476-1 assume !(1 == ~E_3~0); 28655#L1481-1 assume !(1 == ~E_4~0); 28812#L1486-1 assume !(1 == ~E_5~0); 27460#L1491-1 assume !(1 == ~E_6~0); 27128#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27129#L1501-1 assume !(1 == ~E_8~0); 27952#L1506-1 assume !(1 == ~E_9~0); 27953#L1511-1 assume !(1 == ~E_10~0); 27907#L1516-1 assume !(1 == ~E_11~0); 27080#L1521-1 assume !(1 == ~E_12~0); 27081#L1526-1 assume !(1 == ~E_13~0); 27127#L1531-1 assume { :end_inline_reset_delta_events } true; 27657#L1892-2 [2024-10-25 00:40:32,688 INFO L747 eck$LassoCheckResult]: Loop: 27657#L1892-2 assume !false; 28720#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28973#L1233-1 assume !false; 28900#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28221#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28201#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28749#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27169#L1046 assume !(0 != eval_~tmp~0#1); 27171#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27703#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28956#L1258-5 assume !(0 == ~T1_E~0); 27328#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27329#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28948#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28952#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28953#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27560#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27561#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28717#L1298-3 assume !(0 == ~T9_E~0); 28718#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28880#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28716#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28205#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27330#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27331#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28804#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27471#L1338-3 assume !(0 == ~E_4~0); 27472#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28631#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28809#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28810#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28150#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27692#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27693#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28491#L1378-3 assume !(0 == ~E_12~0); 28492#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28672#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28673#L607-42 assume 1 == ~m_pc~0; 28290#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28000#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27832#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27712#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27713#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28266#L626-42 assume 1 == ~t1_pc~0; 27803#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27804#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28904#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28689#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27363#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27364#L645-42 assume !(1 == ~t2_pc~0); 28609#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 28610#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28148#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27580#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27100#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27101#L664-42 assume !(1 == ~t3_pc~0); 27616#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 27617#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28550#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28438#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28439#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28602#L683-42 assume 1 == ~t4_pc~0; 28965#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28317#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28445#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28605#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28870#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28711#L702-42 assume !(1 == ~t5_pc~0); 27793#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 27794#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28102#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28215#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27112#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27113#L721-42 assume 1 == ~t6_pc~0; 27252#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27273#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27451#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27452#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27933#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27767#L740-42 assume 1 == ~t7_pc~0; 27768#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27487#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28063#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27916#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 27917#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28188#L759-42 assume 1 == ~t8_pc~0; 28039#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27973#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27974#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28048#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28049#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28139#L778-42 assume 1 == ~t9_pc~0; 27985#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27987#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28410#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28318#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28319#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28373#L797-42 assume 1 == ~t10_pc~0; 27494#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27495#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28391#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28392#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28411#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28412#L816-42 assume 1 == ~t11_pc~0; 27072#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27073#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28910#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27960#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27671#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27672#L835-42 assume 1 == ~t12_pc~0; 28098#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27997#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28191#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28192#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28770#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28548#L854-42 assume 1 == ~t13_pc~0; 28549#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27593#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27759#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27760#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27873#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27874#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28665#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27423#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27299#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27300#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27923#L1421-3 assume !(1 == ~T5_E~0); 27924#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27465#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27466#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27084#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27085#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28693#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28011#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27639#L1461-3 assume !(1 == ~T13_E~0); 27640#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28950#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27581#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27582#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28005#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27609#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27610#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28045#L1501-3 assume !(1 == ~E_8~0); 28046#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28487#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28475#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28476#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28153#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 28154#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28569#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27398#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 27445#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27446#L1911 assume !(0 == start_simulation_~tmp~3#1); 27977#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28508#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27536#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 27122#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27123#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27246#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28009#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28823#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27657#L1892-2 [2024-10-25 00:40:32,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,689 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2024-10-25 00:40:32,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363346466] [2024-10-25 00:40:32,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,751 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363346466] [2024-10-25 00:40:32,751 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [363346466] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,751 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,752 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705812417] [2024-10-25 00:40:32,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,752 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:32,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,752 INFO L85 PathProgramCache]: Analyzing trace with hash -2020347552, now seen corresponding path program 1 times [2024-10-25 00:40:32,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63690190] [2024-10-25 00:40:32,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,798 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63690190] [2024-10-25 00:40:32,800 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63690190] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,800 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,800 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [263789460] [2024-10-25 00:40:32,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,801 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:32,801 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:32,801 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:32,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:32,801 INFO L87 Difference]: Start difference. First operand 1928 states and 2843 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:32,827 INFO L93 Difference]: Finished difference Result 1928 states and 2842 transitions. [2024-10-25 00:40:32,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2842 transitions. [2024-10-25 00:40:32,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2842 transitions. [2024-10-25 00:40:32,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:32,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:32,842 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2842 transitions. [2024-10-25 00:40:32,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:32,847 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2842 transitions. [2024-10-25 00:40:32,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2842 transitions. [2024-10-25 00:40:32,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:32,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4740663900414939) internal successors, (2842), 1927 states have internal predecessors, (2842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2842 transitions. [2024-10-25 00:40:32,869 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2842 transitions. [2024-10-25 00:40:32,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:32,870 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2842 transitions. [2024-10-25 00:40:32,870 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-25 00:40:32,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2842 transitions. [2024-10-25 00:40:32,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:32,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:32,877 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,877 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:32,878 INFO L745 eck$LassoCheckResult]: Stem: 31211#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 32111#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32112#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32837#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32508#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32509#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31432#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31433#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31910#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31747#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31748#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31496#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31497#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31918#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32102#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32270#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32303#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31512#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31513#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32728#L1258-2 assume !(0 == ~T1_E~0); 31830#L1263-1 assume !(0 == ~T2_E~0); 31831#L1268-1 assume !(0 == ~T3_E~0); 32148#L1273-1 assume !(0 == ~T4_E~0); 32707#L1278-1 assume !(0 == ~T5_E~0); 32565#L1283-1 assume !(0 == ~T6_E~0); 32566#L1288-1 assume !(0 == ~T7_E~0); 32803#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32792#L1298-1 assume !(0 == ~T9_E~0); 32723#L1303-1 assume !(0 == ~T10_E~0); 31310#L1308-1 assume !(0 == ~T11_E~0); 31250#L1313-1 assume !(0 == ~T12_E~0); 31251#L1318-1 assume !(0 == ~T13_E~0); 31256#L1323-1 assume !(0 == ~E_1~0); 31257#L1328-1 assume !(0 == ~E_2~0); 31442#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32436#L1338-1 assume !(0 == ~E_4~0); 32437#L1343-1 assume !(0 == ~E_5~0); 32542#L1348-1 assume !(0 == ~E_6~0); 32822#L1353-1 assume !(0 == ~E_7~0); 32171#L1358-1 assume !(0 == ~E_8~0); 32172#L1363-1 assume !(0 == ~E_9~0); 32458#L1368-1 assume !(0 == ~E_10~0); 31104#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 31105#L1378-1 assume !(0 == ~E_12~0); 31385#L1383-1 assume !(0 == ~E_13~0); 31386#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32176#L607 assume 1 == ~m_pc~0; 32177#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31460#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31973#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31974#L1560 assume !(0 != activate_threads_~tmp~1#1); 32083#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31271#L626 assume !(1 == ~t1_pc~0); 31272#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31553#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31554#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32444#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 31179#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31180#L645 assume 1 == ~t2_pc~0; 31287#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31244#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31353#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31354#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 32057#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32058#L664 assume 1 == ~t3_pc~0; 32820#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31038#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31039#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31702#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31703#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32736#L683 assume !(1 == ~t4_pc~0); 32287#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32241#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31062#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31063#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32394#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31997#L702 assume 1 == ~t5_pc~0; 31998#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31933#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32389#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32726#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32634#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31074#L721 assume !(1 == ~t6_pc~0); 31055#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31056#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31203#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31338#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31718#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32334#L740 assume 1 == ~t7_pc~0; 31120#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30955#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30956#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30945#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30946#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31642#L759 assume !(1 == ~t8_pc~0); 31643#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31674#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32780#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32519#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32520#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32802#L778 assume 1 == ~t9_pc~0; 32692#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31103#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31408#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30981#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30982#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31283#L797 assume !(1 == ~t10_pc~0); 31284#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31418#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32669#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31826#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31827#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32128#L816 assume 1 == ~t11_pc~0; 31016#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31017#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31962#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31724#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31725#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32269#L835 assume 1 == ~t12_pc~0; 32143#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31167#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31006#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31007#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31882#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31883#L854 assume !(1 == ~t13_pc~0); 31498#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31499#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31548#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31201#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31202#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32630#L1401 assume !(1 == ~M_E~0); 31711#L1401-2 assume !(1 == ~T1_E~0); 31712#L1406-1 assume !(1 == ~T2_E~0); 32323#L1411-1 assume !(1 == ~T3_E~0); 32324#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31972#L1421-1 assume !(1 == ~T5_E~0); 31494#L1426-1 assume !(1 == ~T6_E~0); 31495#L1431-1 assume !(1 == ~T7_E~0); 31053#L1436-1 assume !(1 == ~T8_E~0); 31054#L1441-1 assume !(1 == ~T9_E~0); 31819#L1446-1 assume !(1 == ~T10_E~0); 31820#L1451-1 assume !(1 == ~T11_E~0); 32538#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32196#L1461-1 assume !(1 == ~T13_E~0); 31740#L1466-1 assume !(1 == ~E_1~0); 31741#L1471-1 assume !(1 == ~E_2~0); 32517#L1476-1 assume !(1 == ~E_3~0); 32518#L1481-1 assume !(1 == ~E_4~0); 32675#L1486-1 assume !(1 == ~E_5~0); 31323#L1491-1 assume !(1 == ~E_6~0); 30991#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30992#L1501-1 assume !(1 == ~E_8~0); 31815#L1506-1 assume !(1 == ~E_9~0); 31816#L1511-1 assume !(1 == ~E_10~0); 31770#L1516-1 assume !(1 == ~E_11~0); 30943#L1521-1 assume !(1 == ~E_12~0); 30944#L1526-1 assume !(1 == ~E_13~0); 30990#L1531-1 assume { :end_inline_reset_delta_events } true; 31520#L1892-2 [2024-10-25 00:40:32,878 INFO L747 eck$LassoCheckResult]: Loop: 31520#L1892-2 assume !false; 32583#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32836#L1233-1 assume !false; 32763#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32084#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32064#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32612#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31032#L1046 assume !(0 != eval_~tmp~0#1); 31034#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31565#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31566#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32819#L1258-5 assume !(0 == ~T1_E~0); 31191#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31192#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32811#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32815#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32816#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31423#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31424#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32580#L1298-3 assume !(0 == ~T9_E~0); 32581#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32743#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32579#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32068#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 31193#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31194#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32667#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31334#L1338-3 assume !(0 == ~E_4~0); 31335#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32494#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32672#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32673#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32013#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31555#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31556#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32354#L1378-3 assume !(0 == ~E_12~0); 32355#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32535#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32536#L607-42 assume 1 == ~m_pc~0; 32153#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31863#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31695#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31575#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31576#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32129#L626-42 assume 1 == ~t1_pc~0; 31666#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31667#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32767#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32552#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31226#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31227#L645-42 assume !(1 == ~t2_pc~0); 32472#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32473#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32011#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31443#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30963#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30964#L664-42 assume 1 == ~t3_pc~0; 31776#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31480#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32413#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32301#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32302#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32465#L683-42 assume !(1 == ~t4_pc~0); 32179#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32180#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32308#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32468#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32733#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32574#L702-42 assume !(1 == ~t5_pc~0); 31656#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 31657#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31965#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32078#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30975#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30976#L721-42 assume 1 == ~t6_pc~0; 31115#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31136#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31314#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31315#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31796#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31630#L740-42 assume !(1 == ~t7_pc~0); 31349#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31350#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31926#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31779#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 31780#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32051#L759-42 assume 1 == ~t8_pc~0; 31902#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31836#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31837#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31911#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31912#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32002#L778-42 assume 1 == ~t9_pc~0; 31848#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31850#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32273#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32181#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32182#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32236#L797-42 assume 1 == ~t10_pc~0; 31357#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31358#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32254#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32255#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32274#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32275#L816-42 assume 1 == ~t11_pc~0; 30935#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30936#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32773#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31823#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31534#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31535#L835-42 assume !(1 == ~t12_pc~0); 31859#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 31860#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32054#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32055#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32633#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32411#L854-42 assume 1 == ~t13_pc~0; 32412#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 31456#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31622#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31623#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31736#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31737#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32528#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31286#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31162#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31163#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31786#L1421-3 assume !(1 == ~T5_E~0); 31787#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31328#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31329#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30947#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30948#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32556#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31874#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31502#L1461-3 assume !(1 == ~T13_E~0); 31503#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32813#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31444#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31445#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31868#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31472#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31473#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31908#L1501-3 assume !(1 == ~E_8~0); 31909#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32350#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32338#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32339#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32016#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 32017#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32432#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31261#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31308#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31309#L1911 assume !(0 == start_simulation_~tmp~3#1); 31840#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32371#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31399#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30985#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30986#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31109#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31872#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32686#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31520#L1892-2 [2024-10-25 00:40:32,879 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,879 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2024-10-25 00:40:32,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885744131] [2024-10-25 00:40:32,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885744131] [2024-10-25 00:40:32,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885744131] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562223287] [2024-10-25 00:40:32,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,911 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:32,912 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:32,912 INFO L85 PathProgramCache]: Analyzing trace with hash -1736156514, now seen corresponding path program 1 times [2024-10-25 00:40:32,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:32,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936694447] [2024-10-25 00:40:32,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:32,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:32,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:32,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:32,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:32,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936694447] [2024-10-25 00:40:32,962 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936694447] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:32,962 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:32,962 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:32,962 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648821073] [2024-10-25 00:40:32,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:32,962 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:32,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:32,963 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:32,963 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:32,963 INFO L87 Difference]: Start difference. First operand 1928 states and 2842 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:32,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:32,987 INFO L93 Difference]: Finished difference Result 1928 states and 2841 transitions. [2024-10-25 00:40:32,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2841 transitions. [2024-10-25 00:40:32,992 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:32,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2841 transitions. [2024-10-25 00:40:32,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:33,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:33,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2841 transitions. [2024-10-25 00:40:33,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:33,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2841 transitions. [2024-10-25 00:40:33,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2841 transitions. [2024-10-25 00:40:33,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:33,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4735477178423237) internal successors, (2841), 1927 states have internal predecessors, (2841), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:33,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2841 transitions. [2024-10-25 00:40:33,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2841 transitions. [2024-10-25 00:40:33,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:33,026 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2841 transitions. [2024-10-25 00:40:33,026 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-25 00:40:33,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2841 transitions. [2024-10-25 00:40:33,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:33,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:33,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:33,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,033 INFO L745 eck$LassoCheckResult]: Stem: 35074#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35075#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36700#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36371#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36372#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35295#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35296#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35773#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35610#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35611#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35359#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35360#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35781#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35965#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36133#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36166#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35375#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35376#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36591#L1258-2 assume !(0 == ~T1_E~0); 35693#L1263-1 assume !(0 == ~T2_E~0); 35694#L1268-1 assume !(0 == ~T3_E~0); 36011#L1273-1 assume !(0 == ~T4_E~0); 36570#L1278-1 assume !(0 == ~T5_E~0); 36428#L1283-1 assume !(0 == ~T6_E~0); 36429#L1288-1 assume !(0 == ~T7_E~0); 36666#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36655#L1298-1 assume !(0 == ~T9_E~0); 36586#L1303-1 assume !(0 == ~T10_E~0); 35173#L1308-1 assume !(0 == ~T11_E~0); 35113#L1313-1 assume !(0 == ~T12_E~0); 35114#L1318-1 assume !(0 == ~T13_E~0); 35119#L1323-1 assume !(0 == ~E_1~0); 35120#L1328-1 assume !(0 == ~E_2~0); 35305#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36299#L1338-1 assume !(0 == ~E_4~0); 36300#L1343-1 assume !(0 == ~E_5~0); 36405#L1348-1 assume !(0 == ~E_6~0); 36685#L1353-1 assume !(0 == ~E_7~0); 36034#L1358-1 assume !(0 == ~E_8~0); 36035#L1363-1 assume !(0 == ~E_9~0); 36321#L1368-1 assume !(0 == ~E_10~0); 34967#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34968#L1378-1 assume !(0 == ~E_12~0); 35248#L1383-1 assume !(0 == ~E_13~0); 35249#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36039#L607 assume 1 == ~m_pc~0; 36040#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35323#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35836#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35837#L1560 assume !(0 != activate_threads_~tmp~1#1); 35946#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35134#L626 assume !(1 == ~t1_pc~0); 35135#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35416#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35417#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36307#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 35042#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35043#L645 assume 1 == ~t2_pc~0; 35150#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35107#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35216#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35217#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35920#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35921#L664 assume 1 == ~t3_pc~0; 36683#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34901#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34902#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35565#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35566#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36599#L683 assume !(1 == ~t4_pc~0); 36150#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36104#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34925#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34926#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36257#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35860#L702 assume 1 == ~t5_pc~0; 35861#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35796#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36252#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36589#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36497#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34937#L721 assume !(1 == ~t6_pc~0); 34918#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34919#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35066#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35201#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35581#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36197#L740 assume 1 == ~t7_pc~0; 34983#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34818#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34819#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34808#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34809#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35505#L759 assume !(1 == ~t8_pc~0); 35506#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35537#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36643#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36382#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36383#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36665#L778 assume 1 == ~t9_pc~0; 36555#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34966#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35271#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34844#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34845#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35146#L797 assume !(1 == ~t10_pc~0); 35147#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35281#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36532#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35689#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35690#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35991#L816 assume 1 == ~t11_pc~0; 34879#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34880#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35825#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35587#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35588#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36132#L835 assume 1 == ~t12_pc~0; 36006#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35030#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34869#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34870#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35745#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35746#L854 assume !(1 == ~t13_pc~0); 35361#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35362#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35411#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35064#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35065#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36493#L1401 assume !(1 == ~M_E~0); 35574#L1401-2 assume !(1 == ~T1_E~0); 35575#L1406-1 assume !(1 == ~T2_E~0); 36186#L1411-1 assume !(1 == ~T3_E~0); 36187#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35835#L1421-1 assume !(1 == ~T5_E~0); 35357#L1426-1 assume !(1 == ~T6_E~0); 35358#L1431-1 assume !(1 == ~T7_E~0); 34916#L1436-1 assume !(1 == ~T8_E~0); 34917#L1441-1 assume !(1 == ~T9_E~0); 35682#L1446-1 assume !(1 == ~T10_E~0); 35683#L1451-1 assume !(1 == ~T11_E~0); 36401#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36059#L1461-1 assume !(1 == ~T13_E~0); 35603#L1466-1 assume !(1 == ~E_1~0); 35604#L1471-1 assume !(1 == ~E_2~0); 36380#L1476-1 assume !(1 == ~E_3~0); 36381#L1481-1 assume !(1 == ~E_4~0); 36538#L1486-1 assume !(1 == ~E_5~0); 35186#L1491-1 assume !(1 == ~E_6~0); 34854#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34855#L1501-1 assume !(1 == ~E_8~0); 35678#L1506-1 assume !(1 == ~E_9~0); 35679#L1511-1 assume !(1 == ~E_10~0); 35633#L1516-1 assume !(1 == ~E_11~0); 34806#L1521-1 assume !(1 == ~E_12~0); 34807#L1526-1 assume !(1 == ~E_13~0); 34853#L1531-1 assume { :end_inline_reset_delta_events } true; 35383#L1892-2 [2024-10-25 00:40:33,033 INFO L747 eck$LassoCheckResult]: Loop: 35383#L1892-2 assume !false; 36446#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36699#L1233-1 assume !false; 36626#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35947#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35927#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36475#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34895#L1046 assume !(0 != eval_~tmp~0#1); 34897#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35429#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36682#L1258-5 assume !(0 == ~T1_E~0); 35054#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35055#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36674#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36678#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36679#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35286#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35287#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36443#L1298-3 assume !(0 == ~T9_E~0); 36444#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36606#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36442#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35931#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 35056#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35057#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36530#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35197#L1338-3 assume !(0 == ~E_4~0); 35198#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36357#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36535#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36536#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35876#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35418#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35419#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36217#L1378-3 assume !(0 == ~E_12~0); 36218#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36398#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36399#L607-42 assume 1 == ~m_pc~0; 36016#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35726#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35558#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35438#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35439#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35992#L626-42 assume 1 == ~t1_pc~0; 35529#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35530#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36630#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36415#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35089#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35090#L645-42 assume 1 == ~t2_pc~0; 36598#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36336#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35874#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35306#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34826#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34827#L664-42 assume 1 == ~t3_pc~0; 35639#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35343#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36276#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36164#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36165#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36328#L683-42 assume 1 == ~t4_pc~0; 36691#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36043#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36171#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36331#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36596#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36437#L702-42 assume 1 == ~t5_pc~0; 35908#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35520#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35828#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35941#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34838#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34839#L721-42 assume 1 == ~t6_pc~0; 34978#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34999#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35177#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35178#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35659#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35493#L740-42 assume 1 == ~t7_pc~0; 35494#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35213#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35789#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35642#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 35643#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35914#L759-42 assume 1 == ~t8_pc~0; 35765#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35699#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35700#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35774#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35775#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35865#L778-42 assume !(1 == ~t9_pc~0); 35712#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 35713#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36136#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36044#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36045#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36099#L797-42 assume 1 == ~t10_pc~0; 35220#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35221#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36117#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36118#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36137#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36138#L816-42 assume !(1 == ~t11_pc~0); 34800#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 34799#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36636#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35686#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35397#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35398#L835-42 assume 1 == ~t12_pc~0; 35824#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35723#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35917#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35918#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36496#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36274#L854-42 assume 1 == ~t13_pc~0; 36275#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35319#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35485#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35486#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35599#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35600#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36391#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35149#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35025#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35026#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35649#L1421-3 assume !(1 == ~T5_E~0); 35650#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35191#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35192#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34810#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34811#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36419#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35737#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35365#L1461-3 assume !(1 == ~T13_E~0); 35366#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36676#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35307#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35308#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35731#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35335#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35336#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35771#L1501-3 assume !(1 == ~E_8~0); 35772#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36213#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36201#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36202#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35879#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35880#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36295#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35124#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35171#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35172#L1911 assume !(0 == start_simulation_~tmp~3#1); 35703#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36234#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35262#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34848#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34849#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34972#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35735#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36549#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35383#L1892-2 [2024-10-25 00:40:33,034 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,034 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2024-10-25 00:40:33,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220070163] [2024-10-25 00:40:33,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,073 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220070163] [2024-10-25 00:40:33,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220070163] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,074 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,074 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:33,074 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896665187] [2024-10-25 00:40:33,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,075 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:33,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,075 INFO L85 PathProgramCache]: Analyzing trace with hash 442785217, now seen corresponding path program 1 times [2024-10-25 00:40:33,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437438468] [2024-10-25 00:40:33,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,139 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437438468] [2024-10-25 00:40:33,139 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437438468] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,139 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,139 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:33,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484089413] [2024-10-25 00:40:33,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,139 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:33,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:33,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:33,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:33,140 INFO L87 Difference]: Start difference. First operand 1928 states and 2841 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:33,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:33,165 INFO L93 Difference]: Finished difference Result 1928 states and 2840 transitions. [2024-10-25 00:40:33,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2840 transitions. [2024-10-25 00:40:33,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:33,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2840 transitions. [2024-10-25 00:40:33,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:33,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:33,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2840 transitions. [2024-10-25 00:40:33,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:33,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2840 transitions. [2024-10-25 00:40:33,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2840 transitions. [2024-10-25 00:40:33,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:33,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4730290456431536) internal successors, (2840), 1927 states have internal predecessors, (2840), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:33,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2840 transitions. [2024-10-25 00:40:33,204 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2840 transitions. [2024-10-25 00:40:33,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:33,209 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2840 transitions. [2024-10-25 00:40:33,209 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-25 00:40:33,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2840 transitions. [2024-10-25 00:40:33,215 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:33,215 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:33,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:33,217 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,217 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,217 INFO L745 eck$LassoCheckResult]: Stem: 38937#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 38938#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39838#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39839#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40563#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 40234#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40235#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39158#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39159#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39638#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39473#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39474#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39222#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39223#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39644#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39828#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39996#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40030#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 39238#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39239#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40454#L1258-2 assume !(0 == ~T1_E~0); 39556#L1263-1 assume !(0 == ~T2_E~0); 39557#L1268-1 assume !(0 == ~T3_E~0); 39874#L1273-1 assume !(0 == ~T4_E~0); 40433#L1278-1 assume !(0 == ~T5_E~0); 40291#L1283-1 assume !(0 == ~T6_E~0); 40292#L1288-1 assume !(0 == ~T7_E~0); 40530#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40518#L1298-1 assume !(0 == ~T9_E~0); 40449#L1303-1 assume !(0 == ~T10_E~0); 39036#L1308-1 assume !(0 == ~T11_E~0); 38979#L1313-1 assume !(0 == ~T12_E~0); 38980#L1318-1 assume !(0 == ~T13_E~0); 38984#L1323-1 assume !(0 == ~E_1~0); 38985#L1328-1 assume !(0 == ~E_2~0); 39168#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 40162#L1338-1 assume !(0 == ~E_4~0); 40163#L1343-1 assume !(0 == ~E_5~0); 40268#L1348-1 assume !(0 == ~E_6~0); 40548#L1353-1 assume !(0 == ~E_7~0); 39897#L1358-1 assume !(0 == ~E_8~0); 39898#L1363-1 assume !(0 == ~E_9~0); 40184#L1368-1 assume !(0 == ~E_10~0); 38830#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38831#L1378-1 assume !(0 == ~E_12~0); 39113#L1383-1 assume !(0 == ~E_13~0); 39114#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39902#L607 assume 1 == ~m_pc~0; 39903#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39188#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39702#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39703#L1560 assume !(0 != activate_threads_~tmp~1#1); 39809#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38997#L626 assume !(1 == ~t1_pc~0); 38998#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39281#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39282#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40170#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38906#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38907#L645 assume 1 == ~t2_pc~0; 39015#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38970#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39082#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39783#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39784#L664 assume 1 == ~t3_pc~0; 40546#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38768#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38769#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39428#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39429#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40462#L683 assume !(1 == ~t4_pc~0); 40013#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39967#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38788#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38789#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40120#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39727#L702 assume 1 == ~t5_pc~0; 39728#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39660#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40115#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40452#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40361#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38804#L721 assume !(1 == ~t6_pc~0); 38781#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38782#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38929#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39064#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39444#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40060#L740 assume 1 == ~t7_pc~0; 38846#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38681#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38682#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38671#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38672#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39369#L759 assume !(1 == ~t8_pc~0); 39370#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39400#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40509#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40245#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 40246#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40528#L778 assume 1 == ~t9_pc~0; 40420#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38829#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39134#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38707#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38708#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39010#L797 assume !(1 == ~t10_pc~0); 39011#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39144#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40395#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39552#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39553#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39854#L816 assume 1 == ~t11_pc~0; 38744#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38745#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39690#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39450#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39451#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39995#L835 assume 1 == ~t12_pc~0; 39869#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38893#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38732#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38733#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39608#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39609#L854 assume !(1 == ~t13_pc~0); 39224#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 39225#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39276#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38927#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38928#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40356#L1401 assume !(1 == ~M_E~0); 39437#L1401-2 assume !(1 == ~T1_E~0); 39438#L1406-1 assume !(1 == ~T2_E~0); 40049#L1411-1 assume !(1 == ~T3_E~0); 40050#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39698#L1421-1 assume !(1 == ~T5_E~0); 39220#L1426-1 assume !(1 == ~T6_E~0); 39221#L1431-1 assume !(1 == ~T7_E~0); 38779#L1436-1 assume !(1 == ~T8_E~0); 38780#L1441-1 assume !(1 == ~T9_E~0); 39545#L1446-1 assume !(1 == ~T10_E~0); 39546#L1451-1 assume !(1 == ~T11_E~0); 40264#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39922#L1461-1 assume !(1 == ~T13_E~0); 39466#L1466-1 assume !(1 == ~E_1~0); 39467#L1471-1 assume !(1 == ~E_2~0); 40243#L1476-1 assume !(1 == ~E_3~0); 40244#L1481-1 assume !(1 == ~E_4~0); 40401#L1486-1 assume !(1 == ~E_5~0); 39049#L1491-1 assume !(1 == ~E_6~0); 38717#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38718#L1501-1 assume !(1 == ~E_8~0); 39541#L1506-1 assume !(1 == ~E_9~0); 39542#L1511-1 assume !(1 == ~E_10~0); 39496#L1516-1 assume !(1 == ~E_11~0); 38669#L1521-1 assume !(1 == ~E_12~0); 38670#L1526-1 assume !(1 == ~E_13~0); 38716#L1531-1 assume { :end_inline_reset_delta_events } true; 39246#L1892-2 [2024-10-25 00:40:33,217 INFO L747 eck$LassoCheckResult]: Loop: 39246#L1892-2 assume !false; 40309#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40562#L1233-1 assume !false; 40489#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39810#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39790#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40338#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38758#L1046 assume !(0 != eval_~tmp~0#1); 38760#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39291#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39292#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40545#L1258-5 assume !(0 == ~T1_E~0); 38917#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38918#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40537#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40541#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40542#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39149#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39150#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40306#L1298-3 assume !(0 == ~T9_E~0); 40307#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40469#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40305#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39794#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38919#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38920#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40393#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39060#L1338-3 assume !(0 == ~E_4~0); 39061#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40220#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40398#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40399#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39739#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39279#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39280#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40080#L1378-3 assume !(0 == ~E_12~0); 40081#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 40261#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40262#L607-42 assume 1 == ~m_pc~0; 39879#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39589#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39421#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39301#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39302#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39855#L626-42 assume 1 == ~t1_pc~0; 39392#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39393#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40493#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40278#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38952#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38953#L645-42 assume !(1 == ~t2_pc~0); 40198#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40199#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39737#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39169#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38689#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38690#L664-42 assume !(1 == ~t3_pc~0); 39205#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 39206#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40139#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40027#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40028#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40191#L683-42 assume !(1 == ~t4_pc~0); 39905#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39906#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40034#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40194#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40459#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40300#L702-42 assume !(1 == ~t5_pc~0); 39382#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 39383#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39691#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39804#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38701#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38702#L721-42 assume 1 == ~t6_pc~0; 38841#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38862#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39040#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39041#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39522#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39356#L740-42 assume !(1 == ~t7_pc~0); 39075#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 39076#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39652#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39505#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 39506#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39777#L759-42 assume 1 == ~t8_pc~0; 39628#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39562#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39563#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39636#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39637#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39726#L778-42 assume 1 == ~t9_pc~0; 39574#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39576#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39999#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39907#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39908#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39962#L797-42 assume 1 == ~t10_pc~0; 39083#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39084#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39980#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39981#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40000#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40001#L816-42 assume 1 == ~t11_pc~0; 38661#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38662#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40499#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39549#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39260#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39261#L835-42 assume !(1 == ~t12_pc~0); 39585#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39586#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39780#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39781#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40359#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 40137#L854-42 assume 1 == ~t13_pc~0; 40138#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 39182#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39348#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39349#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39462#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39463#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40254#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39009#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38888#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38889#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39512#L1421-3 assume !(1 == ~T5_E~0); 39513#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39054#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39055#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38673#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38674#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40282#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39600#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39228#L1461-3 assume !(1 == ~T13_E~0); 39229#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40539#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39170#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39171#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39594#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39198#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39199#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39634#L1501-3 assume !(1 == ~E_8~0); 39635#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40076#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40064#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40065#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39742#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39743#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40158#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38987#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39034#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39035#L1911 assume !(0 == start_simulation_~tmp~3#1); 39566#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40097#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39125#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38712#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38835#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39598#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40412#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 39246#L1892-2 [2024-10-25 00:40:33,217 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,218 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2024-10-25 00:40:33,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858175972] [2024-10-25 00:40:33,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1858175972] [2024-10-25 00:40:33,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1858175972] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:33,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1263659505] [2024-10-25 00:40:33,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,254 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:33,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,254 INFO L85 PathProgramCache]: Analyzing trace with hash -1414834051, now seen corresponding path program 2 times [2024-10-25 00:40:33,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493847554] [2024-10-25 00:40:33,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,303 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [493847554] [2024-10-25 00:40:33,303 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [493847554] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,303 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,303 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:33,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108399597] [2024-10-25 00:40:33,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,303 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:33,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:33,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:33,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:33,306 INFO L87 Difference]: Start difference. First operand 1928 states and 2840 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:33,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:33,330 INFO L93 Difference]: Finished difference Result 1928 states and 2839 transitions. [2024-10-25 00:40:33,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2839 transitions. [2024-10-25 00:40:33,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:33,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2839 transitions. [2024-10-25 00:40:33,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:33,340 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:33,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2839 transitions. [2024-10-25 00:40:33,342 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:33,342 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2839 transitions. [2024-10-25 00:40:33,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2839 transitions. [2024-10-25 00:40:33,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:33,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4725103734439835) internal successors, (2839), 1927 states have internal predecessors, (2839), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:33,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2839 transitions. [2024-10-25 00:40:33,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2839 transitions. [2024-10-25 00:40:33,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:33,367 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2839 transitions. [2024-10-25 00:40:33,367 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-25 00:40:33,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2839 transitions. [2024-10-25 00:40:33,371 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:33,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:33,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:33,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,373 INFO L745 eck$LassoCheckResult]: Stem: 42800#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 42801#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 43701#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43702#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44426#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 44097#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44098#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43021#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43022#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43501#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43336#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43337#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43085#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43086#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43507#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43691#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43859#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43893#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 43101#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43102#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 44317#L1258-2 assume !(0 == ~T1_E~0); 43419#L1263-1 assume !(0 == ~T2_E~0); 43420#L1268-1 assume !(0 == ~T3_E~0); 43737#L1273-1 assume !(0 == ~T4_E~0); 44296#L1278-1 assume !(0 == ~T5_E~0); 44154#L1283-1 assume !(0 == ~T6_E~0); 44155#L1288-1 assume !(0 == ~T7_E~0); 44393#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44381#L1298-1 assume !(0 == ~T9_E~0); 44312#L1303-1 assume !(0 == ~T10_E~0); 42899#L1308-1 assume !(0 == ~T11_E~0); 42839#L1313-1 assume !(0 == ~T12_E~0); 42840#L1318-1 assume !(0 == ~T13_E~0); 42847#L1323-1 assume !(0 == ~E_1~0); 42848#L1328-1 assume !(0 == ~E_2~0); 43031#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 44025#L1338-1 assume !(0 == ~E_4~0); 44026#L1343-1 assume !(0 == ~E_5~0); 44131#L1348-1 assume !(0 == ~E_6~0); 44411#L1353-1 assume !(0 == ~E_7~0); 43760#L1358-1 assume !(0 == ~E_8~0); 43761#L1363-1 assume !(0 == ~E_9~0); 44047#L1368-1 assume !(0 == ~E_10~0); 42693#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42694#L1378-1 assume !(0 == ~E_12~0); 42976#L1383-1 assume !(0 == ~E_13~0); 42977#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43765#L607 assume 1 == ~m_pc~0; 43766#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43051#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43565#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43566#L1560 assume !(0 != activate_threads_~tmp~1#1); 43672#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42860#L626 assume !(1 == ~t1_pc~0); 42861#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43144#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43145#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44033#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42769#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42770#L645 assume 1 == ~t2_pc~0; 42878#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42833#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42944#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42945#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43646#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43647#L664 assume 1 == ~t3_pc~0; 44409#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42631#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42632#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43291#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 43292#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44325#L683 assume !(1 == ~t4_pc~0); 43876#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43830#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42651#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42652#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43983#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43590#L702 assume 1 == ~t5_pc~0; 43591#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43523#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43978#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44315#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 44224#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42667#L721 assume !(1 == ~t6_pc~0); 42644#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42645#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42792#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42927#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 43307#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43923#L740 assume 1 == ~t7_pc~0; 42709#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42544#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42545#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42534#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42535#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43232#L759 assume !(1 == ~t8_pc~0); 43233#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43263#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44371#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44108#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 44109#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44391#L778 assume 1 == ~t9_pc~0; 44283#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42692#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42997#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42570#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42571#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42873#L797 assume !(1 == ~t10_pc~0); 42874#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43007#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44258#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43415#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43416#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43717#L816 assume 1 == ~t11_pc~0; 42607#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42608#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43553#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43313#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43314#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43858#L835 assume 1 == ~t12_pc~0; 43732#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42756#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42595#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42596#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43471#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43472#L854 assume !(1 == ~t13_pc~0); 43087#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 43088#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 43139#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42790#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42791#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44219#L1401 assume !(1 == ~M_E~0); 43300#L1401-2 assume !(1 == ~T1_E~0); 43301#L1406-1 assume !(1 == ~T2_E~0); 43912#L1411-1 assume !(1 == ~T3_E~0); 43913#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43561#L1421-1 assume !(1 == ~T5_E~0); 43083#L1426-1 assume !(1 == ~T6_E~0); 43084#L1431-1 assume !(1 == ~T7_E~0); 42642#L1436-1 assume !(1 == ~T8_E~0); 42643#L1441-1 assume !(1 == ~T9_E~0); 43410#L1446-1 assume !(1 == ~T10_E~0); 43411#L1451-1 assume !(1 == ~T11_E~0); 44127#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43785#L1461-1 assume !(1 == ~T13_E~0); 43329#L1466-1 assume !(1 == ~E_1~0); 43330#L1471-1 assume !(1 == ~E_2~0); 44106#L1476-1 assume !(1 == ~E_3~0); 44107#L1481-1 assume !(1 == ~E_4~0); 44264#L1486-1 assume !(1 == ~E_5~0); 42912#L1491-1 assume !(1 == ~E_6~0); 42580#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42581#L1501-1 assume !(1 == ~E_8~0); 43404#L1506-1 assume !(1 == ~E_9~0); 43405#L1511-1 assume !(1 == ~E_10~0); 43359#L1516-1 assume !(1 == ~E_11~0); 42532#L1521-1 assume !(1 == ~E_12~0); 42533#L1526-1 assume !(1 == ~E_13~0); 42579#L1531-1 assume { :end_inline_reset_delta_events } true; 43109#L1892-2 [2024-10-25 00:40:33,373 INFO L747 eck$LassoCheckResult]: Loop: 43109#L1892-2 assume !false; 44172#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44425#L1233-1 assume !false; 44352#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43673#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43653#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44201#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42621#L1046 assume !(0 != eval_~tmp~0#1); 42623#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43155#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43156#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44408#L1258-5 assume !(0 == ~T1_E~0); 42784#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42785#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44400#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44404#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44405#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43012#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43013#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44169#L1298-3 assume !(0 == ~T9_E~0); 44170#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44332#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44168#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43657#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42780#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42781#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44256#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42921#L1338-3 assume !(0 == ~E_4~0); 42922#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44083#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44261#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44262#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43602#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43142#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43143#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43943#L1378-3 assume !(0 == ~E_12~0); 43944#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 44124#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44125#L607-42 assume 1 == ~m_pc~0; 43742#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43452#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43284#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43164#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43165#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43718#L626-42 assume 1 == ~t1_pc~0; 43255#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43256#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44356#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44141#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42813#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42814#L645-42 assume 1 == ~t2_pc~0; 44324#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44062#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43600#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43032#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42552#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42553#L664-42 assume 1 == ~t3_pc~0; 43365#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43069#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44002#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43890#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43891#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44054#L683-42 assume 1 == ~t4_pc~0; 44417#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43769#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43897#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44057#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44322#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44163#L702-42 assume 1 == ~t5_pc~0; 43634#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43246#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43554#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43667#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42564#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42565#L721-42 assume 1 == ~t6_pc~0; 42704#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42725#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42903#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42904#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43385#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43219#L740-42 assume 1 == ~t7_pc~0; 43220#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42939#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43515#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43368#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 43369#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43640#L759-42 assume 1 == ~t8_pc~0; 43491#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43425#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43426#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43499#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43500#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43589#L778-42 assume 1 == ~t9_pc~0; 43437#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43439#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43862#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43770#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43771#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43825#L797-42 assume 1 == ~t10_pc~0; 42946#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42947#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43843#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43844#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43863#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43864#L816-42 assume 1 == ~t11_pc~0; 42524#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42525#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44362#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43412#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43123#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43124#L835-42 assume !(1 == ~t12_pc~0); 43448#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 43449#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43642#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43643#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44222#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 44000#L854-42 assume 1 == ~t13_pc~0; 44001#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 43043#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 43211#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43212#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43325#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43326#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44117#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42872#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42751#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42752#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43375#L1421-3 assume !(1 == ~T5_E~0); 43376#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42917#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42918#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42536#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42537#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44145#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43463#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43091#L1461-3 assume !(1 == ~T13_E~0); 43092#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44402#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43033#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43034#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43457#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43061#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43062#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43497#L1501-3 assume !(1 == ~E_8~0); 43498#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43939#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43927#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43928#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43605#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43606#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44021#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42850#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42897#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 42898#L1911 assume !(0 == start_simulation_~tmp~3#1); 43429#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43960#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42988#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42574#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42575#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42698#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43461#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 44275#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 43109#L1892-2 [2024-10-25 00:40:33,374 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,374 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2024-10-25 00:40:33,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401913127] [2024-10-25 00:40:33,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401913127] [2024-10-25 00:40:33,411 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [401913127] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:33,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319969188] [2024-10-25 00:40:33,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,411 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:33,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,412 INFO L85 PathProgramCache]: Analyzing trace with hash -23892062, now seen corresponding path program 1 times [2024-10-25 00:40:33,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295423830] [2024-10-25 00:40:33,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1295423830] [2024-10-25 00:40:33,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1295423830] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:33,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262175690] [2024-10-25 00:40:33,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,457 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:33,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:33,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:33,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:33,458 INFO L87 Difference]: Start difference. First operand 1928 states and 2839 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:33,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:33,482 INFO L93 Difference]: Finished difference Result 1928 states and 2838 transitions. [2024-10-25 00:40:33,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2838 transitions. [2024-10-25 00:40:33,488 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:33,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2838 transitions. [2024-10-25 00:40:33,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:33,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:33,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2838 transitions. [2024-10-25 00:40:33,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:33,528 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2838 transitions. [2024-10-25 00:40:33,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2838 transitions. [2024-10-25 00:40:33,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:33,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4719917012448134) internal successors, (2838), 1927 states have internal predecessors, (2838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:33,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2838 transitions. [2024-10-25 00:40:33,580 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2838 transitions. [2024-10-25 00:40:33,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:33,581 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2838 transitions. [2024-10-25 00:40:33,581 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-25 00:40:33,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2838 transitions. [2024-10-25 00:40:33,588 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:33,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:33,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:33,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,590 INFO L745 eck$LassoCheckResult]: Stem: 46663#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 47563#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47564#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48289#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47960#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47961#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46884#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46885#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47364#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47199#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47200#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46948#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46949#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47370#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47554#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47722#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47755#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46964#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46965#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 48180#L1258-2 assume !(0 == ~T1_E~0); 47282#L1263-1 assume !(0 == ~T2_E~0); 47283#L1268-1 assume !(0 == ~T3_E~0); 47600#L1273-1 assume !(0 == ~T4_E~0); 48159#L1278-1 assume !(0 == ~T5_E~0); 48017#L1283-1 assume !(0 == ~T6_E~0); 48018#L1288-1 assume !(0 == ~T7_E~0); 48256#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48244#L1298-1 assume !(0 == ~T9_E~0); 48175#L1303-1 assume !(0 == ~T10_E~0); 46762#L1308-1 assume !(0 == ~T11_E~0); 46702#L1313-1 assume !(0 == ~T12_E~0); 46703#L1318-1 assume !(0 == ~T13_E~0); 46710#L1323-1 assume !(0 == ~E_1~0); 46711#L1328-1 assume !(0 == ~E_2~0); 46894#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47888#L1338-1 assume !(0 == ~E_4~0); 47889#L1343-1 assume !(0 == ~E_5~0); 47994#L1348-1 assume !(0 == ~E_6~0); 48274#L1353-1 assume !(0 == ~E_7~0); 47623#L1358-1 assume !(0 == ~E_8~0); 47624#L1363-1 assume !(0 == ~E_9~0); 47910#L1368-1 assume !(0 == ~E_10~0); 46556#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46557#L1378-1 assume !(0 == ~E_12~0); 46839#L1383-1 assume !(0 == ~E_13~0); 46840#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47628#L607 assume 1 == ~m_pc~0; 47629#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46912#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47428#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47429#L1560 assume !(0 != activate_threads_~tmp~1#1); 47535#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46723#L626 assume !(1 == ~t1_pc~0); 46724#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47005#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47006#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47896#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46631#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46632#L645 assume 1 == ~t2_pc~0; 46741#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46696#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46807#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46808#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47509#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47510#L664 assume 1 == ~t3_pc~0; 48272#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46494#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46495#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47154#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 47155#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48188#L683 assume !(1 == ~t4_pc~0); 47739#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47693#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46514#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46515#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47846#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47453#L702 assume 1 == ~t5_pc~0; 47454#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47386#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47841#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48178#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 48087#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46530#L721 assume !(1 == ~t6_pc~0); 46507#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46508#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46655#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46790#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 47170#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47786#L740 assume 1 == ~t7_pc~0; 46572#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46407#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46408#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46397#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46398#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47095#L759 assume !(1 == ~t8_pc~0); 47096#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47126#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48234#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47971#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47972#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48254#L778 assume 1 == ~t9_pc~0; 48144#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46555#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46860#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46433#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46434#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46736#L797 assume !(1 == ~t10_pc~0); 46737#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46870#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48121#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47278#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 47279#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47580#L816 assume 1 == ~t11_pc~0; 46470#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46471#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47416#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47176#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 47177#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47721#L835 assume 1 == ~t12_pc~0; 47595#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46619#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46458#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46459#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 47334#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47335#L854 assume !(1 == ~t13_pc~0); 46950#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46951#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 47002#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46653#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46654#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48082#L1401 assume !(1 == ~M_E~0); 47163#L1401-2 assume !(1 == ~T1_E~0); 47164#L1406-1 assume !(1 == ~T2_E~0); 47775#L1411-1 assume !(1 == ~T3_E~0); 47776#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47424#L1421-1 assume !(1 == ~T5_E~0); 46946#L1426-1 assume !(1 == ~T6_E~0); 46947#L1431-1 assume !(1 == ~T7_E~0); 46505#L1436-1 assume !(1 == ~T8_E~0); 46506#L1441-1 assume !(1 == ~T9_E~0); 47273#L1446-1 assume !(1 == ~T10_E~0); 47274#L1451-1 assume !(1 == ~T11_E~0); 47990#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47648#L1461-1 assume !(1 == ~T13_E~0); 47192#L1466-1 assume !(1 == ~E_1~0); 47193#L1471-1 assume !(1 == ~E_2~0); 47969#L1476-1 assume !(1 == ~E_3~0); 47970#L1481-1 assume !(1 == ~E_4~0); 48127#L1486-1 assume !(1 == ~E_5~0); 46775#L1491-1 assume !(1 == ~E_6~0); 46443#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46444#L1501-1 assume !(1 == ~E_8~0); 47267#L1506-1 assume !(1 == ~E_9~0); 47268#L1511-1 assume !(1 == ~E_10~0); 47222#L1516-1 assume !(1 == ~E_11~0); 46395#L1521-1 assume !(1 == ~E_12~0); 46396#L1526-1 assume !(1 == ~E_13~0); 46442#L1531-1 assume { :end_inline_reset_delta_events } true; 46972#L1892-2 [2024-10-25 00:40:33,591 INFO L747 eck$LassoCheckResult]: Loop: 46972#L1892-2 assume !false; 48035#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48288#L1233-1 assume !false; 48215#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47536#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47516#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48064#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46484#L1046 assume !(0 != eval_~tmp~0#1); 46486#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47018#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47019#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48271#L1258-5 assume !(0 == ~T1_E~0); 46645#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46646#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48263#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48267#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48268#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46875#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46876#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48032#L1298-3 assume !(0 == ~T9_E~0); 48033#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48195#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48031#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47520#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46647#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46648#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48119#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46786#L1338-3 assume !(0 == ~E_4~0); 46787#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47946#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48125#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48126#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47465#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47007#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47008#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47806#L1378-3 assume !(0 == ~E_12~0); 47807#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47987#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47988#L607-42 assume 1 == ~m_pc~0; 47605#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 47315#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47147#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47027#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47028#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47581#L626-42 assume !(1 == ~t1_pc~0); 47120#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 47119#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48219#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48004#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46676#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46677#L645-42 assume !(1 == ~t2_pc~0); 47924#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47925#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47463#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46895#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46415#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46416#L664-42 assume !(1 == ~t3_pc~0); 46931#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46932#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47865#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47753#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47754#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47917#L683-42 assume 1 == ~t4_pc~0; 48280#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47632#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47760#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47920#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48185#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48026#L702-42 assume !(1 == ~t5_pc~0); 47108#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 47109#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47417#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47530#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46427#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46428#L721-42 assume 1 == ~t6_pc~0; 46567#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46588#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46766#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46767#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47248#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47082#L740-42 assume !(1 == ~t7_pc~0); 46801#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 46802#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47378#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47231#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 47232#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47503#L759-42 assume 1 == ~t8_pc~0; 47354#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47288#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47289#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47362#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47363#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47452#L778-42 assume 1 == ~t9_pc~0; 47300#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47302#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47725#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47633#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47634#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47688#L797-42 assume 1 == ~t10_pc~0; 46809#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46810#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47706#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47707#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47726#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47727#L816-42 assume 1 == ~t11_pc~0; 46387#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46388#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48225#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47275#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46986#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46987#L835-42 assume 1 == ~t12_pc~0; 47413#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47311#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47505#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47506#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 48085#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47863#L854-42 assume 1 == ~t13_pc~0; 47864#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46906#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 47074#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47075#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 47188#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47189#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47980#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46735#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46614#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46615#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47238#L1421-3 assume !(1 == ~T5_E~0); 47239#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46780#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46781#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46399#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46400#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48008#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47326#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46954#L1461-3 assume !(1 == ~T13_E~0); 46955#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48265#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46896#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46897#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47320#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46924#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46925#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47359#L1501-3 assume !(1 == ~E_8~0); 47360#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47802#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47790#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47791#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47468#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47469#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47884#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46713#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46760#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46761#L1911 assume !(0 == start_simulation_~tmp~3#1); 47292#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47823#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46851#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46437#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46438#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46561#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47324#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48138#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46972#L1892-2 [2024-10-25 00:40:33,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,592 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2024-10-25 00:40:33,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341794955] [2024-10-25 00:40:33,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [341794955] [2024-10-25 00:40:33,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [341794955] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,632 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:33,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97195312] [2024-10-25 00:40:33,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,634 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:33,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,634 INFO L85 PathProgramCache]: Analyzing trace with hash -587463778, now seen corresponding path program 1 times [2024-10-25 00:40:33,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174447919] [2024-10-25 00:40:33,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1174447919] [2024-10-25 00:40:33,701 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1174447919] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,701 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,701 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:33,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917638758] [2024-10-25 00:40:33,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,702 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:33,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:33,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:33,703 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:33,703 INFO L87 Difference]: Start difference. First operand 1928 states and 2838 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:33,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:33,733 INFO L93 Difference]: Finished difference Result 1928 states and 2837 transitions. [2024-10-25 00:40:33,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2837 transitions. [2024-10-25 00:40:33,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:33,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2837 transitions. [2024-10-25 00:40:33,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-10-25 00:40:33,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-10-25 00:40:33,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2837 transitions. [2024-10-25 00:40:33,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:33,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2837 transitions. [2024-10-25 00:40:33,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2837 transitions. [2024-10-25 00:40:33,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-10-25 00:40:33,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4714730290456433) internal successors, (2837), 1927 states have internal predecessors, (2837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:33,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2837 transitions. [2024-10-25 00:40:33,774 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2837 transitions. [2024-10-25 00:40:33,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:33,775 INFO L425 stractBuchiCegarLoop]: Abstraction has 1928 states and 2837 transitions. [2024-10-25 00:40:33,775 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-25 00:40:33,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2837 transitions. [2024-10-25 00:40:33,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-10-25 00:40:33,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:33,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:33,782 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,783 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:33,783 INFO L745 eck$LassoCheckResult]: Stem: 50526#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 51426#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51427#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52152#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51823#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51824#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50747#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50748#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51227#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51062#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 51063#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50811#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50812#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51233#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51417#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51585#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51618#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50827#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50828#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 52043#L1258-2 assume !(0 == ~T1_E~0); 51145#L1263-1 assume !(0 == ~T2_E~0); 51146#L1268-1 assume !(0 == ~T3_E~0); 51463#L1273-1 assume !(0 == ~T4_E~0); 52022#L1278-1 assume !(0 == ~T5_E~0); 51880#L1283-1 assume !(0 == ~T6_E~0); 51881#L1288-1 assume !(0 == ~T7_E~0); 52118#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52107#L1298-1 assume !(0 == ~T9_E~0); 52038#L1303-1 assume !(0 == ~T10_E~0); 50625#L1308-1 assume !(0 == ~T11_E~0); 50565#L1313-1 assume !(0 == ~T12_E~0); 50566#L1318-1 assume !(0 == ~T13_E~0); 50573#L1323-1 assume !(0 == ~E_1~0); 50574#L1328-1 assume !(0 == ~E_2~0); 50757#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51751#L1338-1 assume !(0 == ~E_4~0); 51752#L1343-1 assume !(0 == ~E_5~0); 51857#L1348-1 assume !(0 == ~E_6~0); 52137#L1353-1 assume !(0 == ~E_7~0); 51486#L1358-1 assume !(0 == ~E_8~0); 51487#L1363-1 assume !(0 == ~E_9~0); 51773#L1368-1 assume !(0 == ~E_10~0); 50419#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50420#L1378-1 assume !(0 == ~E_12~0); 50702#L1383-1 assume !(0 == ~E_13~0); 50703#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51491#L607 assume 1 == ~m_pc~0; 51492#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50775#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51291#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51292#L1560 assume !(0 != activate_threads_~tmp~1#1); 51398#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50586#L626 assume !(1 == ~t1_pc~0); 50587#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50868#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50869#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51759#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50494#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50495#L645 assume 1 == ~t2_pc~0; 50604#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50559#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50670#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50671#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 51372#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51373#L664 assume 1 == ~t3_pc~0; 52135#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50355#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50356#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51017#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 51018#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52051#L683 assume !(1 == ~t4_pc~0); 51602#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51556#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50377#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50378#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51709#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51316#L702 assume 1 == ~t5_pc~0; 51317#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51249#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51704#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52041#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51950#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50393#L721 assume !(1 == ~t6_pc~0); 50370#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50371#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50518#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50653#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 51033#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51649#L740 assume 1 == ~t7_pc~0; 50435#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50270#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50271#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50260#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 50261#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50958#L759 assume !(1 == ~t8_pc~0); 50959#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50989#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52097#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51834#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51835#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52117#L778 assume 1 == ~t9_pc~0; 52007#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50418#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50723#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50296#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 50297#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50599#L797 assume !(1 == ~t10_pc~0); 50600#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50733#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51984#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51141#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 51142#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51443#L816 assume 1 == ~t11_pc~0; 50333#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50334#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51277#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51039#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 51040#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51584#L835 assume 1 == ~t12_pc~0; 51458#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50482#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50321#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50322#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 51197#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51198#L854 assume !(1 == ~t13_pc~0); 50813#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50814#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50863#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50516#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50517#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51945#L1401 assume !(1 == ~M_E~0); 51026#L1401-2 assume !(1 == ~T1_E~0); 51027#L1406-1 assume !(1 == ~T2_E~0); 51638#L1411-1 assume !(1 == ~T3_E~0); 51639#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51287#L1421-1 assume !(1 == ~T5_E~0); 50809#L1426-1 assume !(1 == ~T6_E~0); 50810#L1431-1 assume !(1 == ~T7_E~0); 50368#L1436-1 assume !(1 == ~T8_E~0); 50369#L1441-1 assume !(1 == ~T9_E~0); 51136#L1446-1 assume !(1 == ~T10_E~0); 51137#L1451-1 assume !(1 == ~T11_E~0); 51853#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51511#L1461-1 assume !(1 == ~T13_E~0); 51055#L1466-1 assume !(1 == ~E_1~0); 51056#L1471-1 assume !(1 == ~E_2~0); 51832#L1476-1 assume !(1 == ~E_3~0); 51833#L1481-1 assume !(1 == ~E_4~0); 51990#L1486-1 assume !(1 == ~E_5~0); 50638#L1491-1 assume !(1 == ~E_6~0); 50306#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50307#L1501-1 assume !(1 == ~E_8~0); 51130#L1506-1 assume !(1 == ~E_9~0); 51131#L1511-1 assume !(1 == ~E_10~0); 51085#L1516-1 assume !(1 == ~E_11~0); 50258#L1521-1 assume !(1 == ~E_12~0); 50259#L1526-1 assume !(1 == ~E_13~0); 50305#L1531-1 assume { :end_inline_reset_delta_events } true; 50835#L1892-2 [2024-10-25 00:40:33,783 INFO L747 eck$LassoCheckResult]: Loop: 50835#L1892-2 assume !false; 51898#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52151#L1233-1 assume !false; 52078#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51399#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51379#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51927#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 50347#L1046 assume !(0 != eval_~tmp~0#1); 50349#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50881#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50882#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52134#L1258-5 assume !(0 == ~T1_E~0); 50508#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50509#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52126#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52130#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52131#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50738#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50739#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51895#L1298-3 assume !(0 == ~T9_E~0); 51896#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 52058#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51894#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51383#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50510#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50511#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51982#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50649#L1338-3 assume !(0 == ~E_4~0); 50650#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51809#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51988#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51989#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51328#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50870#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50871#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51669#L1378-3 assume !(0 == ~E_12~0); 51670#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51850#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51851#L607-42 assume !(1 == ~m_pc~0); 51472#L607-44 is_master_triggered_~__retres1~0#1 := 0; 51178#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51012#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50890#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50891#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51447#L626-42 assume 1 == ~t1_pc~0; 50984#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50985#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52082#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51867#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50541#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50542#L645-42 assume 1 == ~t2_pc~0; 52050#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51787#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51326#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50758#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50278#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50279#L664-42 assume 1 == ~t3_pc~0; 51091#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50792#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51728#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51616#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51617#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51780#L683-42 assume !(1 == ~t4_pc~0); 51493#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 51494#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51622#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51783#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52048#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51889#L702-42 assume 1 == ~t5_pc~0; 51360#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50972#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51280#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51393#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50290#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50291#L721-42 assume 1 == ~t6_pc~0; 50430#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50451#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50629#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50630#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51111#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50945#L740-42 assume 1 == ~t7_pc~0; 50946#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50665#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51241#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51094#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 51095#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51366#L759-42 assume 1 == ~t8_pc~0; 51217#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51151#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51152#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51225#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51226#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51315#L778-42 assume 1 == ~t9_pc~0; 51163#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51165#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51588#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51495#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51496#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51551#L797-42 assume 1 == ~t10_pc~0; 50672#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50673#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51569#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51570#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51589#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51590#L816-42 assume 1 == ~t11_pc~0; 50250#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50251#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52088#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51138#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50849#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50850#L835-42 assume !(1 == ~t12_pc~0); 51171#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 51172#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51368#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51369#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51948#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51726#L854-42 assume !(1 == ~t13_pc~0); 50768#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 50769#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50937#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50938#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 51051#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51052#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51843#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50598#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50477#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50478#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51101#L1421-3 assume !(1 == ~T5_E~0); 51102#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50643#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50644#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50262#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50263#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51871#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51189#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50817#L1461-3 assume !(1 == ~T13_E~0); 50818#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52128#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50759#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50760#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51183#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50787#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50788#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51222#L1501-3 assume !(1 == ~E_8~0); 51223#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51665#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51653#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51654#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 51331#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 51332#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51747#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50576#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50624#L1911 assume !(0 == start_simulation_~tmp~3#1); 51155#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51686#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50714#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50300#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50301#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50424#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51187#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 52001#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50835#L1892-2 [2024-10-25 00:40:33,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,784 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2024-10-25 00:40:33,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757802152] [2024-10-25 00:40:33,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,833 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,833 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757802152] [2024-10-25 00:40:33,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [757802152] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:33,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [422951840] [2024-10-25 00:40:33,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,834 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:33,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:33,835 INFO L85 PathProgramCache]: Analyzing trace with hash -729787585, now seen corresponding path program 1 times [2024-10-25 00:40:33,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:33,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596092888] [2024-10-25 00:40:33,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:33,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:33,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:33,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:33,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:33,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596092888] [2024-10-25 00:40:33,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596092888] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:33,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:33,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:33,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080896767] [2024-10-25 00:40:33,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:33,887 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:33,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:33,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:33,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:33,888 INFO L87 Difference]: Start difference. First operand 1928 states and 2837 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:34,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:34,037 INFO L93 Difference]: Finished difference Result 3583 states and 5241 transitions. [2024-10-25 00:40:34,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3583 states and 5241 transitions. [2024-10-25 00:40:34,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3410 [2024-10-25 00:40:34,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3583 states to 3583 states and 5241 transitions. [2024-10-25 00:40:34,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3583 [2024-10-25 00:40:34,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3583 [2024-10-25 00:40:34,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3583 states and 5241 transitions. [2024-10-25 00:40:34,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:34,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3583 states and 5241 transitions. [2024-10-25 00:40:34,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3583 states and 5241 transitions. [2024-10-25 00:40:34,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3583 to 3583. [2024-10-25 00:40:34,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3583 states, 3583 states have (on average 1.462740720066983) internal successors, (5241), 3582 states have internal predecessors, (5241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:34,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3583 states to 3583 states and 5241 transitions. [2024-10-25 00:40:34,165 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3583 states and 5241 transitions. [2024-10-25 00:40:34,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:34,166 INFO L425 stractBuchiCegarLoop]: Abstraction has 3583 states and 5241 transitions. [2024-10-25 00:40:34,166 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-25 00:40:34,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3583 states and 5241 transitions. [2024-10-25 00:40:34,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3410 [2024-10-25 00:40:34,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:34,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:34,181 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:34,182 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:34,182 INFO L745 eck$LassoCheckResult]: Stem: 56043#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56044#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56945#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56946#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57730#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 57350#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57351#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56265#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56266#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56744#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56580#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56581#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 56329#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 56330#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56752#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56936#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 57106#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 57140#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 56345#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56346#L1258 assume !(0 == ~M_E~0); 57591#L1258-2 assume !(0 == ~T1_E~0); 56664#L1263-1 assume !(0 == ~T2_E~0); 56665#L1268-1 assume !(0 == ~T3_E~0); 56984#L1273-1 assume !(0 == ~T4_E~0); 57567#L1278-1 assume !(0 == ~T5_E~0); 57410#L1283-1 assume !(0 == ~T6_E~0); 57411#L1288-1 assume !(0 == ~T7_E~0); 57682#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57667#L1298-1 assume !(0 == ~T9_E~0); 57584#L1303-1 assume !(0 == ~T10_E~0); 56142#L1308-1 assume !(0 == ~T11_E~0); 56082#L1313-1 assume !(0 == ~T12_E~0); 56083#L1318-1 assume !(0 == ~T13_E~0); 56088#L1323-1 assume !(0 == ~E_1~0); 56089#L1328-1 assume !(0 == ~E_2~0); 56275#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 57276#L1338-1 assume !(0 == ~E_4~0); 57277#L1343-1 assume !(0 == ~E_5~0); 57387#L1348-1 assume !(0 == ~E_6~0); 57712#L1353-1 assume !(0 == ~E_7~0); 57007#L1358-1 assume !(0 == ~E_8~0); 57008#L1363-1 assume !(0 == ~E_9~0); 57298#L1368-1 assume !(0 == ~E_10~0); 55936#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55937#L1378-1 assume !(0 == ~E_12~0); 56218#L1383-1 assume !(0 == ~E_13~0); 56219#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57011#L607 assume !(1 == ~m_pc~0); 56292#L607-2 is_master_triggered_~__retres1~0#1 := 0; 56293#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56807#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56808#L1560 assume !(0 != activate_threads_~tmp~1#1); 56917#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56103#L626 assume !(1 == ~t1_pc~0); 56104#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56386#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56387#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57284#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 56011#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56012#L645 assume 1 == ~t2_pc~0; 56119#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56076#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56186#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56187#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56891#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56892#L664 assume 1 == ~t3_pc~0; 57704#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55871#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55872#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56535#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56536#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57601#L683 assume !(1 == ~t4_pc~0); 57124#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 57077#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55895#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55896#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57234#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56831#L702 assume 1 == ~t5_pc~0; 56832#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56767#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57229#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57589#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57483#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55906#L721 assume !(1 == ~t6_pc~0); 55888#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55889#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56035#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56171#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56551#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57172#L740 assume 1 == ~t7_pc~0; 55952#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55788#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55789#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55778#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55779#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56475#L759 assume !(1 == ~t8_pc~0); 56476#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56507#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57651#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57362#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 57363#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57681#L778 assume 1 == ~t9_pc~0; 57550#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55935#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56241#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55814#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55815#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 56115#L797 assume !(1 == ~t10_pc~0); 56116#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 56251#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57525#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56660#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56661#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56962#L816 assume 1 == ~t11_pc~0; 55849#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55850#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56796#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56557#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56558#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57105#L835 assume 1 == ~t12_pc~0; 56978#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55999#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55839#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55840#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56716#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56717#L854 assume !(1 == ~t13_pc~0); 56331#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 56332#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56381#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56033#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56034#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57478#L1401 assume !(1 == ~M_E~0); 56544#L1401-2 assume !(1 == ~T1_E~0); 56545#L1406-1 assume !(1 == ~T2_E~0); 57161#L1411-1 assume !(1 == ~T3_E~0); 57162#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56806#L1421-1 assume !(1 == ~T5_E~0); 56327#L1426-1 assume !(1 == ~T6_E~0); 56328#L1431-1 assume !(1 == ~T7_E~0); 55886#L1436-1 assume !(1 == ~T8_E~0); 55887#L1441-1 assume !(1 == ~T9_E~0); 56653#L1446-1 assume !(1 == ~T10_E~0); 56654#L1451-1 assume !(1 == ~T11_E~0); 57383#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 57031#L1461-1 assume !(1 == ~T13_E~0); 56573#L1466-1 assume !(1 == ~E_1~0); 56574#L1471-1 assume !(1 == ~E_2~0); 57360#L1476-1 assume !(1 == ~E_3~0); 57361#L1481-1 assume !(1 == ~E_4~0); 57532#L1486-1 assume !(1 == ~E_5~0); 56155#L1491-1 assume !(1 == ~E_6~0); 55824#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55825#L1501-1 assume !(1 == ~E_8~0); 56649#L1506-1 assume !(1 == ~E_9~0); 56650#L1511-1 assume !(1 == ~E_10~0); 56604#L1516-1 assume !(1 == ~E_11~0); 55776#L1521-1 assume !(1 == ~E_12~0); 55777#L1526-1 assume !(1 == ~E_13~0); 55823#L1531-1 assume { :end_inline_reset_delta_events } true; 56353#L1892-2 [2024-10-25 00:40:34,183 INFO L747 eck$LassoCheckResult]: Loop: 56353#L1892-2 assume !false; 57795#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57794#L1233-1 assume !false; 57633#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56918#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56898#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57460#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55865#L1046 assume !(0 != eval_~tmp~0#1); 55867#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56398#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56399#L1258-3 assume !(0 == ~M_E~0); 57703#L1258-5 assume !(0 == ~T1_E~0); 56023#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56024#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57693#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57698#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57699#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56256#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56257#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57426#L1298-3 assume !(0 == ~T9_E~0); 57427#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 57610#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 57425#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56902#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 56025#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 56026#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57522#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56166#L1338-3 assume !(0 == ~E_4~0); 56167#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57336#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57529#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57530#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 56847#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 56388#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 56389#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 57194#L1378-3 assume !(0 == ~E_12~0); 57195#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 57380#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57381#L607-42 assume !(1 == ~m_pc~0); 56990#L607-44 is_master_triggered_~__retres1~0#1 := 0; 56697#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56528#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56408#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56409#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56963#L626-42 assume 1 == ~t1_pc~0; 56499#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 56500#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57637#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57397#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56058#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56059#L645-42 assume !(1 == ~t2_pc~0); 57312#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 57313#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56845#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56276#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55796#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55797#L664-42 assume 1 == ~t3_pc~0; 56610#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56313#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57253#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57138#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57139#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57305#L683-42 assume !(1 == ~t4_pc~0); 57014#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 57015#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57145#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57308#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57597#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57420#L702-42 assume !(1 == ~t5_pc~0); 56489#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 56490#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56799#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56912#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55808#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55809#L721-42 assume 1 == ~t6_pc~0; 55947#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55968#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56146#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56147#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56630#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56463#L740-42 assume 1 == ~t7_pc~0; 56464#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 56183#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56760#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 56613#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 56614#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56885#L759-42 assume 1 == ~t8_pc~0; 56736#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56670#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56671#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56745#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56746#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56836#L778-42 assume 1 == ~t9_pc~0; 56682#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56684#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57109#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57016#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57017#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57072#L797-42 assume !(1 == ~t10_pc~0); 56192#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 56191#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57090#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57091#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 57110#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 57111#L816-42 assume 1 == ~t11_pc~0; 55768#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55769#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57643#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56657#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 56367#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56368#L835-42 assume !(1 == ~t12_pc~0); 56693#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 56694#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 56888#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 56889#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57482#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57251#L854-42 assume !(1 == ~t13_pc~0); 56288#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 56289#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56455#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56456#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56569#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56570#L1401-3 assume !(1 == ~M_E~0); 57743#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58854#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58853#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58852#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58851#L1421-3 assume !(1 == ~T5_E~0); 58850#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58849#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58848#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 58847#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 58846#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58845#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58844#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58843#L1461-3 assume !(1 == ~T13_E~0); 58842#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 58841#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58840#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58839#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58837#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58835#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58833#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58831#L1501-3 assume !(1 == ~E_8~0); 58829#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 58827#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58825#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58823#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58821#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58819#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58802#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58790#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58788#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 58787#L1911 assume !(0 == start_simulation_~tmp~3#1); 58785#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57211#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56232#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 55818#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 55819#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55941#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56706#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57544#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 56353#L1892-2 [2024-10-25 00:40:34,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:34,184 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2024-10-25 00:40:34,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:34,184 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623228883] [2024-10-25 00:40:34,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:34,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:34,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:34,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:34,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:34,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1623228883] [2024-10-25 00:40:34,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1623228883] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:34,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:34,275 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:34,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159208419] [2024-10-25 00:40:34,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:34,276 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:34,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:34,277 INFO L85 PathProgramCache]: Analyzing trace with hash 1773278808, now seen corresponding path program 1 times [2024-10-25 00:40:34,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:34,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504708385] [2024-10-25 00:40:34,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:34,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:34,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:34,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:34,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:34,344 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1504708385] [2024-10-25 00:40:34,344 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1504708385] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:34,344 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:34,344 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:34,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [171730884] [2024-10-25 00:40:34,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:34,345 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:34,345 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:34,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-25 00:40:34,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-25 00:40:34,346 INFO L87 Difference]: Start difference. First operand 3583 states and 5241 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:34,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:34,524 INFO L93 Difference]: Finished difference Result 7018 states and 10255 transitions. [2024-10-25 00:40:34,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7018 states and 10255 transitions. [2024-10-25 00:40:34,551 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6820 [2024-10-25 00:40:34,568 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7018 states to 7018 states and 10255 transitions. [2024-10-25 00:40:34,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7018 [2024-10-25 00:40:34,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7018 [2024-10-25 00:40:34,574 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7018 states and 10255 transitions. [2024-10-25 00:40:34,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:34,583 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7018 states and 10255 transitions. [2024-10-25 00:40:34,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7018 states and 10255 transitions. [2024-10-25 00:40:34,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7018 to 7018. [2024-10-25 00:40:34,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7018 states, 7018 states have (on average 1.4612425192362497) internal successors, (10255), 7017 states have internal predecessors, (10255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:34,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7018 states to 7018 states and 10255 transitions. [2024-10-25 00:40:34,686 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7018 states and 10255 transitions. [2024-10-25 00:40:34,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-25 00:40:34,688 INFO L425 stractBuchiCegarLoop]: Abstraction has 7018 states and 10255 transitions. [2024-10-25 00:40:34,689 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-25 00:40:34,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7018 states and 10255 transitions. [2024-10-25 00:40:34,712 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6820 [2024-10-25 00:40:34,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:34,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:34,714 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:34,714 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:34,715 INFO L745 eck$LassoCheckResult]: Stem: 66654#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 67559#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67560#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68317#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 67967#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67968#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66878#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66879#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67360#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67194#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 67195#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66943#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66944#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 67366#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67550#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67719#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67753#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 66959#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66960#L1258 assume !(0 == ~M_E~0); 68197#L1258-2 assume !(0 == ~T1_E~0); 67278#L1263-1 assume !(0 == ~T2_E~0); 67279#L1268-1 assume !(0 == ~T3_E~0); 67596#L1273-1 assume !(0 == ~T4_E~0); 68176#L1278-1 assume !(0 == ~T5_E~0); 68025#L1283-1 assume !(0 == ~T6_E~0); 68026#L1288-1 assume !(0 == ~T7_E~0); 68273#L1293-1 assume !(0 == ~T8_E~0); 68262#L1298-1 assume !(0 == ~T9_E~0); 68192#L1303-1 assume !(0 == ~T10_E~0); 66754#L1308-1 assume !(0 == ~T11_E~0); 66693#L1313-1 assume !(0 == ~T12_E~0); 66694#L1318-1 assume !(0 == ~T13_E~0); 66699#L1323-1 assume !(0 == ~E_1~0); 66700#L1328-1 assume !(0 == ~E_2~0); 66888#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 67891#L1338-1 assume !(0 == ~E_4~0); 67892#L1343-1 assume !(0 == ~E_5~0); 68002#L1348-1 assume !(0 == ~E_6~0); 68297#L1353-1 assume !(0 == ~E_7~0); 67619#L1358-1 assume !(0 == ~E_8~0); 67620#L1363-1 assume !(0 == ~E_9~0); 67913#L1368-1 assume !(0 == ~E_10~0); 66547#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 66548#L1378-1 assume !(0 == ~E_12~0); 66831#L1383-1 assume !(0 == ~E_13~0); 66832#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67623#L607 assume !(1 == ~m_pc~0); 66905#L607-2 is_master_triggered_~__retres1~0#1 := 0; 66906#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67421#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67422#L1560 assume !(0 != activate_threads_~tmp~1#1); 67531#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66714#L626 assume !(1 == ~t1_pc~0); 66715#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67000#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67001#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67899#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 66622#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66623#L645 assume 1 == ~t2_pc~0; 66731#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66687#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66799#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66800#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 67505#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67506#L664 assume 1 == ~t3_pc~0; 68295#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66482#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66483#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67149#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 67150#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68205#L683 assume !(1 == ~t4_pc~0); 67736#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67690#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66506#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66507#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67848#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67446#L702 assume 1 == ~t5_pc~0; 67447#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67381#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67842#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68195#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 68096#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66519#L721 assume !(1 == ~t6_pc~0); 66499#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66500#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66646#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66784#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 67165#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67787#L740 assume 1 == ~t7_pc~0; 66563#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66399#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66400#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66389#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 66390#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67090#L759 assume !(1 == ~t8_pc~0); 67091#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 67121#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68250#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67978#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 67979#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68272#L778 assume 1 == ~t9_pc~0; 68158#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66546#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66854#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66425#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 66426#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66728#L797 assume !(1 == ~t10_pc~0); 66729#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66864#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68135#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67274#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 67275#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67576#L816 assume 1 == ~t11_pc~0; 66462#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 66463#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67410#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 67171#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 67172#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67718#L835 assume 1 == ~t12_pc~0; 67591#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66610#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66450#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66451#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 67330#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 67331#L854 assume !(1 == ~t13_pc~0); 66945#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 66946#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66995#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66644#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66645#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68091#L1401 assume !(1 == ~M_E~0); 67158#L1401-2 assume !(1 == ~T1_E~0); 67159#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67776#L1411-1 assume !(1 == ~T3_E~0); 67777#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67420#L1421-1 assume !(1 == ~T5_E~0); 66941#L1426-1 assume !(1 == ~T6_E~0); 66942#L1431-1 assume !(1 == ~T7_E~0); 66497#L1436-1 assume !(1 == ~T8_E~0); 66498#L1441-1 assume !(1 == ~T9_E~0); 67267#L1446-1 assume !(1 == ~T10_E~0); 67268#L1451-1 assume !(1 == ~T11_E~0); 67998#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67645#L1461-1 assume !(1 == ~T13_E~0); 67187#L1466-1 assume !(1 == ~E_1~0); 67188#L1471-1 assume !(1 == ~E_2~0); 67976#L1476-1 assume !(1 == ~E_3~0); 67977#L1481-1 assume !(1 == ~E_4~0); 68141#L1486-1 assume !(1 == ~E_5~0); 66767#L1491-1 assume !(1 == ~E_6~0); 66435#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 66436#L1501-1 assume !(1 == ~E_8~0); 67263#L1506-1 assume !(1 == ~E_9~0); 67264#L1511-1 assume !(1 == ~E_10~0); 67217#L1516-1 assume !(1 == ~E_11~0); 67218#L1521-1 assume !(1 == ~E_12~0); 68418#L1526-1 assume !(1 == ~E_13~0); 68415#L1531-1 assume { :end_inline_reset_delta_events } true; 68401#L1892-2 [2024-10-25 00:40:34,715 INFO L747 eck$LassoCheckResult]: Loop: 68401#L1892-2 assume !false; 68391#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68386#L1233-1 assume !false; 68385#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68369#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68354#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68352#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 68349#L1046 assume !(0 != eval_~tmp~0#1); 68346#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68344#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68341#L1258-3 assume !(0 == ~M_E~0); 68342#L1258-5 assume !(0 == ~T1_E~0); 72727#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72726#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72725#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72724#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 72723#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 72722#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72721#L1293-3 assume !(0 == ~T8_E~0); 72720#L1298-3 assume !(0 == ~T9_E~0); 72719#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 72718#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 72717#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 72716#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 72715#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 72714#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 72713#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72712#L1338-3 assume !(0 == ~E_4~0); 72711#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 72710#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 72709#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 72708#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 72707#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 72706#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 72705#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 72704#L1378-3 assume !(0 == ~E_12~0); 72703#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 72702#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72700#L607-42 assume !(1 == ~m_pc~0); 72696#L607-44 is_master_triggered_~__retres1~0#1 := 0; 72694#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72692#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 72690#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72688#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72686#L626-42 assume !(1 == ~t1_pc~0); 72683#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 72680#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72678#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72676#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72674#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72672#L645-42 assume 1 == ~t2_pc~0; 72669#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 72666#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72664#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72662#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72660#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72658#L664-42 assume !(1 == ~t3_pc~0); 72655#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 72652#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72650#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72648#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 72646#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72644#L683-42 assume 1 == ~t4_pc~0; 72641#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 72638#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72636#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 72634#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 72632#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72630#L702-42 assume !(1 == ~t5_pc~0); 72627#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 72624#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72622#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 72620#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 72618#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72616#L721-42 assume 1 == ~t6_pc~0; 72613#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 72610#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72608#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 72606#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 72604#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72602#L740-42 assume !(1 == ~t7_pc~0); 72599#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 72596#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72594#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 72592#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 72590#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 72588#L759-42 assume !(1 == ~t8_pc~0); 72585#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 72582#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 72580#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 72578#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 72576#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 72574#L778-42 assume 1 == ~t9_pc~0; 72571#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 72568#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72566#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72564#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 72562#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 72560#L797-42 assume !(1 == ~t10_pc~0); 72557#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 72554#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 72552#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 72550#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 72548#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 72546#L816-42 assume 1 == ~t11_pc~0; 72543#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72540#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 72538#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 72536#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 72534#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 72262#L835-42 assume !(1 == ~t12_pc~0); 72259#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 72256#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 72254#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 72252#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 72250#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 72248#L854-42 assume 1 == ~t13_pc~0; 72245#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 72242#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 72240#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 72238#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 72236#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72234#L1401-3 assume !(1 == ~M_E~0); 69041#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72230#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66727#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 72227#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72225#L1421-3 assume !(1 == ~T5_E~0); 72223#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 72222#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72219#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66920#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 72216#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 72214#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 72212#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 72210#L1461-3 assume !(1 == ~T13_E~0); 72207#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 72205#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 72203#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 72201#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 72199#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 72197#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 72194#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 72192#L1501-3 assume !(1 == ~E_8~0); 72190#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 72188#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 72186#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 72184#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 72181#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 72180#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69357#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69345#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69343#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 68703#L1911 assume !(0 == start_simulation_~tmp~3#1); 68700#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68491#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68482#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68478#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 68476#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68474#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68471#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68414#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 68401#L1892-2 [2024-10-25 00:40:34,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:34,716 INFO L85 PathProgramCache]: Analyzing trace with hash -1259435077, now seen corresponding path program 1 times [2024-10-25 00:40:34,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:34,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330381035] [2024-10-25 00:40:34,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:34,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:34,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:34,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:34,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:34,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330381035] [2024-10-25 00:40:34,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1330381035] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:34,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:34,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:34,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16172821] [2024-10-25 00:40:34,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:34,784 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:34,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:34,784 INFO L85 PathProgramCache]: Analyzing trace with hash 958359093, now seen corresponding path program 1 times [2024-10-25 00:40:34,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:34,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917445279] [2024-10-25 00:40:34,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:34,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:34,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:34,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:34,851 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:34,851 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917445279] [2024-10-25 00:40:34,851 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917445279] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:34,852 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:34,852 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:34,852 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100674752] [2024-10-25 00:40:34,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:34,852 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:34,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:34,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-25 00:40:34,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-25 00:40:34,853 INFO L87 Difference]: Start difference. First operand 7018 states and 10255 transitions. cyclomatic complexity: 3239 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:35,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:35,037 INFO L93 Difference]: Finished difference Result 13472 states and 19680 transitions. [2024-10-25 00:40:35,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13472 states and 19680 transitions. [2024-10-25 00:40:35,083 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13240 [2024-10-25 00:40:35,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13472 states to 13472 states and 19680 transitions. [2024-10-25 00:40:35,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13472 [2024-10-25 00:40:35,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13472 [2024-10-25 00:40:35,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13472 states and 19680 transitions. [2024-10-25 00:40:35,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:35,135 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13472 states and 19680 transitions. [2024-10-25 00:40:35,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13472 states and 19680 transitions. [2024-10-25 00:40:35,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13472 to 13468. [2024-10-25 00:40:35,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13468 states, 13468 states have (on average 1.4609444609444608) internal successors, (19676), 13467 states have internal predecessors, (19676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:35,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13468 states to 13468 states and 19676 transitions. [2024-10-25 00:40:35,287 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13468 states and 19676 transitions. [2024-10-25 00:40:35,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-25 00:40:35,288 INFO L425 stractBuchiCegarLoop]: Abstraction has 13468 states and 19676 transitions. [2024-10-25 00:40:35,288 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-25 00:40:35,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13468 states and 19676 transitions. [2024-10-25 00:40:35,324 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13240 [2024-10-25 00:40:35,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:35,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:35,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:35,326 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:35,326 INFO L745 eck$LassoCheckResult]: Stem: 87155#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 87156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 88072#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88073#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88878#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 88488#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88489#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87378#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87379#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87861#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87695#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87696#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 87442#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 87443#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87869#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 88063#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 88233#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 88267#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 87458#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87459#L1258 assume !(0 == ~M_E~0); 88741#L1258-2 assume !(0 == ~T1_E~0); 87780#L1263-1 assume !(0 == ~T2_E~0); 87781#L1268-1 assume !(0 == ~T3_E~0); 88110#L1273-1 assume !(0 == ~T4_E~0); 88719#L1278-1 assume !(0 == ~T5_E~0); 88556#L1283-1 assume !(0 == ~T6_E~0); 88557#L1288-1 assume !(0 == ~T7_E~0); 88826#L1293-1 assume !(0 == ~T8_E~0); 88814#L1298-1 assume !(0 == ~T9_E~0); 88736#L1303-1 assume !(0 == ~T10_E~0); 87254#L1308-1 assume !(0 == ~T11_E~0); 87194#L1313-1 assume !(0 == ~T12_E~0); 87195#L1318-1 assume !(0 == ~T13_E~0); 87200#L1323-1 assume !(0 == ~E_1~0); 87201#L1328-1 assume !(0 == ~E_2~0); 87388#L1333-1 assume !(0 == ~E_3~0); 88409#L1338-1 assume !(0 == ~E_4~0); 88410#L1343-1 assume !(0 == ~E_5~0); 88529#L1348-1 assume !(0 == ~E_6~0); 88856#L1353-1 assume !(0 == ~E_7~0); 88133#L1358-1 assume !(0 == ~E_8~0); 88134#L1363-1 assume !(0 == ~E_9~0); 88432#L1368-1 assume !(0 == ~E_10~0); 87048#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 87049#L1378-1 assume !(0 == ~E_12~0); 87329#L1383-1 assume !(0 == ~E_13~0); 87330#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88137#L607 assume !(1 == ~m_pc~0); 87405#L607-2 is_master_triggered_~__retres1~0#1 := 0; 87406#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87927#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87928#L1560 assume !(0 != activate_threads_~tmp~1#1); 88041#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87215#L626 assume !(1 == ~t1_pc~0); 87216#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87500#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87501#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88417#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 87123#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87124#L645 assume 1 == ~t2_pc~0; 87231#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 87188#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87297#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87298#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 88014#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88015#L664 assume 1 == ~t3_pc~0; 88852#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86982#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86983#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87650#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 87651#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88749#L683 assume !(1 == ~t4_pc~0); 88251#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88203#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87006#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87007#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88366#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87951#L702 assume 1 == ~t5_pc~0; 87952#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87885#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88360#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88739#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 88628#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87018#L721 assume !(1 == ~t6_pc~0); 86999#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 87000#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87147#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87282#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 87666#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88303#L740 assume 1 == ~t7_pc~0; 87064#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86899#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86900#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86889#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 86890#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87590#L759 assume !(1 == ~t8_pc~0); 87591#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 87622#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88801#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88499#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 88500#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88825#L778 assume 1 == ~t9_pc~0; 88700#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87047#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87354#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86925#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 86926#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87227#L797 assume !(1 == ~t10_pc~0); 87228#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 87364#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88674#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87776#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 87777#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88089#L816 assume 1 == ~t11_pc~0; 86960#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86961#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87915#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87672#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 87673#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 88232#L835 assume 1 == ~t12_pc~0; 88105#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 87111#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86950#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86951#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 87832#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87833#L854 assume !(1 == ~t13_pc~0); 87444#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 87445#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 87495#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 87145#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 87146#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88623#L1401 assume !(1 == ~M_E~0); 87659#L1401-2 assume !(1 == ~T1_E~0); 87660#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88631#L1411-1 assume !(1 == ~T3_E~0); 88841#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88842#L1421-1 assume !(1 == ~T5_E~0); 87440#L1426-1 assume !(1 == ~T6_E~0); 87441#L1431-1 assume !(1 == ~T7_E~0); 86997#L1436-1 assume !(1 == ~T8_E~0); 86998#L1441-1 assume !(1 == ~T9_E~0); 87769#L1446-1 assume !(1 == ~T10_E~0); 87770#L1451-1 assume !(1 == ~T11_E~0); 88524#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 88157#L1461-1 assume !(1 == ~T13_E~0); 87688#L1466-1 assume !(1 == ~E_1~0); 87689#L1471-1 assume !(1 == ~E_2~0); 88497#L1476-1 assume !(1 == ~E_3~0); 88498#L1481-1 assume !(1 == ~E_4~0); 88680#L1486-1 assume !(1 == ~E_5~0); 87267#L1491-1 assume !(1 == ~E_6~0); 86935#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 86936#L1501-1 assume !(1 == ~E_8~0); 87765#L1506-1 assume !(1 == ~E_9~0); 87766#L1511-1 assume !(1 == ~E_10~0); 87718#L1516-1 assume !(1 == ~E_11~0); 86887#L1521-1 assume !(1 == ~E_12~0); 86888#L1526-1 assume !(1 == ~E_13~0); 86934#L1531-1 assume { :end_inline_reset_delta_events } true; 98209#L1892-2 [2024-10-25 00:40:35,327 INFO L747 eck$LassoCheckResult]: Loop: 98209#L1892-2 assume !false; 98016#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96585#L1233-1 assume !false; 96584#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 96565#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96563#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 96561#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 96558#L1046 assume !(0 != eval_~tmp~0#1); 96556#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 96553#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 96551#L1258-3 assume !(0 == ~M_E~0); 96549#L1258-5 assume !(0 == ~T1_E~0); 96547#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 96545#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 96544#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88900#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88846#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 87369#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 87370#L1293-3 assume !(0 == ~T8_E~0); 88571#L1298-3 assume !(0 == ~T9_E~0); 88572#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88757#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 88570#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 88025#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 87137#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87138#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88670#L1333-3 assume !(0 == ~E_3~0); 87278#L1338-3 assume !(0 == ~E_4~0); 87279#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88474#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88677#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 88678#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 87967#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 87502#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 87503#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 88325#L1378-3 assume !(0 == ~E_12~0); 88326#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 88521#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88522#L607-42 assume !(1 == ~m_pc~0); 88116#L607-44 is_master_triggered_~__retres1~0#1 := 0; 87813#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87643#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87522#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 87523#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88090#L626-42 assume !(1 == ~t1_pc~0); 87616#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 87615#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88786#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88541#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 87170#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87171#L645-42 assume !(1 == ~t2_pc~0); 88449#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 88450#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87965#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87389#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86907#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86908#L664-42 assume !(1 == ~t3_pc~0); 87425#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 87426#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88385#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88265#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88266#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88442#L683-42 assume 1 == ~t4_pc~0; 88867#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 88141#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88272#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88445#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88746#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88565#L702-42 assume 1 == ~t5_pc~0; 88001#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87605#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87918#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88035#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 86919#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86920#L721-42 assume 1 == ~t6_pc~0; 87059#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 87080#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87258#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87259#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87746#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87578#L740-42 assume 1 == ~t7_pc~0; 87579#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 87294#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87877#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87727#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 87728#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88007#L759-42 assume !(1 == ~t8_pc~0); 87853#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 87786#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87787#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87862#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 87863#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87956#L778-42 assume !(1 == ~t9_pc~0); 87799#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 87800#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88236#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88142#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 88143#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88198#L797-42 assume 1 == ~t10_pc~0; 87301#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 87302#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88217#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 88218#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 88237#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88238#L816-42 assume !(1 == ~t11_pc~0); 86881#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 86880#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 88793#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87773#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 87481#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87482#L835-42 assume !(1 == ~t12_pc~0); 87809#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 87810#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 88011#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 88012#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 88627#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 88383#L854-42 assume 1 == ~t13_pc~0; 88384#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 87402#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 87570#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 87571#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 87684#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87685#L1401-3 assume !(1 == ~M_E~0); 88511#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87230#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87106#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87107#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87736#L1421-3 assume !(1 == ~T5_E~0); 87737#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 87272#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 87273#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86891#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86892#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 88546#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87824#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 87448#L1461-3 assume !(1 == ~T13_E~0); 87449#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 88840#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 87390#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87391#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87818#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87418#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 87419#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87858#L1501-3 assume !(1 == ~E_8~0); 87859#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 88321#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 88309#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 88310#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 87972#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 87973#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 88405#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 87205#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 87252#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 87253#L1911 assume !(0 == start_simulation_~tmp~3#1); 87790#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98245#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98235#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98233#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 98231#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98229#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98227#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 98212#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 98209#L1892-2 [2024-10-25 00:40:35,329 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:35,329 INFO L85 PathProgramCache]: Analyzing trace with hash -312397191, now seen corresponding path program 1 times [2024-10-25 00:40:35,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:35,330 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852432538] [2024-10-25 00:40:35,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:35,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:35,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:35,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:35,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:35,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852432538] [2024-10-25 00:40:35,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [852432538] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:35,425 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:35,425 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:35,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418688108] [2024-10-25 00:40:35,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:35,425 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:35,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:35,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1144070157, now seen corresponding path program 1 times [2024-10-25 00:40:35,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:35,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422460640] [2024-10-25 00:40:35,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:35,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:35,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:35,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:35,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:35,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422460640] [2024-10-25 00:40:35,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1422460640] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:35,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:35,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:35,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73534930] [2024-10-25 00:40:35,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:35,465 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:35,465 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:35,466 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-25 00:40:35,466 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-25 00:40:35,466 INFO L87 Difference]: Start difference. First operand 13468 states and 19676 transitions. cyclomatic complexity: 6212 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:35,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:35,659 INFO L93 Difference]: Finished difference Result 25936 states and 37873 transitions. [2024-10-25 00:40:35,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25936 states and 37873 transitions. [2024-10-25 00:40:35,776 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25680 [2024-10-25 00:40:35,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25936 states to 25936 states and 37873 transitions. [2024-10-25 00:40:35,850 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25936 [2024-10-25 00:40:35,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25936 [2024-10-25 00:40:35,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25936 states and 37873 transitions. [2024-10-25 00:40:35,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:35,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25936 states and 37873 transitions. [2024-10-25 00:40:35,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25936 states and 37873 transitions. [2024-10-25 00:40:36,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25936 to 25928. [2024-10-25 00:40:36,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25928 states, 25928 states have (on average 1.4603903116322123) internal successors, (37865), 25927 states have internal predecessors, (37865), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:36,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25928 states to 25928 states and 37865 transitions. [2024-10-25 00:40:36,391 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25928 states and 37865 transitions. [2024-10-25 00:40:36,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-25 00:40:36,392 INFO L425 stractBuchiCegarLoop]: Abstraction has 25928 states and 37865 transitions. [2024-10-25 00:40:36,392 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-25 00:40:36,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25928 states and 37865 transitions. [2024-10-25 00:40:36,475 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25680 [2024-10-25 00:40:36,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:36,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:36,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:36,478 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:36,478 INFO L745 eck$LassoCheckResult]: Stem: 126572#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 126573#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 127520#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 127521#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 128482#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 127976#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127977#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126797#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126798#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127297#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 127126#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 127127#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 126866#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 126867#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 127305#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 127510#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 127692#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 127729#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 126882#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126883#L1258 assume !(0 == ~M_E~0); 128268#L1258-2 assume !(0 == ~T1_E~0); 127213#L1263-1 assume !(0 == ~T2_E~0); 127214#L1268-1 assume !(0 == ~T3_E~0); 127560#L1273-1 assume !(0 == ~T4_E~0); 128238#L1278-1 assume !(0 == ~T5_E~0); 128050#L1283-1 assume !(0 == ~T6_E~0); 128051#L1288-1 assume !(0 == ~T7_E~0); 128390#L1293-1 assume !(0 == ~T8_E~0); 128371#L1298-1 assume !(0 == ~T9_E~0); 128258#L1303-1 assume !(0 == ~T10_E~0); 126673#L1308-1 assume !(0 == ~T11_E~0); 126611#L1313-1 assume !(0 == ~T12_E~0); 126612#L1318-1 assume !(0 == ~T13_E~0); 126617#L1323-1 assume !(0 == ~E_1~0); 126618#L1328-1 assume !(0 == ~E_2~0); 126808#L1333-1 assume !(0 == ~E_3~0); 127889#L1338-1 assume !(0 == ~E_4~0); 127890#L1343-1 assume !(0 == ~E_5~0); 128020#L1348-1 assume !(0 == ~E_6~0); 128445#L1353-1 assume !(0 == ~E_7~0); 127584#L1358-1 assume !(0 == ~E_8~0); 127585#L1363-1 assume !(0 == ~E_9~0); 127912#L1368-1 assume !(0 == ~E_10~0); 126463#L1373-1 assume !(0 == ~E_11~0); 126464#L1378-1 assume !(0 == ~E_12~0); 126750#L1383-1 assume !(0 == ~E_13~0); 126751#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 127588#L607 assume !(1 == ~m_pc~0); 126826#L607-2 is_master_triggered_~__retres1~0#1 := 0; 126827#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127364#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 127365#L1560 assume !(0 != activate_threads_~tmp~1#1); 127487#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126632#L626 assume !(1 == ~t1_pc~0); 126633#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126924#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126925#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 127897#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 126539#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126540#L645 assume 1 == ~t2_pc~0; 126650#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 126605#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126718#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 127460#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127461#L664 assume 1 == ~t3_pc~0; 128435#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 126396#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126397#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 127080#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 127081#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128281#L683 assume !(1 == ~t4_pc~0); 127712#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 127662#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126420#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126421#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 127840#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 127389#L702 assume 1 == ~t5_pc~0; 127390#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 127321#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127835#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 128261#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 128137#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 126432#L721 assume !(1 == ~t6_pc~0); 126413#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 126414#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 126564#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 126702#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 127096#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 127769#L740 assume 1 == ~t7_pc~0; 126480#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 126313#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 126314#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 126303#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 126304#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 127020#L759 assume !(1 == ~t8_pc~0); 127021#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 127052#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 128352#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 127987#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 127988#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 128389#L778 assume 1 == ~t9_pc~0; 128221#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 126461#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 126773#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 126339#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 126340#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 126644#L797 assume !(1 == ~t10_pc~0); 126645#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 126783#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 128189#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 127209#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 127210#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 127538#L816 assume 1 == ~t11_pc~0; 126374#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 126375#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 127353#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 127102#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 127103#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 127691#L835 assume 1 == ~t12_pc~0; 127555#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 126527#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 126364#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 126365#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 127267#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 127268#L854 assume !(1 == ~t13_pc~0); 126868#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 126869#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 126919#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 126562#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 126563#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128130#L1401 assume !(1 == ~M_E~0); 127089#L1401-2 assume !(1 == ~T1_E~0); 127090#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128140#L1411-1 assume !(1 == ~T3_E~0); 144625#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 144624#L1421-1 assume !(1 == ~T5_E~0); 144623#L1426-1 assume !(1 == ~T6_E~0); 127922#L1431-1 assume !(1 == ~T7_E~0); 126411#L1436-1 assume !(1 == ~T8_E~0); 126412#L1441-1 assume !(1 == ~T9_E~0); 127202#L1446-1 assume !(1 == ~T10_E~0); 127203#L1451-1 assume !(1 == ~T11_E~0); 128016#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 127609#L1461-1 assume !(1 == ~T13_E~0); 127119#L1466-1 assume !(1 == ~E_1~0); 127120#L1471-1 assume !(1 == ~E_2~0); 127985#L1476-1 assume !(1 == ~E_3~0); 127986#L1481-1 assume !(1 == ~E_4~0); 144632#L1486-1 assume !(1 == ~E_5~0); 144631#L1491-1 assume !(1 == ~E_6~0); 144629#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 127624#L1501-1 assume !(1 == ~E_8~0); 127625#L1506-1 assume !(1 == ~E_9~0); 143831#L1511-1 assume !(1 == ~E_10~0); 143829#L1516-1 assume !(1 == ~E_11~0); 143825#L1521-1 assume !(1 == ~E_12~0); 143823#L1526-1 assume !(1 == ~E_13~0); 143821#L1531-1 assume { :end_inline_reset_delta_events } true; 143818#L1892-2 [2024-10-25 00:40:36,479 INFO L747 eck$LassoCheckResult]: Loop: 143818#L1892-2 assume !false; 143128#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143126#L1233-1 assume !false; 143124#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 143110#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 143106#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 143104#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 143101#L1046 assume !(0 != eval_~tmp~0#1); 143100#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 143099#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143098#L1258-3 assume !(0 == ~M_E~0); 143097#L1258-5 assume !(0 == ~T1_E~0); 143096#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 143095#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 143094#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 143093#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 143092#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 143091#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 143090#L1293-3 assume !(0 == ~T8_E~0); 143089#L1298-3 assume !(0 == ~T9_E~0); 143088#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 143087#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 143086#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 143085#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 143084#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 143083#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 143082#L1333-3 assume !(0 == ~E_3~0); 143081#L1338-3 assume !(0 == ~E_4~0); 143080#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 143079#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 143078#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 143077#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 143076#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 143075#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 143074#L1373-3 assume !(0 == ~E_11~0); 143073#L1378-3 assume !(0 == ~E_12~0); 143072#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 143071#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143070#L607-42 assume !(1 == ~m_pc~0); 143068#L607-44 is_master_triggered_~__retres1~0#1 := 0; 143067#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 143066#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 143064#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 143061#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143059#L626-42 assume 1 == ~t1_pc~0; 143056#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 143054#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143052#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 143050#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 143047#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143045#L645-42 assume !(1 == ~t2_pc~0); 143042#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 143040#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143038#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 143036#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 143033#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143031#L664-42 assume 1 == ~t3_pc~0; 143028#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 143026#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 143024#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 143022#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 143019#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143018#L683-42 assume !(1 == ~t4_pc~0); 143016#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 143015#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143014#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 143013#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 143012#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143011#L702-42 assume !(1 == ~t5_pc~0); 143010#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 143008#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143007#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 143006#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 143005#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143004#L721-42 assume !(1 == ~t6_pc~0); 143002#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 143001#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 143000#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 142999#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 142998#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 142997#L740-42 assume 1 == ~t7_pc~0; 142995#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 142994#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 142993#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 142992#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 142990#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 142988#L759-42 assume !(1 == ~t8_pc~0); 142986#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 127219#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 127220#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 127298#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 127299#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 127394#L778-42 assume !(1 == ~t9_pc~0); 127232#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 127233#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 127695#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 127593#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 127594#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 127657#L797-42 assume 1 == ~t10_pc~0; 126721#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 126722#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127676#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 127677#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 127696#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 127697#L816-42 assume 1 == ~t11_pc~0; 126293#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 126294#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128342#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 127206#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 126905#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 126906#L835-42 assume 1 == ~t12_pc~0; 127352#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 127243#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 127457#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 127458#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 128136#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 127859#L854-42 assume 1 == ~t13_pc~0; 127860#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 126823#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 126999#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 127000#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 127115#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127116#L1401-3 assume !(1 == ~M_E~0); 128521#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 129740#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 129738#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 129736#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 129734#L1421-3 assume !(1 == ~T5_E~0); 129731#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 129729#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 129727#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 129725#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 129723#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 129721#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 129718#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 129716#L1461-3 assume !(1 == ~T13_E~0); 129714#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 129712#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 129710#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 129708#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 129705#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 129703#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 129702#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 129701#L1501-3 assume !(1 == ~E_8~0); 129700#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 129699#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 129698#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 129697#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 129525#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 129521#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 129522#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 142606#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 142604#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 142601#L1911 assume !(0 == start_simulation_~tmp~3#1); 142602#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 145877#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 144579#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 144577#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 144575#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 144572#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 144570#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 143820#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 143818#L1892-2 [2024-10-25 00:40:36,479 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:36,480 INFO L85 PathProgramCache]: Analyzing trace with hash -645040329, now seen corresponding path program 1 times [2024-10-25 00:40:36,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:36,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439883277] [2024-10-25 00:40:36,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:36,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:36,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:36,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:36,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:36,537 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439883277] [2024-10-25 00:40:36,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439883277] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:36,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:36,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:36,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1824931773] [2024-10-25 00:40:36,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:36,538 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:36,538 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:36,538 INFO L85 PathProgramCache]: Analyzing trace with hash 1142439058, now seen corresponding path program 1 times [2024-10-25 00:40:36,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:36,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046004504] [2024-10-25 00:40:36,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:36,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:36,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:36,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:36,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:36,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046004504] [2024-10-25 00:40:36,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046004504] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:36,590 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:36,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:36,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902297644] [2024-10-25 00:40:36,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:36,591 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:36,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:36,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:36,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:36,592 INFO L87 Difference]: Start difference. First operand 25928 states and 37865 transitions. cyclomatic complexity: 11945 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:36,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:36,927 INFO L93 Difference]: Finished difference Result 50583 states and 73532 transitions. [2024-10-25 00:40:36,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50583 states and 73532 transitions. [2024-10-25 00:40:37,133 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 50304 [2024-10-25 00:40:37,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50583 states to 50583 states and 73532 transitions. [2024-10-25 00:40:37,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50583 [2024-10-25 00:40:37,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50583 [2024-10-25 00:40:37,554 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50583 states and 73532 transitions. [2024-10-25 00:40:37,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:37,605 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50583 states and 73532 transitions. [2024-10-25 00:40:37,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50583 states and 73532 transitions. [2024-10-25 00:40:38,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50583 to 50551. [2024-10-25 00:40:38,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50551 states, 50551 states have (on average 1.4539771715693062) internal successors, (73500), 50550 states have internal predecessors, (73500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:38,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50551 states to 50551 states and 73500 transitions. [2024-10-25 00:40:38,656 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50551 states and 73500 transitions. [2024-10-25 00:40:38,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:38,657 INFO L425 stractBuchiCegarLoop]: Abstraction has 50551 states and 73500 transitions. [2024-10-25 00:40:38,657 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-25 00:40:38,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50551 states and 73500 transitions. [2024-10-25 00:40:38,960 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 50272 [2024-10-25 00:40:38,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:38,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:38,962 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:38,962 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:38,963 INFO L745 eck$LassoCheckResult]: Stem: 203090#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 203091#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 204031#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 204032#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 205023#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 204502#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 204503#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 203315#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 203316#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 203818#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 203642#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 203643#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 203383#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 203384#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 203826#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 204020#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 204204#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 204243#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 203399#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 203400#L1258 assume !(0 == ~M_E~0); 204792#L1258-2 assume !(0 == ~T1_E~0); 203730#L1263-1 assume !(0 == ~T2_E~0); 203731#L1268-1 assume !(0 == ~T3_E~0); 204069#L1273-1 assume !(0 == ~T4_E~0); 204764#L1278-1 assume !(0 == ~T5_E~0); 204575#L1283-1 assume !(0 == ~T6_E~0); 204576#L1288-1 assume !(0 == ~T7_E~0); 204928#L1293-1 assume !(0 == ~T8_E~0); 204897#L1298-1 assume !(0 == ~T9_E~0); 204787#L1303-1 assume !(0 == ~T10_E~0); 203190#L1308-1 assume !(0 == ~T11_E~0); 203130#L1313-1 assume !(0 == ~T12_E~0); 203131#L1318-1 assume !(0 == ~T13_E~0); 203136#L1323-1 assume !(0 == ~E_1~0); 203137#L1328-1 assume !(0 == ~E_2~0); 203326#L1333-1 assume !(0 == ~E_3~0); 204405#L1338-1 assume !(0 == ~E_4~0); 204406#L1343-1 assume !(0 == ~E_5~0); 204544#L1348-1 assume !(0 == ~E_6~0); 204978#L1353-1 assume !(0 == ~E_7~0); 204093#L1358-1 assume !(0 == ~E_8~0); 204094#L1363-1 assume !(0 == ~E_9~0); 204433#L1368-1 assume !(0 == ~E_10~0); 202982#L1373-1 assume !(0 == ~E_11~0); 202983#L1378-1 assume !(0 == ~E_12~0); 203268#L1383-1 assume !(0 == ~E_13~0); 203269#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 204097#L607 assume !(1 == ~m_pc~0); 203345#L607-2 is_master_triggered_~__retres1~0#1 := 0; 203346#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 203883#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 203884#L1560 assume !(0 != activate_threads_~tmp~1#1); 204001#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 203151#L626 assume !(1 == ~t1_pc~0); 203152#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 203441#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 203442#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 204417#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 203058#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 203059#L645 assume !(1 == ~t2_pc~0); 203123#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 203124#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 203235#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 203236#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 203972#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203973#L664 assume 1 == ~t3_pc~0; 204968#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 202915#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 202916#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 203596#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 203597#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 204805#L683 assume !(1 == ~t4_pc~0); 204225#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 204172#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 202939#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 202940#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 204357#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 203909#L702 assume 1 == ~t5_pc~0; 203910#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 203841#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 204351#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 204790#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 204659#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 202950#L721 assume !(1 == ~t6_pc~0); 202932#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 202933#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 203082#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 203220#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 203613#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 204284#L740 assume 1 == ~t7_pc~0; 202999#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 202831#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 202832#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 202821#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 202822#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 203535#L759 assume !(1 == ~t8_pc~0); 203536#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 203567#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 204877#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 204514#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 204515#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 204925#L778 assume 1 == ~t9_pc~0; 204748#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 202981#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 203291#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 202857#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 202858#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203163#L797 assume !(1 == ~t10_pc~0); 203164#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 203301#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 204720#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 203726#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 203727#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 204048#L816 assume 1 == ~t11_pc~0; 202893#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 202894#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 203872#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 203619#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 203620#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 204203#L835 assume 1 == ~t12_pc~0; 204063#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 203046#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 202882#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 202883#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 203783#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 203784#L854 assume !(1 == ~t13_pc~0); 203385#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 203386#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 203436#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 203080#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 203081#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 204654#L1401 assume !(1 == ~M_E~0); 203605#L1401-2 assume !(1 == ~T1_E~0); 203606#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 204270#L1411-1 assume !(1 == ~T3_E~0); 204271#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 204960#L1421-1 assume !(1 == ~T5_E~0); 207662#L1426-1 assume !(1 == ~T6_E~0); 204443#L1431-1 assume !(1 == ~T7_E~0); 202930#L1436-1 assume !(1 == ~T8_E~0); 202931#L1441-1 assume !(1 == ~T9_E~0); 203719#L1446-1 assume !(1 == ~T10_E~0); 203720#L1451-1 assume !(1 == ~T11_E~0); 205030#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 204120#L1461-1 assume !(1 == ~T13_E~0); 204121#L1466-1 assume !(1 == ~E_1~0); 207449#L1471-1 assume !(1 == ~E_2~0); 207448#L1476-1 assume !(1 == ~E_3~0); 207418#L1481-1 assume !(1 == ~E_4~0); 207284#L1486-1 assume !(1 == ~E_5~0); 207282#L1491-1 assume !(1 == ~E_6~0); 207235#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 207233#L1501-1 assume !(1 == ~E_8~0); 207214#L1506-1 assume !(1 == ~E_9~0); 207200#L1511-1 assume !(1 == ~E_10~0); 207199#L1516-1 assume !(1 == ~E_11~0); 207187#L1521-1 assume !(1 == ~E_12~0); 207178#L1526-1 assume !(1 == ~E_13~0); 207170#L1531-1 assume { :end_inline_reset_delta_events } true; 207163#L1892-2 [2024-10-25 00:40:38,963 INFO L747 eck$LassoCheckResult]: Loop: 207163#L1892-2 assume !false; 207159#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 207158#L1233-1 assume !false; 207157#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 207143#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 207142#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 207141#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 207139#L1046 assume !(0 != eval_~tmp~0#1); 207138#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 207137#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 207136#L1258-3 assume !(0 == ~M_E~0); 207135#L1258-5 assume !(0 == ~T1_E~0); 207131#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 207132#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 216508#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 216506#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 216504#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 216502#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 216500#L1293-3 assume !(0 == ~T8_E~0); 216499#L1298-3 assume !(0 == ~T9_E~0); 216496#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 216494#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 216492#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 216490#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 216488#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 216486#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 216483#L1333-3 assume !(0 == ~E_3~0); 216481#L1338-3 assume !(0 == ~E_4~0); 216479#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 216477#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 216475#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 216473#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 216470#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 216468#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 216466#L1373-3 assume !(0 == ~E_11~0); 216464#L1378-3 assume !(0 == ~E_12~0); 216462#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 216460#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 207073#L607-42 assume !(1 == ~m_pc~0); 207070#L607-44 is_master_triggered_~__retres1~0#1 := 0; 207068#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 207066#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 207064#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 207062#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 207059#L626-42 assume !(1 == ~t1_pc~0); 207057#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 207054#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 207052#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 207050#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 207048#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 207045#L645-42 assume !(1 == ~t2_pc~0); 207043#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 207040#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 207041#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 213086#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 213085#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213084#L664-42 assume !(1 == ~t3_pc~0); 213082#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 213079#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 213076#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 213074#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 213072#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 213070#L683-42 assume !(1 == ~t4_pc~0); 213067#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 213065#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 213063#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 213061#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 213059#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 213057#L702-42 assume !(1 == ~t5_pc~0); 213055#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 213052#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 213050#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 213048#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 213046#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 213044#L721-42 assume 1 == ~t6_pc~0; 213042#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 213039#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213037#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 213035#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 206976#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 206977#L740-42 assume !(1 == ~t7_pc~0); 212681#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 212678#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 212676#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 212674#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 212672#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 212670#L759-42 assume 1 == ~t8_pc~0; 212667#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 212664#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 212662#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 212660#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 212658#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 212656#L778-42 assume 1 == ~t9_pc~0; 212654#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 206949#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 206947#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 206945#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 206942#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 206940#L797-42 assume !(1 == ~t10_pc~0); 206937#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 206934#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 206931#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 206932#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 212021#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 212019#L816-42 assume 1 == ~t11_pc~0; 212016#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 212013#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 212011#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 212008#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 212006#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 212005#L835-42 assume 1 == ~t12_pc~0; 212003#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 212002#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 212001#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 212000#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 211999#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 211998#L854-42 assume 1 == ~t13_pc~0; 211997#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 211722#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 211719#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 211717#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 211715#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 208272#L1401-3 assume !(1 == ~M_E~0); 208268#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 208266#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 206871#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 208263#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 208261#L1421-3 assume !(1 == ~T5_E~0); 208258#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 208256#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 208254#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 206856#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 208132#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 208003#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 208001#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 207999#L1461-3 assume !(1 == ~T13_E~0); 207998#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 207996#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 207994#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 207878#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 207876#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 207874#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 207872#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 207871#L1501-3 assume !(1 == ~E_8~0); 207870#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 207868#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 207739#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 207734#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 207732#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 207730#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 207679#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 207535#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 207533#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 207473#L1911 assume !(0 == start_simulation_~tmp~3#1); 207397#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 207271#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 207227#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 207210#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 207196#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 207186#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 207177#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 207169#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 207163#L1892-2 [2024-10-25 00:40:38,964 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:38,964 INFO L85 PathProgramCache]: Analyzing trace with hash -1648097194, now seen corresponding path program 1 times [2024-10-25 00:40:38,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:38,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007728546] [2024-10-25 00:40:38,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:38,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:38,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:39,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:39,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:39,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007728546] [2024-10-25 00:40:39,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007728546] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:39,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:39,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:39,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [418837104] [2024-10-25 00:40:39,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:39,020 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:39,021 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:39,021 INFO L85 PathProgramCache]: Analyzing trace with hash 1413495345, now seen corresponding path program 1 times [2024-10-25 00:40:39,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:39,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377594620] [2024-10-25 00:40:39,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:39,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:39,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:39,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:39,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:39,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [377594620] [2024-10-25 00:40:39,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [377594620] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:39,063 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:39,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:39,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742490453] [2024-10-25 00:40:39,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:39,064 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:39,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:39,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:39,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:39,065 INFO L87 Difference]: Start difference. First operand 50551 states and 73500 transitions. cyclomatic complexity: 22965 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:39,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:39,613 INFO L93 Difference]: Finished difference Result 97214 states and 140809 transitions. [2024-10-25 00:40:39,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97214 states and 140809 transitions. [2024-10-25 00:40:40,101 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 96872 [2024-10-25 00:40:40,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97214 states to 97214 states and 140809 transitions. [2024-10-25 00:40:40,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97214 [2024-10-25 00:40:40,645 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97214 [2024-10-25 00:40:40,646 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97214 states and 140809 transitions. [2024-10-25 00:40:40,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:40,703 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97214 states and 140809 transitions. [2024-10-25 00:40:40,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97214 states and 140809 transitions. [2024-10-25 00:40:41,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97214 to 97150. [2024-10-25 00:40:41,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97150 states, 97150 states have (on average 1.4487390633041688) internal successors, (140745), 97149 states have internal predecessors, (140745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:41,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97150 states to 97150 states and 140745 transitions. [2024-10-25 00:40:41,944 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97150 states and 140745 transitions. [2024-10-25 00:40:41,945 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:41,945 INFO L425 stractBuchiCegarLoop]: Abstraction has 97150 states and 140745 transitions. [2024-10-25 00:40:41,945 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-25 00:40:41,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97150 states and 140745 transitions. [2024-10-25 00:40:42,458 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 96808 [2024-10-25 00:40:42,458 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:42,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:42,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:42,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:42,461 INFO L745 eck$LassoCheckResult]: Stem: 350859#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 350860#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 351789#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 351790#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 352631#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 352215#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 352216#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 351084#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 351085#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 351575#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 351405#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 351406#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 351152#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 351153#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 351581#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 351778#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 351952#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 351987#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 351168#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 351169#L1258 assume !(0 == ~M_E~0); 352474#L1258-2 assume !(0 == ~T1_E~0); 351491#L1263-1 assume !(0 == ~T2_E~0); 351492#L1268-1 assume !(0 == ~T3_E~0); 351827#L1273-1 assume !(0 == ~T4_E~0); 352452#L1278-1 assume !(0 == ~T5_E~0); 352280#L1283-1 assume !(0 == ~T6_E~0); 352281#L1288-1 assume !(0 == ~T7_E~0); 352570#L1293-1 assume !(0 == ~T8_E~0); 352556#L1298-1 assume !(0 == ~T9_E~0); 352469#L1303-1 assume !(0 == ~T10_E~0); 350960#L1308-1 assume !(0 == ~T11_E~0); 350901#L1313-1 assume !(0 == ~T12_E~0); 350902#L1318-1 assume !(0 == ~T13_E~0); 350906#L1323-1 assume !(0 == ~E_1~0); 350907#L1328-1 assume !(0 == ~E_2~0); 351094#L1333-1 assume !(0 == ~E_3~0); 352135#L1338-1 assume !(0 == ~E_4~0); 352136#L1343-1 assume !(0 == ~E_5~0); 352252#L1348-1 assume !(0 == ~E_6~0); 352603#L1353-1 assume !(0 == ~E_7~0); 351850#L1358-1 assume !(0 == ~E_8~0); 351851#L1363-1 assume !(0 == ~E_9~0); 352159#L1368-1 assume !(0 == ~E_10~0); 350751#L1373-1 assume !(0 == ~E_11~0); 350752#L1378-1 assume !(0 == ~E_12~0); 351039#L1383-1 assume !(0 == ~E_13~0); 351040#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 351854#L607 assume !(1 == ~m_pc~0); 351113#L607-2 is_master_triggered_~__retres1~0#1 := 0; 351114#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 351641#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 351642#L1560 assume !(0 != activate_threads_~tmp~1#1); 351755#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350919#L626 assume !(1 == ~t1_pc~0); 350920#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 351211#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 351212#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 352143#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 350828#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350829#L645 assume !(1 == ~t2_pc~0); 350891#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 350892#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 351007#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 351008#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 351728#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 351729#L664 assume !(1 == ~t3_pc~0); 352179#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 350690#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350691#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 351361#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 351362#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 352484#L683 assume !(1 == ~t4_pc~0); 351970#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 351923#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350710#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350711#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 352087#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 351669#L702 assume 1 == ~t5_pc~0; 351670#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 351597#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 352081#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 352472#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 352360#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350725#L721 assume !(1 == ~t6_pc~0); 350703#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 350704#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350851#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 350990#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 351377#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 352021#L740 assume 1 == ~t7_pc~0; 350767#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 350603#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350604#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 350593#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 350594#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 351300#L759 assume !(1 == ~t8_pc~0); 351301#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 351331#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 352546#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 352226#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 352227#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 352568#L778 assume 1 == ~t9_pc~0; 352432#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 350750#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 351060#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 350629#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 350630#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 350934#L797 assume !(1 == ~t10_pc~0); 350935#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 351070#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 352405#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 351487#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 351488#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 351806#L816 assume 1 == ~t11_pc~0; 350666#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 350667#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 351628#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 351383#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 351384#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 351951#L835 assume 1 == ~t12_pc~0; 351822#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 350814#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 350654#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 350655#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 351543#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 351544#L854 assume !(1 == ~t13_pc~0); 351154#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 351155#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 351206#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 350849#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 350850#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 352353#L1401 assume !(1 == ~M_E~0); 351370#L1401-2 assume !(1 == ~T1_E~0); 351371#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 352361#L1411-1 assume !(1 == ~T3_E~0); 352587#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 352588#L1421-1 assume !(1 == ~T5_E~0); 351150#L1426-1 assume !(1 == ~T6_E~0); 351151#L1431-1 assume !(1 == ~T7_E~0); 350701#L1436-1 assume !(1 == ~T8_E~0); 350702#L1441-1 assume !(1 == ~T9_E~0); 351482#L1446-1 assume !(1 == ~T10_E~0); 351483#L1451-1 assume !(1 == ~T11_E~0); 352638#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 351875#L1461-1 assume !(1 == ~T13_E~0); 351876#L1466-1 assume !(1 == ~E_1~0); 358346#L1471-1 assume !(1 == ~E_2~0); 358344#L1476-1 assume !(1 == ~E_3~0); 358315#L1481-1 assume !(1 == ~E_4~0); 358313#L1486-1 assume !(1 == ~E_5~0); 358311#L1491-1 assume !(1 == ~E_6~0); 358309#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 358270#L1501-1 assume !(1 == ~E_8~0); 358227#L1506-1 assume !(1 == ~E_9~0); 358198#L1511-1 assume !(1 == ~E_10~0); 358184#L1516-1 assume !(1 == ~E_11~0); 358172#L1521-1 assume !(1 == ~E_12~0); 358163#L1526-1 assume !(1 == ~E_13~0); 358155#L1531-1 assume { :end_inline_reset_delta_events } true; 358148#L1892-2 [2024-10-25 00:40:42,462 INFO L747 eck$LassoCheckResult]: Loop: 358148#L1892-2 assume !false; 358144#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 358143#L1233-1 assume !false; 358142#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 358128#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 358127#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 358126#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 358125#L1046 assume !(0 != eval_~tmp~0#1); 358124#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 358123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 358122#L1258-3 assume !(0 == ~M_E~0); 358121#L1258-5 assume !(0 == ~T1_E~0); 358118#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 358119#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 358110#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 358111#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 358102#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 358103#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 358094#L1293-3 assume !(0 == ~T8_E~0); 358095#L1298-3 assume !(0 == ~T9_E~0); 358086#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 358087#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 358078#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 358079#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 358070#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 358071#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 358062#L1333-3 assume !(0 == ~E_3~0); 358063#L1338-3 assume !(0 == ~E_4~0); 358054#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 358055#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 358046#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 358047#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 358038#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 358039#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 358030#L1373-3 assume !(0 == ~E_11~0); 358031#L1378-3 assume !(0 == ~E_12~0); 358022#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 358023#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 358015#L607-42 assume !(1 == ~m_pc~0); 358014#L607-44 is_master_triggered_~__retres1~0#1 := 0; 358005#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 358006#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 357997#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 357998#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 357990#L626-42 assume 1 == ~t1_pc~0; 357985#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 357986#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 357978#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 357979#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 357969#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 357970#L645-42 assume !(1 == ~t2_pc~0); 357961#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 357962#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 357954#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 357955#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 357945#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 357946#L664-42 assume !(1 == ~t3_pc~0); 357938#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 357939#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 357931#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 357932#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 357922#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 357923#L683-42 assume 1 == ~t4_pc~0; 376227#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 357911#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 357912#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 357903#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 357904#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 357896#L702-42 assume !(1 == ~t5_pc~0); 357893#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 357892#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 357884#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 357885#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 357875#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 357876#L721-42 assume 1 == ~t6_pc~0; 376219#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 357863#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 357864#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 357855#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 357856#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 357848#L740-42 assume !(1 == ~t7_pc~0); 357845#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 357844#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 357837#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 357833#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 357834#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 357826#L759-42 assume 1 == ~t8_pc~0; 357821#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 357822#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 357814#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 357815#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 357805#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 357806#L778-42 assume 1 == ~t9_pc~0; 376204#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 357793#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 357794#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 376200#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 357788#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 357789#L797-42 assume 1 == ~t10_pc~0; 357782#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 357783#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 357778#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 357779#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 357771#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 357772#L816-42 assume 1 == ~t11_pc~0; 357765#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 357764#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 357757#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 357758#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 357751#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 357752#L835-42 assume !(1 == ~t12_pc~0); 357744#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 357743#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 376192#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 357734#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 357735#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 357726#L854-42 assume !(1 == ~t13_pc~0); 357728#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 357719#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 357715#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 357716#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 357710#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 357707#L1401-3 assume !(1 == ~M_E~0); 357705#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 357698#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 357699#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 357691#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 357692#L1421-3 assume !(1 == ~T5_E~0); 357684#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 357685#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 357678#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 357676#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 357674#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 357671#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 357672#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 358389#L1461-3 assume !(1 == ~T13_E~0); 358387#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 358384#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 358382#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 358348#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 358347#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 358345#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 358343#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 358341#L1501-3 assume !(1 == ~E_8~0); 358305#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 358303#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 358302#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 358299#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 358298#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 358297#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 358266#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 358255#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 358254#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 358252#L1911 assume !(0 == start_simulation_~tmp~3#1); 358250#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 358221#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 358197#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 358195#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 358181#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 358171#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 358162#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 358154#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 358148#L1892-2 [2024-10-25 00:40:42,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:42,463 INFO L85 PathProgramCache]: Analyzing trace with hash -1375101771, now seen corresponding path program 1 times [2024-10-25 00:40:42,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:42,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384863503] [2024-10-25 00:40:42,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:42,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:42,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:42,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:42,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:42,567 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384863503] [2024-10-25 00:40:42,567 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384863503] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:42,567 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:42,568 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-25 00:40:42,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176585987] [2024-10-25 00:40:42,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:42,568 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:42,568 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:42,569 INFO L85 PathProgramCache]: Analyzing trace with hash 579315346, now seen corresponding path program 1 times [2024-10-25 00:40:42,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:42,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752320475] [2024-10-25 00:40:42,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:42,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:42,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:42,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:42,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:42,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752320475] [2024-10-25 00:40:42,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752320475] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:42,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:42,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:42,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1861017430] [2024-10-25 00:40:42,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:42,634 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:42,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:42,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-25 00:40:42,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-25 00:40:42,635 INFO L87 Difference]: Start difference. First operand 97150 states and 140745 transitions. cyclomatic complexity: 43627 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:43,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:43,242 INFO L93 Difference]: Finished difference Result 99601 states and 143196 transitions. [2024-10-25 00:40:43,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99601 states and 143196 transitions. [2024-10-25 00:40:43,951 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99256 [2024-10-25 00:40:44,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99601 states to 99601 states and 143196 transitions. [2024-10-25 00:40:44,296 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99601 [2024-10-25 00:40:44,366 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99601 [2024-10-25 00:40:44,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99601 states and 143196 transitions. [2024-10-25 00:40:44,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:44,456 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99601 states and 143196 transitions. [2024-10-25 00:40:44,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99601 states and 143196 transitions. [2024-10-25 00:40:45,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99601 to 99601. [2024-10-25 00:40:45,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99601 states, 99601 states have (on average 1.4376964086705957) internal successors, (143196), 99600 states have internal predecessors, (143196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:45,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99601 states to 99601 states and 143196 transitions. [2024-10-25 00:40:45,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99601 states and 143196 transitions. [2024-10-25 00:40:45,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-25 00:40:45,638 INFO L425 stractBuchiCegarLoop]: Abstraction has 99601 states and 143196 transitions. [2024-10-25 00:40:45,639 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-25 00:40:45,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99601 states and 143196 transitions. [2024-10-25 00:40:45,889 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99256 [2024-10-25 00:40:45,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:45,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:45,892 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:45,892 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:45,892 INFO L745 eck$LassoCheckResult]: Stem: 547618#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 547619#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 548542#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 548543#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 549395#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 548976#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 548977#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 547838#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 547839#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 548327#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 548158#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 548159#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 547903#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 547904#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 548333#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 548533#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 548707#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 548741#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 547919#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 547920#L1258 assume !(0 == ~M_E~0); 549236#L1258-2 assume !(0 == ~T1_E~0); 548241#L1263-1 assume !(0 == ~T2_E~0); 548242#L1268-1 assume !(0 == ~T3_E~0); 548579#L1273-1 assume !(0 == ~T4_E~0); 549214#L1278-1 assume !(0 == ~T5_E~0); 549039#L1283-1 assume !(0 == ~T6_E~0); 549040#L1288-1 assume !(0 == ~T7_E~0); 549328#L1293-1 assume !(0 == ~T8_E~0); 549315#L1298-1 assume !(0 == ~T9_E~0); 549230#L1303-1 assume !(0 == ~T10_E~0); 547716#L1308-1 assume !(0 == ~T11_E~0); 547657#L1313-1 assume !(0 == ~T12_E~0); 547658#L1318-1 assume !(0 == ~T13_E~0); 547665#L1323-1 assume !(0 == ~E_1~0); 547666#L1328-1 assume !(0 == ~E_2~0); 547848#L1333-1 assume !(0 == ~E_3~0); 548893#L1338-1 assume !(0 == ~E_4~0); 548894#L1343-1 assume !(0 == ~E_5~0); 549013#L1348-1 assume !(0 == ~E_6~0); 549366#L1353-1 assume !(0 == ~E_7~0); 548602#L1358-1 assume !(0 == ~E_8~0); 548603#L1363-1 assume !(0 == ~E_9~0); 548918#L1368-1 assume !(0 == ~E_10~0); 547510#L1373-1 assume !(0 == ~E_11~0); 547511#L1378-1 assume !(0 == ~E_12~0); 547793#L1383-1 assume !(0 == ~E_13~0); 547794#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 548606#L607 assume !(1 == ~m_pc~0); 547865#L607-2 is_master_triggered_~__retres1~0#1 := 0; 547866#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 548397#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 548398#L1560 assume !(0 != activate_threads_~tmp~1#1); 548509#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 547678#L626 assume !(1 == ~t1_pc~0); 547679#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 547960#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 547961#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 548901#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 547586#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 547587#L645 assume !(1 == ~t2_pc~0); 547650#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 547651#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547759#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 547760#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 548483#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 548484#L664 assume !(1 == ~t3_pc~0); 548941#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 547447#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 547448#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 548113#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 548114#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 549249#L683 assume !(1 == ~t4_pc~0); 548724#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 548903#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 547469#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 547470#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 548845#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 548423#L702 assume 1 == ~t5_pc~0; 548424#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 548350#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548840#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 549234#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 549116#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 547484#L721 assume !(1 == ~t6_pc~0); 547462#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 547463#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 547610#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 547745#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 548129#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548779#L740 assume 1 == ~t7_pc~0; 547526#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 547363#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 547364#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 547353#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 547354#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 548052#L759 assume !(1 == ~t8_pc~0); 548053#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 548083#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 549304#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 548986#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 548987#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 549326#L778 assume 1 == ~t9_pc~0; 549193#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 547509#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 547814#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 547388#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 547389#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 547691#L797 assume !(1 == ~t10_pc~0); 547692#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 547824#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 549163#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 548237#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 548238#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 548559#L816 assume 1 == ~t11_pc~0; 547425#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 547426#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 548383#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 548135#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 548136#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 548706#L835 assume 1 == ~t12_pc~0; 548574#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 547573#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 547413#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 547414#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 548295#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 548296#L854 assume !(1 == ~t13_pc~0); 547905#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 547906#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 547955#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 547608#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 547609#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 549110#L1401 assume !(1 == ~M_E~0); 548122#L1401-2 assume !(1 == ~T1_E~0); 548123#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 549117#L1411-1 assume !(1 == ~T3_E~0); 582376#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 582374#L1421-1 assume !(1 == ~T5_E~0); 547901#L1426-1 assume !(1 == ~T6_E~0); 547902#L1431-1 assume !(1 == ~T7_E~0); 547460#L1436-1 assume !(1 == ~T8_E~0); 547461#L1441-1 assume !(1 == ~T9_E~0); 548232#L1446-1 assume !(1 == ~T10_E~0); 548233#L1451-1 assume !(1 == ~T11_E~0); 549009#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 548626#L1461-1 assume !(1 == ~T13_E~0); 548152#L1466-1 assume !(1 == ~E_1~0); 548153#L1471-1 assume !(1 == ~E_2~0); 548984#L1476-1 assume !(1 == ~E_3~0); 548985#L1481-1 assume !(1 == ~E_4~0); 583559#L1486-1 assume !(1 == ~E_5~0); 583557#L1491-1 assume !(1 == ~E_6~0); 583555#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 583553#L1501-1 assume !(1 == ~E_8~0); 583551#L1506-1 assume !(1 == ~E_9~0); 583548#L1511-1 assume !(1 == ~E_10~0); 583546#L1516-1 assume !(1 == ~E_11~0); 548181#L1521-1 assume !(1 == ~E_12~0); 583543#L1526-1 assume !(1 == ~E_13~0); 583541#L1531-1 assume { :end_inline_reset_delta_events } true; 583538#L1892-2 [2024-10-25 00:40:45,893 INFO L747 eck$LassoCheckResult]: Loop: 583538#L1892-2 assume !false; 578525#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 578524#L1233-1 assume !false; 578523#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 578496#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 578495#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 578494#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 578492#L1046 assume !(0 != eval_~tmp~0#1); 578491#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 578490#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 578489#L1258-3 assume !(0 == ~M_E~0); 578488#L1258-5 assume !(0 == ~T1_E~0); 578487#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 578486#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 578485#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 578484#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 578483#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 578482#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 578481#L1293-3 assume !(0 == ~T8_E~0); 578480#L1298-3 assume !(0 == ~T9_E~0); 578479#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 578478#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 578477#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 578476#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 578475#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 578474#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 578473#L1333-3 assume !(0 == ~E_3~0); 578472#L1338-3 assume !(0 == ~E_4~0); 578471#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 578470#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 578469#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 578467#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 578466#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 578465#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 578463#L1373-3 assume !(0 == ~E_11~0); 578462#L1378-3 assume !(0 == ~E_12~0); 578461#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 578460#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 578459#L607-42 assume !(1 == ~m_pc~0); 578457#L607-44 is_master_triggered_~__retres1~0#1 := 0; 578456#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 578455#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 578452#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 578450#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 578448#L626-42 assume 1 == ~t1_pc~0; 578445#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 578443#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 578441#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 578439#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 578436#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 578434#L645-42 assume !(1 == ~t2_pc~0); 578432#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 578430#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 578428#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 578426#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 578424#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 578422#L664-42 assume !(1 == ~t3_pc~0); 578420#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 578418#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 578416#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 578414#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 578412#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 578407#L683-42 assume 1 == ~t4_pc~0; 578408#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 578409#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 578464#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 578396#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 578394#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 578392#L702-42 assume 1 == ~t5_pc~0; 578388#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 578386#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 578384#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 578381#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 578379#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 578377#L721-42 assume !(1 == ~t6_pc~0); 578374#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 578372#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 578370#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 578367#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 578365#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 578363#L740-42 assume 1 == ~t7_pc~0; 578360#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 578358#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 578356#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 578353#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 578351#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 578349#L759-42 assume 1 == ~t8_pc~0; 578346#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 578344#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 578342#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 578339#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 578337#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 578335#L778-42 assume !(1 == ~t9_pc~0); 578332#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 578330#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 578328#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 578325#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 578323#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 578321#L797-42 assume 1 == ~t10_pc~0; 578318#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 578316#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 578314#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 578311#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 578309#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 578307#L816-42 assume !(1 == ~t11_pc~0); 578304#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 578302#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 578300#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 578297#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 578295#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 578293#L835-42 assume 1 == ~t12_pc~0; 578290#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 578288#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 578286#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 578283#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 578281#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 578279#L854-42 assume !(1 == ~t13_pc~0); 576145#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 576142#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 576140#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 576138#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 572171#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 572156#L1401-3 assume !(1 == ~M_E~0); 561960#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 569381#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 562658#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 569376#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 569374#L1421-3 assume !(1 == ~T5_E~0); 569372#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 569370#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 569368#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 569364#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 569362#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 569360#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 569358#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 569356#L1461-3 assume !(1 == ~T13_E~0); 567243#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 566137#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 564858#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 564853#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 564851#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 564849#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 564846#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 564844#L1501-3 assume !(1 == ~E_8~0); 564842#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 564840#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 564838#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 564834#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 564831#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 564829#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 561878#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 561867#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 561866#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 561863#L1911 assume !(0 == start_simulation_~tmp~3#1); 561864#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 583585#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 583575#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 583573#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 583570#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 583568#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 583566#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 583540#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 583538#L1892-2 [2024-10-25 00:40:45,893 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:45,893 INFO L85 PathProgramCache]: Analyzing trace with hash 1040734579, now seen corresponding path program 1 times [2024-10-25 00:40:45,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:45,893 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30126777] [2024-10-25 00:40:45,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:45,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:45,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:45,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:45,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:45,939 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30126777] [2024-10-25 00:40:45,939 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [30126777] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:45,939 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:45,939 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:45,939 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039177285] [2024-10-25 00:40:45,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:45,940 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:45,940 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:45,940 INFO L85 PathProgramCache]: Analyzing trace with hash -334947054, now seen corresponding path program 1 times [2024-10-25 00:40:45,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:45,940 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770753335] [2024-10-25 00:40:45,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:45,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:45,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:45,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:45,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:45,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770753335] [2024-10-25 00:40:45,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770753335] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:45,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:45,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:45,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1973262770] [2024-10-25 00:40:45,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:45,975 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:45,975 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:45,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:45,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:45,976 INFO L87 Difference]: Start difference. First operand 99601 states and 143196 transitions. cyclomatic complexity: 43627 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:46,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:46,940 INFO L93 Difference]: Finished difference Result 191608 states and 274545 transitions. [2024-10-25 00:40:46,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191608 states and 274545 transitions. [2024-10-25 00:40:48,073 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 191040 [2024-10-25 00:40:48,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191608 states to 191608 states and 274545 transitions. [2024-10-25 00:40:48,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191608 [2024-10-25 00:40:48,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191608 [2024-10-25 00:40:48,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191608 states and 274545 transitions. [2024-10-25 00:40:48,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:48,681 INFO L218 hiAutomatonCegarLoop]: Abstraction has 191608 states and 274545 transitions. [2024-10-25 00:40:48,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191608 states and 274545 transitions. [2024-10-25 00:40:50,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191608 to 191480. [2024-10-25 00:40:50,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191480 states, 191480 states have (on average 1.433136620012534) internal successors, (274417), 191479 states have internal predecessors, (274417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:51,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191480 states to 191480 states and 274417 transitions. [2024-10-25 00:40:51,181 INFO L240 hiAutomatonCegarLoop]: Abstraction has 191480 states and 274417 transitions. [2024-10-25 00:40:51,182 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:51,182 INFO L425 stractBuchiCegarLoop]: Abstraction has 191480 states and 274417 transitions. [2024-10-25 00:40:51,182 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-25 00:40:51,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191480 states and 274417 transitions. [2024-10-25 00:40:51,633 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 190912 [2024-10-25 00:40:51,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:51,634 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:51,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:51,636 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:51,636 INFO L745 eck$LassoCheckResult]: Stem: 838834#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 838835#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 839758#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 839759#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 840646#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 840209#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 840210#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 839057#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 839058#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 839554#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 839382#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 839383#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 839127#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 839128#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 839561#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 839747#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 839925#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 839960#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 839143#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 839144#L1258 assume !(0 == ~M_E~0); 840482#L1258-2 assume !(0 == ~T1_E~0); 839467#L1263-1 assume !(0 == ~T2_E~0); 839468#L1268-1 assume !(0 == ~T3_E~0); 839797#L1273-1 assume !(0 == ~T4_E~0); 840455#L1278-1 assume !(0 == ~T5_E~0); 840274#L1283-1 assume !(0 == ~T6_E~0); 840275#L1288-1 assume !(0 == ~T7_E~0); 840585#L1293-1 assume !(0 == ~T8_E~0); 840568#L1298-1 assume !(0 == ~T9_E~0); 840473#L1303-1 assume !(0 == ~T10_E~0); 838932#L1308-1 assume !(0 == ~T11_E~0); 838873#L1313-1 assume !(0 == ~T12_E~0); 838874#L1318-1 assume !(0 == ~T13_E~0); 838881#L1323-1 assume !(0 == ~E_1~0); 838882#L1328-1 assume !(0 == ~E_2~0); 839068#L1333-1 assume !(0 == ~E_3~0); 840109#L1338-1 assume !(0 == ~E_4~0); 840110#L1343-1 assume !(0 == ~E_5~0); 840247#L1348-1 assume !(0 == ~E_6~0); 840610#L1353-1 assume !(0 == ~E_7~0); 839821#L1358-1 assume !(0 == ~E_8~0); 839822#L1363-1 assume !(0 == ~E_9~0); 840146#L1368-1 assume !(0 == ~E_10~0); 838726#L1373-1 assume !(0 == ~E_11~0); 838727#L1378-1 assume !(0 == ~E_12~0); 839011#L1383-1 assume !(0 == ~E_13~0); 839012#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 839825#L607 assume !(1 == ~m_pc~0); 839090#L607-2 is_master_triggered_~__retres1~0#1 := 0; 839091#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 839622#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 839623#L1560 assume !(0 != activate_threads_~tmp~1#1); 839727#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 838894#L626 assume !(1 == ~t1_pc~0); 838895#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 839187#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839188#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 840121#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 838802#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 838803#L645 assume !(1 == ~t2_pc~0); 838866#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 838867#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 838976#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 838977#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 839702#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 839703#L664 assume !(1 == ~t3_pc~0); 840170#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 838663#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 838664#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 839337#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 839338#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 840491#L683 assume !(1 == ~t4_pc~0); 839943#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 840123#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 838685#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 838686#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 840063#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 839647#L702 assume !(1 == ~t5_pc~0); 839578#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 839579#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 840056#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 840479#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 840353#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 838700#L721 assume !(1 == ~t6_pc~0); 838678#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 838679#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 838826#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 838961#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 839353#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 839995#L740 assume 1 == ~t7_pc~0; 838743#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 838579#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 838580#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 838569#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 838570#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 839278#L759 assume !(1 == ~t8_pc~0); 839279#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 839309#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 840553#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 840220#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 840221#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 840583#L778 assume 1 == ~t9_pc~0; 840435#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 838725#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 839032#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 838604#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 838605#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 838908#L797 assume !(1 == ~t10_pc~0); 838909#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 839043#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 840402#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 839463#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 839464#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 839775#L816 assume 1 == ~t11_pc~0; 838641#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 838642#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 839610#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 839359#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 839360#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 839924#L835 assume 1 == ~t12_pc~0; 839791#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 838790#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 838629#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 838630#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 839521#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 839522#L854 assume !(1 == ~t13_pc~0); 839129#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 839130#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 839180#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 838824#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 838825#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 840346#L1401 assume !(1 == ~M_E~0); 839346#L1401-2 assume !(1 == ~T1_E~0); 839347#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 839984#L1411-1 assume !(1 == ~T3_E~0); 839985#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 839618#L1421-1 assume !(1 == ~T5_E~0); 839125#L1426-1 assume !(1 == ~T6_E~0); 839126#L1431-1 assume !(1 == ~T7_E~0); 838676#L1436-1 assume !(1 == ~T8_E~0); 838677#L1441-1 assume !(1 == ~T9_E~0); 839458#L1446-1 assume !(1 == ~T10_E~0); 839459#L1451-1 assume !(1 == ~T11_E~0); 840243#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 839846#L1461-1 assume !(1 == ~T13_E~0); 839376#L1466-1 assume !(1 == ~E_1~0); 839377#L1471-1 assume !(1 == ~E_2~0); 840218#L1476-1 assume !(1 == ~E_3~0); 840219#L1481-1 assume !(1 == ~E_4~0); 840409#L1486-1 assume !(1 == ~E_5~0); 838945#L1491-1 assume !(1 == ~E_6~0); 838614#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 838615#L1501-1 assume !(1 == ~E_8~0); 839452#L1506-1 assume !(1 == ~E_9~0); 839453#L1511-1 assume !(1 == ~E_10~0); 839405#L1516-1 assume !(1 == ~E_11~0); 838567#L1521-1 assume !(1 == ~E_12~0); 838568#L1526-1 assume !(1 == ~E_13~0); 838613#L1531-1 assume { :end_inline_reset_delta_events } true; 839151#L1892-2 [2024-10-25 00:40:51,637 INFO L747 eck$LassoCheckResult]: Loop: 839151#L1892-2 assume !false; 883368#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 883366#L1233-1 assume !false; 883363#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 882879#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 882878#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 882876#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 882872#L1046 assume !(0 != eval_~tmp~0#1); 882870#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 882868#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 882866#L1258-3 assume !(0 == ~M_E~0); 882864#L1258-5 assume !(0 == ~T1_E~0); 882862#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 882860#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 882857#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 882855#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 882853#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 882851#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 882849#L1293-3 assume !(0 == ~T8_E~0); 882847#L1298-3 assume !(0 == ~T9_E~0); 882845#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 882843#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 882841#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 882839#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 882837#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 882835#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 882833#L1333-3 assume !(0 == ~E_3~0); 882831#L1338-3 assume !(0 == ~E_4~0); 882829#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 882827#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 882825#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 882823#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 882820#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 882818#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 882816#L1373-3 assume !(0 == ~E_11~0); 882815#L1378-3 assume !(0 == ~E_12~0); 882812#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 882810#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 882808#L607-42 assume !(1 == ~m_pc~0); 882805#L607-44 is_master_triggered_~__retres1~0#1 := 0; 882803#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 882801#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 882799#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 882797#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 882795#L626-42 assume !(1 == ~t1_pc~0); 882792#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 882789#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 882787#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 882785#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 882783#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 882781#L645-42 assume !(1 == ~t2_pc~0); 882778#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 882776#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 882774#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 882772#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 882770#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 882768#L664-42 assume !(1 == ~t3_pc~0); 882765#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 882763#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 882761#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 882759#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 882757#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 882755#L683-42 assume 1 == ~t4_pc~0; 882751#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 882749#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 882747#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 882668#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 882666#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 882663#L702-42 assume !(1 == ~t5_pc~0); 882661#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 882659#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 882657#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 882655#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 882653#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 882651#L721-42 assume 1 == ~t6_pc~0; 882649#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 882646#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 882644#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 882642#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 882640#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 882638#L740-42 assume !(1 == ~t7_pc~0); 882636#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 882633#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 882631#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 882629#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 882625#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 882623#L759-42 assume !(1 == ~t8_pc~0); 882604#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 882601#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 882599#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 882597#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 882594#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 882592#L778-42 assume !(1 == ~t9_pc~0); 882589#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 882587#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 882585#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 882583#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 882580#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 882578#L797-42 assume 1 == ~t10_pc~0; 882575#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 882573#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 882571#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 882569#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 882566#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 882564#L816-42 assume !(1 == ~t11_pc~0); 882561#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 882559#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 882557#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 882555#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 882552#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 882550#L835-42 assume !(1 == ~t12_pc~0); 882548#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 882545#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 882543#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 882541#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 882538#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 882536#L854-42 assume !(1 == ~t13_pc~0); 882533#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 882531#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 882529#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 882527#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 882524#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 882522#L1401-3 assume !(1 == ~M_E~0); 881320#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 882519#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 854321#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 882516#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 882513#L1421-3 assume !(1 == ~T5_E~0); 882511#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 882509#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 882507#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 854307#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 882504#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 882501#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 882499#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 882497#L1461-3 assume !(1 == ~T13_E~0); 882495#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 882493#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 882492#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 875146#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 882487#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 882485#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 882484#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 882483#L1501-3 assume !(1 == ~E_8~0); 882482#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 882481#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 882480#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 868911#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 882479#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 882478#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 882474#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 882461#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 882460#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 882458#L1911 assume !(0 == start_simulation_~tmp~3#1); 882459#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 884485#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 884475#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 884473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 884471#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 884468#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 884466#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 884464#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 839151#L1892-2 [2024-10-25 00:40:51,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:51,638 INFO L85 PathProgramCache]: Analyzing trace with hash -944094126, now seen corresponding path program 1 times [2024-10-25 00:40:51,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:51,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350362359] [2024-10-25 00:40:51,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:51,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:51,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:51,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:51,689 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:51,689 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350362359] [2024-10-25 00:40:51,689 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350362359] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:51,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:51,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:51,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168415467] [2024-10-25 00:40:51,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:51,690 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:51,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:51,691 INFO L85 PathProgramCache]: Analyzing trace with hash -453712562, now seen corresponding path program 1 times [2024-10-25 00:40:51,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:51,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731114023] [2024-10-25 00:40:51,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:51,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:51,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:51,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:51,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:51,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731114023] [2024-10-25 00:40:51,725 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1731114023] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:51,725 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:51,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:51,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499215155] [2024-10-25 00:40:51,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:51,726 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:51,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:51,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-25 00:40:51,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-25 00:40:51,727 INFO L87 Difference]: Start difference. First operand 191480 states and 274417 transitions. cyclomatic complexity: 83001 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:54,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:54,084 INFO L93 Difference]: Finished difference Result 459055 states and 654742 transitions. [2024-10-25 00:40:54,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 459055 states and 654742 transitions. [2024-10-25 00:40:56,848 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 457592 [2024-10-25 00:40:57,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 459055 states to 459055 states and 654742 transitions. [2024-10-25 00:40:57,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 459055 [2024-10-25 00:40:58,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 459055 [2024-10-25 00:40:58,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 459055 states and 654742 transitions. [2024-10-25 00:40:59,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:59,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 459055 states and 654742 transitions. [2024-10-25 00:40:59,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 459055 states and 654742 transitions. [2024-10-25 00:41:03,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 459055 to 367895. [2024-10-25 00:41:03,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 367895 states, 367895 states have (on average 1.4288805229753054) internal successors, (525678), 367894 states have internal predecessors, (525678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:41:05,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 367895 states to 367895 states and 525678 transitions. [2024-10-25 00:41:05,193 INFO L240 hiAutomatonCegarLoop]: Abstraction has 367895 states and 525678 transitions. [2024-10-25 00:41:05,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-25 00:41:05,194 INFO L425 stractBuchiCegarLoop]: Abstraction has 367895 states and 525678 transitions. [2024-10-25 00:41:05,194 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-25 00:41:05,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 367895 states and 525678 transitions. [2024-10-25 00:41:06,149 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 367008 [2024-10-25 00:41:06,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:41:06,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:41:06,152 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:41:06,152 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:41:06,152 INFO L745 eck$LassoCheckResult]: Stem: 1489375#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1489376#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1490305#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1490306#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1491213#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1490745#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1490746#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1489600#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1489601#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1490096#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1489923#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1489924#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1489667#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1489668#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1490102#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1490295#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1490468#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1490504#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1489683#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1489684#L1258 assume !(0 == ~M_E~0); 1491032#L1258-2 assume !(0 == ~T1_E~0); 1490008#L1263-1 assume !(0 == ~T2_E~0); 1490009#L1268-1 assume !(0 == ~T3_E~0); 1490342#L1273-1 assume !(0 == ~T4_E~0); 1491004#L1278-1 assume !(0 == ~T5_E~0); 1490818#L1283-1 assume !(0 == ~T6_E~0); 1490819#L1288-1 assume !(0 == ~T7_E~0); 1491139#L1293-1 assume !(0 == ~T8_E~0); 1491117#L1298-1 assume !(0 == ~T9_E~0); 1491022#L1303-1 assume !(0 == ~T10_E~0); 1489474#L1308-1 assume !(0 == ~T11_E~0); 1489417#L1313-1 assume !(0 == ~T12_E~0); 1489418#L1318-1 assume !(0 == ~T13_E~0); 1489422#L1323-1 assume !(0 == ~E_1~0); 1489423#L1328-1 assume !(0 == ~E_2~0); 1489611#L1333-1 assume !(0 == ~E_3~0); 1490652#L1338-1 assume !(0 == ~E_4~0); 1490653#L1343-1 assume !(0 == ~E_5~0); 1490783#L1348-1 assume !(0 == ~E_6~0); 1491174#L1353-1 assume !(0 == ~E_7~0); 1490365#L1358-1 assume !(0 == ~E_8~0); 1490366#L1363-1 assume !(0 == ~E_9~0); 1490680#L1368-1 assume !(0 == ~E_10~0); 1489270#L1373-1 assume !(0 == ~E_11~0); 1489271#L1378-1 assume !(0 == ~E_12~0); 1489551#L1383-1 assume !(0 == ~E_13~0); 1489552#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1490370#L607 assume !(1 == ~m_pc~0); 1489630#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1489631#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1490162#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1490163#L1560 assume !(0 != activate_threads_~tmp~1#1); 1490273#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1489435#L626 assume !(1 == ~t1_pc~0); 1489436#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1489726#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1489727#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1490660#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1489344#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1489345#L645 assume !(1 == ~t2_pc~0); 1489407#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1489408#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1489520#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1489521#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1490246#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1490247#L664 assume !(1 == ~t3_pc~0); 1490701#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1489210#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1489211#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1489878#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1489879#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1491043#L683 assume !(1 == ~t4_pc~0); 1490486#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1490662#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1489230#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1489231#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1490604#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1490187#L702 assume !(1 == ~t5_pc~0); 1490117#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1490118#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1490598#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1491026#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1490905#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1489245#L721 assume !(1 == ~t6_pc~0); 1489223#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1489224#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1489367#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1489504#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1489894#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1490536#L740 assume !(1 == ~t7_pc~0); 1490537#L740-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1489124#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1489125#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1489114#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1489115#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1489815#L759 assume !(1 == ~t8_pc~0); 1489816#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1489847#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1491105#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1490757#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1490758#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1491136#L778 assume 1 == ~t9_pc~0; 1490984#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1489269#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1489573#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1489149#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1489150#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1489449#L797 assume !(1 == ~t10_pc~0); 1489450#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1489585#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1490954#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1490004#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1490005#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1490322#L816 assume 1 == ~t11_pc~0; 1489186#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1489187#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1490150#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1489900#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1489901#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1490467#L835 assume 1 == ~t12_pc~0; 1490337#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1489331#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1489174#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1489175#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1490063#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1490064#L854 assume !(1 == ~t13_pc~0); 1489669#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1489670#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1489721#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1489365#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1489366#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1490894#L1401 assume !(1 == ~M_E~0); 1489887#L1401-2 assume !(1 == ~T1_E~0); 1489888#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1490525#L1411-1 assume !(1 == ~T3_E~0); 1490526#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1490158#L1421-1 assume !(1 == ~T5_E~0); 1489665#L1426-1 assume !(1 == ~T6_E~0); 1489666#L1431-1 assume !(1 == ~T7_E~0); 1489221#L1436-1 assume !(1 == ~T8_E~0); 1489222#L1441-1 assume !(1 == ~T9_E~0); 1489999#L1446-1 assume !(1 == ~T10_E~0); 1490000#L1451-1 assume !(1 == ~T11_E~0); 1490779#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1490390#L1461-1 assume !(1 == ~T13_E~0); 1489917#L1466-1 assume !(1 == ~E_1~0); 1489918#L1471-1 assume !(1 == ~E_2~0); 1490755#L1476-1 assume !(1 == ~E_3~0); 1490756#L1481-1 assume !(1 == ~E_4~0); 1490961#L1486-1 assume !(1 == ~E_5~0); 1489489#L1491-1 assume !(1 == ~E_6~0); 1489159#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1489160#L1501-1 assume !(1 == ~E_8~0); 1489993#L1506-1 assume !(1 == ~E_9~0); 1489994#L1511-1 assume !(1 == ~E_10~0); 1489945#L1516-1 assume !(1 == ~E_11~0); 1489946#L1521-1 assume !(1 == ~E_12~0); 1632290#L1526-1 assume !(1 == ~E_13~0); 1632287#L1531-1 assume { :end_inline_reset_delta_events } true; 1632284#L1892-2 [2024-10-25 00:41:06,153 INFO L747 eck$LassoCheckResult]: Loop: 1632284#L1892-2 assume !false; 1583567#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1583565#L1233-1 assume !false; 1583563#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1577279#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1577277#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1577275#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1577271#L1046 assume !(0 != eval_~tmp~0#1); 1577272#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1632667#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1632665#L1258-3 assume !(0 == ~M_E~0); 1632663#L1258-5 assume !(0 == ~T1_E~0); 1632661#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1632659#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1632657#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1632654#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1632652#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1632650#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1632648#L1293-3 assume !(0 == ~T8_E~0); 1632646#L1298-3 assume !(0 == ~T9_E~0); 1632644#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1632642#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1632640#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1632638#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1632636#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1632634#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1632632#L1333-3 assume !(0 == ~E_3~0); 1632630#L1338-3 assume !(0 == ~E_4~0); 1632628#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1632626#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1632624#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1632622#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1632621#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1632617#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1632615#L1373-3 assume !(0 == ~E_11~0); 1632613#L1378-3 assume !(0 == ~E_12~0); 1632611#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1632608#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1632606#L607-42 assume !(1 == ~m_pc~0); 1632603#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1632601#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1632599#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1632597#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1632595#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632593#L626-42 assume 1 == ~t1_pc~0; 1632590#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1632587#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1632585#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1632583#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1632581#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1632579#L645-42 assume !(1 == ~t2_pc~0); 1632577#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1632576#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1632574#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1632572#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1632570#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1632568#L664-42 assume !(1 == ~t3_pc~0); 1632566#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1632563#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1632561#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1632559#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1632557#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1632550#L683-42 assume !(1 == ~t4_pc~0); 1632548#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1632546#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1632544#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1632542#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 1632539#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1632536#L702-42 assume !(1 == ~t5_pc~0); 1632534#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1632532#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1632530#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1632528#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1632526#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1632523#L721-42 assume !(1 == ~t6_pc~0); 1632520#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1632518#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1632516#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1632514#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1632512#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1632509#L740-42 assume !(1 == ~t7_pc~0); 1565575#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1632506#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1632504#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1632502#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 1632500#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1632497#L759-42 assume 1 == ~t8_pc~0; 1632494#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1632492#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1632490#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1632488#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1632487#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1632486#L778-42 assume !(1 == ~t9_pc~0); 1632484#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1632483#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1632482#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1632481#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1632480#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1632479#L797-42 assume 1 == ~t10_pc~0; 1632477#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1632474#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1632472#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1632470#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1632468#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1632466#L816-42 assume !(1 == ~t11_pc~0); 1632463#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1632461#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1632458#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1632456#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1632454#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1632452#L835-42 assume 1 == ~t12_pc~0; 1632449#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1632447#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1632445#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1632443#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1632441#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1632439#L854-42 assume !(1 == ~t13_pc~0); 1632436#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1632434#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1632432#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1632430#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1632428#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1632426#L1401-3 assume !(1 == ~M_E~0); 1632422#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1632420#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1623331#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1632414#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1632412#L1421-3 assume !(1 == ~T5_E~0); 1632409#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1632407#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1632405#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1632401#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1632399#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1632397#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1632395#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1632393#L1461-3 assume !(1 == ~T13_E~0); 1632391#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1632388#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1632386#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1632382#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1632380#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1632378#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1632376#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1632375#L1501-3 assume !(1 == ~E_8~0); 1632373#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1632371#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1632369#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1623283#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1632366#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1632363#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1632351#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1632339#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1632337#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1632334#L1911 assume !(0 == start_simulation_~tmp~3#1); 1632331#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1632314#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1632304#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1632302#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1632300#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1632297#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1632295#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1632286#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1632284#L1892-2 [2024-10-25 00:41:06,154 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:41:06,154 INFO L85 PathProgramCache]: Analyzing trace with hash -37337679, now seen corresponding path program 1 times [2024-10-25 00:41:06,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:41:06,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731244303] [2024-10-25 00:41:06,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:41:06,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:41:06,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:41:06,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:41:06,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:41:06,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731244303] [2024-10-25 00:41:06,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1731244303] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:41:06,196 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:41:06,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:41:06,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044178580] [2024-10-25 00:41:06,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:41:06,197 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:41:06,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:41:06,197 INFO L85 PathProgramCache]: Analyzing trace with hash 188398893, now seen corresponding path program 1 times [2024-10-25 00:41:06,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:41:06,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371640731] [2024-10-25 00:41:06,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:41:06,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:41:06,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:41:06,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:41:06,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:41:06,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371640731] [2024-10-25 00:41:06,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1371640731] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:41:06,232 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:41:06,232 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:41:06,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732802093] [2024-10-25 00:41:06,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:41:06,233 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:41:06,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:41:06,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:41:06,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:41:06,233 INFO L87 Difference]: Start difference. First operand 367895 states and 525678 transitions. cyclomatic complexity: 157847 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:41:09,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:41:09,944 INFO L93 Difference]: Finished difference Result 706678 states and 1006731 transitions. [2024-10-25 00:41:09,944 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 706678 states and 1006731 transitions.