./Ultimate.py --spec /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/properties/termination.prp --file /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4a390ef5 Calling Ultimate with: /root/.sdkman/candidates/java/current/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4a390ef-m [2024-10-25 00:40:30,415 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-25 00:40:30,484 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-25 00:40:30,490 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-25 00:40:30,491 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-25 00:40:30,522 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-25 00:40:30,523 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-25 00:40:30,524 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-25 00:40:30,524 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-25 00:40:30,525 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-25 00:40:30,526 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-25 00:40:30,526 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-25 00:40:30,527 INFO L153 SettingsManager]: * Use SBE=true [2024-10-25 00:40:30,527 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-25 00:40:30,527 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-25 00:40:30,527 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-25 00:40:30,528 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-25 00:40:30,531 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-25 00:40:30,531 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-25 00:40:30,531 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-25 00:40:30,532 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-25 00:40:30,532 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-25 00:40:30,533 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-25 00:40:30,533 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-25 00:40:30,533 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-25 00:40:30,534 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-25 00:40:30,534 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-25 00:40:30,534 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-25 00:40:30,535 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-25 00:40:30,535 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-25 00:40:30,535 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-25 00:40:30,536 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-25 00:40:30,536 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-25 00:40:30,536 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-25 00:40:30,537 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-25 00:40:30,537 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-25 00:40:30,537 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-25 00:40:30,537 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-25 00:40:30,538 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-25 00:40:30,538 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2024-10-25 00:40:30,835 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-25 00:40:30,865 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-25 00:40:30,869 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-25 00:40:30,871 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-25 00:40:30,871 INFO L274 PluginConnector]: CDTParser initialized [2024-10-25 00:40:30,872 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c [2024-10-25 00:40:32,352 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-25 00:40:32,578 INFO L384 CDTParser]: Found 1 translation units. [2024-10-25 00:40:32,579 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c [2024-10-25 00:40:32,595 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8297f5c59/64fd65636237400f9dffe8773074b361/FLAG3f1284d1f [2024-10-25 00:40:32,936 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8297f5c59/64fd65636237400f9dffe8773074b361 [2024-10-25 00:40:32,938 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-25 00:40:32,939 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-25 00:40:32,941 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-25 00:40:32,941 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-25 00:40:32,946 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-25 00:40:32,947 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.10 12:40:32" (1/1) ... [2024-10-25 00:40:32,948 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@587b5a41 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:32, skipping insertion in model container [2024-10-25 00:40:32,948 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.10 12:40:32" (1/1) ... [2024-10-25 00:40:32,998 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-25 00:40:33,329 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-25 00:40:33,347 INFO L200 MainTranslator]: Completed pre-run [2024-10-25 00:40:33,466 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-25 00:40:33,495 INFO L204 MainTranslator]: Completed translation [2024-10-25 00:40:33,496 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33 WrapperNode [2024-10-25 00:40:33,496 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-25 00:40:33,497 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-25 00:40:33,497 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-25 00:40:33,498 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-25 00:40:33,504 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,520 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,611 INFO L138 Inliner]: procedures = 56, calls = 72, calls flagged for inlining = 67, calls inlined = 304, statements flattened = 4745 [2024-10-25 00:40:33,612 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-25 00:40:33,612 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-25 00:40:33,613 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-25 00:40:33,613 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-25 00:40:33,624 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,628 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,640 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,689 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-25 00:40:33,689 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,690 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,740 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,782 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,795 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,809 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,825 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-25 00:40:33,827 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-25 00:40:33,827 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-25 00:40:33,827 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-25 00:40:33,828 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (1/1) ... [2024-10-25 00:40:33,834 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-25 00:40:33,845 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-10-25 00:40:33,865 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-25 00:40:33,871 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-25 00:40:33,962 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-25 00:40:33,963 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-25 00:40:33,964 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-25 00:40:33,966 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-25 00:40:34,135 INFO L238 CfgBuilder]: Building ICFG [2024-10-25 00:40:34,137 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-25 00:40:37,109 INFO L? ?]: Removed 1014 outVars from TransFormulas that were not future-live. [2024-10-25 00:40:37,109 INFO L287 CfgBuilder]: Performing block encoding [2024-10-25 00:40:37,164 INFO L309 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-25 00:40:37,164 INFO L314 CfgBuilder]: Removed 18 assume(true) statements. [2024-10-25 00:40:37,164 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.10 12:40:37 BoogieIcfgContainer [2024-10-25 00:40:37,165 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-25 00:40:37,166 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-25 00:40:37,166 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-25 00:40:37,170 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-25 00:40:37,170 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-25 00:40:37,171 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 25.10 12:40:32" (1/3) ... [2024-10-25 00:40:37,172 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@467ab067 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.10 12:40:37, skipping insertion in model container [2024-10-25 00:40:37,173 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-25 00:40:37,173 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.10 12:40:33" (2/3) ... [2024-10-25 00:40:37,173 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@467ab067 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.10 12:40:37, skipping insertion in model container [2024-10-25 00:40:37,173 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-25 00:40:37,173 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.10 12:40:37" (3/3) ... [2024-10-25 00:40:37,175 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.16.cil.c [2024-10-25 00:40:37,281 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-25 00:40:37,281 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-25 00:40:37,281 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-25 00:40:37,282 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-25 00:40:37,282 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-25 00:40:37,282 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-25 00:40:37,282 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-25 00:40:37,282 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-25 00:40:37,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2069 states, 2068 states have (on average 1.4956479690522244) internal successors, (3093), 2068 states have internal predecessors, (3093), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:37,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1880 [2024-10-25 00:40:37,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:37,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:37,421 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:37,421 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:37,421 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-25 00:40:37,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2069 states, 2068 states have (on average 1.4956479690522244) internal successors, (3093), 2068 states have internal predecessors, (3093), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:37,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1880 [2024-10-25 00:40:37,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:37,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:37,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:37,463 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:37,475 INFO L745 eck$LassoCheckResult]: Stem: 166#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1978#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 754#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1975#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1939#L939true assume !(1 == ~m_i~0);~m_st~0 := 2; 468#L939-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1678#L944-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 303#L949-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1342#L954-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1984#L959-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 677#L964-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1184#L969-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1792#L974-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 610#L979-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 959#L984-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 249#L989-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 448#L994-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1215#L999-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 574#L1004-1true assume !(1 == ~t14_i~0);~t14_st~0 := 2; 44#L1009-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124#L1342true assume !(0 == ~M_E~0); 428#L1342-2true assume !(0 == ~T1_E~0); 1624#L1347-1true assume !(0 == ~T2_E~0); 1316#L1352-1true assume !(0 == ~T3_E~0); 1083#L1357-1true assume !(0 == ~T4_E~0); 443#L1362-1true assume !(0 == ~T5_E~0); 1395#L1367-1true assume !(0 == ~T6_E~0); 204#L1372-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 559#L1377-1true assume !(0 == ~T8_E~0); 392#L1382-1true assume !(0 == ~T9_E~0); 952#L1387-1true assume !(0 == ~T10_E~0); 1536#L1392-1true assume !(0 == ~T11_E~0); 415#L1397-1true assume !(0 == ~T12_E~0); 1693#L1402-1true assume !(0 == ~T13_E~0); 216#L1407-1true assume !(0 == ~T14_E~0); 1873#L1412-1true assume 0 == ~E_1~0;~E_1~0 := 1; 1210#L1417-1true assume !(0 == ~E_2~0); 2068#L1422-1true assume !(0 == ~E_3~0); 1692#L1427-1true assume !(0 == ~E_4~0); 320#L1432-1true assume !(0 == ~E_5~0); 1544#L1437-1true assume !(0 == ~E_6~0); 1129#L1442-1true assume !(0 == ~E_7~0); 1467#L1447-1true assume !(0 == ~E_8~0); 945#L1452-1true assume 0 == ~E_9~0;~E_9~0 := 1; 109#L1457-1true assume !(0 == ~E_10~0); 1161#L1462-1true assume !(0 == ~E_11~0); 1870#L1467-1true assume !(0 == ~E_12~0); 1178#L1472-1true assume !(0 == ~E_13~0); 1370#L1477-1true assume !(0 == ~E_14~0); 897#L1482-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199#L646true assume 1 == ~m_pc~0; 618#L647true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 626#L657true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 644#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 250#L1666true assume !(0 != activate_threads_~tmp~1#1); 2003#L1666-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1757#L665true assume !(1 == ~t1_pc~0); 534#L665-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1208#L676true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1050#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1715#L1674true assume !(0 != activate_threads_~tmp___0~0#1); 788#L1674-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 894#L684true assume 1 == ~t2_pc~0; 1882#L685true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 885#L695true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1323#L1682true assume !(0 != activate_threads_~tmp___1~0#1); 1827#L1682-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1803#L703true assume !(1 == ~t3_pc~0); 332#L703-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1413#L714true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1033#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32#L1690true assume !(0 != activate_threads_~tmp___2~0#1); 265#L1690-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1339#L722true assume 1 == ~t4_pc~0; 758#L723true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 597#L733true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1630#L1698true assume !(0 != activate_threads_~tmp___3~0#1); 645#L1698-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125#L741true assume 1 == ~t5_pc~0; 279#L742true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 816#L752true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1670#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 867#L1706true assume !(0 != activate_threads_~tmp___4~0#1); 1394#L1706-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 429#L760true assume !(1 == ~t6_pc~0); 743#L760-2true is_transmit6_triggered_~__retres1~6#1 := 0; 992#L771true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 238#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1671#L1714true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 723#L1714-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1412#L779true assume 1 == ~t7_pc~0; 141#L780true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69#L790true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1995#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1387#L1722true assume !(0 != activate_threads_~tmp___6~0#1); 287#L1722-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1702#L798true assume !(1 == ~t8_pc~0); 1955#L798-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1265#L809true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1615#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1759#L1730true assume !(0 != activate_threads_~tmp___7~0#1); 1926#L1730-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60#L817true assume 1 == ~t9_pc~0; 835#L818true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 490#L828true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 268#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1875#L1738true assume !(0 != activate_threads_~tmp___8~0#1); 255#L1738-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 780#L836true assume !(1 == ~t10_pc~0); 269#L836-2true is_transmit10_triggered_~__retres1~10#1 := 0; 229#L847true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1376#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 371#L1746true assume !(0 != activate_threads_~tmp___9~0#1); 1279#L1746-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1285#L855true assume 1 == ~t11_pc~0; 624#L856true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1154#L866true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1497#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 943#L1754true assume !(0 != activate_threads_~tmp___10~0#1); 793#L1754-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198#L874true assume !(1 == ~t12_pc~0); 1652#L874-2true is_transmit12_triggered_~__retres1~12#1 := 0; 292#L885true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2005#L1762true assume !(0 != activate_threads_~tmp___11~0#1); 48#L1762-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1874#L893true assume 1 == ~t13_pc~0; 1552#L894true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 391#L904true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1426#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1569#L1770true assume !(0 != activate_threads_~tmp___12~0#1); 1406#L1770-2true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1777#L912true assume 1 == ~t14_pc~0; 1134#L913true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 2041#L923true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1206#is_transmit14_triggered_returnLabel#1true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 165#L1778true assume !(0 != activate_threads_~tmp___13~0#1); 638#L1778-2true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1356#L1495true assume 1 == ~M_E~0;~M_E~0 := 2; 1006#L1495-2true assume !(1 == ~T1_E~0); 1683#L1500-1true assume !(1 == ~T2_E~0); 719#L1505-1true assume !(1 == ~T3_E~0); 1933#L1510-1true assume !(1 == ~T4_E~0); 765#L1515-1true assume !(1 == ~T5_E~0); 1736#L1520-1true assume !(1 == ~T6_E~0); 1402#L1525-1true assume !(1 == ~T7_E~0); 1034#L1530-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 252#L1535-1true assume !(1 == ~T9_E~0); 1851#L1540-1true assume !(1 == ~T10_E~0); 15#L1545-1true assume !(1 == ~T11_E~0); 1990#L1550-1true assume !(1 == ~T12_E~0); 129#L1555-1true assume !(1 == ~T13_E~0); 281#L1560-1true assume !(1 == ~T14_E~0); 1713#L1565-1true assume !(1 == ~E_1~0); 1946#L1570-1true assume 1 == ~E_2~0;~E_2~0 := 2; 915#L1575-1true assume !(1 == ~E_3~0); 446#L1580-1true assume !(1 == ~E_4~0); 782#L1585-1true assume !(1 == ~E_5~0); 1052#L1590-1true assume !(1 == ~E_6~0); 464#L1595-1true assume !(1 == ~E_7~0); 1911#L1600-1true assume !(1 == ~E_8~0); 727#L1605-1true assume !(1 == ~E_9~0); 1659#L1610-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1247#L1615-1true assume !(1 == ~E_11~0); 358#L1620-1true assume !(1 == ~E_12~0); 1116#L1625-1true assume !(1 == ~E_13~0); 946#L1630-1true assume !(1 == ~E_14~0); 463#L1635-1true assume { :end_inline_reset_delta_events } true; 430#L2017-2true [2024-10-25 00:40:37,483 INFO L747 eck$LassoCheckResult]: Loop: 430#L2017-2true assume !false; 47#L2018true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 236#L1316-1true assume !true; 585#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 354#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 623#L1342-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1089#L1342-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1173#L1347-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 756#L1352-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1365#L1357-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 2052#L1362-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1896#L1367-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1860#L1372-3true assume !(0 == ~T7_E~0); 38#L1377-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 486#L1382-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 379#L1387-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1135#L1392-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1967#L1397-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1676#L1402-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 711#L1407-3true assume 0 == ~T14_E~0;~T14_E~0 := 1; 178#L1412-3true assume !(0 == ~E_1~0); 1407#L1417-3true assume 0 == ~E_2~0;~E_2~0 := 1; 648#L1422-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1358#L1427-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1546#L1432-3true assume 0 == ~E_5~0;~E_5~0 := 1; 983#L1437-3true assume 0 == ~E_6~0;~E_6~0 := 1; 724#L1442-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1005#L1447-3true assume 0 == ~E_8~0;~E_8~0 := 1; 67#L1452-3true assume !(0 == ~E_9~0); 2019#L1457-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1262#L1462-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1700#L1467-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1054#L1472-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1720#L1477-3true assume 0 == ~E_14~0;~E_14~0 := 1; 177#L1482-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 517#L646-42true assume !(1 == ~m_pc~0); 1690#L646-44true is_master_triggered_~__retres1~0#1 := 0; 1319#L657-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 435#is_master_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1628#L1666-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1718#L1666-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1226#L665-42true assume 1 == ~t1_pc~0; 1190#L666-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1549#L676-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1887#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 270#L1674-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1898#L1674-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1895#L684-42true assume 1 == ~t2_pc~0; 865#L685-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1908#L695-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 668#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 674#L1682-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 774#L1682-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1750#L703-42true assume 1 == ~t3_pc~0; 957#L704-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1864#L714-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1021#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1639#L1690-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1058#L1690-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 697#L722-42true assume !(1 == ~t4_pc~0); 1499#L722-44true is_transmit4_triggered_~__retres1~4#1 := 0; 1727#L733-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1100#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 349#L1698-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1940#L1698-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1739#L741-42true assume !(1 == ~t5_pc~0); 1074#L741-44true is_transmit5_triggered_~__retres1~5#1 := 0; 601#L752-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 720#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1916#L1706-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 529#L1706-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 631#L760-42true assume !(1 == ~t6_pc~0); 869#L760-44true is_transmit6_triggered_~__retres1~6#1 := 0; 735#L771-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1649#L1714-42true assume !(0 != activate_threads_~tmp___5~0#1); 501#L1714-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1332#L779-42true assume 1 == ~t7_pc~0; 1249#L780-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1885#L790-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 741#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1710#L1722-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 228#L1722-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 496#L798-42true assume 1 == ~t8_pc~0; 1943#L799-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1443#L809-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 880#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 751#L1730-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 143#L1730-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1381#L817-42true assume !(1 == ~t9_pc~0); 1156#L817-44true is_transmit9_triggered_~__retres1~9#1 := 0; 295#L828-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1913#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1194#L1738-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 981#L1738-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1525#L836-42true assume !(1 == ~t10_pc~0); 1830#L836-44true is_transmit10_triggered_~__retres1~10#1 := 0; 317#L847-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 864#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1562#L1746-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1706#L1746-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2061#L855-42true assume 1 == ~t11_pc~0; 1730#L856-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85#L866-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1568#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1175#L1754-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2063#L1754-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 413#L874-42true assume !(1 == ~t12_pc~0); 577#L874-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1496#L885-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 701#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 896#L1762-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 163#L1762-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2001#L893-42true assume !(1 == ~t13_pc~0); 806#L893-44true is_transmit13_triggered_~__retres1~13#1 := 0; 1850#L904-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 393#is_transmit13_triggered_returnLabel#15true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 734#L1770-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 369#L1770-44true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1862#L912-42true assume !(1 == ~t14_pc~0); 988#L912-44true is_transmit14_triggered_~__retres1~14#1 := 0; 25#L923-14true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 439#is_transmit14_triggered_returnLabel#15true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1229#L1778-42true assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 226#L1778-44true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 608#L1495-3true assume !(1 == ~M_E~0); 974#L1495-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1583#L1500-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1078#L1505-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 352#L1510-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 333#L1515-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 792#L1520-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1003#L1525-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1589#L1530-3true assume !(1 == ~T8_E~0); 246#L1535-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 267#L1540-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1300#L1545-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1545#L1550-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1523#L1555-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 510#L1560-3true assume 1 == ~T14_E~0;~T14_E~0 := 2; 1027#L1565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1890#L1570-3true assume !(1 == ~E_2~0); 977#L1575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1427#L1580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1533#L1585-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1769#L1590-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1674#L1595-3true assume 1 == ~E_7~0;~E_7~0 := 2; 813#L1600-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1325#L1605-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1408#L1610-3true assume !(1 == ~E_10~0); 360#L1615-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1932#L1620-3true assume 1 == ~E_12~0;~E_12~0 := 2; 783#L1625-3true assume 1 == ~E_13~0;~E_13~0 := 2; 2055#L1630-3true assume 1 == ~E_14~0;~E_14~0 := 2; 700#L1635-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 326#L1022-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 532#L1100-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 215#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1004#L2036true assume !(0 == start_simulation_~tmp~3#1); 1183#L2036-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1641#L1022-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1428#L1100-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 736#L1991true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1744#L1998true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1404#stop_simulation_returnLabel#1true start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1821#L2049true assume !(0 != start_simulation_~tmp___0~1#1); 430#L2017-2true [2024-10-25 00:40:37,499 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:37,501 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 1 times [2024-10-25 00:40:37,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:37,510 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500135429] [2024-10-25 00:40:37,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:37,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:37,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:37,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:37,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:37,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1500135429] [2024-10-25 00:40:37,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1500135429] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:37,933 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:37,933 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:37,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844565478] [2024-10-25 00:40:37,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:37,941 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:37,943 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:37,944 INFO L85 PathProgramCache]: Analyzing trace with hash -114923038, now seen corresponding path program 1 times [2024-10-25 00:40:37,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:37,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791706831] [2024-10-25 00:40:37,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:37,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:37,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:38,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:38,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:38,039 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [791706831] [2024-10-25 00:40:38,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [791706831] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:38,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:38,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:38,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272239076] [2024-10-25 00:40:38,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:38,041 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:38,042 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:38,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-10-25 00:40:38,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-10-25 00:40:38,088 INFO L87 Difference]: Start difference. First operand has 2069 states, 2068 states have (on average 1.4956479690522244) internal successors, (3093), 2068 states have internal predecessors, (3093), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 83.5) internal successors, (167), 2 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:38,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:38,170 INFO L93 Difference]: Finished difference Result 2067 states and 3054 transitions. [2024-10-25 00:40:38,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2067 states and 3054 transitions. [2024-10-25 00:40:38,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:38,222 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2067 states to 2062 states and 3049 transitions. [2024-10-25 00:40:38,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:38,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:38,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3049 transitions. [2024-10-25 00:40:38,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:38,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3049 transitions. [2024-10-25 00:40:38,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3049 transitions. [2024-10-25 00:40:38,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:38,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4786614936954414) internal successors, (3049), 2061 states have internal predecessors, (3049), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:38,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3049 transitions. [2024-10-25 00:40:38,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3049 transitions. [2024-10-25 00:40:38,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-10-25 00:40:38,360 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3049 transitions. [2024-10-25 00:40:38,360 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-25 00:40:38,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3049 transitions. [2024-10-25 00:40:38,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:38,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:38,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:38,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:38,380 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:38,381 INFO L745 eck$LassoCheckResult]: Stem: 4502#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 4503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 5434#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5435#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6196#L939 assume !(1 == ~m_i~0);~m_st~0 := 2; 5039#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5040#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4752#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4753#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6005#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5331#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5332#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5870#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5237#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5238#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4662#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4663#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5009#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5191#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 4243#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4244#L1342 assume !(0 == ~M_E~0); 4412#L1342-2 assume !(0 == ~T1_E~0); 4976#L1347-1 assume !(0 == ~T2_E~0); 5986#L1352-1 assume !(0 == ~T3_E~0); 5777#L1357-1 assume !(0 == ~T4_E~0); 4998#L1362-1 assume !(0 == ~T5_E~0); 4999#L1367-1 assume !(0 == ~T6_E~0); 4577#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4578#L1377-1 assume !(0 == ~T8_E~0); 4916#L1382-1 assume !(0 == ~T9_E~0); 4917#L1387-1 assume !(0 == ~T10_E~0); 5658#L1392-1 assume !(0 == ~T11_E~0); 4957#L1397-1 assume !(0 == ~T12_E~0); 4958#L1402-1 assume !(0 == ~T13_E~0); 4601#L1407-1 assume !(0 == ~T14_E~0); 4602#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5902#L1417-1 assume !(0 == ~E_2~0); 5903#L1422-1 assume !(0 == ~E_3~0); 6140#L1427-1 assume !(0 == ~E_4~0); 4781#L1432-1 assume !(0 == ~E_5~0); 4782#L1437-1 assume !(0 == ~E_6~0); 5822#L1442-1 assume !(0 == ~E_7~0); 5823#L1447-1 assume !(0 == ~E_8~0); 5652#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 4381#L1457-1 assume !(0 == ~E_10~0); 4382#L1462-1 assume !(0 == ~E_11~0); 5852#L1467-1 assume !(0 == ~E_12~0); 5865#L1472-1 assume !(0 == ~E_13~0); 5866#L1477-1 assume !(0 == ~E_14~0); 5601#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4566#L646 assume 1 == ~m_pc~0; 4567#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5247#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5262#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4664#L1666 assume !(0 != activate_threads_~tmp~1#1); 4665#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6161#L665 assume !(1 == ~t1_pc~0); 5142#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5143#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5751#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5752#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 5483#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5484#L684 assume 1 == ~t2_pc~0; 5598#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5522#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4651#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 5991#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6174#L703 assume !(1 == ~t3_pc~0); 4806#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4807#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5738#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4215#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 4216#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4694#L722 assume 1 == ~t4_pc~0; 5441#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4881#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4326#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4327#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 5283#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4413#L741 assume 1 == ~t5_pc~0; 4414#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4716#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5516#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5568#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 5569#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4977#L760 assume !(1 == ~t6_pc~0); 4805#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4804#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4642#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4643#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5398#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5399#L779 assume 1 == ~t7_pc~0; 4450#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4297#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4298#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6023#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 4728#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4729#L798 assume !(1 == ~t8_pc~0); 6033#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5950#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5951#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6115#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 6163#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4276#L817 assume 1 == ~t9_pc~0; 4277#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5075#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4698#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4699#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 4676#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4677#L836 assume !(1 == ~t10_pc~0); 4700#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4626#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4627#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4882#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 4883#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5963#L855 assume 1 == ~t11_pc~0; 5258#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5259#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5846#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5649#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 5489#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4563#L874 assume !(1 == ~t12_pc~0); 4564#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4737#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4265#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4266#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 4251#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4252#L893 assume 1 == ~t13_pc~0; 6098#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4604#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4915#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 6046#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 6038#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 6039#L912 assume 1 == ~t14_pc~0; 5829#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 5830#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 5899#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4500#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 4501#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5276#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 5707#L1495-2 assume !(1 == ~T1_E~0); 5708#L1500-1 assume !(1 == ~T2_E~0); 5392#L1505-1 assume !(1 == ~T3_E~0); 5393#L1510-1 assume !(1 == ~T4_E~0); 5451#L1515-1 assume !(1 == ~T5_E~0); 5452#L1520-1 assume !(1 == ~T6_E~0); 6034#L1525-1 assume !(1 == ~T7_E~0); 5739#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4669#L1535-1 assume !(1 == ~T9_E~0); 4670#L1540-1 assume !(1 == ~T10_E~0); 4176#L1545-1 assume !(1 == ~T11_E~0); 4177#L1550-1 assume !(1 == ~T12_E~0); 4423#L1555-1 assume !(1 == ~T13_E~0); 4424#L1560-1 assume !(1 == ~T14_E~0); 4719#L1565-1 assume !(1 == ~E_1~0); 6149#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5622#L1575-1 assume !(1 == ~E_3~0); 5004#L1580-1 assume !(1 == ~E_4~0); 5005#L1585-1 assume !(1 == ~E_5~0); 5475#L1590-1 assume !(1 == ~E_6~0); 5033#L1595-1 assume !(1 == ~E_7~0); 5034#L1600-1 assume !(1 == ~E_8~0); 5406#L1605-1 assume !(1 == ~E_9~0); 5407#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5937#L1615-1 assume !(1 == ~E_11~0); 4855#L1620-1 assume !(1 == ~E_12~0); 4856#L1625-1 assume !(1 == ~E_13~0); 5653#L1630-1 assume !(1 == ~E_14~0); 5032#L1635-1 assume { :end_inline_reset_delta_events } true; 4978#L2017-2 [2024-10-25 00:40:38,385 INFO L747 eck$LassoCheckResult]: Loop: 4978#L2017-2 assume !false; 4249#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4250#L1316-1 assume !false; 4638#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5648#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4189#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4526#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5672#L1115 assume !(0 != eval_~tmp~0#1); 5203#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4850#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4851#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5257#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5784#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5437#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5438#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6017#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6189#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6181#L1372-3 assume !(0 == ~T7_E~0); 4229#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4230#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4895#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4896#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5832#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 6135#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5384#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 4524#L1412-3 assume !(0 == ~E_1~0); 4525#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5286#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5287#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6015#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5692#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5400#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5401#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4293#L1452-3 assume !(0 == ~E_9~0); 4294#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5948#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5949#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5756#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5757#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 4522#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4523#L646-42 assume 1 == ~m_pc~0; 5118#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5987#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4986#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4987#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6119#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5919#L665-42 assume 1 == ~t1_pc~0; 5877#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5879#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6094#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4701#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4702#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6188#L684-42 assume 1 == ~t2_pc~0; 5564#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5565#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5317#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5318#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5327#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5463#L703-42 assume !(1 == ~t3_pc~0); 5665#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 5664#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5728#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5729#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5761#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5367#L722-42 assume 1 == ~t4_pc~0; 5368#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5797#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5793#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4843#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4844#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6155#L741-42 assume 1 == ~t5_pc~0; 6099#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5222#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5223#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5394#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5136#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5137#L760-42 assume !(1 == ~t6_pc~0); 5264#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 5413#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4615#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4616#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 5091#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5092#L779-42 assume 1 == ~t7_pc~0; 5938#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5885#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5421#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5422#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4624#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4625#L798-42 assume !(1 == ~t8_pc~0); 4241#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 4242#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5583#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5431#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4456#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4457#L817-42 assume 1 == ~t9_pc~0; 5229#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4739#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4740#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5883#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5687#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5688#L836-42 assume 1 == ~t10_pc~0; 5788#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4776#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4777#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5563#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6101#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6143#L855-42 assume 1 == ~t11_pc~0; 6153#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4332#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4333#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5863#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5864#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4954#L874-42 assume !(1 == ~t12_pc~0); 4955#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 5182#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5372#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5373#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4496#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4497#L893-42 assume 1 == ~t13_pc~0; 5714#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5503#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4918#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4919#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4878#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 4879#L912-42 assume 1 == ~t14_pc~0; 6136#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 4199#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4200#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4992#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 4621#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4622#L1495-3 assume !(1 == ~M_E~0); 5234#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5678#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5774#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4849#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4808#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4809#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5488#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5704#L1530-3 assume !(1 == ~T8_E~0); 4658#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4659#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4697#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5978#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 6085#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5106#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 5107#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5735#L1570-3 assume !(1 == ~E_2~0); 5682#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5683#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6047#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6089#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6134#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5510#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5511#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5992#L1610-3 assume !(1 == ~E_10~0); 4859#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4860#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5476#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5477#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 5371#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4792#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4408#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4599#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4600#L2036 assume !(0 == start_simulation_~tmp~3#1); 5705#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5869#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 5023#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4245#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 4246#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5414#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6036#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 6037#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 4978#L2017-2 [2024-10-25 00:40:38,385 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:38,386 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 2 times [2024-10-25 00:40:38,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:38,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296367002] [2024-10-25 00:40:38,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:38,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:38,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:38,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:38,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:38,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296367002] [2024-10-25 00:40:38,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296367002] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:38,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:38,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:38,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2089882681] [2024-10-25 00:40:38,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:38,524 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:38,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:38,525 INFO L85 PathProgramCache]: Analyzing trace with hash -903547823, now seen corresponding path program 1 times [2024-10-25 00:40:38,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:38,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703935400] [2024-10-25 00:40:38,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:38,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:38,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:38,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:38,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:38,810 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703935400] [2024-10-25 00:40:38,810 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703935400] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:38,810 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:38,810 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:38,810 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451417175] [2024-10-25 00:40:38,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:38,811 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:38,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:38,813 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:38,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:38,817 INFO L87 Difference]: Start difference. First operand 2062 states and 3049 transitions. cyclomatic complexity: 988 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:38,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:38,864 INFO L93 Difference]: Finished difference Result 2062 states and 3048 transitions. [2024-10-25 00:40:38,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3048 transitions. [2024-10-25 00:40:38,878 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:38,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3048 transitions. [2024-10-25 00:40:38,891 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:38,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:38,893 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3048 transitions. [2024-10-25 00:40:38,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:38,898 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3048 transitions. [2024-10-25 00:40:38,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3048 transitions. [2024-10-25 00:40:38,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:38,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.478176527643065) internal successors, (3048), 2061 states have internal predecessors, (3048), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:38,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3048 transitions. [2024-10-25 00:40:38,938 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3048 transitions. [2024-10-25 00:40:38,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:38,939 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3048 transitions. [2024-10-25 00:40:38,939 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-25 00:40:38,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3048 transitions. [2024-10-25 00:40:38,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:38,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:38,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:38,958 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:38,959 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:38,959 INFO L745 eck$LassoCheckResult]: Stem: 8633#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 8634#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 9565#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9566#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10327#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 9170#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9171#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8883#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8884#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10136#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9462#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9463#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10001#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9368#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9369#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8793#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8794#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9140#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9322#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 8374#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8375#L1342 assume !(0 == ~M_E~0); 8543#L1342-2 assume !(0 == ~T1_E~0); 9107#L1347-1 assume !(0 == ~T2_E~0); 10117#L1352-1 assume !(0 == ~T3_E~0); 9908#L1357-1 assume !(0 == ~T4_E~0); 9129#L1362-1 assume !(0 == ~T5_E~0); 9130#L1367-1 assume !(0 == ~T6_E~0); 8708#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8709#L1377-1 assume !(0 == ~T8_E~0); 9047#L1382-1 assume !(0 == ~T9_E~0); 9048#L1387-1 assume !(0 == ~T10_E~0); 9789#L1392-1 assume !(0 == ~T11_E~0); 9088#L1397-1 assume !(0 == ~T12_E~0); 9089#L1402-1 assume !(0 == ~T13_E~0); 8732#L1407-1 assume !(0 == ~T14_E~0); 8733#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 10033#L1417-1 assume !(0 == ~E_2~0); 10034#L1422-1 assume !(0 == ~E_3~0); 10271#L1427-1 assume !(0 == ~E_4~0); 8912#L1432-1 assume !(0 == ~E_5~0); 8913#L1437-1 assume !(0 == ~E_6~0); 9953#L1442-1 assume !(0 == ~E_7~0); 9954#L1447-1 assume !(0 == ~E_8~0); 9783#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8512#L1457-1 assume !(0 == ~E_10~0); 8513#L1462-1 assume !(0 == ~E_11~0); 9983#L1467-1 assume !(0 == ~E_12~0); 9996#L1472-1 assume !(0 == ~E_13~0); 9997#L1477-1 assume !(0 == ~E_14~0); 9732#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8697#L646 assume 1 == ~m_pc~0; 8698#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9378#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9393#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8795#L1666 assume !(0 != activate_threads_~tmp~1#1); 8796#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10292#L665 assume !(1 == ~t1_pc~0); 9273#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9274#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9882#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9883#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 9614#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9615#L684 assume 1 == ~t2_pc~0; 9729#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9653#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8781#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8782#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 10122#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10305#L703 assume !(1 == ~t3_pc~0); 8937#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8938#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9869#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8346#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 8347#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8825#L722 assume 1 == ~t4_pc~0; 9572#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9012#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8457#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8458#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 9414#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8544#L741 assume 1 == ~t5_pc~0; 8545#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8847#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9647#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9699#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 9700#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9108#L760 assume !(1 == ~t6_pc~0); 8936#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8935#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8773#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8774#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9529#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9530#L779 assume 1 == ~t7_pc~0; 8581#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8428#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8429#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10154#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 8859#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8860#L798 assume !(1 == ~t8_pc~0); 10164#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10081#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10082#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10246#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 10294#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8407#L817 assume 1 == ~t9_pc~0; 8408#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9206#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8829#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8830#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 8807#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8808#L836 assume !(1 == ~t10_pc~0); 8831#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8757#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8758#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9013#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 9014#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10094#L855 assume 1 == ~t11_pc~0; 9389#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9390#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9977#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9780#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 9620#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8694#L874 assume !(1 == ~t12_pc~0); 8695#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8868#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8396#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8397#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 8382#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8383#L893 assume 1 == ~t13_pc~0; 10229#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8735#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9046#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10177#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 10169#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 10170#L912 assume 1 == ~t14_pc~0; 9960#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 9961#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 10030#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8631#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 8632#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9407#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 9838#L1495-2 assume !(1 == ~T1_E~0); 9839#L1500-1 assume !(1 == ~T2_E~0); 9523#L1505-1 assume !(1 == ~T3_E~0); 9524#L1510-1 assume !(1 == ~T4_E~0); 9582#L1515-1 assume !(1 == ~T5_E~0); 9583#L1520-1 assume !(1 == ~T6_E~0); 10165#L1525-1 assume !(1 == ~T7_E~0); 9870#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8800#L1535-1 assume !(1 == ~T9_E~0); 8801#L1540-1 assume !(1 == ~T10_E~0); 8307#L1545-1 assume !(1 == ~T11_E~0); 8308#L1550-1 assume !(1 == ~T12_E~0); 8554#L1555-1 assume !(1 == ~T13_E~0); 8555#L1560-1 assume !(1 == ~T14_E~0); 8850#L1565-1 assume !(1 == ~E_1~0); 10280#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9753#L1575-1 assume !(1 == ~E_3~0); 9135#L1580-1 assume !(1 == ~E_4~0); 9136#L1585-1 assume !(1 == ~E_5~0); 9606#L1590-1 assume !(1 == ~E_6~0); 9164#L1595-1 assume !(1 == ~E_7~0); 9165#L1600-1 assume !(1 == ~E_8~0); 9537#L1605-1 assume !(1 == ~E_9~0); 9538#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10068#L1615-1 assume !(1 == ~E_11~0); 8986#L1620-1 assume !(1 == ~E_12~0); 8987#L1625-1 assume !(1 == ~E_13~0); 9784#L1630-1 assume !(1 == ~E_14~0); 9163#L1635-1 assume { :end_inline_reset_delta_events } true; 9109#L2017-2 [2024-10-25 00:40:38,960 INFO L747 eck$LassoCheckResult]: Loop: 9109#L2017-2 assume !false; 8380#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8381#L1316-1 assume !false; 8769#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9779#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8320#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8657#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9803#L1115 assume !(0 != eval_~tmp~0#1); 9334#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8981#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8982#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9388#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9915#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9568#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9569#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10148#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10320#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10312#L1372-3 assume !(0 == ~T7_E~0); 8360#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8361#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9026#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9027#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9963#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10266#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9515#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 8655#L1412-3 assume !(0 == ~E_1~0); 8656#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9417#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9418#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10146#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9823#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9531#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9532#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8424#L1452-3 assume !(0 == ~E_9~0); 8425#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10079#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10080#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 9887#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9888#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 8653#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8654#L646-42 assume 1 == ~m_pc~0; 9249#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10118#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9117#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9118#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10250#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10050#L665-42 assume 1 == ~t1_pc~0; 10008#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10010#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10225#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8832#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8833#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10319#L684-42 assume !(1 == ~t2_pc~0); 9697#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9696#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9448#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9449#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9458#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9594#L703-42 assume 1 == ~t3_pc~0; 9794#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9795#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9859#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9860#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9892#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9498#L722-42 assume 1 == ~t4_pc~0; 9499#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9928#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9924#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8974#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8975#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10286#L741-42 assume !(1 == ~t5_pc~0); 9904#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 9353#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9354#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9525#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9267#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9268#L760-42 assume !(1 == ~t6_pc~0); 9395#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 9544#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8746#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8747#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 9222#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9223#L779-42 assume 1 == ~t7_pc~0; 10069#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10016#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9552#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9553#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8755#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8756#L798-42 assume !(1 == ~t8_pc~0); 8372#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 8373#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9714#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9562#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8587#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8588#L817-42 assume 1 == ~t9_pc~0; 9362#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8870#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8871#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10014#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9818#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9819#L836-42 assume !(1 == ~t10_pc~0); 9920#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 8907#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8908#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9694#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10232#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10274#L855-42 assume 1 == ~t11_pc~0; 10284#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8463#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8464#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9994#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9995#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9085#L874-42 assume !(1 == ~t12_pc~0); 9086#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 9316#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9503#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9504#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8627#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8628#L893-42 assume !(1 == ~t13_pc~0); 9633#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 9634#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9049#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9050#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 9009#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 9010#L912-42 assume !(1 == ~t14_pc~0); 9826#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 8330#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 8331#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9123#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 8752#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8753#L1495-3 assume !(1 == ~M_E~0); 9365#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9809#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9905#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8980#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8939#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8940#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9619#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9835#L1530-3 assume !(1 == ~T8_E~0); 8789#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8790#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8828#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10109#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 10216#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9237#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 9238#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9866#L1570-3 assume !(1 == ~E_2~0); 9813#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9814#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10178#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10221#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10265#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9641#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9642#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10123#L1610-3 assume !(1 == ~E_10~0); 8990#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8991#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9607#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9608#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 9502#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 8923#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8539#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8730#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8731#L2036 assume !(0 == start_simulation_~tmp~3#1); 9836#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 10000#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 9154#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8376#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 8377#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9545#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10167#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10168#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 9109#L2017-2 [2024-10-25 00:40:38,961 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:38,962 INFO L85 PathProgramCache]: Analyzing trace with hash -1949208090, now seen corresponding path program 1 times [2024-10-25 00:40:38,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:38,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899586482] [2024-10-25 00:40:38,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:38,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:38,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:39,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:39,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:39,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899586482] [2024-10-25 00:40:39,043 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899586482] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:39,043 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:39,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:39,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295904733] [2024-10-25 00:40:39,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:39,045 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:39,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:39,045 INFO L85 PathProgramCache]: Analyzing trace with hash -102240755, now seen corresponding path program 1 times [2024-10-25 00:40:39,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:39,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070024890] [2024-10-25 00:40:39,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:39,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:39,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:39,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:39,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:39,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070024890] [2024-10-25 00:40:39,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070024890] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:39,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:39,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:39,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2021901099] [2024-10-25 00:40:39,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:39,150 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:39,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:39,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:39,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:39,151 INFO L87 Difference]: Start difference. First operand 2062 states and 3048 transitions. cyclomatic complexity: 987 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:39,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:39,196 INFO L93 Difference]: Finished difference Result 2062 states and 3047 transitions. [2024-10-25 00:40:39,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3047 transitions. [2024-10-25 00:40:39,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:39,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3047 transitions. [2024-10-25 00:40:39,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:39,223 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:39,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3047 transitions. [2024-10-25 00:40:39,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:39,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3047 transitions. [2024-10-25 00:40:39,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3047 transitions. [2024-10-25 00:40:39,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:39,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4776915615906887) internal successors, (3047), 2061 states have internal predecessors, (3047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:39,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3047 transitions. [2024-10-25 00:40:39,264 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3047 transitions. [2024-10-25 00:40:39,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:39,266 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3047 transitions. [2024-10-25 00:40:39,266 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-25 00:40:39,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3047 transitions. [2024-10-25 00:40:39,276 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:39,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:39,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:39,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:39,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:39,280 INFO L745 eck$LassoCheckResult]: Stem: 12764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 12765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 13696#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13697#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14458#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 13301#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13302#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13014#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13015#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14267#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13593#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13594#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14132#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13499#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13500#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12924#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12925#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13271#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13453#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 12505#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12506#L1342 assume !(0 == ~M_E~0); 12674#L1342-2 assume !(0 == ~T1_E~0); 13238#L1347-1 assume !(0 == ~T2_E~0); 14248#L1352-1 assume !(0 == ~T3_E~0); 14039#L1357-1 assume !(0 == ~T4_E~0); 13260#L1362-1 assume !(0 == ~T5_E~0); 13261#L1367-1 assume !(0 == ~T6_E~0); 12839#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12840#L1377-1 assume !(0 == ~T8_E~0); 13178#L1382-1 assume !(0 == ~T9_E~0); 13179#L1387-1 assume !(0 == ~T10_E~0); 13920#L1392-1 assume !(0 == ~T11_E~0); 13221#L1397-1 assume !(0 == ~T12_E~0); 13222#L1402-1 assume !(0 == ~T13_E~0); 12863#L1407-1 assume !(0 == ~T14_E~0); 12864#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14164#L1417-1 assume !(0 == ~E_2~0); 14165#L1422-1 assume !(0 == ~E_3~0); 14402#L1427-1 assume !(0 == ~E_4~0); 13043#L1432-1 assume !(0 == ~E_5~0); 13044#L1437-1 assume !(0 == ~E_6~0); 14084#L1442-1 assume !(0 == ~E_7~0); 14085#L1447-1 assume !(0 == ~E_8~0); 13914#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 12643#L1457-1 assume !(0 == ~E_10~0); 12644#L1462-1 assume !(0 == ~E_11~0); 14114#L1467-1 assume !(0 == ~E_12~0); 14127#L1472-1 assume !(0 == ~E_13~0); 14128#L1477-1 assume !(0 == ~E_14~0); 13863#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12828#L646 assume 1 == ~m_pc~0; 12829#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13509#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13524#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12926#L1666 assume !(0 != activate_threads_~tmp~1#1); 12927#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14423#L665 assume !(1 == ~t1_pc~0); 13404#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13405#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14013#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14014#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 13745#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13746#L684 assume 1 == ~t2_pc~0; 13860#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13784#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12912#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12913#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 14253#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14436#L703 assume !(1 == ~t3_pc~0); 13068#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13069#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14000#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12477#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 12478#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12956#L722 assume 1 == ~t4_pc~0; 13703#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13143#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12588#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12589#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 13545#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12675#L741 assume 1 == ~t5_pc~0; 12676#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12978#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13778#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13830#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 13831#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13239#L760 assume !(1 == ~t6_pc~0); 13067#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13066#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12904#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12905#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13660#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13661#L779 assume 1 == ~t7_pc~0; 12712#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12559#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12560#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14285#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 12990#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12991#L798 assume !(1 == ~t8_pc~0); 14295#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14212#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14213#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14377#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 14425#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12538#L817 assume 1 == ~t9_pc~0; 12539#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13337#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12960#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12961#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 12938#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12939#L836 assume !(1 == ~t10_pc~0); 12962#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12888#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12889#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13144#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 13145#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14225#L855 assume 1 == ~t11_pc~0; 13520#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13521#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14108#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13911#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 13751#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12825#L874 assume !(1 == ~t12_pc~0); 12826#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12999#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12527#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12528#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 12513#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12514#L893 assume 1 == ~t13_pc~0; 14360#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12866#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13177#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14308#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 14300#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 14301#L912 assume 1 == ~t14_pc~0; 14091#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 14092#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 14161#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12762#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 12763#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13538#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 13969#L1495-2 assume !(1 == ~T1_E~0); 13970#L1500-1 assume !(1 == ~T2_E~0); 13654#L1505-1 assume !(1 == ~T3_E~0); 13655#L1510-1 assume !(1 == ~T4_E~0); 13713#L1515-1 assume !(1 == ~T5_E~0); 13714#L1520-1 assume !(1 == ~T6_E~0); 14296#L1525-1 assume !(1 == ~T7_E~0); 14001#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12931#L1535-1 assume !(1 == ~T9_E~0); 12932#L1540-1 assume !(1 == ~T10_E~0); 12438#L1545-1 assume !(1 == ~T11_E~0); 12439#L1550-1 assume !(1 == ~T12_E~0); 12685#L1555-1 assume !(1 == ~T13_E~0); 12686#L1560-1 assume !(1 == ~T14_E~0); 12981#L1565-1 assume !(1 == ~E_1~0); 14411#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13884#L1575-1 assume !(1 == ~E_3~0); 13266#L1580-1 assume !(1 == ~E_4~0); 13267#L1585-1 assume !(1 == ~E_5~0); 13737#L1590-1 assume !(1 == ~E_6~0); 13295#L1595-1 assume !(1 == ~E_7~0); 13296#L1600-1 assume !(1 == ~E_8~0); 13668#L1605-1 assume !(1 == ~E_9~0); 13669#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14199#L1615-1 assume !(1 == ~E_11~0); 13117#L1620-1 assume !(1 == ~E_12~0); 13118#L1625-1 assume !(1 == ~E_13~0); 13915#L1630-1 assume !(1 == ~E_14~0); 13294#L1635-1 assume { :end_inline_reset_delta_events } true; 13240#L2017-2 [2024-10-25 00:40:39,281 INFO L747 eck$LassoCheckResult]: Loop: 13240#L2017-2 assume !false; 12511#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12512#L1316-1 assume !false; 12900#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13910#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12451#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12788#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13934#L1115 assume !(0 != eval_~tmp~0#1); 13465#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13112#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13113#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13519#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14046#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13699#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13700#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14279#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14451#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14443#L1372-3 assume !(0 == ~T7_E~0); 12491#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12492#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13157#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13158#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14094#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14397#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13646#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 12786#L1412-3 assume !(0 == ~E_1~0); 12787#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13548#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13549#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14277#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13954#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13662#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13663#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12555#L1452-3 assume !(0 == ~E_9~0); 12556#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14210#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14211#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14018#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 14019#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 12784#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12785#L646-42 assume 1 == ~m_pc~0; 13380#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14249#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13248#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13249#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14381#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14181#L665-42 assume 1 == ~t1_pc~0; 14139#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14141#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14356#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12963#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12964#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14450#L684-42 assume 1 == ~t2_pc~0; 13826#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13827#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13579#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13580#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13589#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13725#L703-42 assume 1 == ~t3_pc~0; 13926#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13927#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13990#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13991#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14023#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13629#L722-42 assume 1 == ~t4_pc~0; 13630#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14059#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14055#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13105#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13106#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14417#L741-42 assume !(1 == ~t5_pc~0); 14035#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 13484#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13485#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13656#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13398#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13399#L760-42 assume !(1 == ~t6_pc~0); 13526#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 13675#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12877#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12878#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 13353#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13354#L779-42 assume !(1 == ~t7_pc~0); 14146#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 14147#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13683#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13684#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12886#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12887#L798-42 assume 1 == ~t8_pc~0; 13346#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12504#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13845#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13693#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12718#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12719#L817-42 assume 1 == ~t9_pc~0; 13493#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13001#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13002#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14145#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13949#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13950#L836-42 assume 1 == ~t10_pc~0; 14050#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13038#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13039#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13825#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14363#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14405#L855-42 assume !(1 == ~t11_pc~0); 14416#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 12594#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12595#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14125#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14126#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13216#L874-42 assume !(1 == ~t12_pc~0); 13217#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 13447#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13634#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13635#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12758#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12759#L893-42 assume !(1 == ~t13_pc~0); 13764#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 13765#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13180#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13181#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 13140#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 13141#L912-42 assume !(1 == ~t14_pc~0); 13957#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 12461#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12462#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13254#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 12883#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12884#L1495-3 assume !(1 == ~M_E~0); 13496#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13940#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14036#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13111#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13070#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13071#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13750#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13966#L1530-3 assume !(1 == ~T8_E~0); 12920#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12921#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12959#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14240#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14347#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13368#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 13369#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13997#L1570-3 assume !(1 == ~E_2~0); 13944#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13945#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14309#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14352#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14396#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13775#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13776#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14254#L1610-3 assume !(1 == ~E_10~0); 13121#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13122#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13738#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13739#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 13633#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13054#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12670#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12861#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12862#L2036 assume !(0 == start_simulation_~tmp~3#1); 13967#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 14131#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 13279#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12507#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 12508#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13676#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14298#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14299#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 13240#L2017-2 [2024-10-25 00:40:39,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:39,282 INFO L85 PathProgramCache]: Analyzing trace with hash -224599768, now seen corresponding path program 1 times [2024-10-25 00:40:39,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:39,283 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342218607] [2024-10-25 00:40:39,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:39,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:39,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:39,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:39,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:39,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342218607] [2024-10-25 00:40:39,393 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342218607] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:39,394 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:39,394 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:39,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916208486] [2024-10-25 00:40:39,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:39,397 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:39,398 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:39,398 INFO L85 PathProgramCache]: Analyzing trace with hash 850948718, now seen corresponding path program 1 times [2024-10-25 00:40:39,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:39,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921195584] [2024-10-25 00:40:39,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:39,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:39,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:39,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:39,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:39,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921195584] [2024-10-25 00:40:39,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921195584] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:39,506 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:39,506 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:39,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [171323667] [2024-10-25 00:40:39,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:39,507 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:39,508 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:39,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:39,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:39,509 INFO L87 Difference]: Start difference. First operand 2062 states and 3047 transitions. cyclomatic complexity: 986 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:39,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:39,555 INFO L93 Difference]: Finished difference Result 2062 states and 3046 transitions. [2024-10-25 00:40:39,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3046 transitions. [2024-10-25 00:40:39,575 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:39,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3046 transitions. [2024-10-25 00:40:39,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:39,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:39,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3046 transitions. [2024-10-25 00:40:39,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:39,597 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3046 transitions. [2024-10-25 00:40:39,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3046 transitions. [2024-10-25 00:40:39,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:39,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4772065955383122) internal successors, (3046), 2061 states have internal predecessors, (3046), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:39,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3046 transitions. [2024-10-25 00:40:39,648 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3046 transitions. [2024-10-25 00:40:39,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:39,650 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3046 transitions. [2024-10-25 00:40:39,651 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-25 00:40:39,651 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3046 transitions. [2024-10-25 00:40:39,659 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:39,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:39,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:39,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:39,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:39,666 INFO L745 eck$LassoCheckResult]: Stem: 16895#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 16896#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 17827#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17828#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18589#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 17432#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17433#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17145#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17146#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18398#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17724#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17725#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18263#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17630#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17631#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17055#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17056#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17402#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17584#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 16636#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16637#L1342 assume !(0 == ~M_E~0); 16805#L1342-2 assume !(0 == ~T1_E~0); 17369#L1347-1 assume !(0 == ~T2_E~0); 18379#L1352-1 assume !(0 == ~T3_E~0); 18170#L1357-1 assume !(0 == ~T4_E~0); 17391#L1362-1 assume !(0 == ~T5_E~0); 17392#L1367-1 assume !(0 == ~T6_E~0); 16970#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16971#L1377-1 assume !(0 == ~T8_E~0); 17309#L1382-1 assume !(0 == ~T9_E~0); 17310#L1387-1 assume !(0 == ~T10_E~0); 18051#L1392-1 assume !(0 == ~T11_E~0); 17352#L1397-1 assume !(0 == ~T12_E~0); 17353#L1402-1 assume !(0 == ~T13_E~0); 16994#L1407-1 assume !(0 == ~T14_E~0); 16995#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 18295#L1417-1 assume !(0 == ~E_2~0); 18296#L1422-1 assume !(0 == ~E_3~0); 18533#L1427-1 assume !(0 == ~E_4~0); 17174#L1432-1 assume !(0 == ~E_5~0); 17175#L1437-1 assume !(0 == ~E_6~0); 18215#L1442-1 assume !(0 == ~E_7~0); 18216#L1447-1 assume !(0 == ~E_8~0); 18045#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16774#L1457-1 assume !(0 == ~E_10~0); 16775#L1462-1 assume !(0 == ~E_11~0); 18245#L1467-1 assume !(0 == ~E_12~0); 18258#L1472-1 assume !(0 == ~E_13~0); 18259#L1477-1 assume !(0 == ~E_14~0); 17994#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16959#L646 assume 1 == ~m_pc~0; 16960#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17640#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17655#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17057#L1666 assume !(0 != activate_threads_~tmp~1#1); 17058#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18554#L665 assume !(1 == ~t1_pc~0); 17535#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17536#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18144#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18145#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 17876#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17877#L684 assume 1 == ~t2_pc~0; 17991#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17915#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17043#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17044#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 18384#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18567#L703 assume !(1 == ~t3_pc~0); 17199#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17200#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18131#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16608#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 16609#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17087#L722 assume 1 == ~t4_pc~0; 17834#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17274#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16719#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16720#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 17676#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16806#L741 assume 1 == ~t5_pc~0; 16807#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17109#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17909#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17961#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 17962#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17370#L760 assume !(1 == ~t6_pc~0); 17198#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17197#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17035#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17036#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17791#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17792#L779 assume 1 == ~t7_pc~0; 16843#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16690#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16691#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18416#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 17121#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17122#L798 assume !(1 == ~t8_pc~0); 18426#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18343#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18344#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18508#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 18556#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16669#L817 assume 1 == ~t9_pc~0; 16670#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17468#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17091#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17092#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 17069#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17070#L836 assume !(1 == ~t10_pc~0); 17093#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17019#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17020#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17275#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 17276#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18356#L855 assume 1 == ~t11_pc~0; 17651#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17652#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18239#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18042#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 17882#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16956#L874 assume !(1 == ~t12_pc~0); 16957#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17130#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16658#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16659#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 16644#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16645#L893 assume 1 == ~t13_pc~0; 18491#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16997#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17308#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18439#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 18431#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 18432#L912 assume 1 == ~t14_pc~0; 18222#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 18223#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 18292#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16893#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 16894#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17669#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 18100#L1495-2 assume !(1 == ~T1_E~0); 18101#L1500-1 assume !(1 == ~T2_E~0); 17785#L1505-1 assume !(1 == ~T3_E~0); 17786#L1510-1 assume !(1 == ~T4_E~0); 17844#L1515-1 assume !(1 == ~T5_E~0); 17845#L1520-1 assume !(1 == ~T6_E~0); 18427#L1525-1 assume !(1 == ~T7_E~0); 18132#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17062#L1535-1 assume !(1 == ~T9_E~0); 17063#L1540-1 assume !(1 == ~T10_E~0); 16569#L1545-1 assume !(1 == ~T11_E~0); 16570#L1550-1 assume !(1 == ~T12_E~0); 16816#L1555-1 assume !(1 == ~T13_E~0); 16817#L1560-1 assume !(1 == ~T14_E~0); 17112#L1565-1 assume !(1 == ~E_1~0); 18542#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 18015#L1575-1 assume !(1 == ~E_3~0); 17397#L1580-1 assume !(1 == ~E_4~0); 17398#L1585-1 assume !(1 == ~E_5~0); 17868#L1590-1 assume !(1 == ~E_6~0); 17426#L1595-1 assume !(1 == ~E_7~0); 17427#L1600-1 assume !(1 == ~E_8~0); 17799#L1605-1 assume !(1 == ~E_9~0); 17800#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 18330#L1615-1 assume !(1 == ~E_11~0); 17248#L1620-1 assume !(1 == ~E_12~0); 17249#L1625-1 assume !(1 == ~E_13~0); 18046#L1630-1 assume !(1 == ~E_14~0); 17425#L1635-1 assume { :end_inline_reset_delta_events } true; 17371#L2017-2 [2024-10-25 00:40:39,668 INFO L747 eck$LassoCheckResult]: Loop: 17371#L2017-2 assume !false; 16642#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16643#L1316-1 assume !false; 17031#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 18041#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16582#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16919#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18065#L1115 assume !(0 != eval_~tmp~0#1); 17596#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17243#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17244#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17650#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18177#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17830#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17831#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18410#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18582#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18574#L1372-3 assume !(0 == ~T7_E~0); 16622#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16623#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17288#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17289#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18225#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18528#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17777#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 16917#L1412-3 assume !(0 == ~E_1~0); 16918#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17679#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17680#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18408#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18085#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17793#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17794#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16686#L1452-3 assume !(0 == ~E_9~0); 16687#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18341#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18342#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18149#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18150#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 16915#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16916#L646-42 assume 1 == ~m_pc~0; 17511#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18380#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17379#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17380#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18512#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18312#L665-42 assume !(1 == ~t1_pc~0); 18272#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 18273#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18487#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17094#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17095#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18581#L684-42 assume 1 == ~t2_pc~0; 17958#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17959#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17710#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17711#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17720#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17856#L703-42 assume 1 == ~t3_pc~0; 18057#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18058#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18121#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18122#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18154#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17760#L722-42 assume 1 == ~t4_pc~0; 17761#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18190#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18186#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17236#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17237#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18548#L741-42 assume !(1 == ~t5_pc~0); 18166#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 17615#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17616#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17787#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17529#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17530#L760-42 assume !(1 == ~t6_pc~0); 17657#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 17806#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17008#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17009#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 17484#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17485#L779-42 assume !(1 == ~t7_pc~0); 18277#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18278#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17814#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17815#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17017#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17018#L798-42 assume 1 == ~t8_pc~0; 17477#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16635#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17976#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17824#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16849#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16850#L817-42 assume 1 == ~t9_pc~0; 17624#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17132#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17133#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18276#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18080#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18081#L836-42 assume 1 == ~t10_pc~0; 18181#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17169#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17170#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17956#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18494#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18536#L855-42 assume 1 == ~t11_pc~0; 18546#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16725#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16726#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18256#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18257#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17347#L874-42 assume !(1 == ~t12_pc~0); 17348#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 17578#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17765#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17766#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16889#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16890#L893-42 assume !(1 == ~t13_pc~0); 17895#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 17896#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17311#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17312#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 17271#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 17272#L912-42 assume 1 == ~t14_pc~0; 18529#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 16592#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 16593#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17385#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 17014#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17015#L1495-3 assume !(1 == ~M_E~0); 17627#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18071#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18167#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17242#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17201#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17202#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17881#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18097#L1530-3 assume !(1 == ~T8_E~0); 17051#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17052#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17090#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18371#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18478#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17499#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 17500#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18128#L1570-3 assume !(1 == ~E_2~0); 18075#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18076#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18440#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18483#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18527#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17906#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17907#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18385#L1610-3 assume !(1 == ~E_10~0); 17252#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17253#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17869#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17870#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 17764#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17185#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16801#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16992#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 16993#L2036 assume !(0 == start_simulation_~tmp~3#1); 18098#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 18262#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 17410#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16638#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 16639#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17807#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18429#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18430#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 17371#L2017-2 [2024-10-25 00:40:39,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:39,669 INFO L85 PathProgramCache]: Analyzing trace with hash -723156570, now seen corresponding path program 1 times [2024-10-25 00:40:39,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:39,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992986226] [2024-10-25 00:40:39,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:39,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:39,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:39,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:39,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:39,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992986226] [2024-10-25 00:40:39,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992986226] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:39,734 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:39,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:39,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1169542722] [2024-10-25 00:40:39,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:39,735 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:39,736 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:39,736 INFO L85 PathProgramCache]: Analyzing trace with hash 1267461967, now seen corresponding path program 1 times [2024-10-25 00:40:39,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:39,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876721645] [2024-10-25 00:40:39,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:39,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:39,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:39,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:39,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:39,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876721645] [2024-10-25 00:40:39,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876721645] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:39,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:39,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:39,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020596750] [2024-10-25 00:40:39,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:39,822 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:39,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:39,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:39,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:39,824 INFO L87 Difference]: Start difference. First operand 2062 states and 3046 transitions. cyclomatic complexity: 985 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:39,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:39,859 INFO L93 Difference]: Finished difference Result 2062 states and 3045 transitions. [2024-10-25 00:40:39,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3045 transitions. [2024-10-25 00:40:39,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:39,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3045 transitions. [2024-10-25 00:40:39,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:39,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:39,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3045 transitions. [2024-10-25 00:40:39,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:39,888 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3045 transitions. [2024-10-25 00:40:39,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3045 transitions. [2024-10-25 00:40:39,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:39,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.476721629485936) internal successors, (3045), 2061 states have internal predecessors, (3045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:39,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3045 transitions. [2024-10-25 00:40:39,926 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3045 transitions. [2024-10-25 00:40:39,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:39,927 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3045 transitions. [2024-10-25 00:40:39,928 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-25 00:40:39,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3045 transitions. [2024-10-25 00:40:39,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:39,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:39,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:39,939 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:39,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:39,940 INFO L745 eck$LassoCheckResult]: Stem: 21026#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 21027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 21958#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21959#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22720#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 21563#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21564#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21276#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21277#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22529#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21855#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21856#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22394#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21761#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21762#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21186#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21187#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21533#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21715#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 20769#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20770#L1342 assume !(0 == ~M_E~0); 20936#L1342-2 assume !(0 == ~T1_E~0); 21500#L1347-1 assume !(0 == ~T2_E~0); 22510#L1352-1 assume !(0 == ~T3_E~0); 22301#L1357-1 assume !(0 == ~T4_E~0); 21522#L1362-1 assume !(0 == ~T5_E~0); 21523#L1367-1 assume !(0 == ~T6_E~0); 21101#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21102#L1377-1 assume !(0 == ~T8_E~0); 21440#L1382-1 assume !(0 == ~T9_E~0); 21441#L1387-1 assume !(0 == ~T10_E~0); 22182#L1392-1 assume !(0 == ~T11_E~0); 21483#L1397-1 assume !(0 == ~T12_E~0); 21484#L1402-1 assume !(0 == ~T13_E~0); 21125#L1407-1 assume !(0 == ~T14_E~0); 21126#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 22426#L1417-1 assume !(0 == ~E_2~0); 22427#L1422-1 assume !(0 == ~E_3~0); 22664#L1427-1 assume !(0 == ~E_4~0); 21305#L1432-1 assume !(0 == ~E_5~0); 21306#L1437-1 assume !(0 == ~E_6~0); 22346#L1442-1 assume !(0 == ~E_7~0); 22347#L1447-1 assume !(0 == ~E_8~0); 22176#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 20905#L1457-1 assume !(0 == ~E_10~0); 20906#L1462-1 assume !(0 == ~E_11~0); 22376#L1467-1 assume !(0 == ~E_12~0); 22389#L1472-1 assume !(0 == ~E_13~0); 22390#L1477-1 assume !(0 == ~E_14~0); 22125#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21090#L646 assume 1 == ~m_pc~0; 21091#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21771#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21786#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21188#L1666 assume !(0 != activate_threads_~tmp~1#1); 21189#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22685#L665 assume !(1 == ~t1_pc~0); 21666#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21667#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22275#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22276#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 22007#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22008#L684 assume 1 == ~t2_pc~0; 22122#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22046#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21174#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21175#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 22515#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22698#L703 assume !(1 == ~t3_pc~0); 21330#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21331#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22262#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20739#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 20740#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21218#L722 assume 1 == ~t4_pc~0; 21965#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21405#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20850#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20851#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 21807#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20937#L741 assume 1 == ~t5_pc~0; 20938#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21240#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22040#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22092#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 22093#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21501#L760 assume !(1 == ~t6_pc~0); 21329#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21328#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21166#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21167#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21922#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21923#L779 assume 1 == ~t7_pc~0; 20974#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20821#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20822#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22547#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 21252#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21253#L798 assume !(1 == ~t8_pc~0); 22557#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22474#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22475#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22639#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 22687#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20800#L817 assume 1 == ~t9_pc~0; 20801#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21599#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21222#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21223#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 21200#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21201#L836 assume !(1 == ~t10_pc~0); 21224#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21150#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21151#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21406#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 21407#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22487#L855 assume 1 == ~t11_pc~0; 21782#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21783#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22370#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22173#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 22013#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21087#L874 assume !(1 == ~t12_pc~0); 21088#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21261#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20789#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20790#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 20775#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20776#L893 assume 1 == ~t13_pc~0; 22622#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21128#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21439#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22570#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 22562#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 22563#L912 assume 1 == ~t14_pc~0; 22353#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 22354#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 22423#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21024#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 21025#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21800#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 22231#L1495-2 assume !(1 == ~T1_E~0); 22232#L1500-1 assume !(1 == ~T2_E~0); 21916#L1505-1 assume !(1 == ~T3_E~0); 21917#L1510-1 assume !(1 == ~T4_E~0); 21975#L1515-1 assume !(1 == ~T5_E~0); 21976#L1520-1 assume !(1 == ~T6_E~0); 22558#L1525-1 assume !(1 == ~T7_E~0); 22263#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21193#L1535-1 assume !(1 == ~T9_E~0); 21194#L1540-1 assume !(1 == ~T10_E~0); 20700#L1545-1 assume !(1 == ~T11_E~0); 20701#L1550-1 assume !(1 == ~T12_E~0); 20947#L1555-1 assume !(1 == ~T13_E~0); 20948#L1560-1 assume !(1 == ~T14_E~0); 21243#L1565-1 assume !(1 == ~E_1~0); 22673#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22146#L1575-1 assume !(1 == ~E_3~0); 21528#L1580-1 assume !(1 == ~E_4~0); 21529#L1585-1 assume !(1 == ~E_5~0); 21999#L1590-1 assume !(1 == ~E_6~0); 21557#L1595-1 assume !(1 == ~E_7~0); 21558#L1600-1 assume !(1 == ~E_8~0); 21930#L1605-1 assume !(1 == ~E_9~0); 21931#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22461#L1615-1 assume !(1 == ~E_11~0); 21379#L1620-1 assume !(1 == ~E_12~0); 21380#L1625-1 assume !(1 == ~E_13~0); 22177#L1630-1 assume !(1 == ~E_14~0); 21556#L1635-1 assume { :end_inline_reset_delta_events } true; 21502#L2017-2 [2024-10-25 00:40:39,941 INFO L747 eck$LassoCheckResult]: Loop: 21502#L2017-2 assume !false; 20773#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20774#L1316-1 assume !false; 21162#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22172#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20713#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 21050#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22196#L1115 assume !(0 != eval_~tmp~0#1); 21727#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21374#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21375#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21781#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22308#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21961#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21962#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22541#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22713#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22705#L1372-3 assume !(0 == ~T7_E~0); 20753#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20754#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21419#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21420#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22356#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22659#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21908#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 21048#L1412-3 assume !(0 == ~E_1~0); 21049#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21810#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21811#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22539#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22216#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21924#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21925#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20817#L1452-3 assume !(0 == ~E_9~0); 20818#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22472#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22473#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22280#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22281#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 21046#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21047#L646-42 assume 1 == ~m_pc~0; 21642#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22511#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21510#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21511#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22643#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22443#L665-42 assume 1 == ~t1_pc~0; 22402#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22404#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22618#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21225#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21226#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22712#L684-42 assume 1 == ~t2_pc~0; 22089#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22090#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21841#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21842#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21851#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21987#L703-42 assume 1 == ~t3_pc~0; 22188#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22189#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22252#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22253#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22285#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21891#L722-42 assume 1 == ~t4_pc~0; 21892#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22321#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22317#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21367#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21368#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22679#L741-42 assume !(1 == ~t5_pc~0); 22297#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 21746#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21747#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21918#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21660#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21661#L760-42 assume !(1 == ~t6_pc~0); 21788#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 21937#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21139#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21140#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 21615#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21616#L779-42 assume !(1 == ~t7_pc~0); 22408#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22409#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21945#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21946#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21148#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21149#L798-42 assume 1 == ~t8_pc~0; 21608#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20766#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22107#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21955#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20980#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20981#L817-42 assume 1 == ~t9_pc~0; 21755#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21263#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21264#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22407#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22211#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22212#L836-42 assume 1 == ~t10_pc~0; 22312#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21300#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21301#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22087#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22625#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22667#L855-42 assume 1 == ~t11_pc~0; 22677#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20856#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20857#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22387#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22388#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21478#L874-42 assume !(1 == ~t12_pc~0); 21479#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 21710#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21896#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21897#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21020#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21021#L893-42 assume !(1 == ~t13_pc~0); 22026#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 22027#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21442#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21443#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 21402#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 21403#L912-42 assume 1 == ~t14_pc~0; 22660#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 20723#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20724#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21516#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 21145#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21146#L1495-3 assume !(1 == ~M_E~0); 21758#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22202#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22298#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21373#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21332#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21333#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22012#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22228#L1530-3 assume !(1 == ~T8_E~0); 21182#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21183#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21221#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22502#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22609#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21630#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 21631#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22259#L1570-3 assume !(1 == ~E_2~0); 22206#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22207#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22571#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22613#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22658#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22034#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22035#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22516#L1610-3 assume !(1 == ~E_10~0); 21383#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21384#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 22000#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 22001#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 21894#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 21316#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20932#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 21121#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21122#L2036 assume !(0 == start_simulation_~tmp~3#1); 22229#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22393#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 21541#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 20767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 20768#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21938#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22560#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22561#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 21502#L2017-2 [2024-10-25 00:40:39,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:39,942 INFO L85 PathProgramCache]: Analyzing trace with hash -1293428376, now seen corresponding path program 1 times [2024-10-25 00:40:39,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:39,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897462206] [2024-10-25 00:40:39,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:39,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:39,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:40,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:40,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:40,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897462206] [2024-10-25 00:40:40,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [897462206] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:40,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:40,010 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:40,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2123188379] [2024-10-25 00:40:40,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:40,010 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:40,011 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:40,011 INFO L85 PathProgramCache]: Analyzing trace with hash 596088560, now seen corresponding path program 1 times [2024-10-25 00:40:40,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:40,011 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524384084] [2024-10-25 00:40:40,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:40,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:40,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:40,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:40,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:40,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524384084] [2024-10-25 00:40:40,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524384084] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:40,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:40,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:40,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806897767] [2024-10-25 00:40:40,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:40,127 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:40,127 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:40,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:40,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:40,128 INFO L87 Difference]: Start difference. First operand 2062 states and 3045 transitions. cyclomatic complexity: 984 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:40,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:40,161 INFO L93 Difference]: Finished difference Result 2062 states and 3044 transitions. [2024-10-25 00:40:40,161 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3044 transitions. [2024-10-25 00:40:40,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:40,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3044 transitions. [2024-10-25 00:40:40,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:40,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:40,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3044 transitions. [2024-10-25 00:40:40,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:40,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3044 transitions. [2024-10-25 00:40:40,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3044 transitions. [2024-10-25 00:40:40,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:40,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4762366634335597) internal successors, (3044), 2061 states have internal predecessors, (3044), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:40,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3044 transitions. [2024-10-25 00:40:40,237 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3044 transitions. [2024-10-25 00:40:40,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:40,241 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3044 transitions. [2024-10-25 00:40:40,241 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-25 00:40:40,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3044 transitions. [2024-10-25 00:40:40,249 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:40,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:40,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:40,251 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:40,252 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:40,252 INFO L745 eck$LassoCheckResult]: Stem: 25157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 25158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 26089#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26090#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26851#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 25694#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25695#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25407#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25408#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26660#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25986#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25987#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26525#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25892#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25893#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25317#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25318#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25664#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25846#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 24900#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24901#L1342 assume !(0 == ~M_E~0); 25067#L1342-2 assume !(0 == ~T1_E~0); 25631#L1347-1 assume !(0 == ~T2_E~0); 26641#L1352-1 assume !(0 == ~T3_E~0); 26432#L1357-1 assume !(0 == ~T4_E~0); 25653#L1362-1 assume !(0 == ~T5_E~0); 25654#L1367-1 assume !(0 == ~T6_E~0); 25232#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25233#L1377-1 assume !(0 == ~T8_E~0); 25571#L1382-1 assume !(0 == ~T9_E~0); 25572#L1387-1 assume !(0 == ~T10_E~0); 26313#L1392-1 assume !(0 == ~T11_E~0); 25614#L1397-1 assume !(0 == ~T12_E~0); 25615#L1402-1 assume !(0 == ~T13_E~0); 25256#L1407-1 assume !(0 == ~T14_E~0); 25257#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 26557#L1417-1 assume !(0 == ~E_2~0); 26558#L1422-1 assume !(0 == ~E_3~0); 26795#L1427-1 assume !(0 == ~E_4~0); 25436#L1432-1 assume !(0 == ~E_5~0); 25437#L1437-1 assume !(0 == ~E_6~0); 26477#L1442-1 assume !(0 == ~E_7~0); 26478#L1447-1 assume !(0 == ~E_8~0); 26307#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 25036#L1457-1 assume !(0 == ~E_10~0); 25037#L1462-1 assume !(0 == ~E_11~0); 26507#L1467-1 assume !(0 == ~E_12~0); 26520#L1472-1 assume !(0 == ~E_13~0); 26521#L1477-1 assume !(0 == ~E_14~0); 26256#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25221#L646 assume 1 == ~m_pc~0; 25222#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 25902#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25917#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25319#L1666 assume !(0 != activate_threads_~tmp~1#1); 25320#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26816#L665 assume !(1 == ~t1_pc~0); 25797#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25798#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26406#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26407#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 26138#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26139#L684 assume 1 == ~t2_pc~0; 26253#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26177#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25305#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25306#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 26646#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26829#L703 assume !(1 == ~t3_pc~0); 25461#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25462#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26393#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24870#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 24871#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25349#L722 assume 1 == ~t4_pc~0; 26096#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25536#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24981#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24982#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 25938#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25068#L741 assume 1 == ~t5_pc~0; 25069#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25371#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26171#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26223#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 26224#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25632#L760 assume !(1 == ~t6_pc~0); 25460#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25459#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25297#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25298#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26053#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26054#L779 assume 1 == ~t7_pc~0; 25105#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24952#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24953#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26678#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 25383#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25384#L798 assume !(1 == ~t8_pc~0); 26688#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26605#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26606#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26770#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 26818#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24931#L817 assume 1 == ~t9_pc~0; 24932#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25730#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25353#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25354#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 25331#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25332#L836 assume !(1 == ~t10_pc~0); 25355#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25281#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25282#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25537#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 25538#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26618#L855 assume 1 == ~t11_pc~0; 25913#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25914#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26501#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26304#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 26144#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25218#L874 assume !(1 == ~t12_pc~0); 25219#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25392#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24920#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24921#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 24906#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24907#L893 assume 1 == ~t13_pc~0; 26753#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25259#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25570#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26701#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 26693#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 26694#L912 assume 1 == ~t14_pc~0; 26484#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 26485#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 26554#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25155#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 25156#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25931#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 26362#L1495-2 assume !(1 == ~T1_E~0); 26363#L1500-1 assume !(1 == ~T2_E~0); 26047#L1505-1 assume !(1 == ~T3_E~0); 26048#L1510-1 assume !(1 == ~T4_E~0); 26106#L1515-1 assume !(1 == ~T5_E~0); 26107#L1520-1 assume !(1 == ~T6_E~0); 26689#L1525-1 assume !(1 == ~T7_E~0); 26394#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25324#L1535-1 assume !(1 == ~T9_E~0); 25325#L1540-1 assume !(1 == ~T10_E~0); 24831#L1545-1 assume !(1 == ~T11_E~0); 24832#L1550-1 assume !(1 == ~T12_E~0); 25078#L1555-1 assume !(1 == ~T13_E~0); 25079#L1560-1 assume !(1 == ~T14_E~0); 25374#L1565-1 assume !(1 == ~E_1~0); 26804#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 26277#L1575-1 assume !(1 == ~E_3~0); 25659#L1580-1 assume !(1 == ~E_4~0); 25660#L1585-1 assume !(1 == ~E_5~0); 26130#L1590-1 assume !(1 == ~E_6~0); 25688#L1595-1 assume !(1 == ~E_7~0); 25689#L1600-1 assume !(1 == ~E_8~0); 26061#L1605-1 assume !(1 == ~E_9~0); 26062#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26592#L1615-1 assume !(1 == ~E_11~0); 25510#L1620-1 assume !(1 == ~E_12~0); 25511#L1625-1 assume !(1 == ~E_13~0); 26308#L1630-1 assume !(1 == ~E_14~0); 25687#L1635-1 assume { :end_inline_reset_delta_events } true; 25633#L2017-2 [2024-10-25 00:40:40,254 INFO L747 eck$LassoCheckResult]: Loop: 25633#L2017-2 assume !false; 24904#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24905#L1316-1 assume !false; 25293#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26303#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24844#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 25181#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26327#L1115 assume !(0 != eval_~tmp~0#1); 25858#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25505#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25506#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25912#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26439#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26092#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26093#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26672#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26844#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26836#L1372-3 assume !(0 == ~T7_E~0); 24884#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24885#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25550#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25551#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26487#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26790#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 26039#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 25179#L1412-3 assume !(0 == ~E_1~0); 25180#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25941#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25942#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26670#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26348#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26055#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26056#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24948#L1452-3 assume !(0 == ~E_9~0); 24949#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26603#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26604#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26411#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26412#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 25177#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25178#L646-42 assume 1 == ~m_pc~0; 25773#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 26642#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25641#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25642#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26774#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26574#L665-42 assume 1 == ~t1_pc~0; 26533#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26535#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26749#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25356#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25357#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26843#L684-42 assume 1 == ~t2_pc~0; 26220#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26221#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25972#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25973#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25982#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26118#L703-42 assume !(1 == ~t3_pc~0); 26321#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 26320#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26383#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26384#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26416#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26022#L722-42 assume 1 == ~t4_pc~0; 26023#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26452#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26448#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25498#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25499#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26810#L741-42 assume 1 == ~t5_pc~0; 26754#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25877#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25878#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26049#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25791#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25792#L760-42 assume 1 == ~t6_pc~0; 25920#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26068#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25270#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25271#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 25746#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25747#L779-42 assume 1 == ~t7_pc~0; 26593#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26540#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26076#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26077#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25279#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25280#L798-42 assume !(1 == ~t8_pc~0); 24896#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 24897#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26238#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26086#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25111#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25112#L817-42 assume 1 == ~t9_pc~0; 25886#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25394#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25395#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26538#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26342#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26343#L836-42 assume 1 == ~t10_pc~0; 26443#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25431#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25432#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26218#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26756#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26798#L855-42 assume 1 == ~t11_pc~0; 26808#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24987#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24988#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26518#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26519#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25609#L874-42 assume !(1 == ~t12_pc~0); 25610#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25841#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26027#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26028#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25151#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25152#L893-42 assume 1 == ~t13_pc~0; 26368#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 26156#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25573#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25574#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 25533#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 25534#L912-42 assume 1 == ~t14_pc~0; 26791#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 24852#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 24853#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25647#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 25276#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25277#L1495-3 assume !(1 == ~M_E~0); 25889#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26333#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26429#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25503#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25463#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25464#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26143#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26359#L1530-3 assume !(1 == ~T8_E~0); 25313#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25314#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25352#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26633#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26740#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25761#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 25762#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26387#L1570-3 assume !(1 == ~E_2~0); 26337#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26338#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26702#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26744#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26789#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26165#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26166#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26647#L1610-3 assume !(1 == ~E_10~0); 25514#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25515#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26131#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 26132#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 26025#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 25447#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25063#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 25252#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 25253#L2036 assume !(0 == start_simulation_~tmp~3#1); 26360#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26524#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25672#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 24898#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 24899#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26069#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26691#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26692#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 25633#L2017-2 [2024-10-25 00:40:40,255 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:40,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1597669734, now seen corresponding path program 1 times [2024-10-25 00:40:40,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:40,256 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425663151] [2024-10-25 00:40:40,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:40,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:40,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:40,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:40,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:40,314 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425663151] [2024-10-25 00:40:40,314 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425663151] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:40,314 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:40,314 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:40,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1294804298] [2024-10-25 00:40:40,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:40,314 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:40,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:40,315 INFO L85 PathProgramCache]: Analyzing trace with hash -1259144270, now seen corresponding path program 1 times [2024-10-25 00:40:40,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:40,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139665873] [2024-10-25 00:40:40,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:40,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:40,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:40,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:40,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:40,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139665873] [2024-10-25 00:40:40,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139665873] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:40,392 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:40,392 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:40,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1410938505] [2024-10-25 00:40:40,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:40,393 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:40,393 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:40,393 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:40,394 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:40,394 INFO L87 Difference]: Start difference. First operand 2062 states and 3044 transitions. cyclomatic complexity: 983 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:40,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:40,434 INFO L93 Difference]: Finished difference Result 2062 states and 3043 transitions. [2024-10-25 00:40:40,434 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3043 transitions. [2024-10-25 00:40:40,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:40,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3043 transitions. [2024-10-25 00:40:40,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:40,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:40,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3043 transitions. [2024-10-25 00:40:40,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:40,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3043 transitions. [2024-10-25 00:40:40,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3043 transitions. [2024-10-25 00:40:40,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:40,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4757516973811833) internal successors, (3043), 2061 states have internal predecessors, (3043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:40,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3043 transitions. [2024-10-25 00:40:40,513 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3043 transitions. [2024-10-25 00:40:40,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:40,514 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3043 transitions. [2024-10-25 00:40:40,514 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-25 00:40:40,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3043 transitions. [2024-10-25 00:40:40,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:40,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:40,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:40,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:40,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:40,526 INFO L745 eck$LassoCheckResult]: Stem: 29288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 29289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 30220#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30221#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30982#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 29825#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29826#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29538#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29539#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30791#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30117#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30118#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30656#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30023#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30024#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29448#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29449#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29795#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29977#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 29031#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29032#L1342 assume !(0 == ~M_E~0); 29198#L1342-2 assume !(0 == ~T1_E~0); 29762#L1347-1 assume !(0 == ~T2_E~0); 30772#L1352-1 assume !(0 == ~T3_E~0); 30563#L1357-1 assume !(0 == ~T4_E~0); 29784#L1362-1 assume !(0 == ~T5_E~0); 29785#L1367-1 assume !(0 == ~T6_E~0); 29363#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29364#L1377-1 assume !(0 == ~T8_E~0); 29702#L1382-1 assume !(0 == ~T9_E~0); 29703#L1387-1 assume !(0 == ~T10_E~0); 30444#L1392-1 assume !(0 == ~T11_E~0); 29745#L1397-1 assume !(0 == ~T12_E~0); 29746#L1402-1 assume !(0 == ~T13_E~0); 29387#L1407-1 assume !(0 == ~T14_E~0); 29388#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30688#L1417-1 assume !(0 == ~E_2~0); 30689#L1422-1 assume !(0 == ~E_3~0); 30926#L1427-1 assume !(0 == ~E_4~0); 29567#L1432-1 assume !(0 == ~E_5~0); 29568#L1437-1 assume !(0 == ~E_6~0); 30608#L1442-1 assume !(0 == ~E_7~0); 30609#L1447-1 assume !(0 == ~E_8~0); 30438#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 29167#L1457-1 assume !(0 == ~E_10~0); 29168#L1462-1 assume !(0 == ~E_11~0); 30638#L1467-1 assume !(0 == ~E_12~0); 30651#L1472-1 assume !(0 == ~E_13~0); 30652#L1477-1 assume !(0 == ~E_14~0); 30387#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29352#L646 assume 1 == ~m_pc~0; 29353#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30033#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30048#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29450#L1666 assume !(0 != activate_threads_~tmp~1#1); 29451#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30947#L665 assume !(1 == ~t1_pc~0); 29928#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29929#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30537#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30538#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 30269#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30270#L684 assume 1 == ~t2_pc~0; 30384#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30308#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29436#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29437#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 30777#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30960#L703 assume !(1 == ~t3_pc~0); 29592#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29593#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30524#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29001#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 29002#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29480#L722 assume 1 == ~t4_pc~0; 30227#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29667#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29112#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29113#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 30069#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29199#L741 assume 1 == ~t5_pc~0; 29200#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29502#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30302#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30354#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 30355#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29763#L760 assume !(1 == ~t6_pc~0); 29591#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29590#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29428#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29429#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30184#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30185#L779 assume 1 == ~t7_pc~0; 29236#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29083#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29084#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30809#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 29514#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29515#L798 assume !(1 == ~t8_pc~0); 30819#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30736#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30737#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30901#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 30949#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29062#L817 assume 1 == ~t9_pc~0; 29063#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29861#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29484#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29485#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 29462#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29463#L836 assume !(1 == ~t10_pc~0); 29486#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29412#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29413#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29668#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 29669#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30749#L855 assume 1 == ~t11_pc~0; 30044#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30045#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30632#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30435#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 30275#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29349#L874 assume !(1 == ~t12_pc~0); 29350#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29523#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29051#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29052#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 29037#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29038#L893 assume 1 == ~t13_pc~0; 30884#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29390#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29701#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30832#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 30824#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 30825#L912 assume 1 == ~t14_pc~0; 30615#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 30616#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 30685#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29286#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 29287#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30062#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 30493#L1495-2 assume !(1 == ~T1_E~0); 30494#L1500-1 assume !(1 == ~T2_E~0); 30178#L1505-1 assume !(1 == ~T3_E~0); 30179#L1510-1 assume !(1 == ~T4_E~0); 30237#L1515-1 assume !(1 == ~T5_E~0); 30238#L1520-1 assume !(1 == ~T6_E~0); 30820#L1525-1 assume !(1 == ~T7_E~0); 30525#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29455#L1535-1 assume !(1 == ~T9_E~0); 29456#L1540-1 assume !(1 == ~T10_E~0); 28962#L1545-1 assume !(1 == ~T11_E~0); 28963#L1550-1 assume !(1 == ~T12_E~0); 29209#L1555-1 assume !(1 == ~T13_E~0); 29210#L1560-1 assume !(1 == ~T14_E~0); 29505#L1565-1 assume !(1 == ~E_1~0); 30935#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30408#L1575-1 assume !(1 == ~E_3~0); 29790#L1580-1 assume !(1 == ~E_4~0); 29791#L1585-1 assume !(1 == ~E_5~0); 30261#L1590-1 assume !(1 == ~E_6~0); 29819#L1595-1 assume !(1 == ~E_7~0); 29820#L1600-1 assume !(1 == ~E_8~0); 30192#L1605-1 assume !(1 == ~E_9~0); 30193#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30723#L1615-1 assume !(1 == ~E_11~0); 29641#L1620-1 assume !(1 == ~E_12~0); 29642#L1625-1 assume !(1 == ~E_13~0); 30439#L1630-1 assume !(1 == ~E_14~0); 29818#L1635-1 assume { :end_inline_reset_delta_events } true; 29764#L2017-2 [2024-10-25 00:40:40,526 INFO L747 eck$LassoCheckResult]: Loop: 29764#L2017-2 assume !false; 29035#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29036#L1316-1 assume !false; 29424#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30434#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28975#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29312#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30458#L1115 assume !(0 != eval_~tmp~0#1); 29991#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29636#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29637#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30043#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30570#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30223#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30224#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30803#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30975#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30967#L1372-3 assume !(0 == ~T7_E~0); 29015#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29016#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29681#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29682#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30618#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 30921#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30170#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 29310#L1412-3 assume !(0 == ~E_1~0); 29311#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30072#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30073#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30801#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30481#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30186#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30187#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29079#L1452-3 assume !(0 == ~E_9~0); 29080#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30734#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30735#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 30542#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30543#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 29308#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29309#L646-42 assume 1 == ~m_pc~0; 29904#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30773#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29772#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29773#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30905#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30705#L665-42 assume 1 == ~t1_pc~0; 30664#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30666#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30880#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29487#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29488#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30974#L684-42 assume !(1 == ~t2_pc~0); 30353#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 30352#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30103#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30104#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30113#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30249#L703-42 assume 1 == ~t3_pc~0; 30450#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30451#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30514#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30515#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30547#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30153#L722-42 assume 1 == ~t4_pc~0; 30154#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30583#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30579#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29629#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29630#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30941#L741-42 assume 1 == ~t5_pc~0; 30885#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30008#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30009#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30180#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29922#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29923#L760-42 assume !(1 == ~t6_pc~0); 30050#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 30199#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29401#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29402#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 29877#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29878#L779-42 assume 1 == ~t7_pc~0; 30724#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30671#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30207#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30208#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29410#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29411#L798-42 assume !(1 == ~t8_pc~0); 29027#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 29028#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30369#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30217#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29242#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29243#L817-42 assume 1 == ~t9_pc~0; 30017#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29525#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29526#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30669#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30473#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30474#L836-42 assume 1 == ~t10_pc~0; 30574#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 29562#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29563#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30349#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30887#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30929#L855-42 assume 1 == ~t11_pc~0; 30939#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29118#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29119#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30648#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30649#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29737#L874-42 assume !(1 == ~t12_pc~0); 29738#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 29967#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30158#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30159#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29282#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29283#L893-42 assume 1 == ~t13_pc~0; 30499#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30287#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29704#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29705#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 29664#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 29665#L912-42 assume 1 == ~t14_pc~0; 30922#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 28983#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 28984#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29778#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 29407#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29408#L1495-3 assume !(1 == ~M_E~0); 30020#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30464#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30560#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29634#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29594#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29595#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30274#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30490#L1530-3 assume !(1 == ~T8_E~0); 29444#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29445#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29483#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30764#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30871#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29892#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 29893#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30519#L1570-3 assume !(1 == ~E_2~0); 30468#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30469#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30833#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30875#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30920#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30296#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30297#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30778#L1610-3 assume !(1 == ~E_10~0); 29645#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29646#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30262#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30263#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 30156#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 29578#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29194#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29383#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29384#L2036 assume !(0 == start_simulation_~tmp~3#1); 30491#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30655#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29803#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29029#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 29030#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30200#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30822#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30823#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 29764#L2017-2 [2024-10-25 00:40:40,527 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:40,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1911299672, now seen corresponding path program 1 times [2024-10-25 00:40:40,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:40,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417111209] [2024-10-25 00:40:40,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:40,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:40,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:40,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:40,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:40,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417111209] [2024-10-25 00:40:40,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417111209] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:40,578 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:40,578 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:40,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958124522] [2024-10-25 00:40:40,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:40,578 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:40,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:40,579 INFO L85 PathProgramCache]: Analyzing trace with hash 712511761, now seen corresponding path program 1 times [2024-10-25 00:40:40,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:40,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437306040] [2024-10-25 00:40:40,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:40,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:40,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:40,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:40,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:40,648 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1437306040] [2024-10-25 00:40:40,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1437306040] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:40,650 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:40,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:40,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1468319739] [2024-10-25 00:40:40,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:40,675 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:40,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:40,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:40,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:40,676 INFO L87 Difference]: Start difference. First operand 2062 states and 3043 transitions. cyclomatic complexity: 982 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:40,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:40,711 INFO L93 Difference]: Finished difference Result 2062 states and 3042 transitions. [2024-10-25 00:40:40,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3042 transitions. [2024-10-25 00:40:40,720 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:40,729 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3042 transitions. [2024-10-25 00:40:40,730 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:40,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:40,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3042 transitions. [2024-10-25 00:40:40,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:40,735 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3042 transitions. [2024-10-25 00:40:40,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3042 transitions. [2024-10-25 00:40:40,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:40,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.475266731328807) internal successors, (3042), 2061 states have internal predecessors, (3042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:40,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3042 transitions. [2024-10-25 00:40:40,777 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3042 transitions. [2024-10-25 00:40:40,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:40,778 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3042 transitions. [2024-10-25 00:40:40,780 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-25 00:40:40,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3042 transitions. [2024-10-25 00:40:40,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:40,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:40,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:40,790 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:40,790 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:40,790 INFO L745 eck$LassoCheckResult]: Stem: 33419#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 33420#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 34351#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34352#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35113#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 33956#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33957#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33669#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33670#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34922#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34248#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34249#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34787#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 34154#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34155#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33579#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33580#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33926#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 34108#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 33162#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33163#L1342 assume !(0 == ~M_E~0); 33329#L1342-2 assume !(0 == ~T1_E~0); 33893#L1347-1 assume !(0 == ~T2_E~0); 34903#L1352-1 assume !(0 == ~T3_E~0); 34694#L1357-1 assume !(0 == ~T4_E~0); 33915#L1362-1 assume !(0 == ~T5_E~0); 33916#L1367-1 assume !(0 == ~T6_E~0); 33494#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33495#L1377-1 assume !(0 == ~T8_E~0); 33833#L1382-1 assume !(0 == ~T9_E~0); 33834#L1387-1 assume !(0 == ~T10_E~0); 34575#L1392-1 assume !(0 == ~T11_E~0); 33876#L1397-1 assume !(0 == ~T12_E~0); 33877#L1402-1 assume !(0 == ~T13_E~0); 33518#L1407-1 assume !(0 == ~T14_E~0); 33519#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 34819#L1417-1 assume !(0 == ~E_2~0); 34820#L1422-1 assume !(0 == ~E_3~0); 35057#L1427-1 assume !(0 == ~E_4~0); 33698#L1432-1 assume !(0 == ~E_5~0); 33699#L1437-1 assume !(0 == ~E_6~0); 34739#L1442-1 assume !(0 == ~E_7~0); 34740#L1447-1 assume !(0 == ~E_8~0); 34569#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 33298#L1457-1 assume !(0 == ~E_10~0); 33299#L1462-1 assume !(0 == ~E_11~0); 34769#L1467-1 assume !(0 == ~E_12~0); 34782#L1472-1 assume !(0 == ~E_13~0); 34783#L1477-1 assume !(0 == ~E_14~0); 34518#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33483#L646 assume 1 == ~m_pc~0; 33484#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34164#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34179#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33581#L1666 assume !(0 != activate_threads_~tmp~1#1); 33582#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35078#L665 assume !(1 == ~t1_pc~0); 34059#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34060#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34668#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34669#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 34400#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34401#L684 assume 1 == ~t2_pc~0; 34515#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34441#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33567#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33568#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 34908#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35091#L703 assume !(1 == ~t3_pc~0); 33723#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33724#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34655#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33132#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 33133#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33611#L722 assume 1 == ~t4_pc~0; 34358#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33798#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33243#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33244#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 34200#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33330#L741 assume 1 == ~t5_pc~0; 33331#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33633#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34433#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34485#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 34486#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33894#L760 assume !(1 == ~t6_pc~0); 33722#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33721#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33559#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33560#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34315#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34316#L779 assume 1 == ~t7_pc~0; 33367#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33214#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33215#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34940#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 33645#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33646#L798 assume !(1 == ~t8_pc~0); 34950#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34867#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34868#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35032#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 35080#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33193#L817 assume 1 == ~t9_pc~0; 33194#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33992#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33615#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33616#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 33593#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33594#L836 assume !(1 == ~t10_pc~0); 33617#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33543#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33544#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33799#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 33800#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34880#L855 assume 1 == ~t11_pc~0; 34175#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34176#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34763#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34566#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 34406#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33480#L874 assume !(1 == ~t12_pc~0); 33481#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33654#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33182#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33183#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 33168#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33169#L893 assume 1 == ~t13_pc~0; 35015#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33521#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33832#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34963#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 34955#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 34956#L912 assume 1 == ~t14_pc~0; 34746#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 34747#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 34816#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33417#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 33418#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34193#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 34624#L1495-2 assume !(1 == ~T1_E~0); 34625#L1500-1 assume !(1 == ~T2_E~0); 34309#L1505-1 assume !(1 == ~T3_E~0); 34310#L1510-1 assume !(1 == ~T4_E~0); 34368#L1515-1 assume !(1 == ~T5_E~0); 34369#L1520-1 assume !(1 == ~T6_E~0); 34951#L1525-1 assume !(1 == ~T7_E~0); 34656#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33586#L1535-1 assume !(1 == ~T9_E~0); 33587#L1540-1 assume !(1 == ~T10_E~0); 33093#L1545-1 assume !(1 == ~T11_E~0); 33094#L1550-1 assume !(1 == ~T12_E~0); 33340#L1555-1 assume !(1 == ~T13_E~0); 33341#L1560-1 assume !(1 == ~T14_E~0); 33636#L1565-1 assume !(1 == ~E_1~0); 35066#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34539#L1575-1 assume !(1 == ~E_3~0); 33921#L1580-1 assume !(1 == ~E_4~0); 33922#L1585-1 assume !(1 == ~E_5~0); 34392#L1590-1 assume !(1 == ~E_6~0); 33950#L1595-1 assume !(1 == ~E_7~0); 33951#L1600-1 assume !(1 == ~E_8~0); 34323#L1605-1 assume !(1 == ~E_9~0); 34324#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 34854#L1615-1 assume !(1 == ~E_11~0); 33772#L1620-1 assume !(1 == ~E_12~0); 33773#L1625-1 assume !(1 == ~E_13~0); 34570#L1630-1 assume !(1 == ~E_14~0); 33949#L1635-1 assume { :end_inline_reset_delta_events } true; 33895#L2017-2 [2024-10-25 00:40:40,791 INFO L747 eck$LassoCheckResult]: Loop: 33895#L2017-2 assume !false; 33166#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33167#L1316-1 assume !false; 33555#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34565#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33106#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33443#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34589#L1115 assume !(0 != eval_~tmp~0#1); 34122#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33767#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33768#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34174#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34701#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34354#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34355#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34934#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35106#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35098#L1372-3 assume !(0 == ~T7_E~0); 33146#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33147#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33812#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33813#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34749#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35052#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34301#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 33441#L1412-3 assume !(0 == ~E_1~0); 33442#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34203#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34204#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34932#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34612#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34317#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34318#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33210#L1452-3 assume !(0 == ~E_9~0); 33211#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34865#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34866#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 34673#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34674#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 33439#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33440#L646-42 assume 1 == ~m_pc~0; 34035#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34904#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33903#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33904#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35036#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34836#L665-42 assume 1 == ~t1_pc~0; 34795#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34797#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35011#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33618#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33619#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35105#L684-42 assume 1 == ~t2_pc~0; 34482#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34483#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34234#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34235#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34244#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34380#L703-42 assume 1 == ~t3_pc~0; 34581#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34582#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34645#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34646#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34678#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34284#L722-42 assume 1 == ~t4_pc~0; 34285#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34714#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34710#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33760#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33761#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35072#L741-42 assume !(1 == ~t5_pc~0); 34690#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 34139#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34140#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34311#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34053#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34054#L760-42 assume !(1 == ~t6_pc~0); 34181#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34330#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33532#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33533#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 34008#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34009#L779-42 assume !(1 == ~t7_pc~0); 34801#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 34802#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34338#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34339#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33541#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33542#L798-42 assume 1 == ~t8_pc~0; 34001#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33159#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34500#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34348#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33373#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33374#L817-42 assume 1 == ~t9_pc~0; 34148#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33656#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33657#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34800#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34604#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34605#L836-42 assume 1 == ~t10_pc~0; 34705#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33693#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33694#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34480#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35018#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35060#L855-42 assume 1 == ~t11_pc~0; 35070#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33247#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33248#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34779#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34780#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33868#L874-42 assume !(1 == ~t12_pc~0); 33869#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 34098#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34289#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34290#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33413#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33414#L893-42 assume !(1 == ~t13_pc~0); 34417#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 34418#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33835#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33836#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 33795#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 33796#L912-42 assume !(1 == ~t14_pc~0); 34608#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 33114#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 33115#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33909#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 33538#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33539#L1495-3 assume !(1 == ~M_E~0); 34151#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34595#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34691#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33765#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33725#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33726#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34405#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34621#L1530-3 assume !(1 == ~T8_E~0); 33575#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33576#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33614#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34895#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35002#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34023#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 34024#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34650#L1570-3 assume !(1 == ~E_2~0); 34599#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34600#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34964#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35006#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35051#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34427#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34428#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34909#L1610-3 assume !(1 == ~E_10~0); 33776#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33777#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34393#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 34394#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 34287#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 33709#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33325#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33514#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33515#L2036 assume !(0 == start_simulation_~tmp~3#1); 34622#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34786#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33934#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33160#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 33161#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34331#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34953#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34954#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 33895#L2017-2 [2024-10-25 00:40:40,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:40,792 INFO L85 PathProgramCache]: Analyzing trace with hash 1716285734, now seen corresponding path program 1 times [2024-10-25 00:40:40,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:40,792 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233383354] [2024-10-25 00:40:40,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:40,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:40,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:40,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:40,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:40,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233383354] [2024-10-25 00:40:40,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233383354] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:40,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:40,846 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:40,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176823136] [2024-10-25 00:40:40,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:40,847 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:40,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:40,848 INFO L85 PathProgramCache]: Analyzing trace with hash 2028923279, now seen corresponding path program 1 times [2024-10-25 00:40:40,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:40,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533877013] [2024-10-25 00:40:40,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:40,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:40,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:40,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:40,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:40,926 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533877013] [2024-10-25 00:40:40,926 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533877013] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:40,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:40,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:40,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400812482] [2024-10-25 00:40:40,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:40,927 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:40,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:40,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:40,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:40,928 INFO L87 Difference]: Start difference. First operand 2062 states and 3042 transitions. cyclomatic complexity: 981 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:40,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:40,961 INFO L93 Difference]: Finished difference Result 2062 states and 3041 transitions. [2024-10-25 00:40:40,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3041 transitions. [2024-10-25 00:40:40,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:40,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3041 transitions. [2024-10-25 00:40:40,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:40,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:40,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3041 transitions. [2024-10-25 00:40:40,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:40,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3041 transitions. [2024-10-25 00:40:40,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3041 transitions. [2024-10-25 00:40:41,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:41,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4747817652764306) internal successors, (3041), 2061 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:41,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3041 transitions. [2024-10-25 00:40:41,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3041 transitions. [2024-10-25 00:40:41,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:41,044 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3041 transitions. [2024-10-25 00:40:41,045 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-25 00:40:41,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3041 transitions. [2024-10-25 00:40:41,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:41,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:41,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:41,055 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:41,055 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:41,055 INFO L745 eck$LassoCheckResult]: Stem: 37550#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 37551#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 38482#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38483#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39244#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 38087#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38088#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37800#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37801#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39053#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38379#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38380#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38918#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38285#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38286#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37710#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37711#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38057#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38239#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 37293#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37294#L1342 assume !(0 == ~M_E~0); 37460#L1342-2 assume !(0 == ~T1_E~0); 38024#L1347-1 assume !(0 == ~T2_E~0); 39034#L1352-1 assume !(0 == ~T3_E~0); 38825#L1357-1 assume !(0 == ~T4_E~0); 38046#L1362-1 assume !(0 == ~T5_E~0); 38047#L1367-1 assume !(0 == ~T6_E~0); 37625#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37626#L1377-1 assume !(0 == ~T8_E~0); 37964#L1382-1 assume !(0 == ~T9_E~0); 37965#L1387-1 assume !(0 == ~T10_E~0); 38706#L1392-1 assume !(0 == ~T11_E~0); 38007#L1397-1 assume !(0 == ~T12_E~0); 38008#L1402-1 assume !(0 == ~T13_E~0); 37649#L1407-1 assume !(0 == ~T14_E~0); 37650#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 38950#L1417-1 assume !(0 == ~E_2~0); 38951#L1422-1 assume !(0 == ~E_3~0); 39188#L1427-1 assume !(0 == ~E_4~0); 37829#L1432-1 assume !(0 == ~E_5~0); 37830#L1437-1 assume !(0 == ~E_6~0); 38870#L1442-1 assume !(0 == ~E_7~0); 38871#L1447-1 assume !(0 == ~E_8~0); 38700#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 37429#L1457-1 assume !(0 == ~E_10~0); 37430#L1462-1 assume !(0 == ~E_11~0); 38900#L1467-1 assume !(0 == ~E_12~0); 38913#L1472-1 assume !(0 == ~E_13~0); 38914#L1477-1 assume !(0 == ~E_14~0); 38649#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37614#L646 assume 1 == ~m_pc~0; 37615#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38295#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38310#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37712#L1666 assume !(0 != activate_threads_~tmp~1#1); 37713#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39209#L665 assume !(1 == ~t1_pc~0); 38190#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38191#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38799#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38800#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 38531#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38532#L684 assume 1 == ~t2_pc~0; 38646#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38572#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37698#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37699#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 39039#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39222#L703 assume !(1 == ~t3_pc~0); 37854#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37855#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38786#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37263#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 37264#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37742#L722 assume 1 == ~t4_pc~0; 38489#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37929#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37374#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37375#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 38331#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37461#L741 assume 1 == ~t5_pc~0; 37462#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37764#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38564#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38616#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 38617#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38025#L760 assume !(1 == ~t6_pc~0); 37853#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37852#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37690#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37691#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38446#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38447#L779 assume 1 == ~t7_pc~0; 37498#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37345#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37346#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39071#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 37776#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37777#L798 assume !(1 == ~t8_pc~0); 39081#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 38998#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38999#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39163#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 39211#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37324#L817 assume 1 == ~t9_pc~0; 37325#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38123#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37746#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37747#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 37724#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37725#L836 assume !(1 == ~t10_pc~0); 37748#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37674#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37675#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37930#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 37931#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39011#L855 assume 1 == ~t11_pc~0; 38306#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38307#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38894#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38697#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 38537#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37611#L874 assume !(1 == ~t12_pc~0); 37612#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37785#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37313#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37314#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 37299#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37300#L893 assume 1 == ~t13_pc~0; 39146#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37652#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37963#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 39094#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 39086#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 39087#L912 assume 1 == ~t14_pc~0; 38877#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 38878#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 38947#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37548#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 37549#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38324#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 38755#L1495-2 assume !(1 == ~T1_E~0); 38756#L1500-1 assume !(1 == ~T2_E~0); 38440#L1505-1 assume !(1 == ~T3_E~0); 38441#L1510-1 assume !(1 == ~T4_E~0); 38499#L1515-1 assume !(1 == ~T5_E~0); 38500#L1520-1 assume !(1 == ~T6_E~0); 39082#L1525-1 assume !(1 == ~T7_E~0); 38787#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37717#L1535-1 assume !(1 == ~T9_E~0); 37718#L1540-1 assume !(1 == ~T10_E~0); 37224#L1545-1 assume !(1 == ~T11_E~0); 37225#L1550-1 assume !(1 == ~T12_E~0); 37471#L1555-1 assume !(1 == ~T13_E~0); 37472#L1560-1 assume !(1 == ~T14_E~0); 37767#L1565-1 assume !(1 == ~E_1~0); 39197#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 38670#L1575-1 assume !(1 == ~E_3~0); 38052#L1580-1 assume !(1 == ~E_4~0); 38053#L1585-1 assume !(1 == ~E_5~0); 38523#L1590-1 assume !(1 == ~E_6~0); 38081#L1595-1 assume !(1 == ~E_7~0); 38082#L1600-1 assume !(1 == ~E_8~0); 38454#L1605-1 assume !(1 == ~E_9~0); 38455#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 38985#L1615-1 assume !(1 == ~E_11~0); 37903#L1620-1 assume !(1 == ~E_12~0); 37904#L1625-1 assume !(1 == ~E_13~0); 38701#L1630-1 assume !(1 == ~E_14~0); 38080#L1635-1 assume { :end_inline_reset_delta_events } true; 38026#L2017-2 [2024-10-25 00:40:41,056 INFO L747 eck$LassoCheckResult]: Loop: 38026#L2017-2 assume !false; 37297#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37298#L1316-1 assume !false; 37686#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38696#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37237#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37574#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38720#L1115 assume !(0 != eval_~tmp~0#1); 38253#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37898#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37899#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38305#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38832#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38485#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38486#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39065#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39237#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39229#L1372-3 assume !(0 == ~T7_E~0); 37277#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37278#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37943#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37944#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38880#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39183#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38432#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 37572#L1412-3 assume !(0 == ~E_1~0); 37573#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38334#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38335#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39063#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38743#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38448#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38449#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37341#L1452-3 assume !(0 == ~E_9~0); 37342#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38996#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38997#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38804#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38805#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 37570#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37571#L646-42 assume 1 == ~m_pc~0; 38166#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39035#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38034#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38035#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39167#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38967#L665-42 assume 1 == ~t1_pc~0; 38926#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38928#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39142#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37749#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37750#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39236#L684-42 assume 1 == ~t2_pc~0; 38613#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38614#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38365#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38366#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38375#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38511#L703-42 assume 1 == ~t3_pc~0; 38712#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38713#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38776#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38777#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38809#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38415#L722-42 assume 1 == ~t4_pc~0; 38416#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38845#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38841#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37891#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37892#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39203#L741-42 assume !(1 == ~t5_pc~0); 38821#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 38270#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38271#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38442#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38184#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38185#L760-42 assume !(1 == ~t6_pc~0); 38312#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 38461#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37663#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37664#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 38139#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38140#L779-42 assume !(1 == ~t7_pc~0); 38932#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38933#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38469#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38470#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37672#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37673#L798-42 assume 1 == ~t8_pc~0; 38132#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37290#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38631#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38479#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37504#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37505#L817-42 assume 1 == ~t9_pc~0; 38279#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37787#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37788#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38931#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38735#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38736#L836-42 assume 1 == ~t10_pc~0; 38837#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37824#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37825#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38610#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39148#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39191#L855-42 assume 1 == ~t11_pc~0; 39201#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37378#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37379#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38910#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38911#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37999#L874-42 assume !(1 == ~t12_pc~0); 38000#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 38229#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38420#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38421#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37544#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37545#L893-42 assume !(1 == ~t13_pc~0); 38550#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 38551#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37966#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37967#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 37926#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 37927#L912-42 assume 1 == ~t14_pc~0; 39184#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 37245#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 37246#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38040#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 37669#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37670#L1495-3 assume !(1 == ~M_E~0); 38282#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38726#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38822#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37896#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37856#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37857#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38536#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38752#L1530-3 assume !(1 == ~T8_E~0); 37706#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37707#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37745#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39026#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39133#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38154#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 38155#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38782#L1570-3 assume !(1 == ~E_2~0); 38730#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38731#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39095#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39137#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39182#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38558#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38559#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39040#L1610-3 assume !(1 == ~E_10~0); 37907#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37908#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38524#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38525#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 38418#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 37840#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37456#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37645#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37646#L2036 assume !(0 == start_simulation_~tmp~3#1); 38753#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38917#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 38065#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37291#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 37292#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38462#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39084#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 39085#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 38026#L2017-2 [2024-10-25 00:40:41,057 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:41,057 INFO L85 PathProgramCache]: Analyzing trace with hash -383452696, now seen corresponding path program 1 times [2024-10-25 00:40:41,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:41,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565327233] [2024-10-25 00:40:41,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:41,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:41,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:41,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:41,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:41,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565327233] [2024-10-25 00:40:41,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565327233] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:41,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:41,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:41,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [470683069] [2024-10-25 00:40:41,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:41,116 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:41,116 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:41,116 INFO L85 PathProgramCache]: Analyzing trace with hash 596088560, now seen corresponding path program 2 times [2024-10-25 00:40:41,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:41,117 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552959797] [2024-10-25 00:40:41,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:41,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:41,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:41,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:41,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:41,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552959797] [2024-10-25 00:40:41,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1552959797] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:41,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:41,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:41,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677291518] [2024-10-25 00:40:41,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:41,195 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:41,195 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:41,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:41,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:41,196 INFO L87 Difference]: Start difference. First operand 2062 states and 3041 transitions. cyclomatic complexity: 980 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:41,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:41,231 INFO L93 Difference]: Finished difference Result 2062 states and 3040 transitions. [2024-10-25 00:40:41,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3040 transitions. [2024-10-25 00:40:41,241 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:41,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3040 transitions. [2024-10-25 00:40:41,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:41,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:41,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3040 transitions. [2024-10-25 00:40:41,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:41,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3040 transitions. [2024-10-25 00:40:41,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3040 transitions. [2024-10-25 00:40:41,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:41,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4742967992240543) internal successors, (3040), 2061 states have internal predecessors, (3040), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:41,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3040 transitions. [2024-10-25 00:40:41,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3040 transitions. [2024-10-25 00:40:41,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:41,357 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3040 transitions. [2024-10-25 00:40:41,357 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-25 00:40:41,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3040 transitions. [2024-10-25 00:40:41,365 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:41,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:41,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:41,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:41,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:41,369 INFO L745 eck$LassoCheckResult]: Stem: 41681#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 41682#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 42613#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42614#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43375#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 42218#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42219#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41931#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41932#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43184#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42510#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42511#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43049#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42416#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42417#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41841#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41842#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 42188#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42370#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 41424#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41425#L1342 assume !(0 == ~M_E~0); 41591#L1342-2 assume !(0 == ~T1_E~0); 42155#L1347-1 assume !(0 == ~T2_E~0); 43165#L1352-1 assume !(0 == ~T3_E~0); 42956#L1357-1 assume !(0 == ~T4_E~0); 42177#L1362-1 assume !(0 == ~T5_E~0); 42178#L1367-1 assume !(0 == ~T6_E~0); 41756#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41757#L1377-1 assume !(0 == ~T8_E~0); 42095#L1382-1 assume !(0 == ~T9_E~0); 42096#L1387-1 assume !(0 == ~T10_E~0); 42837#L1392-1 assume !(0 == ~T11_E~0); 42138#L1397-1 assume !(0 == ~T12_E~0); 42139#L1402-1 assume !(0 == ~T13_E~0); 41780#L1407-1 assume !(0 == ~T14_E~0); 41781#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 43081#L1417-1 assume !(0 == ~E_2~0); 43082#L1422-1 assume !(0 == ~E_3~0); 43319#L1427-1 assume !(0 == ~E_4~0); 41960#L1432-1 assume !(0 == ~E_5~0); 41961#L1437-1 assume !(0 == ~E_6~0); 43001#L1442-1 assume !(0 == ~E_7~0); 43002#L1447-1 assume !(0 == ~E_8~0); 42831#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 41560#L1457-1 assume !(0 == ~E_10~0); 41561#L1462-1 assume !(0 == ~E_11~0); 43031#L1467-1 assume !(0 == ~E_12~0); 43044#L1472-1 assume !(0 == ~E_13~0); 43045#L1477-1 assume !(0 == ~E_14~0); 42780#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41745#L646 assume 1 == ~m_pc~0; 41746#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42426#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42441#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41843#L1666 assume !(0 != activate_threads_~tmp~1#1); 41844#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43340#L665 assume !(1 == ~t1_pc~0); 42321#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42322#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42930#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42931#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 42662#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42663#L684 assume 1 == ~t2_pc~0; 42779#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42703#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41829#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41830#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 43170#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43353#L703 assume !(1 == ~t3_pc~0); 41985#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41986#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42917#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41394#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 41395#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41873#L722 assume 1 == ~t4_pc~0; 42620#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42060#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41505#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41506#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 42462#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41592#L741 assume 1 == ~t5_pc~0; 41593#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41895#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42747#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 42748#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42156#L760 assume !(1 == ~t6_pc~0); 41984#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41983#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41821#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41822#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42577#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42578#L779 assume 1 == ~t7_pc~0; 41629#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41476#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41477#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43202#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 41907#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41908#L798 assume !(1 == ~t8_pc~0); 43212#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43129#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43130#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43294#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 43342#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41455#L817 assume 1 == ~t9_pc~0; 41456#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42254#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41877#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41878#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 41855#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41856#L836 assume !(1 == ~t10_pc~0); 41879#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41805#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41806#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42061#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 42062#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43142#L855 assume 1 == ~t11_pc~0; 42437#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42438#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43025#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42828#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 42668#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41742#L874 assume !(1 == ~t12_pc~0); 41743#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41916#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41444#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41445#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 41430#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41431#L893 assume 1 == ~t13_pc~0; 43277#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41783#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42094#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 43225#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 43217#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 43218#L912 assume 1 == ~t14_pc~0; 43008#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 43009#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 43078#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41679#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 41680#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42455#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 42886#L1495-2 assume !(1 == ~T1_E~0); 42887#L1500-1 assume !(1 == ~T2_E~0); 42571#L1505-1 assume !(1 == ~T3_E~0); 42572#L1510-1 assume !(1 == ~T4_E~0); 42630#L1515-1 assume !(1 == ~T5_E~0); 42631#L1520-1 assume !(1 == ~T6_E~0); 43213#L1525-1 assume !(1 == ~T7_E~0); 42918#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41848#L1535-1 assume !(1 == ~T9_E~0); 41849#L1540-1 assume !(1 == ~T10_E~0); 41355#L1545-1 assume !(1 == ~T11_E~0); 41356#L1550-1 assume !(1 == ~T12_E~0); 41602#L1555-1 assume !(1 == ~T13_E~0); 41603#L1560-1 assume !(1 == ~T14_E~0); 41900#L1565-1 assume !(1 == ~E_1~0); 43328#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 42801#L1575-1 assume !(1 == ~E_3~0); 42183#L1580-1 assume !(1 == ~E_4~0); 42184#L1585-1 assume !(1 == ~E_5~0); 42654#L1590-1 assume !(1 == ~E_6~0); 42212#L1595-1 assume !(1 == ~E_7~0); 42213#L1600-1 assume !(1 == ~E_8~0); 42585#L1605-1 assume !(1 == ~E_9~0); 42586#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 43116#L1615-1 assume !(1 == ~E_11~0); 42034#L1620-1 assume !(1 == ~E_12~0); 42035#L1625-1 assume !(1 == ~E_13~0); 42832#L1630-1 assume !(1 == ~E_14~0); 42211#L1635-1 assume { :end_inline_reset_delta_events } true; 42157#L2017-2 [2024-10-25 00:40:41,369 INFO L747 eck$LassoCheckResult]: Loop: 42157#L2017-2 assume !false; 41428#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41429#L1316-1 assume !false; 41817#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42827#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41368#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41707#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42851#L1115 assume !(0 != eval_~tmp~0#1); 42384#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42029#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42030#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42436#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42963#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42616#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42617#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43196#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43368#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43360#L1372-3 assume !(0 == ~T7_E~0); 41408#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41409#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42074#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 42075#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43011#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43314#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42563#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 41703#L1412-3 assume !(0 == ~E_1~0); 41704#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42465#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42466#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43194#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42874#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42579#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42580#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41472#L1452-3 assume !(0 == ~E_9~0); 41473#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43127#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43128#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 42935#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42936#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 41701#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41702#L646-42 assume 1 == ~m_pc~0; 42297#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43166#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42165#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42166#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43298#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43098#L665-42 assume 1 == ~t1_pc~0; 43057#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43059#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43273#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41880#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41881#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43367#L684-42 assume 1 == ~t2_pc~0; 42744#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42745#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42496#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42497#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42506#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42642#L703-42 assume 1 == ~t3_pc~0; 42843#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42844#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42907#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42908#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42940#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42546#L722-42 assume 1 == ~t4_pc~0; 42547#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42976#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42972#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42022#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42023#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43334#L741-42 assume !(1 == ~t5_pc~0); 42952#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42401#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42402#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42573#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42315#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42316#L760-42 assume !(1 == ~t6_pc~0); 42443#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 42592#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41794#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41795#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 42270#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42271#L779-42 assume !(1 == ~t7_pc~0); 43063#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43064#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42600#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42601#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41803#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41804#L798-42 assume 1 == ~t8_pc~0; 42263#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41421#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42762#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42610#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41635#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41636#L817-42 assume 1 == ~t9_pc~0; 42410#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41918#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41919#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43062#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42866#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42867#L836-42 assume 1 == ~t10_pc~0; 42965#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41955#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41956#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42741#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43279#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43322#L855-42 assume 1 == ~t11_pc~0; 43332#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41509#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41510#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43041#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43042#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42130#L874-42 assume !(1 == ~t12_pc~0); 42131#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 42360#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42551#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42552#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41675#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41676#L893-42 assume !(1 == ~t13_pc~0); 42681#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 42682#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42097#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42098#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42057#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 42058#L912-42 assume 1 == ~t14_pc~0; 43315#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 41376#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 41377#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42171#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 41800#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41801#L1495-3 assume !(1 == ~M_E~0); 42413#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42857#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42953#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42027#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41987#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41988#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42667#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42883#L1530-3 assume !(1 == ~T8_E~0); 41837#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41838#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41876#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43157#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43264#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42285#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 42286#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42913#L1570-3 assume !(1 == ~E_2~0); 42861#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42862#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43226#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43268#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43313#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42689#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42690#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43171#L1610-3 assume !(1 == ~E_10~0); 42038#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 42039#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42655#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42656#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 42549#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 41971#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41587#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41776#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41777#L2036 assume !(0 == start_simulation_~tmp~3#1); 42884#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 43048#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 42196#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41422#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 41423#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42593#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43215#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 43216#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 42157#L2017-2 [2024-10-25 00:40:41,369 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:41,370 INFO L85 PathProgramCache]: Analyzing trace with hash -1364407510, now seen corresponding path program 1 times [2024-10-25 00:40:41,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:41,370 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349557535] [2024-10-25 00:40:41,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:41,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:41,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:41,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:41,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:41,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349557535] [2024-10-25 00:40:41,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1349557535] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:41,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:41,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:41,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822915233] [2024-10-25 00:40:41,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:41,424 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:41,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:41,426 INFO L85 PathProgramCache]: Analyzing trace with hash 596088560, now seen corresponding path program 3 times [2024-10-25 00:40:41,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:41,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587653347] [2024-10-25 00:40:41,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:41,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:41,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:41,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:41,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:41,537 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587653347] [2024-10-25 00:40:41,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587653347] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:41,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:41,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:41,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295887876] [2024-10-25 00:40:41,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:41,538 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:41,538 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:41,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:41,539 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:41,546 INFO L87 Difference]: Start difference. First operand 2062 states and 3040 transitions. cyclomatic complexity: 979 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:41,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:41,589 INFO L93 Difference]: Finished difference Result 2062 states and 3039 transitions. [2024-10-25 00:40:41,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3039 transitions. [2024-10-25 00:40:41,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:41,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3039 transitions. [2024-10-25 00:40:41,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:41,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:41,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3039 transitions. [2024-10-25 00:40:41,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:41,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3039 transitions. [2024-10-25 00:40:41,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3039 transitions. [2024-10-25 00:40:41,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:41,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.473811833171678) internal successors, (3039), 2061 states have internal predecessors, (3039), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:41,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3039 transitions. [2024-10-25 00:40:41,658 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3039 transitions. [2024-10-25 00:40:41,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:41,659 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3039 transitions. [2024-10-25 00:40:41,659 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-25 00:40:41,660 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3039 transitions. [2024-10-25 00:40:41,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:41,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:41,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:41,669 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:41,670 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:41,670 INFO L745 eck$LassoCheckResult]: Stem: 45812#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 45813#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 46744#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46745#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47506#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 46349#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46350#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46062#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46063#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47315#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46641#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46642#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47180#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46547#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46548#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45972#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45973#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 46319#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46501#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 45555#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45556#L1342 assume !(0 == ~M_E~0); 45722#L1342-2 assume !(0 == ~T1_E~0); 46286#L1347-1 assume !(0 == ~T2_E~0); 47296#L1352-1 assume !(0 == ~T3_E~0); 47087#L1357-1 assume !(0 == ~T4_E~0); 46308#L1362-1 assume !(0 == ~T5_E~0); 46309#L1367-1 assume !(0 == ~T6_E~0); 45887#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45888#L1377-1 assume !(0 == ~T8_E~0); 46226#L1382-1 assume !(0 == ~T9_E~0); 46227#L1387-1 assume !(0 == ~T10_E~0); 46968#L1392-1 assume !(0 == ~T11_E~0); 46269#L1397-1 assume !(0 == ~T12_E~0); 46270#L1402-1 assume !(0 == ~T13_E~0); 45911#L1407-1 assume !(0 == ~T14_E~0); 45912#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 47212#L1417-1 assume !(0 == ~E_2~0); 47213#L1422-1 assume !(0 == ~E_3~0); 47450#L1427-1 assume !(0 == ~E_4~0); 46091#L1432-1 assume !(0 == ~E_5~0); 46092#L1437-1 assume !(0 == ~E_6~0); 47132#L1442-1 assume !(0 == ~E_7~0); 47133#L1447-1 assume !(0 == ~E_8~0); 46962#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 45691#L1457-1 assume !(0 == ~E_10~0); 45692#L1462-1 assume !(0 == ~E_11~0); 47162#L1467-1 assume !(0 == ~E_12~0); 47175#L1472-1 assume !(0 == ~E_13~0); 47176#L1477-1 assume !(0 == ~E_14~0); 46911#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45876#L646 assume 1 == ~m_pc~0; 45877#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46557#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46572#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45974#L1666 assume !(0 != activate_threads_~tmp~1#1); 45975#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47471#L665 assume !(1 == ~t1_pc~0); 46452#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46453#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47061#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47062#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 46793#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46794#L684 assume 1 == ~t2_pc~0; 46910#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46834#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45960#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45961#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 47301#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47484#L703 assume !(1 == ~t3_pc~0); 46116#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46117#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45525#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 45526#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46004#L722 assume 1 == ~t4_pc~0; 46751#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46191#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45636#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45637#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 46593#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45723#L741 assume 1 == ~t5_pc~0; 45724#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46026#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46826#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46878#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 46879#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46287#L760 assume !(1 == ~t6_pc~0); 46115#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46114#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45952#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45953#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46708#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46709#L779 assume 1 == ~t7_pc~0; 45760#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45607#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45608#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47333#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 46038#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46039#L798 assume !(1 == ~t8_pc~0); 47343#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47260#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47261#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47425#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 47473#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45586#L817 assume 1 == ~t9_pc~0; 45587#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46385#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46008#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46009#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 45986#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45987#L836 assume !(1 == ~t10_pc~0); 46010#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45936#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45937#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46192#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 46193#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47273#L855 assume 1 == ~t11_pc~0; 46568#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46569#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47156#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46959#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 46799#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45873#L874 assume !(1 == ~t12_pc~0); 45874#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 46047#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45575#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45576#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 45561#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45562#L893 assume 1 == ~t13_pc~0; 47408#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45914#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46225#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 47356#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 47348#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 47349#L912 assume 1 == ~t14_pc~0; 47139#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 47140#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 47209#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45810#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 45811#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46586#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 47017#L1495-2 assume !(1 == ~T1_E~0); 47018#L1500-1 assume !(1 == ~T2_E~0); 46702#L1505-1 assume !(1 == ~T3_E~0); 46703#L1510-1 assume !(1 == ~T4_E~0); 46761#L1515-1 assume !(1 == ~T5_E~0); 46762#L1520-1 assume !(1 == ~T6_E~0); 47344#L1525-1 assume !(1 == ~T7_E~0); 47049#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45979#L1535-1 assume !(1 == ~T9_E~0); 45980#L1540-1 assume !(1 == ~T10_E~0); 45486#L1545-1 assume !(1 == ~T11_E~0); 45487#L1550-1 assume !(1 == ~T12_E~0); 45733#L1555-1 assume !(1 == ~T13_E~0); 45734#L1560-1 assume !(1 == ~T14_E~0); 46031#L1565-1 assume !(1 == ~E_1~0); 47459#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 46932#L1575-1 assume !(1 == ~E_3~0); 46314#L1580-1 assume !(1 == ~E_4~0); 46315#L1585-1 assume !(1 == ~E_5~0); 46785#L1590-1 assume !(1 == ~E_6~0); 46343#L1595-1 assume !(1 == ~E_7~0); 46344#L1600-1 assume !(1 == ~E_8~0); 46716#L1605-1 assume !(1 == ~E_9~0); 46717#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 47247#L1615-1 assume !(1 == ~E_11~0); 46165#L1620-1 assume !(1 == ~E_12~0); 46166#L1625-1 assume !(1 == ~E_13~0); 46963#L1630-1 assume !(1 == ~E_14~0); 46342#L1635-1 assume { :end_inline_reset_delta_events } true; 46288#L2017-2 [2024-10-25 00:40:41,670 INFO L747 eck$LassoCheckResult]: Loop: 46288#L2017-2 assume !false; 45559#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45560#L1316-1 assume !false; 45948#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46958#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45499#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45838#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46982#L1115 assume !(0 != eval_~tmp~0#1); 46515#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46161#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46567#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47094#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46747#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46748#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47327#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47499#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47491#L1372-3 assume !(0 == ~T7_E~0); 45539#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45540#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46205#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46206#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47142#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47445#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46694#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 45834#L1412-3 assume !(0 == ~E_1~0); 45835#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46596#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46597#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47325#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47005#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46710#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46711#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45603#L1452-3 assume !(0 == ~E_9~0); 45604#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47258#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47259#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47066#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47067#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 45832#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45833#L646-42 assume 1 == ~m_pc~0; 46428#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 47297#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46296#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46297#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47429#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47229#L665-42 assume 1 == ~t1_pc~0; 47188#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47190#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47404#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46011#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46012#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47498#L684-42 assume 1 == ~t2_pc~0; 46875#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46876#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46627#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46628#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46637#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46773#L703-42 assume !(1 == ~t3_pc~0); 46976#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46975#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47038#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47039#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47071#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46677#L722-42 assume 1 == ~t4_pc~0; 46678#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47107#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47103#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46153#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46154#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47465#L741-42 assume 1 == ~t5_pc~0; 47409#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46532#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46533#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46704#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46446#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46447#L760-42 assume !(1 == ~t6_pc~0); 46574#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 46723#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45925#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45926#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 46401#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46402#L779-42 assume 1 == ~t7_pc~0; 47248#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47195#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46731#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46732#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45934#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45935#L798-42 assume 1 == ~t8_pc~0; 46394#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45552#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46893#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46741#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45766#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45767#L817-42 assume 1 == ~t9_pc~0; 46541#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46049#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46050#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47193#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46997#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46998#L836-42 assume 1 == ~t10_pc~0; 47096#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46086#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46087#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46872#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47410#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47453#L855-42 assume 1 == ~t11_pc~0; 47463#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45640#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45641#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47172#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47173#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46261#L874-42 assume !(1 == ~t12_pc~0); 46262#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 46491#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46682#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46683#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45806#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45807#L893-42 assume !(1 == ~t13_pc~0); 46812#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 46813#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46228#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46229#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46188#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 46189#L912-42 assume 1 == ~t14_pc~0; 47446#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 45507#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45508#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46302#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 45931#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45932#L1495-3 assume !(1 == ~M_E~0); 46544#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46988#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47084#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46158#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46118#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46119#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46798#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47014#L1530-3 assume !(1 == ~T8_E~0); 45968#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45969#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46007#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47288#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47395#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46416#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 46417#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47045#L1570-3 assume !(1 == ~E_2~0); 46992#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46993#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47357#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47399#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47444#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46820#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46821#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47302#L1610-3 assume !(1 == ~E_10~0); 46169#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46170#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46786#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46787#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 46680#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46102#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45718#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45907#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 45908#L2036 assume !(0 == start_simulation_~tmp~3#1); 47015#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 47179#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 46327#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45553#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 45554#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46724#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47346#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 47347#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 46288#L2017-2 [2024-10-25 00:40:41,671 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:41,671 INFO L85 PathProgramCache]: Analyzing trace with hash 405064104, now seen corresponding path program 1 times [2024-10-25 00:40:41,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:41,671 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932066707] [2024-10-25 00:40:41,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:41,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:41,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:41,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:41,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:41,722 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932066707] [2024-10-25 00:40:41,722 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932066707] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:41,722 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:41,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:41,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466250126] [2024-10-25 00:40:41,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:41,723 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:41,724 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:41,724 INFO L85 PathProgramCache]: Analyzing trace with hash -345840495, now seen corresponding path program 1 times [2024-10-25 00:40:41,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:41,724 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936838125] [2024-10-25 00:40:41,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:41,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:41,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:41,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:41,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:41,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936838125] [2024-10-25 00:40:41,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936838125] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:41,791 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:41,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:41,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229259206] [2024-10-25 00:40:41,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:41,792 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:41,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:41,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:41,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:41,793 INFO L87 Difference]: Start difference. First operand 2062 states and 3039 transitions. cyclomatic complexity: 978 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:41,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:41,830 INFO L93 Difference]: Finished difference Result 2062 states and 3038 transitions. [2024-10-25 00:40:41,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3038 transitions. [2024-10-25 00:40:41,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:41,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3038 transitions. [2024-10-25 00:40:41,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:41,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:41,853 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3038 transitions. [2024-10-25 00:40:41,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:41,857 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3038 transitions. [2024-10-25 00:40:41,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3038 transitions. [2024-10-25 00:40:41,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:41,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4733268671193016) internal successors, (3038), 2061 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:41,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3038 transitions. [2024-10-25 00:40:41,897 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3038 transitions. [2024-10-25 00:40:41,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:41,898 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3038 transitions. [2024-10-25 00:40:41,899 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-25 00:40:41,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3038 transitions. [2024-10-25 00:40:41,944 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:41,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:41,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:41,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:41,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:41,949 INFO L745 eck$LassoCheckResult]: Stem: 49943#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 49944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 50875#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50876#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51637#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 50480#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50481#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50193#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50194#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51446#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50772#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50773#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 51311#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50678#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50679#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50103#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50104#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50450#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50632#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 49686#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49687#L1342 assume !(0 == ~M_E~0); 49853#L1342-2 assume !(0 == ~T1_E~0); 50417#L1347-1 assume !(0 == ~T2_E~0); 51427#L1352-1 assume !(0 == ~T3_E~0); 51218#L1357-1 assume !(0 == ~T4_E~0); 50439#L1362-1 assume !(0 == ~T5_E~0); 50440#L1367-1 assume !(0 == ~T6_E~0); 50018#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50019#L1377-1 assume !(0 == ~T8_E~0); 50357#L1382-1 assume !(0 == ~T9_E~0); 50358#L1387-1 assume !(0 == ~T10_E~0); 51099#L1392-1 assume !(0 == ~T11_E~0); 50400#L1397-1 assume !(0 == ~T12_E~0); 50401#L1402-1 assume !(0 == ~T13_E~0); 50042#L1407-1 assume !(0 == ~T14_E~0); 50043#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 51343#L1417-1 assume !(0 == ~E_2~0); 51344#L1422-1 assume !(0 == ~E_3~0); 51581#L1427-1 assume !(0 == ~E_4~0); 50222#L1432-1 assume !(0 == ~E_5~0); 50223#L1437-1 assume !(0 == ~E_6~0); 51263#L1442-1 assume !(0 == ~E_7~0); 51264#L1447-1 assume !(0 == ~E_8~0); 51093#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 49822#L1457-1 assume !(0 == ~E_10~0); 49823#L1462-1 assume !(0 == ~E_11~0); 51293#L1467-1 assume !(0 == ~E_12~0); 51306#L1472-1 assume !(0 == ~E_13~0); 51307#L1477-1 assume !(0 == ~E_14~0); 51042#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50007#L646 assume 1 == ~m_pc~0; 50008#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50688#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50703#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50105#L1666 assume !(0 != activate_threads_~tmp~1#1); 50106#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51602#L665 assume !(1 == ~t1_pc~0); 50583#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50584#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51192#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51193#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 50924#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50925#L684 assume 1 == ~t2_pc~0; 51041#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50965#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50091#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50092#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 51432#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51615#L703 assume !(1 == ~t3_pc~0); 50247#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50248#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51179#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49656#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 49657#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50135#L722 assume 1 == ~t4_pc~0; 50882#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50322#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49767#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49768#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 50724#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49854#L741 assume 1 == ~t5_pc~0; 49855#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50157#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50957#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51009#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 51010#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50418#L760 assume !(1 == ~t6_pc~0); 50246#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50245#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50083#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50084#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50839#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50840#L779 assume 1 == ~t7_pc~0; 49891#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49738#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49739#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51464#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 50169#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50170#L798 assume !(1 == ~t8_pc~0); 51474#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51391#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51392#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51556#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 51604#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49717#L817 assume 1 == ~t9_pc~0; 49718#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50516#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50139#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50140#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 50117#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50118#L836 assume !(1 == ~t10_pc~0); 50141#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50067#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50068#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50323#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 50324#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51404#L855 assume 1 == ~t11_pc~0; 50699#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50700#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51287#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51090#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 50930#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50004#L874 assume !(1 == ~t12_pc~0); 50005#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50178#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49706#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49707#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 49692#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49693#L893 assume 1 == ~t13_pc~0; 51539#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50045#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50356#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51487#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 51479#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 51480#L912 assume 1 == ~t14_pc~0; 51270#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 51271#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 51342#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 49941#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 49942#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50717#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 51148#L1495-2 assume !(1 == ~T1_E~0); 51149#L1500-1 assume !(1 == ~T2_E~0); 50833#L1505-1 assume !(1 == ~T3_E~0); 50834#L1510-1 assume !(1 == ~T4_E~0); 50892#L1515-1 assume !(1 == ~T5_E~0); 50893#L1520-1 assume !(1 == ~T6_E~0); 51475#L1525-1 assume !(1 == ~T7_E~0); 51180#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50110#L1535-1 assume !(1 == ~T9_E~0); 50111#L1540-1 assume !(1 == ~T10_E~0); 49617#L1545-1 assume !(1 == ~T11_E~0); 49618#L1550-1 assume !(1 == ~T12_E~0); 49864#L1555-1 assume !(1 == ~T13_E~0); 49865#L1560-1 assume !(1 == ~T14_E~0); 50162#L1565-1 assume !(1 == ~E_1~0); 51590#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 51063#L1575-1 assume !(1 == ~E_3~0); 50445#L1580-1 assume !(1 == ~E_4~0); 50446#L1585-1 assume !(1 == ~E_5~0); 50916#L1590-1 assume !(1 == ~E_6~0); 50474#L1595-1 assume !(1 == ~E_7~0); 50475#L1600-1 assume !(1 == ~E_8~0); 50847#L1605-1 assume !(1 == ~E_9~0); 50848#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 51378#L1615-1 assume !(1 == ~E_11~0); 50296#L1620-1 assume !(1 == ~E_12~0); 50297#L1625-1 assume !(1 == ~E_13~0); 51094#L1630-1 assume !(1 == ~E_14~0); 50473#L1635-1 assume { :end_inline_reset_delta_events } true; 50419#L2017-2 [2024-10-25 00:40:41,949 INFO L747 eck$LassoCheckResult]: Loop: 50419#L2017-2 assume !false; 49690#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49691#L1316-1 assume !false; 50079#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 51089#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49630#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49969#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 51113#L1115 assume !(0 != eval_~tmp~0#1); 50646#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50291#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50292#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50698#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51225#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50878#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50879#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51458#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51630#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51622#L1372-3 assume !(0 == ~T7_E~0); 49670#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49671#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50336#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50337#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51273#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51576#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50825#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 49965#L1412-3 assume !(0 == ~E_1~0); 49966#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50727#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50728#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51456#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51136#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50841#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50842#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49734#L1452-3 assume !(0 == ~E_9~0); 49735#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51389#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51390#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 51197#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51198#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 49963#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49964#L646-42 assume !(1 == ~m_pc~0); 50560#L646-44 is_master_triggered_~__retres1~0#1 := 0; 51428#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50427#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50428#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51560#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51360#L665-42 assume 1 == ~t1_pc~0; 51319#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51321#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51535#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50142#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50143#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51629#L684-42 assume !(1 == ~t2_pc~0); 51008#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 51007#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50758#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50759#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50768#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50904#L703-42 assume 1 == ~t3_pc~0; 51105#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51106#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51169#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51170#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51202#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50808#L722-42 assume 1 == ~t4_pc~0; 50809#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51238#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51234#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50284#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50285#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51596#L741-42 assume 1 == ~t5_pc~0; 51540#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50663#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50664#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50835#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50577#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50578#L760-42 assume !(1 == ~t6_pc~0); 50705#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 50854#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50056#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50057#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 50532#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50533#L779-42 assume 1 == ~t7_pc~0; 51379#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51326#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50862#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50863#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50065#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50066#L798-42 assume !(1 == ~t8_pc~0); 49682#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 49683#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51024#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50872#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49897#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49898#L817-42 assume 1 == ~t9_pc~0; 50672#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50180#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50181#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51324#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51128#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51129#L836-42 assume 1 == ~t10_pc~0; 51227#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50217#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50218#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51003#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51541#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51584#L855-42 assume 1 == ~t11_pc~0; 51594#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49771#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49772#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51303#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51304#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50392#L874-42 assume !(1 == ~t12_pc~0); 50393#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50622#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50813#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50814#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49937#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49938#L893-42 assume 1 == ~t13_pc~0; 51154#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50944#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50359#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50360#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50319#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 50320#L912-42 assume 1 == ~t14_pc~0; 51577#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 49638#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 49639#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50433#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 50062#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50063#L1495-3 assume !(1 == ~M_E~0); 50675#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51119#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51215#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50289#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50249#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50250#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50929#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51145#L1530-3 assume !(1 == ~T8_E~0); 50099#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50100#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50138#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51419#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51526#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50547#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 50548#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51176#L1570-3 assume !(1 == ~E_2~0); 51123#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51124#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51488#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51530#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51575#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50951#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50952#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51433#L1610-3 assume !(1 == ~E_10~0); 50300#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50301#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50917#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50918#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 50811#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50233#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49849#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 50038#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50039#L2036 assume !(0 == start_simulation_~tmp~3#1); 51146#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 51310#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 50458#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49684#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 49685#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50855#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51477#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 51478#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 50419#L2017-2 [2024-10-25 00:40:41,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:41,950 INFO L85 PathProgramCache]: Analyzing trace with hash 1016333162, now seen corresponding path program 1 times [2024-10-25 00:40:41,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:41,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117465153] [2024-10-25 00:40:41,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:41,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:41,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:42,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:42,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:42,015 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117465153] [2024-10-25 00:40:42,015 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117465153] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:42,015 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:42,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:42,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1963429941] [2024-10-25 00:40:42,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:42,016 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:42,016 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:42,017 INFO L85 PathProgramCache]: Analyzing trace with hash 88761904, now seen corresponding path program 1 times [2024-10-25 00:40:42,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:42,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809130896] [2024-10-25 00:40:42,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:42,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:42,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:42,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:42,094 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:42,094 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809130896] [2024-10-25 00:40:42,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1809130896] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:42,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:42,094 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:42,094 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [706751165] [2024-10-25 00:40:42,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:42,095 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:42,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:42,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:42,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:42,096 INFO L87 Difference]: Start difference. First operand 2062 states and 3038 transitions. cyclomatic complexity: 977 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:42,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:42,136 INFO L93 Difference]: Finished difference Result 2062 states and 3037 transitions. [2024-10-25 00:40:42,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3037 transitions. [2024-10-25 00:40:42,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:42,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3037 transitions. [2024-10-25 00:40:42,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:42,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:42,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3037 transitions. [2024-10-25 00:40:42,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:42,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3037 transitions. [2024-10-25 00:40:42,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3037 transitions. [2024-10-25 00:40:42,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:42,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.4728419010669254) internal successors, (3037), 2061 states have internal predecessors, (3037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:42,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3037 transitions. [2024-10-25 00:40:42,207 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3037 transitions. [2024-10-25 00:40:42,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:42,208 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3037 transitions. [2024-10-25 00:40:42,208 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-25 00:40:42,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3037 transitions. [2024-10-25 00:40:42,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:42,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:42,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:42,219 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:42,219 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:42,220 INFO L745 eck$LassoCheckResult]: Stem: 54074#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 54075#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 55006#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55007#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55768#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 54611#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54612#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54324#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54325#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55577#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54903#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54904#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55442#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54809#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54810#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54234#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54235#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54581#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54763#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 53817#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53818#L1342 assume !(0 == ~M_E~0); 53984#L1342-2 assume !(0 == ~T1_E~0); 54548#L1347-1 assume !(0 == ~T2_E~0); 55558#L1352-1 assume !(0 == ~T3_E~0); 55349#L1357-1 assume !(0 == ~T4_E~0); 54570#L1362-1 assume !(0 == ~T5_E~0); 54571#L1367-1 assume !(0 == ~T6_E~0); 54149#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54150#L1377-1 assume !(0 == ~T8_E~0); 54488#L1382-1 assume !(0 == ~T9_E~0); 54489#L1387-1 assume !(0 == ~T10_E~0); 55230#L1392-1 assume !(0 == ~T11_E~0); 54531#L1397-1 assume !(0 == ~T12_E~0); 54532#L1402-1 assume !(0 == ~T13_E~0); 54173#L1407-1 assume !(0 == ~T14_E~0); 54174#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 55474#L1417-1 assume !(0 == ~E_2~0); 55475#L1422-1 assume !(0 == ~E_3~0); 55712#L1427-1 assume !(0 == ~E_4~0); 54353#L1432-1 assume !(0 == ~E_5~0); 54354#L1437-1 assume !(0 == ~E_6~0); 55394#L1442-1 assume !(0 == ~E_7~0); 55395#L1447-1 assume !(0 == ~E_8~0); 55224#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 53953#L1457-1 assume !(0 == ~E_10~0); 53954#L1462-1 assume !(0 == ~E_11~0); 55424#L1467-1 assume !(0 == ~E_12~0); 55437#L1472-1 assume !(0 == ~E_13~0); 55438#L1477-1 assume !(0 == ~E_14~0); 55173#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54138#L646 assume 1 == ~m_pc~0; 54139#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54819#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54834#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54236#L1666 assume !(0 != activate_threads_~tmp~1#1); 54237#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55733#L665 assume !(1 == ~t1_pc~0); 54714#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54715#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55323#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55324#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 55055#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55056#L684 assume 1 == ~t2_pc~0; 55172#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55096#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54224#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54225#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 55563#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55746#L703 assume !(1 == ~t3_pc~0); 54378#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54379#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55310#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53787#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 53788#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54266#L722 assume 1 == ~t4_pc~0; 55013#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54453#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53898#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53899#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 54855#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53985#L741 assume 1 == ~t5_pc~0; 53986#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54288#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55088#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55140#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 55141#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54549#L760 assume !(1 == ~t6_pc~0); 54377#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 54376#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54214#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54215#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54970#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54971#L779 assume 1 == ~t7_pc~0; 54022#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53869#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53870#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55595#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 54300#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54301#L798 assume !(1 == ~t8_pc~0); 55605#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 55522#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55523#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55687#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 55735#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53848#L817 assume 1 == ~t9_pc~0; 53849#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54647#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54270#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54271#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 54248#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54249#L836 assume !(1 == ~t10_pc~0); 54272#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 54198#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54199#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54454#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 54455#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55535#L855 assume 1 == ~t11_pc~0; 54830#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54831#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55418#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55221#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 55061#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54135#L874 assume !(1 == ~t12_pc~0); 54136#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54309#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53837#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53838#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 53823#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53824#L893 assume 1 == ~t13_pc~0; 55670#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54176#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54487#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 55618#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 55610#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 55611#L912 assume 1 == ~t14_pc~0; 55401#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 55402#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 55473#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54072#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 54073#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54848#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 55279#L1495-2 assume !(1 == ~T1_E~0); 55280#L1500-1 assume !(1 == ~T2_E~0); 54964#L1505-1 assume !(1 == ~T3_E~0); 54965#L1510-1 assume !(1 == ~T4_E~0); 55023#L1515-1 assume !(1 == ~T5_E~0); 55024#L1520-1 assume !(1 == ~T6_E~0); 55606#L1525-1 assume !(1 == ~T7_E~0); 55311#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54241#L1535-1 assume !(1 == ~T9_E~0); 54242#L1540-1 assume !(1 == ~T10_E~0); 53748#L1545-1 assume !(1 == ~T11_E~0); 53749#L1550-1 assume !(1 == ~T12_E~0); 53995#L1555-1 assume !(1 == ~T13_E~0); 53996#L1560-1 assume !(1 == ~T14_E~0); 54293#L1565-1 assume !(1 == ~E_1~0); 55721#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 55194#L1575-1 assume !(1 == ~E_3~0); 54576#L1580-1 assume !(1 == ~E_4~0); 54577#L1585-1 assume !(1 == ~E_5~0); 55047#L1590-1 assume !(1 == ~E_6~0); 54605#L1595-1 assume !(1 == ~E_7~0); 54606#L1600-1 assume !(1 == ~E_8~0); 54978#L1605-1 assume !(1 == ~E_9~0); 54979#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 55509#L1615-1 assume !(1 == ~E_11~0); 54427#L1620-1 assume !(1 == ~E_12~0); 54428#L1625-1 assume !(1 == ~E_13~0); 55225#L1630-1 assume !(1 == ~E_14~0); 54604#L1635-1 assume { :end_inline_reset_delta_events } true; 54550#L2017-2 [2024-10-25 00:40:42,220 INFO L747 eck$LassoCheckResult]: Loop: 54550#L2017-2 assume !false; 53821#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53822#L1316-1 assume !false; 54210#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55220#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53761#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 54100#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55244#L1115 assume !(0 != eval_~tmp~0#1); 54777#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54422#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54423#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54829#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55356#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55009#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55010#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55589#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55761#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55753#L1372-3 assume !(0 == ~T7_E~0); 53801#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53802#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54467#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54468#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55404#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 55707#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54956#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 54096#L1412-3 assume !(0 == ~E_1~0); 54097#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54858#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54859#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55587#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55267#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54972#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54973#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53865#L1452-3 assume !(0 == ~E_9~0); 53866#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55520#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55521#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 55328#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 55329#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 54094#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54095#L646-42 assume 1 == ~m_pc~0; 54690#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 55559#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54558#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54559#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55691#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55491#L665-42 assume 1 == ~t1_pc~0; 55450#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55452#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55666#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54273#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54274#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55760#L684-42 assume 1 == ~t2_pc~0; 55137#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55138#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54889#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54890#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54899#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55035#L703-42 assume 1 == ~t3_pc~0; 55236#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55237#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55300#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55301#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55333#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54939#L722-42 assume 1 == ~t4_pc~0; 54940#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 55369#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55365#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54415#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54416#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55727#L741-42 assume !(1 == ~t5_pc~0); 55345#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 54794#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54795#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54966#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54708#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54709#L760-42 assume !(1 == ~t6_pc~0); 54836#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 54985#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54187#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54188#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 54663#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54664#L779-42 assume !(1 == ~t7_pc~0); 55456#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 55457#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54993#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54994#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54196#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54197#L798-42 assume 1 == ~t8_pc~0; 54656#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53814#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55155#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55003#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54028#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54029#L817-42 assume 1 == ~t9_pc~0; 54801#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54311#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54312#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55455#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55259#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55260#L836-42 assume 1 == ~t10_pc~0; 55358#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 54348#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54349#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55134#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55672#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55715#L855-42 assume 1 == ~t11_pc~0; 55725#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53902#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53903#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55434#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 55435#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54526#L874-42 assume 1 == ~t12_pc~0; 54528#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54753#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54944#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54945#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54068#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54069#L893-42 assume !(1 == ~t13_pc~0); 55074#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 55075#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54490#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54491#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54450#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 54451#L912-42 assume 1 == ~t14_pc~0; 55708#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 53769#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53770#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54564#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 54193#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54194#L1495-3 assume !(1 == ~M_E~0); 54806#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55250#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55346#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54420#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54380#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54381#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55060#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55276#L1530-3 assume !(1 == ~T8_E~0); 54230#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54231#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54269#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 55550#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55657#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54678#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 54679#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55307#L1570-3 assume !(1 == ~E_2~0); 55254#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55255#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55619#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55661#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55706#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 55082#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 55083#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 55564#L1610-3 assume !(1 == ~E_10~0); 54431#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54432#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 55048#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 55049#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 54942#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 54364#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53980#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 54169#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54170#L2036 assume !(0 == start_simulation_~tmp~3#1); 55277#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55441#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 54589#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 53815#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 53816#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54986#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55608#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 55609#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 54550#L2017-2 [2024-10-25 00:40:42,221 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:42,221 INFO L85 PathProgramCache]: Analyzing trace with hash -1873442456, now seen corresponding path program 1 times [2024-10-25 00:40:42,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:42,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740194840] [2024-10-25 00:40:42,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:42,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:42,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:42,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:42,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:42,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740194840] [2024-10-25 00:40:42,279 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740194840] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:42,280 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:42,280 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:42,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [843486902] [2024-10-25 00:40:42,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:42,281 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:42,281 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:42,281 INFO L85 PathProgramCache]: Analyzing trace with hash -1792394543, now seen corresponding path program 1 times [2024-10-25 00:40:42,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:42,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264460966] [2024-10-25 00:40:42,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:42,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:42,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:42,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:42,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:42,348 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264460966] [2024-10-25 00:40:42,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264460966] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:42,349 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:42,349 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:42,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1056397175] [2024-10-25 00:40:42,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:42,351 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:42,351 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:42,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:42,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:42,352 INFO L87 Difference]: Start difference. First operand 2062 states and 3037 transitions. cyclomatic complexity: 976 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:42,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:42,385 INFO L93 Difference]: Finished difference Result 2062 states and 3036 transitions. [2024-10-25 00:40:42,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2062 states and 3036 transitions. [2024-10-25 00:40:42,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:42,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2062 states to 2062 states and 3036 transitions. [2024-10-25 00:40:42,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2062 [2024-10-25 00:40:42,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2062 [2024-10-25 00:40:42,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2062 states and 3036 transitions. [2024-10-25 00:40:42,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:42,414 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3036 transitions. [2024-10-25 00:40:42,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2062 states and 3036 transitions. [2024-10-25 00:40:42,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2062 to 2062. [2024-10-25 00:40:42,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2062 states, 2062 states have (on average 1.472356935014549) internal successors, (3036), 2061 states have internal predecessors, (3036), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:42,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2062 states to 2062 states and 3036 transitions. [2024-10-25 00:40:42,451 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2062 states and 3036 transitions. [2024-10-25 00:40:42,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:42,452 INFO L425 stractBuchiCegarLoop]: Abstraction has 2062 states and 3036 transitions. [2024-10-25 00:40:42,453 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-25 00:40:42,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2062 states and 3036 transitions. [2024-10-25 00:40:42,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1877 [2024-10-25 00:40:42,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:42,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:42,464 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:42,464 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:42,464 INFO L745 eck$LassoCheckResult]: Stem: 58205#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 58206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 59137#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59138#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59899#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 58742#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58743#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58455#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58456#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59708#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59034#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59035#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59573#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58940#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58941#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 58365#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 58366#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 58712#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 58894#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 57948#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57949#L1342 assume !(0 == ~M_E~0); 58115#L1342-2 assume !(0 == ~T1_E~0); 58679#L1347-1 assume !(0 == ~T2_E~0); 59689#L1352-1 assume !(0 == ~T3_E~0); 59480#L1357-1 assume !(0 == ~T4_E~0); 58701#L1362-1 assume !(0 == ~T5_E~0); 58702#L1367-1 assume !(0 == ~T6_E~0); 58280#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58281#L1377-1 assume !(0 == ~T8_E~0); 58619#L1382-1 assume !(0 == ~T9_E~0); 58620#L1387-1 assume !(0 == ~T10_E~0); 59361#L1392-1 assume !(0 == ~T11_E~0); 58662#L1397-1 assume !(0 == ~T12_E~0); 58663#L1402-1 assume !(0 == ~T13_E~0); 58304#L1407-1 assume !(0 == ~T14_E~0); 58305#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 59605#L1417-1 assume !(0 == ~E_2~0); 59606#L1422-1 assume !(0 == ~E_3~0); 59843#L1427-1 assume !(0 == ~E_4~0); 58484#L1432-1 assume !(0 == ~E_5~0); 58485#L1437-1 assume !(0 == ~E_6~0); 59525#L1442-1 assume !(0 == ~E_7~0); 59526#L1447-1 assume !(0 == ~E_8~0); 59355#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 58084#L1457-1 assume !(0 == ~E_10~0); 58085#L1462-1 assume !(0 == ~E_11~0); 59555#L1467-1 assume !(0 == ~E_12~0); 59568#L1472-1 assume !(0 == ~E_13~0); 59569#L1477-1 assume !(0 == ~E_14~0); 59304#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58269#L646 assume 1 == ~m_pc~0; 58270#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58950#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58965#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58367#L1666 assume !(0 != activate_threads_~tmp~1#1); 58368#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59864#L665 assume !(1 == ~t1_pc~0); 58845#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58846#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59454#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59455#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 59186#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59187#L684 assume 1 == ~t2_pc~0; 59303#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59227#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58355#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58356#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 59694#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59877#L703 assume !(1 == ~t3_pc~0); 58509#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58510#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59441#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57918#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 57919#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58397#L722 assume 1 == ~t4_pc~0; 59144#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58584#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58029#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58030#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 58986#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58116#L741 assume 1 == ~t5_pc~0; 58117#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58419#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59219#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59271#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 59272#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58680#L760 assume !(1 == ~t6_pc~0); 58508#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 58507#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58346#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59101#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59102#L779 assume 1 == ~t7_pc~0; 58153#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58000#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58001#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59726#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 58431#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58432#L798 assume !(1 == ~t8_pc~0); 59736#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59653#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59654#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59818#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 59866#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57979#L817 assume 1 == ~t9_pc~0; 57980#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58778#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58401#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58402#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 58379#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58380#L836 assume !(1 == ~t10_pc~0); 58403#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58329#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58330#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58585#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 58586#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59666#L855 assume 1 == ~t11_pc~0; 58961#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58962#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59549#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59352#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 59192#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58266#L874 assume !(1 == ~t12_pc~0); 58267#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58440#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57968#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57969#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 57954#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57955#L893 assume 1 == ~t13_pc~0; 59801#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 58307#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58618#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59749#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 59741#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 59742#L912 assume 1 == ~t14_pc~0; 59532#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 59533#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 59604#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 58203#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 58204#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58979#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 59410#L1495-2 assume !(1 == ~T1_E~0); 59411#L1500-1 assume !(1 == ~T2_E~0); 59095#L1505-1 assume !(1 == ~T3_E~0); 59096#L1510-1 assume !(1 == ~T4_E~0); 59154#L1515-1 assume !(1 == ~T5_E~0); 59155#L1520-1 assume !(1 == ~T6_E~0); 59737#L1525-1 assume !(1 == ~T7_E~0); 59442#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 58372#L1535-1 assume !(1 == ~T9_E~0); 58373#L1540-1 assume !(1 == ~T10_E~0); 57879#L1545-1 assume !(1 == ~T11_E~0); 57880#L1550-1 assume !(1 == ~T12_E~0); 58126#L1555-1 assume !(1 == ~T13_E~0); 58127#L1560-1 assume !(1 == ~T14_E~0); 58424#L1565-1 assume !(1 == ~E_1~0); 59852#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 59325#L1575-1 assume !(1 == ~E_3~0); 58707#L1580-1 assume !(1 == ~E_4~0); 58708#L1585-1 assume !(1 == ~E_5~0); 59178#L1590-1 assume !(1 == ~E_6~0); 58736#L1595-1 assume !(1 == ~E_7~0); 58737#L1600-1 assume !(1 == ~E_8~0); 59111#L1605-1 assume !(1 == ~E_9~0); 59112#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 59640#L1615-1 assume !(1 == ~E_11~0); 58558#L1620-1 assume !(1 == ~E_12~0); 58559#L1625-1 assume !(1 == ~E_13~0); 59356#L1630-1 assume !(1 == ~E_14~0); 58735#L1635-1 assume { :end_inline_reset_delta_events } true; 58681#L2017-2 [2024-10-25 00:40:42,465 INFO L747 eck$LassoCheckResult]: Loop: 58681#L2017-2 assume !false; 57952#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57953#L1316-1 assume !false; 58341#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 59351#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57892#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 58232#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 59375#L1115 assume !(0 != eval_~tmp~0#1); 58908#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58553#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58554#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58960#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59487#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59140#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59141#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59720#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59892#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59884#L1372-3 assume !(0 == ~T7_E~0); 57932#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57933#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 58598#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58599#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59535#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59838#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59087#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 58227#L1412-3 assume !(0 == ~E_1~0); 58228#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58989#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58990#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59718#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59398#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59103#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59104#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57996#L1452-3 assume !(0 == ~E_9~0); 57997#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59651#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59652#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 59459#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59460#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 58225#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58226#L646-42 assume 1 == ~m_pc~0; 58821#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59690#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58689#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58690#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59822#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59622#L665-42 assume 1 == ~t1_pc~0; 59581#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59583#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59797#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58404#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58405#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59891#L684-42 assume 1 == ~t2_pc~0; 59268#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59269#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59020#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59021#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59030#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59166#L703-42 assume 1 == ~t3_pc~0; 59367#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 59368#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59431#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59432#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59464#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59070#L722-42 assume !(1 == ~t4_pc~0); 59072#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 59500#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59496#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58546#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58547#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59858#L741-42 assume !(1 == ~t5_pc~0); 59476#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 58925#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58926#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59097#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58839#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58840#L760-42 assume !(1 == ~t6_pc~0); 58967#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 59116#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58318#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58319#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 58794#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58795#L779-42 assume !(1 == ~t7_pc~0); 59587#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 59588#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59124#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59125#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58327#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58328#L798-42 assume 1 == ~t8_pc~0; 58787#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 57945#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59286#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59134#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58155#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58156#L817-42 assume 1 == ~t9_pc~0; 58932#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58442#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58443#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59586#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59390#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59391#L836-42 assume 1 == ~t10_pc~0; 59489#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58479#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58480#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59265#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59803#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59846#L855-42 assume 1 == ~t11_pc~0; 59856#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58033#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58034#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59565#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59566#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58657#L874-42 assume !(1 == ~t12_pc~0); 58658#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 58884#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59075#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59076#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58199#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58200#L893-42 assume !(1 == ~t13_pc~0); 59205#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 59206#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58621#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58622#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58581#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 58582#L912-42 assume !(1 == ~t14_pc~0); 59394#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 57900#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57901#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 58695#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 58324#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58325#L1495-3 assume !(1 == ~M_E~0); 58937#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59381#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59477#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58551#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58511#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58512#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 59191#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 59407#L1530-3 assume !(1 == ~T8_E~0); 58361#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 58362#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58400#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59681#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59788#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58809#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 58810#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59438#L1570-3 assume !(1 == ~E_2~0); 59385#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59386#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59750#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59792#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59837#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59213#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59214#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59695#L1610-3 assume !(1 == ~E_10~0); 58562#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58563#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 59179#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 59180#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 59073#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58495#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 58111#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 58300#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 58301#L2036 assume !(0 == start_simulation_~tmp~3#1); 59408#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 59572#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 58720#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 57946#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 57947#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59117#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59739#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 59740#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 58681#L2017-2 [2024-10-25 00:40:42,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:42,466 INFO L85 PathProgramCache]: Analyzing trace with hash 527190954, now seen corresponding path program 1 times [2024-10-25 00:40:42,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:42,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458310790] [2024-10-25 00:40:42,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:42,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:42,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:42,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:42,565 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:42,565 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458310790] [2024-10-25 00:40:42,565 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458310790] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:42,566 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:42,566 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:42,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896168763] [2024-10-25 00:40:42,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:42,566 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:42,567 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:42,567 INFO L85 PathProgramCache]: Analyzing trace with hash 1582164910, now seen corresponding path program 1 times [2024-10-25 00:40:42,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:42,567 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778975712] [2024-10-25 00:40:42,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:42,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:42,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:42,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:42,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:42,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1778975712] [2024-10-25 00:40:42,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1778975712] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:42,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:42,638 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:42,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451921690] [2024-10-25 00:40:42,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:42,639 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:42,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:42,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-25 00:40:42,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-25 00:40:42,640 INFO L87 Difference]: Start difference. First operand 2062 states and 3036 transitions. cyclomatic complexity: 975 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:42,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:42,825 INFO L93 Difference]: Finished difference Result 3966 states and 5830 transitions. [2024-10-25 00:40:42,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3966 states and 5830 transitions. [2024-10-25 00:40:42,846 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3754 [2024-10-25 00:40:42,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3966 states to 3966 states and 5830 transitions. [2024-10-25 00:40:42,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3966 [2024-10-25 00:40:42,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3966 [2024-10-25 00:40:42,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3966 states and 5830 transitions. [2024-10-25 00:40:42,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:42,870 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3966 states and 5830 transitions. [2024-10-25 00:40:42,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3966 states and 5830 transitions. [2024-10-25 00:40:42,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3966 to 3966. [2024-10-25 00:40:42,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3966 states, 3966 states have (on average 1.469994957135653) internal successors, (5830), 3965 states have internal predecessors, (5830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:42,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3966 states to 3966 states and 5830 transitions. [2024-10-25 00:40:42,951 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3966 states and 5830 transitions. [2024-10-25 00:40:42,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-25 00:40:42,952 INFO L425 stractBuchiCegarLoop]: Abstraction has 3966 states and 5830 transitions. [2024-10-25 00:40:42,952 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-25 00:40:42,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3966 states and 5830 transitions. [2024-10-25 00:40:42,966 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3754 [2024-10-25 00:40:42,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:42,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:42,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:42,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:42,969 INFO L745 eck$LassoCheckResult]: Stem: 64243#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 64244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 65185#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65186#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66082#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 64784#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64785#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64494#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64495#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65813#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65079#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65080#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65659#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64984#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64985#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64404#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64405#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64753#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 64937#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 63984#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63985#L1342 assume !(0 == ~M_E~0); 64153#L1342-2 assume !(0 == ~T1_E~0); 64720#L1347-1 assume !(0 == ~T2_E~0); 65790#L1352-1 assume !(0 == ~T3_E~0); 65551#L1357-1 assume !(0 == ~T4_E~0); 64742#L1362-1 assume !(0 == ~T5_E~0); 64743#L1367-1 assume !(0 == ~T6_E~0); 64318#L1372-1 assume !(0 == ~T7_E~0); 64319#L1377-1 assume !(0 == ~T8_E~0); 64660#L1382-1 assume !(0 == ~T9_E~0); 64661#L1387-1 assume !(0 == ~T10_E~0); 65422#L1392-1 assume !(0 == ~T11_E~0); 64701#L1397-1 assume !(0 == ~T12_E~0); 64702#L1402-1 assume !(0 == ~T13_E~0); 64342#L1407-1 assume !(0 == ~T14_E~0); 64343#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 65694#L1417-1 assume !(0 == ~E_2~0); 65695#L1422-1 assume !(0 == ~E_3~0); 65993#L1427-1 assume !(0 == ~E_4~0); 64523#L1432-1 assume !(0 == ~E_5~0); 64524#L1437-1 assume !(0 == ~E_6~0); 65603#L1442-1 assume !(0 == ~E_7~0); 65604#L1447-1 assume !(0 == ~E_8~0); 65416#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 64122#L1457-1 assume !(0 == ~E_10~0); 64123#L1462-1 assume !(0 == ~E_11~0); 65637#L1467-1 assume !(0 == ~E_12~0); 65653#L1472-1 assume !(0 == ~E_13~0); 65654#L1477-1 assume !(0 == ~E_14~0); 65361#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64307#L646 assume 1 == ~m_pc~0; 64308#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 64995#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65010#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64406#L1666 assume !(0 != activate_threads_~tmp~1#1); 64407#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66024#L665 assume !(1 == ~t1_pc~0); 64887#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64888#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65521#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65522#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 65235#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65236#L684 assume 1 == ~t2_pc~0; 65358#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65278#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64392#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64393#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 65795#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66046#L703 assume !(1 == ~t3_pc~0); 64548#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64549#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65508#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63956#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 63957#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64436#L722 assume 1 == ~t4_pc~0; 65192#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64624#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64067#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64068#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 65031#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64154#L741 assume 1 == ~t5_pc~0; 64155#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64458#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65271#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65326#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 65327#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64721#L760 assume !(1 == ~t6_pc~0); 64547#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64546#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64384#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64385#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65147#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65148#L779 assume 1 == ~t7_pc~0; 64191#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64038#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64039#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65836#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 64470#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64471#L798 assume !(1 == ~t8_pc~0); 65847#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 65748#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65749#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65962#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 66026#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64017#L817 assume 1 == ~t9_pc~0; 64018#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64820#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64440#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64441#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 64418#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64419#L836 assume !(1 == ~t10_pc~0); 64442#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64367#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64368#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64625#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 64626#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65763#L855 assume 1 == ~t11_pc~0; 65006#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65007#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65629#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65413#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 65242#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64304#L874 assume !(1 == ~t12_pc~0); 64305#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 64479#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64006#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64007#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 63992#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 63993#L893 assume 1 == ~t13_pc~0; 65930#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 64345#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64659#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 65865#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 65853#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 65854#L912 assume 1 == ~t14_pc~0; 65611#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 65612#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 65691#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 64241#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 64242#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65024#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 65475#L1495-2 assume !(1 == ~T1_E~0); 65476#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65141#L1505-1 assume !(1 == ~T3_E~0); 65142#L1510-1 assume !(1 == ~T4_E~0); 65202#L1515-1 assume !(1 == ~T5_E~0); 65203#L1520-1 assume !(1 == ~T6_E~0); 65848#L1525-1 assume !(1 == ~T7_E~0); 65849#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66518#L1535-1 assume !(1 == ~T9_E~0); 66055#L1540-1 assume !(1 == ~T10_E~0); 63917#L1545-1 assume !(1 == ~T11_E~0); 63918#L1550-1 assume !(1 == ~T12_E~0); 64164#L1555-1 assume !(1 == ~T13_E~0); 64165#L1560-1 assume !(1 == ~T14_E~0); 64461#L1565-1 assume !(1 == ~E_1~0); 66005#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 66084#L1575-1 assume !(1 == ~E_3~0); 66434#L1580-1 assume !(1 == ~E_4~0); 65226#L1585-1 assume !(1 == ~E_5~0); 65227#L1590-1 assume !(1 == ~E_6~0); 66433#L1595-1 assume !(1 == ~E_7~0); 66075#L1600-1 assume !(1 == ~E_8~0); 65155#L1605-1 assume !(1 == ~E_9~0); 65156#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65734#L1615-1 assume !(1 == ~E_11~0); 64597#L1620-1 assume !(1 == ~E_12~0); 64598#L1625-1 assume !(1 == ~E_13~0); 65417#L1630-1 assume !(1 == ~E_14~0); 64776#L1635-1 assume { :end_inline_reset_delta_events } true; 64777#L2017-2 [2024-10-25 00:40:42,970 INFO L747 eck$LassoCheckResult]: Loop: 64777#L2017-2 assume !false; 66129#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64379#L1316-1 assume !false; 64380#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 66124#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 66113#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 65767#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65768#L1115 assume !(0 != eval_~tmp~0#1); 66111#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66110#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66109#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65558#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65559#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66108#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67668#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67666#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67664#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67662#L1372-3 assume !(0 == ~T7_E~0); 67659#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67657#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67655#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67653#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 67651#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 67649#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 67646#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 67645#L1412-3 assume !(0 == ~E_1~0); 67644#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67643#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67642#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67641#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67640#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67639#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67638#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67637#L1452-3 assume !(0 == ~E_9~0); 67636#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 67635#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67634#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 67633#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 67632#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 67631#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67630#L646-42 assume !(1 == ~m_pc~0); 67629#L646-44 is_master_triggered_~__retres1~0#1 := 0; 67120#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67119#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67118#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67117#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67116#L665-42 assume 1 == ~t1_pc~0; 65667#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65669#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65926#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64443#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64444#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66070#L684-42 assume 1 == ~t2_pc~0; 65322#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65323#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65065#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65066#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65075#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65214#L703-42 assume 1 == ~t3_pc~0; 66021#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 67101#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67100#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67099#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67098#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67097#L722-42 assume 1 == ~t4_pc~0; 65576#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65577#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65572#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64585#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64586#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66083#L741-42 assume 1 == ~t5_pc~0; 65931#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64968#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64969#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65143#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64881#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64882#L760-42 assume !(1 == ~t6_pc~0); 65012#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 66688#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66687#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66686#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 66683#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65802#L779-42 assume 1 == ~t7_pc~0; 65735#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65676#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65170#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65171#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64365#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64366#L798-42 assume 1 == ~t8_pc~0; 64829#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63983#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65877#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66624#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66622#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65832#L817-42 assume 1 == ~t9_pc~0; 65833#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66599#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66593#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66592#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66591#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66590#L836-42 assume 1 == ~t10_pc~0; 65563#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64518#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64519#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65933#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65934#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66576#L855-42 assume !(1 == ~t11_pc~0); 66011#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 64073#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64074#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65651#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65652#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64698#L874-42 assume !(1 == ~t12_pc~0); 64699#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 64928#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65121#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65122#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64237#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 64238#L893-42 assume !(1 == ~t13_pc~0); 66101#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 66544#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66542#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 66541#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66540#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 66539#L912-42 assume 1 == ~t14_pc~0; 65985#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 63940#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 63941#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 64736#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 64362#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64363#L1495-3 assume !(1 == ~M_E~0); 64981#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65444#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65547#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64590#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64550#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64551#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66526#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65470#L1530-3 assume !(1 == ~T8_E~0); 66524#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 66517#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65781#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65782#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 65924#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 66499#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 66497#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66496#L1570-3 assume !(1 == ~E_2~0); 66495#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66494#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66493#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66492#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 66491#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66490#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65796#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65797#L1610-3 assume !(1 == ~E_10~0); 66485#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 66483#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 65228#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 65229#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 66105#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 66448#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 66438#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 66436#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 65472#L2036 assume !(0 == start_simulation_~tmp~3#1); 65473#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 65972#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 64767#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 63986#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 63987#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65163#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66017#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 66051#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 64777#L2017-2 [2024-10-25 00:40:42,971 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:42,971 INFO L85 PathProgramCache]: Analyzing trace with hash 1463218542, now seen corresponding path program 1 times [2024-10-25 00:40:42,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:42,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934491579] [2024-10-25 00:40:42,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:42,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:42,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:43,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:43,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:43,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934491579] [2024-10-25 00:40:43,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934491579] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:43,051 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:43,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:43,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1646257847] [2024-10-25 00:40:43,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:43,052 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:43,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:43,053 INFO L85 PathProgramCache]: Analyzing trace with hash 696783792, now seen corresponding path program 1 times [2024-10-25 00:40:43,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:43,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133517555] [2024-10-25 00:40:43,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:43,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:43,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:43,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:43,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:43,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133517555] [2024-10-25 00:40:43,120 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133517555] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:43,120 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:43,120 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:43,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [251293208] [2024-10-25 00:40:43,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:43,121 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:43,121 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:43,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-25 00:40:43,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-25 00:40:43,121 INFO L87 Difference]: Start difference. First operand 3966 states and 5830 transitions. cyclomatic complexity: 1866 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:43,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:43,352 INFO L93 Difference]: Finished difference Result 7544 states and 11081 transitions. [2024-10-25 00:40:43,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7544 states and 11081 transitions. [2024-10-25 00:40:43,398 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7292 [2024-10-25 00:40:43,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7544 states to 7544 states and 11081 transitions. [2024-10-25 00:40:43,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7544 [2024-10-25 00:40:43,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7544 [2024-10-25 00:40:43,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7544 states and 11081 transitions. [2024-10-25 00:40:43,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:43,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7544 states and 11081 transitions. [2024-10-25 00:40:43,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7544 states and 11081 transitions. [2024-10-25 00:40:43,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7544 to 7540. [2024-10-25 00:40:43,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7540 states, 7540 states have (on average 1.4690981432360743) internal successors, (11077), 7539 states have internal predecessors, (11077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:43,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7540 states to 7540 states and 11077 transitions. [2024-10-25 00:40:43,684 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7540 states and 11077 transitions. [2024-10-25 00:40:43,685 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-25 00:40:43,685 INFO L425 stractBuchiCegarLoop]: Abstraction has 7540 states and 11077 transitions. [2024-10-25 00:40:43,685 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-25 00:40:43,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7540 states and 11077 transitions. [2024-10-25 00:40:43,711 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7292 [2024-10-25 00:40:43,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:43,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:43,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:43,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:43,715 INFO L745 eck$LassoCheckResult]: Stem: 75764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 75765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 76729#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76730#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77619#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 76316#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76317#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76024#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76025#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77342#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76617#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76618#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77191#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76522#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76523#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75929#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 75930#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76284#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 76473#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 75504#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75505#L1342 assume !(0 == ~M_E~0); 75673#L1342-2 assume !(0 == ~T1_E~0); 76249#L1347-1 assume !(0 == ~T2_E~0); 77322#L1352-1 assume !(0 == ~T3_E~0); 77092#L1357-1 assume !(0 == ~T4_E~0); 76273#L1362-1 assume !(0 == ~T5_E~0); 76274#L1367-1 assume !(0 == ~T6_E~0); 75841#L1372-1 assume !(0 == ~T7_E~0); 75842#L1377-1 assume !(0 == ~T8_E~0); 76189#L1382-1 assume !(0 == ~T9_E~0); 76190#L1387-1 assume !(0 == ~T10_E~0); 76962#L1392-1 assume !(0 == ~T11_E~0); 76230#L1397-1 assume !(0 == ~T12_E~0); 76231#L1402-1 assume !(0 == ~T13_E~0); 75866#L1407-1 assume !(0 == ~T14_E~0); 75867#L1412-1 assume !(0 == ~E_1~0); 77224#L1417-1 assume !(0 == ~E_2~0); 77225#L1422-1 assume !(0 == ~E_3~0); 77526#L1427-1 assume !(0 == ~E_4~0); 76053#L1432-1 assume !(0 == ~E_5~0); 76054#L1437-1 assume !(0 == ~E_6~0); 77137#L1442-1 assume !(0 == ~E_7~0); 77138#L1447-1 assume !(0 == ~E_8~0); 76956#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 75642#L1457-1 assume !(0 == ~E_10~0); 75643#L1462-1 assume !(0 == ~E_11~0); 77170#L1467-1 assume !(0 == ~E_12~0); 77185#L1472-1 assume !(0 == ~E_13~0); 77186#L1477-1 assume !(0 == ~E_14~0); 76901#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75830#L646 assume 1 == ~m_pc~0; 75831#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 76532#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76547#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75931#L1666 assume !(0 != activate_threads_~tmp~1#1); 75932#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77553#L665 assume !(1 == ~t1_pc~0); 76422#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76423#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77065#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77066#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 76779#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76780#L684 assume 1 == ~t2_pc~0; 76897#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76819#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75917#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75918#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 77327#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77571#L703 assume !(1 == ~t3_pc~0); 76078#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76079#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77049#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75476#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 75477#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75962#L722 assume 1 == ~t4_pc~0; 76736#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76153#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75587#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75588#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 76569#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75674#L741 assume 1 == ~t5_pc~0; 75675#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75984#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76813#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76865#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 76866#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76250#L760 assume !(1 == ~t6_pc~0); 76077#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76076#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75909#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75910#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76689#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76690#L779 assume 1 == ~t7_pc~0; 75711#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75558#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75559#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77367#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 75998#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75999#L798 assume !(1 == ~t8_pc~0); 77379#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 77279#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77280#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77490#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 77555#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75537#L817 assume 1 == ~t9_pc~0; 75538#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76353#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75966#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75967#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 75943#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75944#L836 assume !(1 == ~t10_pc~0); 75968#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75891#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75892#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76154#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 76155#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77295#L855 assume 1 == ~t11_pc~0; 76543#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76544#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77162#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76953#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 76785#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75827#L874 assume !(1 == ~t12_pc~0); 75828#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76007#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75526#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75527#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 75512#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 75513#L893 assume 1 == ~t13_pc~0; 77464#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 75869#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76188#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77394#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 77385#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 77386#L912 assume 1 == ~t14_pc~0; 77144#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 77145#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 77221#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 75762#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 75763#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76562#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 77014#L1495-2 assume !(1 == ~T1_E~0); 77015#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77518#L1505-1 assume !(1 == ~T3_E~0); 77907#L1510-1 assume !(1 == ~T4_E~0); 77906#L1515-1 assume !(1 == ~T5_E~0); 77905#L1520-1 assume !(1 == ~T6_E~0); 77904#L1525-1 assume !(1 == ~T7_E~0); 77903#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75936#L1535-1 assume !(1 == ~T9_E~0); 75937#L1540-1 assume !(1 == ~T10_E~0); 75437#L1545-1 assume !(1 == ~T11_E~0); 75438#L1550-1 assume !(1 == ~T12_E~0); 77628#L1555-1 assume !(1 == ~T13_E~0); 75987#L1560-1 assume !(1 == ~T14_E~0); 75988#L1565-1 assume !(1 == ~E_1~0); 77823#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 77789#L1575-1 assume !(1 == ~E_3~0); 77786#L1580-1 assume !(1 == ~E_4~0); 77775#L1585-1 assume !(1 == ~E_5~0); 77769#L1590-1 assume !(1 == ~E_6~0); 77765#L1595-1 assume !(1 == ~E_7~0); 77759#L1600-1 assume !(1 == ~E_8~0); 77741#L1605-1 assume !(1 == ~E_9~0); 77717#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77715#L1615-1 assume !(1 == ~E_11~0); 77713#L1620-1 assume !(1 == ~E_12~0); 77703#L1625-1 assume !(1 == ~E_13~0); 77694#L1630-1 assume !(1 == ~E_14~0); 77686#L1635-1 assume { :end_inline_reset_delta_events } true; 77679#L2017-2 [2024-10-25 00:40:43,716 INFO L747 eck$LassoCheckResult]: Loop: 77679#L2017-2 assume !false; 77675#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77674#L1316-1 assume !false; 77673#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77668#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77657#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77656#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 77654#L1115 assume !(0 != eval_~tmp~0#1); 77653#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77652#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77651#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77650#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77648#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77649#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82866#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82865#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82864#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 82863#L1372-3 assume !(0 == ~T7_E~0); 82862#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 82861#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 82860#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 82859#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 77625#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 77516#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76674#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 75786#L1412-3 assume !(0 == ~E_1~0); 75787#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76572#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76573#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 77353#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76997#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76691#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76692#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 75554#L1452-3 assume !(0 == ~E_9~0); 75555#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77277#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77278#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 77070#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 77071#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 75784#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75785#L646-42 assume !(1 == ~m_pc~0); 76399#L646-44 is_master_triggered_~__retres1~0#1 := 0; 77323#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76260#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76261#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77496#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77244#L665-42 assume !(1 == ~t1_pc~0); 77199#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 77200#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77460#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75969#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75970#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77596#L684-42 assume 1 == ~t2_pc~0; 76861#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76862#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81333#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81332#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81038#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81034#L703-42 assume 1 == ~t3_pc~0; 81031#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81027#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81023#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81020#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81017#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81013#L722-42 assume 1 == ~t4_pc~0; 81009#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 81006#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81002#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80999#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80996#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80992#L741-42 assume 1 == ~t5_pc~0; 80989#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 80986#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80983#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80954#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80953#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80952#L760-42 assume !(1 == ~t6_pc~0); 80951#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 80949#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80948#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80947#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 80946#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 80945#L779-42 assume !(1 == ~t7_pc~0); 80944#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 80942#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80941#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 80940#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 80939#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80938#L798-42 assume !(1 == ~t8_pc~0); 80937#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 80934#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80931#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80929#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 80927#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80925#L817-42 assume !(1 == ~t9_pc~0); 80923#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 80920#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 80917#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 80915#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 76992#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76993#L836-42 assume !(1 == ~t10_pc~0); 77104#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 76048#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76049#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76860#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77471#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77531#L855-42 assume !(1 == ~t11_pc~0); 77647#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 79241#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 79213#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 79211#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 79198#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 79197#L874-42 assume !(1 == ~t12_pc~0); 79175#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 79172#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79170#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 79168#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 79166#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 79164#L893-42 assume 1 == ~t13_pc~0; 79161#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 79160#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 79157#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 79155#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 79154#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 79153#L912-42 assume 1 == ~t14_pc~0; 79113#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 79110#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 79108#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 79106#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 79104#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79102#L1495-3 assume !(1 == ~M_E~0); 79099#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 79097#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77480#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79086#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 79079#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 79078#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 79077#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 79017#L1530-3 assume !(1 == ~T8_E~0); 79042#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 79039#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 79037#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78102#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78061#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 78023#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 78021#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78018#L1570-3 assume !(1 == ~E_2~0); 78016#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78014#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77977#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77937#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77896#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77894#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77892#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77891#L1610-3 assume !(1 == ~E_10~0); 77890#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 77888#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 77861#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 77859#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 77857#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77815#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77805#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77785#L2036 assume !(0 == start_simulation_~tmp~3#1); 77758#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77735#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77716#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77714#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 77712#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77702#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77693#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 77685#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 77679#L2017-2 [2024-10-25 00:40:43,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:43,716 INFO L85 PathProgramCache]: Analyzing trace with hash -1432795152, now seen corresponding path program 1 times [2024-10-25 00:40:43,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:43,717 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171376680] [2024-10-25 00:40:43,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:43,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:43,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:43,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:43,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:43,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171376680] [2024-10-25 00:40:43,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171376680] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:43,794 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:43,794 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:43,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94068069] [2024-10-25 00:40:43,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:43,795 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:43,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:43,795 INFO L85 PathProgramCache]: Analyzing trace with hash -989565012, now seen corresponding path program 1 times [2024-10-25 00:40:43,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:43,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259117967] [2024-10-25 00:40:43,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:43,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:43,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:43,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:43,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:43,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259117967] [2024-10-25 00:40:43,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259117967] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:43,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:43,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:43,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890206766] [2024-10-25 00:40:43,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:43,858 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:43,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:43,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-25 00:40:43,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-25 00:40:43,859 INFO L87 Difference]: Start difference. First operand 7540 states and 11077 transitions. cyclomatic complexity: 3541 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:44,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:44,088 INFO L93 Difference]: Finished difference Result 14440 states and 21190 transitions. [2024-10-25 00:40:44,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14440 states and 21190 transitions. [2024-10-25 00:40:44,166 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14156 [2024-10-25 00:40:44,222 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14440 states to 14440 states and 21190 transitions. [2024-10-25 00:40:44,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14440 [2024-10-25 00:40:44,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14440 [2024-10-25 00:40:44,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14440 states and 21190 transitions. [2024-10-25 00:40:44,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:44,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14440 states and 21190 transitions. [2024-10-25 00:40:44,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14440 states and 21190 transitions. [2024-10-25 00:40:44,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14440 to 14436. [2024-10-25 00:40:44,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14436 states, 14436 states have (on average 1.467581047381546) internal successors, (21186), 14435 states have internal predecessors, (21186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:44,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14436 states to 14436 states and 21186 transitions. [2024-10-25 00:40:44,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14436 states and 21186 transitions. [2024-10-25 00:40:44,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-25 00:40:44,696 INFO L425 stractBuchiCegarLoop]: Abstraction has 14436 states and 21186 transitions. [2024-10-25 00:40:44,696 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-25 00:40:44,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14436 states and 21186 transitions. [2024-10-25 00:40:44,750 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14156 [2024-10-25 00:40:44,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:44,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:44,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:44,753 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:44,754 INFO L745 eck$LassoCheckResult]: Stem: 97755#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 97756#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 98701#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 98702#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 99508#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 98296#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98297#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98005#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98006#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 99294#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98596#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98597#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 99153#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 98500#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 98501#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97915#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97916#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 98265#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 98453#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 97494#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97495#L1342 assume !(0 == ~M_E~0); 97663#L1342-2 assume !(0 == ~T1_E~0); 98232#L1347-1 assume !(0 == ~T2_E~0); 99272#L1352-1 assume !(0 == ~T3_E~0); 99054#L1357-1 assume !(0 == ~T4_E~0); 98254#L1362-1 assume !(0 == ~T5_E~0); 98255#L1367-1 assume !(0 == ~T6_E~0); 97830#L1372-1 assume !(0 == ~T7_E~0); 97831#L1377-1 assume !(0 == ~T8_E~0); 98171#L1382-1 assume !(0 == ~T9_E~0); 98172#L1387-1 assume !(0 == ~T10_E~0); 98932#L1392-1 assume !(0 == ~T11_E~0); 98213#L1397-1 assume !(0 == ~T12_E~0); 98214#L1402-1 assume !(0 == ~T13_E~0); 97854#L1407-1 assume !(0 == ~T14_E~0); 97855#L1412-1 assume !(0 == ~E_1~0); 99185#L1417-1 assume !(0 == ~E_2~0); 99186#L1422-1 assume !(0 == ~E_3~0); 99443#L1427-1 assume !(0 == ~E_4~0); 98036#L1432-1 assume !(0 == ~E_5~0); 98037#L1437-1 assume !(0 == ~E_6~0); 99099#L1442-1 assume !(0 == ~E_7~0); 99100#L1447-1 assume !(0 == ~E_8~0); 98924#L1452-1 assume !(0 == ~E_9~0); 97632#L1457-1 assume !(0 == ~E_10~0); 97633#L1462-1 assume !(0 == ~E_11~0); 99131#L1467-1 assume !(0 == ~E_12~0); 99147#L1472-1 assume !(0 == ~E_13~0); 99148#L1477-1 assume !(0 == ~E_14~0); 98870#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97819#L646 assume 1 == ~m_pc~0; 97820#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 98510#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98525#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97917#L1666 assume !(0 != activate_threads_~tmp~1#1); 97918#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99468#L665 assume !(1 == ~t1_pc~0); 98402#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 98403#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99026#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99027#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 98750#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98751#L684 assume 1 == ~t2_pc~0; 98867#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 98791#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97903#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97904#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 99277#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99482#L703 assume !(1 == ~t3_pc~0); 98061#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 98062#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99013#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97466#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 97467#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97947#L722 assume 1 == ~t4_pc~0; 98708#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 98136#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97577#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97578#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 98547#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97664#L741 assume 1 == ~t5_pc~0; 97665#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 97969#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98785#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 98837#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 98838#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98233#L760 assume !(1 == ~t6_pc~0); 98060#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 98059#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97895#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97896#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 98663#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 98664#L779 assume 1 == ~t7_pc~0; 97703#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 97548#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97549#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99316#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 97981#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97982#L798 assume !(1 == ~t8_pc~0); 99326#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 99234#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99235#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99417#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 99470#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97527#L817 assume 1 == ~t9_pc~0; 97528#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 98334#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97951#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97952#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 97929#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97930#L836 assume !(1 == ~t10_pc~0); 97953#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 97879#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97880#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 98137#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 98138#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 99249#L855 assume 1 == ~t11_pc~0; 98521#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 98522#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99125#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98921#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 98756#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97816#L874 assume !(1 == ~t12_pc~0); 97817#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97990#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 97516#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 97517#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 97502#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 97503#L893 assume 1 == ~t13_pc~0; 99397#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 97857#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 98170#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 99340#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 99332#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 99333#L912 assume 1 == ~t14_pc~0; 99107#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 99108#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 99182#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 97753#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 97754#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98540#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 98982#L1495-2 assume !(1 == ~T1_E~0); 98983#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98657#L1505-1 assume !(1 == ~T3_E~0); 98658#L1510-1 assume !(1 == ~T4_E~0); 98718#L1515-1 assume !(1 == ~T5_E~0); 98719#L1520-1 assume !(1 == ~T6_E~0); 99327#L1525-1 assume !(1 == ~T7_E~0); 99328#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 100052#L1535-1 assume !(1 == ~T9_E~0); 100050#L1540-1 assume !(1 == ~T10_E~0); 100048#L1545-1 assume !(1 == ~T11_E~0); 99894#L1550-1 assume !(1 == ~T12_E~0); 99891#L1555-1 assume !(1 == ~T13_E~0); 99889#L1560-1 assume !(1 == ~T14_E~0); 99887#L1565-1 assume !(1 == ~E_1~0); 99788#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 99786#L1575-1 assume !(1 == ~E_3~0); 99783#L1580-1 assume !(1 == ~E_4~0); 99781#L1585-1 assume !(1 == ~E_5~0); 99779#L1590-1 assume !(1 == ~E_6~0); 99777#L1595-1 assume !(1 == ~E_7~0); 99775#L1600-1 assume !(1 == ~E_8~0); 99632#L1605-1 assume !(1 == ~E_9~0); 99614#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 99602#L1615-1 assume !(1 == ~E_11~0); 99592#L1620-1 assume !(1 == ~E_12~0); 99582#L1625-1 assume !(1 == ~E_13~0); 99573#L1630-1 assume !(1 == ~E_14~0); 99565#L1635-1 assume { :end_inline_reset_delta_events } true; 99558#L2017-2 [2024-10-25 00:40:44,754 INFO L747 eck$LassoCheckResult]: Loop: 99558#L2017-2 assume !false; 99554#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99553#L1316-1 assume !false; 99552#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 99547#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 99536#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 99535#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 99533#L1115 assume !(0 != eval_~tmp~0#1); 99532#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 99531#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 99530#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 99529#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99527#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 99528#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 102551#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 102549#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 102547#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 102544#L1372-3 assume !(0 == ~T7_E~0); 102542#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 102540#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 102538#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 102536#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 102534#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 102531#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 102529#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 102527#L1412-3 assume !(0 == ~E_1~0); 102525#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 102523#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102521#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 102518#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102516#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 102514#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 102512#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 102510#L1452-3 assume !(0 == ~E_9~0); 102508#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 102505#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 102503#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 102501#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 102499#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 102497#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102495#L646-42 assume 1 == ~m_pc~0; 102491#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 102489#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102487#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102485#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 102483#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102481#L665-42 assume !(1 == ~t1_pc~0); 102477#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 102475#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102473#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102471#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 102469#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102467#L684-42 assume !(1 == ~t2_pc~0); 102464#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 102461#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102459#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102457#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 102455#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102454#L703-42 assume !(1 == ~t3_pc~0); 102449#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 102447#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102445#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102444#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102443#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102442#L722-42 assume !(1 == ~t4_pc~0); 102441#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 102439#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102438#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102437#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 102436#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102435#L741-42 assume !(1 == ~t5_pc~0); 102433#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 102432#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102431#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 102430#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 102429#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102428#L760-42 assume 1 == ~t6_pc~0; 102425#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 102422#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102420#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 102418#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 102416#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102414#L779-42 assume 1 == ~t7_pc~0; 102411#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 102410#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102407#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 102405#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 102403#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102401#L798-42 assume !(1 == ~t8_pc~0); 102399#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 102396#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102393#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 102391#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102389#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102387#L817-42 assume !(1 == ~t9_pc~0); 102384#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 101610#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 101607#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 101605#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 101603#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 101601#L836-42 assume 1 == ~t10_pc~0; 101599#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 101596#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 101593#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 101591#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101589#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 101587#L855-42 assume !(1 == ~t11_pc~0); 101584#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 101580#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 101578#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 101576#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 101574#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 101572#L874-42 assume !(1 == ~t12_pc~0); 101569#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 101568#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 101565#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 101563#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 101561#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 101559#L893-42 assume !(1 == ~t13_pc~0); 101557#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 101554#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 101551#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 101549#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 101547#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 101545#L912-42 assume 1 == ~t14_pc~0; 101533#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 101530#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 101528#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 101526#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 101523#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101521#L1495-3 assume !(1 == ~M_E~0); 101519#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101517#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 99407#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101514#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101511#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101510#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100878#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 98978#L1530-3 assume !(1 == ~T8_E~0); 100874#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 100872#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100870#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 100868#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 100866#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 100863#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 100537#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100533#L1570-3 assume !(1 == ~E_2~0); 100531#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 100529#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100295#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100293#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 100290#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 100288#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 100286#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 100282#L1610-3 assume !(1 == ~E_10~0); 100280#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 100278#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 100275#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 100273#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 100271#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 100034#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 100024#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 99880#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 99876#L2036 assume !(0 == start_simulation_~tmp~3#1); 99746#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 99624#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 99613#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 99601#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 99591#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 99581#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 99572#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 99564#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 99558#L2017-2 [2024-10-25 00:40:44,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:44,755 INFO L85 PathProgramCache]: Analyzing trace with hash -1867300750, now seen corresponding path program 1 times [2024-10-25 00:40:44,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:44,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882748968] [2024-10-25 00:40:44,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:44,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:44,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:44,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:44,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:44,843 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882748968] [2024-10-25 00:40:44,843 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882748968] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:44,843 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:44,843 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:44,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458830655] [2024-10-25 00:40:44,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:44,844 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:44,844 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:44,844 INFO L85 PathProgramCache]: Analyzing trace with hash 2109817291, now seen corresponding path program 1 times [2024-10-25 00:40:44,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:44,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568994521] [2024-10-25 00:40:44,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:44,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:44,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:44,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:44,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:44,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568994521] [2024-10-25 00:40:44,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [568994521] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:44,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:44,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:44,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [279532437] [2024-10-25 00:40:44,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:44,901 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:44,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:44,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:44,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:44,902 INFO L87 Difference]: Start difference. First operand 14436 states and 21186 transitions. cyclomatic complexity: 6758 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:45,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:45,093 INFO L93 Difference]: Finished difference Result 21601 states and 31488 transitions. [2024-10-25 00:40:45,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21601 states and 31488 transitions. [2024-10-25 00:40:45,347 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21306 [2024-10-25 00:40:45,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21601 states to 21601 states and 31488 transitions. [2024-10-25 00:40:45,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21601 [2024-10-25 00:40:45,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21601 [2024-10-25 00:40:45,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21601 states and 31488 transitions. [2024-10-25 00:40:45,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:45,483 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21601 states and 31488 transitions. [2024-10-25 00:40:45,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21601 states and 31488 transitions. [2024-10-25 00:40:45,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21601 to 21169. [2024-10-25 00:40:45,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21169 states, 21169 states have (on average 1.4587368321602343) internal successors, (30880), 21168 states have internal predecessors, (30880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:45,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21169 states to 21169 states and 30880 transitions. [2024-10-25 00:40:45,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21169 states and 30880 transitions. [2024-10-25 00:40:45,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:45,906 INFO L425 stractBuchiCegarLoop]: Abstraction has 21169 states and 30880 transitions. [2024-10-25 00:40:45,906 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-25 00:40:45,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21169 states and 30880 transitions. [2024-10-25 00:40:45,986 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 20882 [2024-10-25 00:40:45,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:45,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:45,990 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:45,990 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:45,990 INFO L745 eck$LassoCheckResult]: Stem: 133796#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 133797#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 134752#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134753#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 135610#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 134337#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 134338#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 134046#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 134047#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 135362#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 134641#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 134642#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 135214#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 134544#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 134545#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 133955#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 133956#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 134307#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 134496#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 133540#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 133541#L1342 assume !(0 == ~M_E~0); 133707#L1342-2 assume !(0 == ~T1_E~0); 134273#L1347-1 assume !(0 == ~T2_E~0); 135340#L1352-1 assume !(0 == ~T3_E~0); 135113#L1357-1 assume !(0 == ~T4_E~0); 134295#L1362-1 assume !(0 == ~T5_E~0); 134296#L1367-1 assume !(0 == ~T6_E~0); 133870#L1372-1 assume !(0 == ~T7_E~0); 133871#L1377-1 assume !(0 == ~T8_E~0); 134213#L1382-1 assume !(0 == ~T9_E~0); 134214#L1387-1 assume !(0 == ~T10_E~0); 134990#L1392-1 assume !(0 == ~T11_E~0); 134256#L1397-1 assume !(0 == ~T12_E~0); 134257#L1402-1 assume !(0 == ~T13_E~0); 133894#L1407-1 assume !(0 == ~T14_E~0); 133895#L1412-1 assume !(0 == ~E_1~0); 135247#L1417-1 assume !(0 == ~E_2~0); 135248#L1422-1 assume !(0 == ~E_3~0); 135533#L1427-1 assume !(0 == ~E_4~0); 134075#L1432-1 assume !(0 == ~E_5~0); 134076#L1437-1 assume !(0 == ~E_6~0); 135164#L1442-1 assume !(0 == ~E_7~0); 135165#L1447-1 assume !(0 == ~E_8~0); 134984#L1452-1 assume !(0 == ~E_9~0); 133676#L1457-1 assume !(0 == ~E_10~0); 133677#L1462-1 assume !(0 == ~E_11~0); 135196#L1467-1 assume !(0 == ~E_12~0); 135209#L1472-1 assume !(0 == ~E_13~0); 135210#L1477-1 assume !(0 == ~E_14~0); 134929#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133860#L646 assume !(1 == ~m_pc~0); 133861#L646-2 is_master_triggered_~__retres1~0#1 := 0; 134571#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134572#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 133957#L1666 assume !(0 != activate_threads_~tmp~1#1); 133958#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135559#L665 assume !(1 == ~t1_pc~0); 134444#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 134445#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135087#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 135088#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 134802#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134803#L684 assume 1 == ~t2_pc~0; 134928#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 134846#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 133944#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 135345#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 135574#L703 assume !(1 == ~t3_pc~0); 134100#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 134101#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135073#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 133510#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 133511#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133987#L722 assume 1 == ~t4_pc~0; 134759#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 134178#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 133621#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 133622#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 134593#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133708#L741 assume 1 == ~t5_pc~0; 133709#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 134009#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 134836#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 134895#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 134896#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134274#L760 assume !(1 == ~t6_pc~0); 134099#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 134098#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 133935#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 133936#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 134709#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 134710#L779 assume 1 == ~t7_pc~0; 133744#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 133592#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 133593#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 135385#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 134022#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 134023#L798 assume !(1 == ~t8_pc~0); 135395#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 135299#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 135300#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 135499#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 135561#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133571#L817 assume 1 == ~t9_pc~0; 133572#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 134375#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 133991#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 133992#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 133969#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133970#L836 assume !(1 == ~t10_pc~0); 133993#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 133919#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133920#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 134179#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 134180#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 135314#L855 assume 1 == ~t11_pc~0; 134567#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 134568#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 135190#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 134981#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 134808#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 133857#L874 assume !(1 == ~t12_pc~0); 133858#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 134031#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 133560#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 133561#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 133546#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 133547#L893 assume 1 == ~t13_pc~0; 135477#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 133897#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 134212#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 135411#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 135400#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 135401#L912 assume 1 == ~t14_pc~0; 135172#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 135173#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 135244#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 133794#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 133795#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134586#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 135041#L1495-2 assume !(1 == ~T1_E~0); 135042#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134703#L1505-1 assume !(1 == ~T3_E~0); 134704#L1510-1 assume !(1 == ~T4_E~0); 134769#L1515-1 assume !(1 == ~T5_E~0); 134770#L1520-1 assume !(1 == ~T6_E~0); 135396#L1525-1 assume !(1 == ~T7_E~0); 135074#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 135075#L1535-1 assume !(1 == ~T9_E~0); 135584#L1540-1 assume !(1 == ~T10_E~0); 135585#L1545-1 assume !(1 == ~T11_E~0); 135620#L1550-1 assume !(1 == ~T12_E~0); 135621#L1555-1 assume !(1 == ~T13_E~0); 134014#L1560-1 assume !(1 == ~T14_E~0); 134015#L1565-1 assume !(1 == ~E_1~0); 146572#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 146571#L1575-1 assume !(1 == ~E_3~0); 146570#L1580-1 assume !(1 == ~E_4~0); 146569#L1585-1 assume !(1 == ~E_5~0); 146568#L1590-1 assume !(1 == ~E_6~0); 146567#L1595-1 assume !(1 == ~E_7~0); 146566#L1600-1 assume !(1 == ~E_8~0); 146565#L1605-1 assume !(1 == ~E_9~0); 134718#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 146519#L1615-1 assume !(1 == ~E_11~0); 146503#L1620-1 assume !(1 == ~E_12~0); 146504#L1625-1 assume !(1 == ~E_13~0); 148145#L1630-1 assume !(1 == ~E_14~0); 148144#L1635-1 assume { :end_inline_reset_delta_events } true; 146451#L2017-2 [2024-10-25 00:40:45,991 INFO L747 eck$LassoCheckResult]: Loop: 146451#L2017-2 assume !false; 146452#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 146444#L1316-1 assume !false; 146445#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 146437#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 146427#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 146422#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 146423#L1115 assume !(0 != eval_~tmp~0#1); 148127#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 148126#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 148125#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 148124#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 148120#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 148121#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 154476#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 154475#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 154474#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 154473#L1372-3 assume !(0 == ~T7_E~0); 154472#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 154471#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 154470#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 154469#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 154468#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 154467#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 154466#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 154465#L1412-3 assume !(0 == ~E_1~0); 154464#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 154463#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 154462#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 154461#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 154460#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 154459#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 154458#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 154457#L1452-3 assume !(0 == ~E_9~0); 154456#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 154455#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 154454#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 154453#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 154452#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 154451#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134417#L646-42 assume !(1 == ~m_pc~0); 134418#L646-44 is_master_triggered_~__retres1~0#1 := 0; 135341#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134283#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134284#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 153771#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153770#L665-42 assume !(1 == ~t1_pc~0); 153768#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 153767#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153766#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 153765#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 153764#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153763#L684-42 assume !(1 == ~t2_pc~0); 153762#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 153760#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153759#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 153758#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 153757#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153756#L703-42 assume !(1 == ~t3_pc~0); 153754#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 153753#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153752#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 153751#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 153750#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153749#L722-42 assume 1 == ~t4_pc~0; 153747#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 153746#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153745#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 153744#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 153743#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153742#L741-42 assume !(1 == ~t5_pc~0); 153740#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 153739#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153738#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 153737#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 153736#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 153735#L760-42 assume !(1 == ~t6_pc~0); 153734#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 153732#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 153731#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 153730#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 153729#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 153728#L779-42 assume 1 == ~t7_pc~0; 135285#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 135230#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 134735#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 134736#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 133917#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 133918#L798-42 assume 1 == ~t8_pc~0; 134384#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 133534#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 134909#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 134749#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 133748#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133749#L817-42 assume 1 == ~t9_pc~0; 153303#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 153300#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 153297#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 153294#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 153291#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 153288#L836-42 assume !(1 == ~t10_pc~0); 153283#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 153280#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 153277#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 153274#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 153271#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 153268#L855-42 assume !(1 == ~t11_pc~0); 153264#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 153260#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 153257#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 153254#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 153251#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 153248#L874-42 assume !(1 == ~t12_pc~0); 153243#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 153240#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 153238#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 153236#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 153234#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 153232#L893-42 assume !(1 == ~t13_pc~0); 153230#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 153227#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 153225#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 153223#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 153221#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 153219#L912-42 assume !(1 == ~t14_pc~0); 153216#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 153214#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 153212#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 153210#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 133914#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133915#L1495-3 assume !(1 == ~M_E~0); 135011#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 135012#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 135490#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 147788#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 147787#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 147786#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 147784#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 145982#L1530-3 assume !(1 == ~T8_E~0); 147781#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 147779#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 147777#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 147774#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 147771#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 147767#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 147763#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 147760#L1570-3 assume !(1 == ~E_2~0); 147758#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 147755#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 147753#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 147751#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 147748#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 147746#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 147744#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 135346#L1610-3 assume !(1 == ~E_10~0); 147741#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 147739#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 147736#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 147734#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 147320#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 146618#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 146607#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 146604#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 146605#L2036 assume !(0 == start_simulation_~tmp~3#1); 148470#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 146559#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 146550#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 148153#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 148151#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 146488#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 146474#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 146475#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 146451#L2017-2 [2024-10-25 00:40:45,992 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:45,992 INFO L85 PathProgramCache]: Analyzing trace with hash 1199377425, now seen corresponding path program 1 times [2024-10-25 00:40:45,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:45,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936811670] [2024-10-25 00:40:45,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:45,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:46,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:46,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:46,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:46,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936811670] [2024-10-25 00:40:46,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936811670] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:46,078 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:46,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:46,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067933182] [2024-10-25 00:40:46,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:46,079 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:46,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:46,081 INFO L85 PathProgramCache]: Analyzing trace with hash 672932906, now seen corresponding path program 1 times [2024-10-25 00:40:46,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:46,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188931502] [2024-10-25 00:40:46,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:46,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:46,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:46,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:46,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:46,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188931502] [2024-10-25 00:40:46,270 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1188931502] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:46,270 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:46,270 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:46,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801426752] [2024-10-25 00:40:46,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:46,271 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:46,271 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:46,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:46,272 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:46,273 INFO L87 Difference]: Start difference. First operand 21169 states and 30880 transitions. cyclomatic complexity: 9723 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:46,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:46,532 INFO L93 Difference]: Finished difference Result 40616 states and 59005 transitions. [2024-10-25 00:40:46,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40616 states and 59005 transitions. [2024-10-25 00:40:46,719 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 40298 [2024-10-25 00:40:46,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40616 states to 40616 states and 59005 transitions. [2024-10-25 00:40:46,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40616 [2024-10-25 00:40:46,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40616 [2024-10-25 00:40:46,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40616 states and 59005 transitions. [2024-10-25 00:40:46,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:46,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40616 states and 59005 transitions. [2024-10-25 00:40:46,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40616 states and 59005 transitions. [2024-10-25 00:40:47,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40616 to 40592. [2024-10-25 00:40:47,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40592 states, 40592 states have (on average 1.453020299566417) internal successors, (58981), 40591 states have internal predecessors, (58981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:47,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40592 states to 40592 states and 58981 transitions. [2024-10-25 00:40:47,989 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40592 states and 58981 transitions. [2024-10-25 00:40:47,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:47,989 INFO L425 stractBuchiCegarLoop]: Abstraction has 40592 states and 58981 transitions. [2024-10-25 00:40:47,990 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-25 00:40:47,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40592 states and 58981 transitions. [2024-10-25 00:40:48,098 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 40274 [2024-10-25 00:40:48,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:48,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:48,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:48,101 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:48,101 INFO L745 eck$LassoCheckResult]: Stem: 195587#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 195588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 196553#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 196554#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 197496#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 196133#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 196134#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 195841#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 195842#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 197199#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 196442#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 196443#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 197047#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 196338#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 196339#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 195748#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 195749#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 196102#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 196290#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 195330#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 195331#L1342 assume !(0 == ~M_E~0); 195498#L1342-2 assume !(0 == ~T1_E~0); 196069#L1347-1 assume !(0 == ~T2_E~0); 197175#L1352-1 assume !(0 == ~T3_E~0); 196938#L1357-1 assume !(0 == ~T4_E~0); 196091#L1362-1 assume !(0 == ~T5_E~0); 196092#L1367-1 assume !(0 == ~T6_E~0); 195661#L1372-1 assume !(0 == ~T7_E~0); 195662#L1377-1 assume !(0 == ~T8_E~0); 196008#L1382-1 assume !(0 == ~T9_E~0); 196009#L1387-1 assume !(0 == ~T10_E~0); 196798#L1392-1 assume !(0 == ~T11_E~0); 196049#L1397-1 assume !(0 == ~T12_E~0); 196050#L1402-1 assume !(0 == ~T13_E~0); 195686#L1407-1 assume !(0 == ~T14_E~0); 195687#L1412-1 assume !(0 == ~E_1~0); 197079#L1417-1 assume !(0 == ~E_2~0); 197080#L1422-1 assume !(0 == ~E_3~0); 197394#L1427-1 assume !(0 == ~E_4~0); 195870#L1432-1 assume !(0 == ~E_5~0); 195871#L1437-1 assume !(0 == ~E_6~0); 196993#L1442-1 assume !(0 == ~E_7~0); 196994#L1447-1 assume !(0 == ~E_8~0); 196791#L1452-1 assume !(0 == ~E_9~0); 195467#L1457-1 assume !(0 == ~E_10~0); 195468#L1462-1 assume !(0 == ~E_11~0); 197027#L1467-1 assume !(0 == ~E_12~0); 197041#L1472-1 assume !(0 == ~E_13~0); 197042#L1477-1 assume !(0 == ~E_14~0); 196734#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 195651#L646 assume !(1 == ~m_pc~0); 195652#L646-2 is_master_triggered_~__retres1~0#1 := 0; 196366#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 196367#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 195750#L1666 assume !(0 != activate_threads_~tmp~1#1); 195751#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 197430#L665 assume !(1 == ~t1_pc~0); 196237#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 196238#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 196903#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 196904#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 196606#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 196607#L684 assume !(1 == ~t2_pc~0); 196648#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 196649#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 195736#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 195737#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 197180#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 197444#L703 assume !(1 == ~t3_pc~0); 195895#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 195896#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 196889#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 195302#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 195303#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 195780#L722 assume 1 == ~t4_pc~0; 196560#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 195973#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 195412#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 195413#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 196390#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 195499#L741 assume 1 == ~t5_pc~0; 195500#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 195802#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 196642#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 196700#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 196701#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 196070#L760 assume !(1 == ~t6_pc~0); 195894#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 195893#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 195728#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 195729#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 196513#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 196514#L779 assume 1 == ~t7_pc~0; 195535#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 195384#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 195385#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 197226#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 195814#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 195815#L798 assume !(1 == ~t8_pc~0); 197236#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 197133#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 197134#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 197356#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 197432#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 195363#L817 assume 1 == ~t9_pc~0; 195364#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 196170#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 195784#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 195785#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 195762#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 195763#L836 assume !(1 == ~t10_pc~0); 195786#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 195711#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 195712#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 195974#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 195975#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 197149#L855 assume 1 == ~t11_pc~0; 196362#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 196363#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 197021#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 196788#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 196613#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 195648#L874 assume !(1 == ~t12_pc~0); 195649#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 195825#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 195352#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 195353#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 195338#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 195339#L893 assume 1 == ~t13_pc~0; 197325#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 195689#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 196007#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 197253#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 197241#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 197242#L912 assume 1 == ~t14_pc~0; 197000#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 197001#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 197076#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 195585#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 195586#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 196383#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 196856#L1495-2 assume !(1 == ~T1_E~0); 196857#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 197385#L1505-1 assume !(1 == ~T3_E~0); 207368#L1510-1 assume !(1 == ~T4_E~0); 196572#L1515-1 assume !(1 == ~T5_E~0); 196573#L1520-1 assume !(1 == ~T6_E~0); 197237#L1525-1 assume !(1 == ~T7_E~0); 196890#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 195755#L1535-1 assume !(1 == ~T9_E~0); 195756#L1540-1 assume !(1 == ~T10_E~0); 205223#L1545-1 assume !(1 == ~T11_E~0); 205224#L1550-1 assume !(1 == ~T12_E~0); 205216#L1555-1 assume !(1 == ~T13_E~0); 205217#L1560-1 assume !(1 == ~T14_E~0); 197409#L1565-1 assume !(1 == ~E_1~0); 197410#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 196757#L1575-1 assume !(1 == ~E_3~0); 196097#L1580-1 assume !(1 == ~E_4~0); 196098#L1585-1 assume !(1 == ~E_5~0); 196597#L1590-1 assume !(1 == ~E_6~0); 196127#L1595-1 assume !(1 == ~E_7~0); 196128#L1600-1 assume !(1 == ~E_8~0); 197486#L1605-1 assume !(1 == ~E_9~0); 205194#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 210449#L1615-1 assume !(1 == ~E_11~0); 210446#L1620-1 assume !(1 == ~E_12~0); 210444#L1625-1 assume !(1 == ~E_13~0); 210442#L1630-1 assume !(1 == ~E_14~0); 210440#L1635-1 assume { :end_inline_reset_delta_events } true; 210437#L2017-2 [2024-10-25 00:40:48,102 INFO L747 eck$LassoCheckResult]: Loop: 210437#L2017-2 assume !false; 204804#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 204803#L1316-1 assume !false; 204801#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 204802#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 227845#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 227844#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 227842#L1115 assume !(0 != eval_~tmp~0#1); 227843#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 233761#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 233758#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 233754#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 233752#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 233750#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 233748#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 233746#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 233744#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 233740#L1372-3 assume !(0 == ~T7_E~0); 233738#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 233736#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 233733#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 233539#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 227583#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 227582#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 227581#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 222761#L1412-3 assume !(0 == ~E_1~0); 222759#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 222757#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 222755#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 222753#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 222751#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 222749#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 222747#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 222745#L1452-3 assume !(0 == ~E_9~0); 222743#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 222741#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 222739#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 222737#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 222735#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 222733#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 222731#L646-42 assume !(1 == ~m_pc~0); 222729#L646-44 is_master_triggered_~__retres1~0#1 := 0; 222727#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 222725#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 222723#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 222721#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222719#L665-42 assume 1 == ~t1_pc~0; 222717#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 222714#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222712#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 222710#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 222708#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 222706#L684-42 assume !(1 == ~t2_pc~0); 222704#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 222702#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222700#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 222698#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 222696#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222694#L703-42 assume 1 == ~t3_pc~0; 222690#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 222686#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222684#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 222682#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 222680#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 222678#L722-42 assume 1 == ~t4_pc~0; 222675#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 222672#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 222670#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 222668#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 222666#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 222664#L741-42 assume 1 == ~t5_pc~0; 222662#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 222658#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 222657#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 222656#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 216137#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 210825#L760-42 assume !(1 == ~t6_pc~0); 210822#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 210819#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 210817#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 210815#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 210813#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 210811#L779-42 assume !(1 == ~t7_pc~0); 210807#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 210804#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 210802#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 210800#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 210798#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 210795#L798-42 assume !(1 == ~t8_pc~0); 210793#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 210790#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 210788#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 210786#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 210784#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 210783#L817-42 assume !(1 == ~t9_pc~0); 210782#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 210778#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 210776#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 210774#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 210772#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 210770#L836-42 assume 1 == ~t10_pc~0; 210768#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 210764#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 210762#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 210760#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 210758#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 210756#L855-42 assume !(1 == ~t11_pc~0); 210754#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 210750#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 210748#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 210746#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 210744#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 210742#L874-42 assume !(1 == ~t12_pc~0); 210739#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 210736#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 210734#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 210732#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 210730#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 210728#L893-42 assume !(1 == ~t13_pc~0); 210726#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 210722#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 210720#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 210718#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 210716#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 210714#L912-42 assume !(1 == ~t14_pc~0); 210711#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 210709#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 210705#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 210704#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 210702#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210700#L1495-3 assume !(1 == ~M_E~0); 210698#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 210694#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 205576#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 210689#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 210687#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 210685#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 210683#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 210679#L1530-3 assume !(1 == ~T8_E~0); 210677#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 210675#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 210673#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 210671#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 210669#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 210667#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 210665#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 210663#L1570-3 assume !(1 == ~E_2~0); 210661#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 210659#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 210658#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 210656#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 210654#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 210651#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 210648#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 205499#L1610-3 assume !(1 == ~E_10~0); 210647#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 210646#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 210645#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 210644#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 210643#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 210631#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 210620#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 210617#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 210612#L2036 assume !(0 == start_simulation_~tmp~3#1); 210607#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 210480#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 210469#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 210467#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 210465#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 210463#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 210460#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 210439#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 210437#L2017-2 [2024-10-25 00:40:48,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:48,102 INFO L85 PathProgramCache]: Analyzing trace with hash 752619056, now seen corresponding path program 1 times [2024-10-25 00:40:48,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:48,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315757067] [2024-10-25 00:40:48,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:48,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:48,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:48,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:48,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:48,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315757067] [2024-10-25 00:40:48,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315757067] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:48,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:48,314 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:48,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556546364] [2024-10-25 00:40:48,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:48,314 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:48,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:48,315 INFO L85 PathProgramCache]: Analyzing trace with hash -868176053, now seen corresponding path program 1 times [2024-10-25 00:40:48,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:48,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468634576] [2024-10-25 00:40:48,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:48,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:48,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:48,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:48,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:48,388 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [468634576] [2024-10-25 00:40:48,388 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [468634576] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:48,388 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:48,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:48,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639889087] [2024-10-25 00:40:48,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:48,389 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:48,390 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:48,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:48,390 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:48,390 INFO L87 Difference]: Start difference. First operand 40592 states and 58981 transitions. cyclomatic complexity: 18413 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:48,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:48,981 INFO L93 Difference]: Finished difference Result 78045 states and 112996 transitions. [2024-10-25 00:40:48,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78045 states and 112996 transitions. [2024-10-25 00:40:49,234 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 77640 [2024-10-25 00:40:49,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78045 states to 78045 states and 112996 transitions. [2024-10-25 00:40:49,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78045 [2024-10-25 00:40:49,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78045 [2024-10-25 00:40:49,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78045 states and 112996 transitions. [2024-10-25 00:40:49,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:49,738 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78045 states and 112996 transitions. [2024-10-25 00:40:49,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78045 states and 112996 transitions. [2024-10-25 00:40:50,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78045 to 77997. [2024-10-25 00:40:50,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77997 states, 77997 states have (on average 1.448106978473531) internal successors, (112948), 77996 states have internal predecessors, (112948), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:51,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77997 states to 77997 states and 112948 transitions. [2024-10-25 00:40:51,229 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77997 states and 112948 transitions. [2024-10-25 00:40:51,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:51,230 INFO L425 stractBuchiCegarLoop]: Abstraction has 77997 states and 112948 transitions. [2024-10-25 00:40:51,231 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-25 00:40:51,232 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77997 states and 112948 transitions. [2024-10-25 00:40:51,408 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 77592 [2024-10-25 00:40:51,408 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:51,408 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:51,410 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:51,410 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:51,411 INFO L745 eck$LassoCheckResult]: Stem: 314229#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 314230#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 315204#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 315205#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 316142#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 314784#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 314785#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 314483#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 314484#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 315844#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 315090#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 315091#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 315693#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 314989#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 314990#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 314390#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 314391#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 314752#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 314942#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 313976#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 313977#L1342 assume !(0 == ~M_E~0); 314142#L1342-2 assume !(0 == ~T1_E~0); 314716#L1347-1 assume !(0 == ~T2_E~0); 315822#L1352-1 assume !(0 == ~T3_E~0); 315585#L1357-1 assume !(0 == ~T4_E~0); 314738#L1362-1 assume !(0 == ~T5_E~0); 314739#L1367-1 assume !(0 == ~T6_E~0); 314308#L1372-1 assume !(0 == ~T7_E~0); 314309#L1377-1 assume !(0 == ~T8_E~0); 314652#L1382-1 assume !(0 == ~T9_E~0); 314653#L1387-1 assume !(0 == ~T10_E~0); 315449#L1392-1 assume !(0 == ~T11_E~0); 314698#L1397-1 assume !(0 == ~T12_E~0); 314699#L1402-1 assume !(0 == ~T13_E~0); 314328#L1407-1 assume !(0 == ~T14_E~0); 314329#L1412-1 assume !(0 == ~E_1~0); 315729#L1417-1 assume !(0 == ~E_2~0); 315730#L1422-1 assume !(0 == ~E_3~0); 316045#L1427-1 assume !(0 == ~E_4~0); 314512#L1432-1 assume !(0 == ~E_5~0); 314513#L1437-1 assume !(0 == ~E_6~0); 315637#L1442-1 assume !(0 == ~E_7~0); 315638#L1447-1 assume !(0 == ~E_8~0); 315442#L1452-1 assume !(0 == ~E_9~0); 314113#L1457-1 assume !(0 == ~E_10~0); 314114#L1462-1 assume !(0 == ~E_11~0); 315674#L1467-1 assume !(0 == ~E_12~0); 315688#L1472-1 assume !(0 == ~E_13~0); 315689#L1477-1 assume !(0 == ~E_14~0); 315389#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 314298#L646 assume !(1 == ~m_pc~0); 314299#L646-2 is_master_triggered_~__retres1~0#1 := 0; 315016#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 315017#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 314392#L1666 assume !(0 != activate_threads_~tmp~1#1); 314393#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 316080#L665 assume !(1 == ~t1_pc~0); 314887#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 314888#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 315554#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 315555#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 315251#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 315252#L684 assume !(1 == ~t2_pc~0); 315301#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 315302#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 314380#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 314381#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 315828#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 316097#L703 assume !(1 == ~t3_pc~0); 314537#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 314538#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 315541#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 313946#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 313947#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 314424#L722 assume !(1 == ~t4_pc~0); 314615#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 314616#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 314056#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 314057#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 315041#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 314143#L741 assume 1 == ~t5_pc~0; 314144#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 314444#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 315291#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 315355#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 315356#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 314717#L760 assume !(1 == ~t6_pc~0); 314536#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 314535#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314370#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 314371#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 315163#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 315164#L779 assume 1 == ~t7_pc~0; 314179#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 314028#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 314029#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 315875#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 314456#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 314457#L798 assume !(1 == ~t8_pc~0); 315884#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 315779#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 315780#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 316007#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 316082#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 314009#L817 assume 1 == ~t9_pc~0; 314010#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 314822#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 314426#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 314427#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 314403#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 314404#L836 assume !(1 == ~t10_pc~0); 314428#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 314354#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 314355#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 314617#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 314618#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 315792#L855 assume 1 == ~t11_pc~0; 315012#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 315013#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 315668#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 315439#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 315261#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 314291#L874 assume !(1 == ~t12_pc~0); 314292#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 314465#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 313996#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 313997#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 313984#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 313985#L893 assume 1 == ~t13_pc~0; 315979#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 314331#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 314651#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 315899#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 315890#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 315891#L912 assume 1 == ~t14_pc~0; 315646#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 315647#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 315724#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 314227#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 314228#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 315036#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 315507#L1495-2 assume !(1 == ~T1_E~0); 315508#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 315156#L1505-1 assume !(1 == ~T3_E~0); 315157#L1510-1 assume !(1 == ~T4_E~0); 315219#L1515-1 assume !(1 == ~T5_E~0); 315220#L1520-1 assume !(1 == ~T6_E~0); 329334#L1525-1 assume !(1 == ~T7_E~0); 329335#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 333457#L1535-1 assume !(1 == ~T9_E~0); 333456#L1540-1 assume !(1 == ~T10_E~0); 329326#L1545-1 assume !(1 == ~T11_E~0); 329324#L1550-1 assume !(1 == ~T12_E~0); 329321#L1555-1 assume !(1 == ~T13_E~0); 329319#L1560-1 assume !(1 == ~T14_E~0); 316057#L1565-1 assume !(1 == ~E_1~0); 316058#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 315411#L1575-1 assume !(1 == ~E_3~0); 314745#L1580-1 assume !(1 == ~E_4~0); 314746#L1585-1 assume !(1 == ~E_5~0); 315243#L1590-1 assume !(1 == ~E_6~0); 314778#L1595-1 assume !(1 == ~E_7~0); 314779#L1600-1 assume !(1 == ~E_8~0); 315174#L1605-1 assume !(1 == ~E_9~0); 315175#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 350419#L1615-1 assume !(1 == ~E_11~0); 350417#L1620-1 assume !(1 == ~E_12~0); 350415#L1625-1 assume !(1 == ~E_13~0); 350413#L1630-1 assume !(1 == ~E_14~0); 350410#L1635-1 assume { :end_inline_reset_delta_events } true; 350407#L2017-2 [2024-10-25 00:40:51,411 INFO L747 eck$LassoCheckResult]: Loop: 350407#L2017-2 assume !false; 346543#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 346542#L1316-1 assume !false; 346541#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 346536#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 346525#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 346524#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 346522#L1115 assume !(0 != eval_~tmp~0#1); 346523#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 350820#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 350818#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 350816#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 350814#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 350812#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 350810#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 350808#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 350806#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 350804#L1372-3 assume !(0 == ~T7_E~0); 350802#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 350800#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 350798#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 350796#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 350794#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 350792#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 350790#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 350788#L1412-3 assume !(0 == ~E_1~0); 350786#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 350784#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 350782#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 350780#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 350778#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 350776#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 350774#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 350772#L1452-3 assume !(0 == ~E_9~0); 350770#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 350768#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 350766#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 350764#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 350762#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 350760#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 350758#L646-42 assume !(1 == ~m_pc~0); 350756#L646-44 is_master_triggered_~__retres1~0#1 := 0; 350754#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 350752#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 350750#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 350748#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350746#L665-42 assume 1 == ~t1_pc~0; 350743#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 350740#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350738#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 350736#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 350734#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350732#L684-42 assume !(1 == ~t2_pc~0); 350730#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 350728#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 350726#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 350724#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 350722#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 350720#L703-42 assume 1 == ~t3_pc~0; 350717#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 350714#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350712#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350710#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 350708#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 350706#L722-42 assume !(1 == ~t4_pc~0); 350704#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 350702#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350700#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 350698#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 350696#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 350694#L741-42 assume 1 == ~t5_pc~0; 350691#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 350688#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 350686#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 350684#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 350682#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350680#L760-42 assume !(1 == ~t6_pc~0); 350677#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 350674#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350672#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 350670#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 350668#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 350666#L779-42 assume !(1 == ~t7_pc~0); 350663#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 350660#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350658#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 350656#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 350654#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 350652#L798-42 assume !(1 == ~t8_pc~0); 350649#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 350646#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 350644#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 350642#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 350640#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 350638#L817-42 assume !(1 == ~t9_pc~0); 350635#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 350632#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 350630#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 350628#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 350626#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 350624#L836-42 assume 1 == ~t10_pc~0; 350621#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 350618#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 350616#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 350614#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 350612#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 350610#L855-42 assume !(1 == ~t11_pc~0); 350607#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 350604#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 350602#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 350600#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 350598#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 350596#L874-42 assume 1 == ~t12_pc~0; 350593#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 350590#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 350588#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 350586#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 350584#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 350582#L893-42 assume !(1 == ~t13_pc~0); 350579#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 350576#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 350574#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 350572#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 350570#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 350568#L912-42 assume 1 == ~t14_pc~0; 350565#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 350562#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 350560#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 350558#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 350556#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 350554#L1495-3 assume !(1 == ~M_E~0); 350552#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 350550#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 325611#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 350546#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 350544#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 350542#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 350540#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 334859#L1530-3 assume !(1 == ~T8_E~0); 350538#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 350536#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 350534#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 350532#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 350530#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 350528#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 350527#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 350524#L1570-3 assume !(1 == ~E_2~0); 350523#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 350522#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 350521#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 350520#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 350519#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 350518#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 350517#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 325563#L1610-3 assume !(1 == ~E_10~0); 350516#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 350515#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 350514#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 350513#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 350512#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 350492#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 350482#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 350480#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 350477#L2036 assume !(0 == start_simulation_~tmp~3#1); 350474#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 350453#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 350442#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 350439#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 350437#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 350435#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 350433#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 350409#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 350407#L2017-2 [2024-10-25 00:40:51,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:51,412 INFO L85 PathProgramCache]: Analyzing trace with hash 1108215503, now seen corresponding path program 1 times [2024-10-25 00:40:51,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:51,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101113142] [2024-10-25 00:40:51,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:51,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:51,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:51,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:51,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:51,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101113142] [2024-10-25 00:40:51,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101113142] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:51,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:51,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:40:51,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592827817] [2024-10-25 00:40:51,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:51,466 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:51,466 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:51,467 INFO L85 PathProgramCache]: Analyzing trace with hash -841284948, now seen corresponding path program 1 times [2024-10-25 00:40:51,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:51,467 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216449616] [2024-10-25 00:40:51,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:51,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:51,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:51,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:51,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:51,515 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216449616] [2024-10-25 00:40:51,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1216449616] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:51,516 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:51,516 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:51,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1313432176] [2024-10-25 00:40:51,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:51,516 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:51,517 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:51,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:40:51,517 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:40:51,517 INFO L87 Difference]: Start difference. First operand 77997 states and 112948 transitions. cyclomatic complexity: 34999 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:52,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:52,248 INFO L93 Difference]: Finished difference Result 150044 states and 216577 transitions. [2024-10-25 00:40:52,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 150044 states and 216577 transitions. [2024-10-25 00:40:53,071 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 149416 [2024-10-25 00:40:53,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 150044 states to 150044 states and 216577 transitions. [2024-10-25 00:40:53,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 150044 [2024-10-25 00:40:53,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 150044 [2024-10-25 00:40:53,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150044 states and 216577 transitions. [2024-10-25 00:40:53,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:40:53,928 INFO L218 hiAutomatonCegarLoop]: Abstraction has 150044 states and 216577 transitions. [2024-10-25 00:40:54,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150044 states and 216577 transitions. [2024-10-25 00:40:55,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150044 to 149948. [2024-10-25 00:40:56,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149948 states, 149948 states have (on average 1.4437071518126283) internal successors, (216481), 149947 states have internal predecessors, (216481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:56,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149948 states to 149948 states and 216481 transitions. [2024-10-25 00:40:56,422 INFO L240 hiAutomatonCegarLoop]: Abstraction has 149948 states and 216481 transitions. [2024-10-25 00:40:56,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-25 00:40:56,423 INFO L425 stractBuchiCegarLoop]: Abstraction has 149948 states and 216481 transitions. [2024-10-25 00:40:56,423 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-25 00:40:56,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149948 states and 216481 transitions. [2024-10-25 00:40:57,343 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 149320 [2024-10-25 00:40:57,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:40:57,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:40:57,348 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:57,348 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:40:57,352 INFO L745 eck$LassoCheckResult]: Stem: 542274#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 542275#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 543227#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 543228#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 544148#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 542818#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 542819#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 542522#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 542523#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 543868#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 543117#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 543118#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 543713#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 543017#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 543018#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 542431#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 542432#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 542786#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 542971#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 542024#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 542025#L1342 assume !(0 == ~M_E~0); 542189#L1342-2 assume !(0 == ~T1_E~0); 542753#L1347-1 assume !(0 == ~T2_E~0); 543846#L1352-1 assume !(0 == ~T3_E~0); 543599#L1357-1 assume !(0 == ~T4_E~0); 542775#L1362-1 assume !(0 == ~T5_E~0); 542776#L1367-1 assume !(0 == ~T6_E~0); 542346#L1372-1 assume !(0 == ~T7_E~0); 542347#L1377-1 assume !(0 == ~T8_E~0); 542691#L1382-1 assume !(0 == ~T9_E~0); 542692#L1387-1 assume !(0 == ~T10_E~0); 543466#L1392-1 assume !(0 == ~T11_E~0); 542735#L1397-1 assume !(0 == ~T12_E~0); 542736#L1402-1 assume !(0 == ~T13_E~0); 542371#L1407-1 assume !(0 == ~T14_E~0); 542372#L1412-1 assume !(0 == ~E_1~0); 543749#L1417-1 assume !(0 == ~E_2~0); 543750#L1422-1 assume !(0 == ~E_3~0); 544052#L1427-1 assume !(0 == ~E_4~0); 542551#L1432-1 assume !(0 == ~E_5~0); 542552#L1437-1 assume !(0 == ~E_6~0); 543656#L1442-1 assume !(0 == ~E_7~0); 543657#L1447-1 assume !(0 == ~E_8~0); 543460#L1452-1 assume !(0 == ~E_9~0); 542158#L1457-1 assume !(0 == ~E_10~0); 542159#L1462-1 assume !(0 == ~E_11~0); 543689#L1467-1 assume !(0 == ~E_12~0); 543706#L1472-1 assume !(0 == ~E_13~0); 543707#L1477-1 assume !(0 == ~E_14~0); 543402#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 542336#L646 assume !(1 == ~m_pc~0); 542337#L646-2 is_master_triggered_~__retres1~0#1 := 0; 543046#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 543047#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 542433#L1666 assume !(0 != activate_threads_~tmp~1#1); 542434#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 544085#L665 assume !(1 == ~t1_pc~0); 542920#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 542921#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 543568#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 543569#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 543277#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 543278#L684 assume !(1 == ~t2_pc~0); 543320#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 543321#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 542421#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 542422#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 543853#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 544103#L703 assume !(1 == ~t3_pc~0); 542577#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 542578#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 543554#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 541994#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 541995#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 542462#L722 assume !(1 == ~t4_pc~0); 542654#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 542655#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 542103#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 542104#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 543070#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 542190#L741 assume !(1 == ~t5_pc~0); 542191#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 543312#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 543313#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 543369#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 543370#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 542754#L760 assume !(1 == ~t6_pc~0); 542576#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 542575#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 542411#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 542412#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 543188#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 543189#L779 assume 1 == ~t7_pc~0; 542224#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 542076#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 542077#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 543893#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 542497#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 542498#L798 assume !(1 == ~t8_pc~0); 543905#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 543802#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 543803#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 544018#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 544087#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 542057#L817 assume 1 == ~t9_pc~0; 542058#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 542854#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 542466#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 542467#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 542444#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 542445#L836 assume !(1 == ~t10_pc~0); 542468#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 542395#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 542396#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 542656#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 542657#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 543817#L855 assume 1 == ~t11_pc~0; 543042#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 543043#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 543682#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 543457#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 543283#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 542333#L874 assume !(1 == ~t12_pc~0); 542334#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 542506#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 542044#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 542045#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 542030#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 542031#L893 assume 1 == ~t13_pc~0; 543987#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 542374#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 542690#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 543923#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 543910#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 543911#L912 assume 1 == ~t14_pc~0; 543665#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 543666#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 543744#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 542272#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 542273#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 543063#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 543522#L1495-2 assume !(1 == ~T1_E~0); 543523#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 543182#L1505-1 assume !(1 == ~T3_E~0); 543183#L1510-1 assume !(1 == ~T4_E~0); 543243#L1515-1 assume !(1 == ~T5_E~0); 543244#L1520-1 assume !(1 == ~T6_E~0); 543906#L1525-1 assume !(1 == ~T7_E~0); 543555#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 543556#L1535-1 assume !(1 == ~T9_E~0); 544121#L1540-1 assume !(1 == ~T10_E~0); 544122#L1545-1 assume !(1 == ~T11_E~0); 544164#L1550-1 assume !(1 == ~T12_E~0); 544165#L1555-1 assume !(1 == ~T13_E~0); 542487#L1560-1 assume !(1 == ~T14_E~0); 542488#L1565-1 assume !(1 == ~E_1~0); 559791#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 559790#L1575-1 assume !(1 == ~E_3~0); 559789#L1580-1 assume !(1 == ~E_4~0); 559788#L1585-1 assume !(1 == ~E_5~0); 559787#L1590-1 assume !(1 == ~E_6~0); 559786#L1595-1 assume !(1 == ~E_7~0); 559785#L1600-1 assume !(1 == ~E_8~0); 559784#L1605-1 assume !(1 == ~E_9~0); 558197#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 559779#L1615-1 assume !(1 == ~E_11~0); 559775#L1620-1 assume !(1 == ~E_12~0); 559776#L1625-1 assume !(1 == ~E_13~0); 563816#L1630-1 assume !(1 == ~E_14~0); 563815#L1635-1 assume { :end_inline_reset_delta_events } true; 559758#L2017-2 [2024-10-25 00:40:57,353 INFO L747 eck$LassoCheckResult]: Loop: 559758#L2017-2 assume !false; 559759#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 559681#L1316-1 assume !false; 559682#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 559473#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 559463#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 559440#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 559441#L1115 assume !(0 != eval_~tmp~0#1); 563798#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 563796#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 563794#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 563792#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 563789#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 563787#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 563785#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 563783#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 563781#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 563779#L1372-3 assume !(0 == ~T7_E~0); 563777#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 563775#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 563773#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 563771#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 563769#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 563767#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 563765#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 563763#L1412-3 assume !(0 == ~E_1~0); 563761#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 563759#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 563757#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 563755#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 563753#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 563751#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 563749#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 563747#L1452-3 assume !(0 == ~E_9~0); 563745#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 563743#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 563741#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 563739#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 563737#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 563735#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 563733#L646-42 assume !(1 == ~m_pc~0); 563731#L646-44 is_master_triggered_~__retres1~0#1 := 0; 563729#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 563727#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 563725#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 563723#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 563719#L665-42 assume !(1 == ~t1_pc~0); 563720#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 565337#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 565336#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 565335#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 565334#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 565333#L684-42 assume !(1 == ~t2_pc~0); 565332#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 565331#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 565330#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 565329#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 565328#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 565327#L703-42 assume !(1 == ~t3_pc~0); 565325#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 565324#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 565323#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 565322#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 565321#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 565320#L722-42 assume !(1 == ~t4_pc~0); 565319#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 565318#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 565317#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 565316#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 565315#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 565314#L741-42 assume !(1 == ~t5_pc~0); 565313#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 565312#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 565311#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 565310#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 565309#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 565308#L760-42 assume 1 == ~t6_pc~0; 565306#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 565305#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 565304#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 565303#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 565302#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 565301#L779-42 assume 1 == ~t7_pc~0; 563631#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 563629#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 563627#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 563625#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 563623#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 563621#L798-42 assume 1 == ~t8_pc~0; 563617#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 563615#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 563613#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 563611#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 563609#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 563607#L817-42 assume 1 == ~t9_pc~0; 563602#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 563600#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 563598#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 563596#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 563594#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 563589#L836-42 assume !(1 == ~t10_pc~0); 563590#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 565281#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 565280#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 565279#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 565278#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 565277#L855-42 assume 1 == ~t11_pc~0; 563570#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 563568#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 563566#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 563564#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 563562#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 563559#L874-42 assume !(1 == ~t12_pc~0); 563556#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 563554#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 563552#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 563550#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 563548#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 563545#L893-42 assume 1 == ~t13_pc~0; 563542#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 563540#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 563538#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 563536#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 563534#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 563531#L912-42 assume 1 == ~t14_pc~0; 563532#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 565257#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 565256#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 565255#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 565254#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 565253#L1495-3 assume !(1 == ~M_E~0); 565252#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 565251#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 558701#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 565250#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 565249#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 565248#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 565247#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 565244#L1530-3 assume !(1 == ~T8_E~0); 565243#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 565242#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 563493#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 563494#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 563488#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 563486#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 563482#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 563483#L1570-3 assume !(1 == ~E_2~0); 565115#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 565100#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 563472#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 563473#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 563466#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 563467#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 563460#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 558647#L1610-3 assume !(1 == ~E_10~0); 563454#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 563455#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 563448#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 563449#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 563442#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 563443#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 563991#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 563990#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 563988#L2036 assume !(0 == start_simulation_~tmp~3#1); 559841#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 559842#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 563823#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 563822#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 563821#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 563820#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 559792#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 559793#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 559758#L2017-2 [2024-10-25 00:40:57,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:57,355 INFO L85 PathProgramCache]: Analyzing trace with hash 1070768814, now seen corresponding path program 1 times [2024-10-25 00:40:57,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:57,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632604830] [2024-10-25 00:40:57,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:57,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:57,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:57,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:57,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:57,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632604830] [2024-10-25 00:40:57,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632604830] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:57,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:57,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-25 00:40:57,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [434000333] [2024-10-25 00:40:57,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:57,500 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:40:57,501 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:40:57,501 INFO L85 PathProgramCache]: Analyzing trace with hash -487083315, now seen corresponding path program 1 times [2024-10-25 00:40:57,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:40:57,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324500640] [2024-10-25 00:40:57,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:40:57,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:40:57,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:40:57,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:40:57,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:40:57,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324500640] [2024-10-25 00:40:57,561 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324500640] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:40:57,561 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:40:57,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:40:57,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869960347] [2024-10-25 00:40:57,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:40:57,562 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:40:57,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:40:57,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-25 00:40:57,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-25 00:40:57,563 INFO L87 Difference]: Start difference. First operand 149948 states and 216481 transitions. cyclomatic complexity: 66629 Second operand has 5 states, 5 states have (on average 34.0) internal successors, (170), 5 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:40:58,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:40:58,443 INFO L93 Difference]: Finished difference Result 153503 states and 220036 transitions. [2024-10-25 00:40:58,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153503 states and 220036 transitions. [2024-10-25 00:40:59,757 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 152872 [2024-10-25 00:41:00,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153503 states to 153503 states and 220036 transitions. [2024-10-25 00:41:00,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153503 [2024-10-25 00:41:00,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153503 [2024-10-25 00:41:00,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153503 states and 220036 transitions. [2024-10-25 00:41:00,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:41:00,364 INFO L218 hiAutomatonCegarLoop]: Abstraction has 153503 states and 220036 transitions. [2024-10-25 00:41:00,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153503 states and 220036 transitions. [2024-10-25 00:41:02,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153503 to 153503. [2024-10-25 00:41:02,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 153503 states, 153503 states have (on average 1.433431268444265) internal successors, (220036), 153502 states have internal predecessors, (220036), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:41:03,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153503 states to 153503 states and 220036 transitions. [2024-10-25 00:41:03,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 153503 states and 220036 transitions. [2024-10-25 00:41:03,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-25 00:41:03,185 INFO L425 stractBuchiCegarLoop]: Abstraction has 153503 states and 220036 transitions. [2024-10-25 00:41:03,185 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-25 00:41:03,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 153503 states and 220036 transitions. [2024-10-25 00:41:03,579 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 152872 [2024-10-25 00:41:03,580 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:41:03,580 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:41:03,581 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:41:03,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:41:03,582 INFO L745 eck$LassoCheckResult]: Stem: 845735#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 845736#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 846684#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 846685#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 847585#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 846276#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 846277#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 845986#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 845987#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 847305#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 846572#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 846573#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 847159#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 846474#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 846475#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 845895#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 845896#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 846243#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 846426#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 845484#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 845485#L1342 assume !(0 == ~M_E~0); 845650#L1342-2 assume !(0 == ~T1_E~0); 846209#L1347-1 assume !(0 == ~T2_E~0); 847284#L1352-1 assume !(0 == ~T3_E~0); 847049#L1357-1 assume !(0 == ~T4_E~0); 846232#L1362-1 assume !(0 == ~T5_E~0); 846233#L1367-1 assume !(0 == ~T6_E~0); 845813#L1372-1 assume !(0 == ~T7_E~0); 845814#L1377-1 assume !(0 == ~T8_E~0); 846148#L1382-1 assume !(0 == ~T9_E~0); 846149#L1387-1 assume !(0 == ~T10_E~0); 846925#L1392-1 assume !(0 == ~T11_E~0); 846191#L1397-1 assume !(0 == ~T12_E~0); 846192#L1402-1 assume !(0 == ~T13_E~0); 845833#L1407-1 assume !(0 == ~T14_E~0); 845834#L1412-1 assume !(0 == ~E_1~0); 847193#L1417-1 assume !(0 == ~E_2~0); 847194#L1422-1 assume !(0 == ~E_3~0); 847501#L1427-1 assume !(0 == ~E_4~0); 846013#L1432-1 assume !(0 == ~E_5~0); 846014#L1437-1 assume !(0 == ~E_6~0); 847104#L1442-1 assume !(0 == ~E_7~0); 847105#L1447-1 assume !(0 == ~E_8~0); 846918#L1452-1 assume !(0 == ~E_9~0); 845621#L1457-1 assume !(0 == ~E_10~0); 845622#L1462-1 assume !(0 == ~E_11~0); 847137#L1467-1 assume !(0 == ~E_12~0); 847154#L1472-1 assume !(0 == ~E_13~0); 847155#L1477-1 assume !(0 == ~E_14~0); 846861#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 845803#L646 assume !(1 == ~m_pc~0); 845804#L646-2 is_master_triggered_~__retres1~0#1 := 0; 846502#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 846503#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 845897#L1666 assume !(0 != activate_threads_~tmp~1#1); 845898#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 847527#L665 assume !(1 == ~t1_pc~0); 846376#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 846377#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 847019#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 847020#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 846732#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 846733#L684 assume !(1 == ~t2_pc~0); 846777#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 846778#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 845885#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 845886#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 847291#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 847546#L703 assume !(1 == ~t3_pc~0); 846037#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 846038#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 847006#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 845454#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 845455#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 845926#L722 assume !(1 == ~t4_pc~0); 846112#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 846113#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 845564#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 845565#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 846525#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 845651#L741 assume !(1 == ~t5_pc~0); 845652#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 846766#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 846767#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 846828#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 846829#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 846210#L760 assume !(1 == ~t6_pc~0); 846036#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 846670#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 846964#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 847490#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 846642#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 846643#L779 assume 1 == ~t7_pc~0; 845685#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 845536#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 845537#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 847340#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 845959#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 845960#L798 assume !(1 == ~t8_pc~0); 847349#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 847246#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 847247#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 847466#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 847529#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 845517#L817 assume 1 == ~t9_pc~0; 845518#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 846311#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 845930#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 845931#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 845908#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 845909#L836 assume !(1 == ~t10_pc~0); 845932#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 845859#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 845860#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 846114#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 846115#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 847258#L855 assume 1 == ~t11_pc~0; 846498#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 846499#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 847131#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 846915#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 846738#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 845796#L874 assume !(1 == ~t12_pc~0); 845797#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 845968#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 845504#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 845505#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 845490#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 845491#L893 assume 1 == ~t13_pc~0; 847442#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 845836#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 846147#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 847366#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 847355#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 847356#L912 assume 1 == ~t14_pc~0; 847112#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 847113#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 847190#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 845733#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 845734#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 846520#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 846974#L1495-2 assume !(1 == ~T1_E~0); 846975#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 846636#L1505-1 assume !(1 == ~T3_E~0); 846637#L1510-1 assume !(1 == ~T4_E~0); 846699#L1515-1 assume !(1 == ~T5_E~0); 846700#L1520-1 assume !(1 == ~T6_E~0); 847351#L1525-1 assume !(1 == ~T7_E~0); 847007#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 845902#L1535-1 assume !(1 == ~T9_E~0); 845903#L1540-1 assume !(1 == ~T10_E~0); 845415#L1545-1 assume !(1 == ~T11_E~0); 845416#L1550-1 assume !(1 == ~T12_E~0); 845659#L1555-1 assume !(1 == ~T13_E~0); 845660#L1560-1 assume !(1 == ~T14_E~0); 845952#L1565-1 assume !(1 == ~E_1~0); 847511#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 885421#L1575-1 assume !(1 == ~E_3~0); 885419#L1580-1 assume !(1 == ~E_4~0); 885417#L1585-1 assume !(1 == ~E_5~0); 885415#L1590-1 assume !(1 == ~E_6~0); 885413#L1595-1 assume !(1 == ~E_7~0); 885411#L1600-1 assume !(1 == ~E_8~0); 882933#L1605-1 assume !(1 == ~E_9~0); 882929#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 882927#L1615-1 assume !(1 == ~E_11~0); 882925#L1620-1 assume !(1 == ~E_12~0); 882923#L1625-1 assume !(1 == ~E_13~0); 882876#L1630-1 assume !(1 == ~E_14~0); 882865#L1635-1 assume { :end_inline_reset_delta_events } true; 882855#L2017-2 [2024-10-25 00:41:03,583 INFO L747 eck$LassoCheckResult]: Loop: 882855#L2017-2 assume !false; 882847#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 882845#L1316-1 assume !false; 882843#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 882775#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 882760#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 882751#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 882744#L1115 assume !(0 != eval_~tmp~0#1); 882745#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 887183#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 887181#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 887179#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 887177#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 887174#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 887172#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 887170#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 887168#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 887166#L1372-3 assume !(0 == ~T7_E~0); 887165#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 887160#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 887158#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 887156#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 887154#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 887153#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 887152#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 887151#L1412-3 assume !(0 == ~E_1~0); 887148#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 887144#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 887140#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 887136#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 887135#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 887134#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 887133#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 887132#L1452-3 assume !(0 == ~E_9~0); 887131#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 887130#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 887129#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 887128#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 887127#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 887126#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 887125#L646-42 assume !(1 == ~m_pc~0); 887124#L646-44 is_master_triggered_~__retres1~0#1 := 0; 887123#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 887121#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 887120#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 887119#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 887118#L665-42 assume 1 == ~t1_pc~0; 887117#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 887115#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 887114#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 887113#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 887111#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 887109#L684-42 assume !(1 == ~t2_pc~0); 887108#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 887107#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 887106#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 887105#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 887104#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 887102#L703-42 assume 1 == ~t3_pc~0; 887100#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 887097#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 887095#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 887093#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 887091#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 887089#L722-42 assume !(1 == ~t4_pc~0); 887086#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 887084#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 887082#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 887080#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 887078#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 887076#L741-42 assume !(1 == ~t5_pc~0); 887074#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 887072#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 887070#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 887068#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 887066#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 887064#L760-42 assume !(1 == ~t6_pc~0); 887061#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 887112#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 887110#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 887053#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 887051#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 887049#L779-42 assume !(1 == ~t7_pc~0); 887047#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 887044#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 887042#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 887040#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 887038#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 887036#L798-42 assume 1 == ~t8_pc~0; 887033#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 887031#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 887029#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 887027#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 887025#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 887021#L817-42 assume !(1 == ~t9_pc~0); 887019#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 887016#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 887014#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 887011#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 887009#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 887007#L836-42 assume 1 == ~t10_pc~0; 887004#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 887001#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 886999#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 886997#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 886995#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 886993#L855-42 assume 1 == ~t11_pc~0; 886989#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 886987#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 886985#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 886983#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 886981#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 886979#L874-42 assume !(1 == ~t12_pc~0); 886975#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 886973#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 886971#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 886969#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 886967#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 886965#L893-42 assume 1 == ~t13_pc~0; 886961#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 886959#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 886957#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 886955#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 886953#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 886951#L912-42 assume 1 == ~t14_pc~0; 886948#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 886945#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 886943#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 886941#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 886939#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 886937#L1495-3 assume !(1 == ~M_E~0); 886934#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 886932#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 881797#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 886927#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 886925#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 886923#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 886920#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 885329#L1530-3 assume !(1 == ~T8_E~0); 886917#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 886915#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 886913#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 886911#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 886908#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 886906#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 886904#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 886900#L1570-3 assume !(1 == ~E_2~0); 886898#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 886897#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 886893#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 886891#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 886889#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 886888#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 886885#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 884289#L1610-3 assume !(1 == ~E_10~0); 886884#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 886883#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 886882#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 886881#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 886880#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 884761#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 884751#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 884749#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 884747#L2036 assume !(0 == start_simulation_~tmp~3#1); 884744#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 882914#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 882903#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 882901#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 882899#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 882897#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 882875#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 882864#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 882855#L2017-2 [2024-10-25 00:41:03,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:41:03,584 INFO L85 PathProgramCache]: Analyzing trace with hash -71733652, now seen corresponding path program 1 times [2024-10-25 00:41:03,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:41:03,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169429864] [2024-10-25 00:41:03,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:41:03,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:41:03,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:41:03,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:41:03,689 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:41:03,689 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [169429864] [2024-10-25 00:41:03,689 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [169429864] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:41:03,689 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:41:03,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:41:03,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556328103] [2024-10-25 00:41:03,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:41:03,690 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:41:03,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:41:03,691 INFO L85 PathProgramCache]: Analyzing trace with hash 1212304589, now seen corresponding path program 1 times [2024-10-25 00:41:03,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:41:03,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140914278] [2024-10-25 00:41:03,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:41:03,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:41:03,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:41:03,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:41:03,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:41:03,759 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140914278] [2024-10-25 00:41:03,759 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1140914278] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:41:03,759 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:41:03,760 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:41:03,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28637160] [2024-10-25 00:41:03,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:41:03,760 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:41:03,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:41:03,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-25 00:41:03,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-25 00:41:03,762 INFO L87 Difference]: Start difference. First operand 153503 states and 220036 transitions. cyclomatic complexity: 66629 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:41:06,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:41:06,106 INFO L93 Difference]: Finished difference Result 430813 states and 614014 transitions. [2024-10-25 00:41:06,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430813 states and 614014 transitions. [2024-10-25 00:41:08,986 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 428712 [2024-10-25 00:41:10,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430813 states to 430813 states and 614014 transitions. [2024-10-25 00:41:10,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430813 [2024-10-25 00:41:11,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430813 [2024-10-25 00:41:11,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430813 states and 614014 transitions. [2024-10-25 00:41:11,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-25 00:41:11,297 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430813 states and 614014 transitions. [2024-10-25 00:41:11,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430813 states and 614014 transitions. [2024-10-25 00:41:16,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430813 to 424765. [2024-10-25 00:41:16,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 424765 states, 424765 states have (on average 1.4261014914128989) internal successors, (605758), 424764 states have internal predecessors, (605758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:41:19,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 424765 states to 424765 states and 605758 transitions. [2024-10-25 00:41:19,343 INFO L240 hiAutomatonCegarLoop]: Abstraction has 424765 states and 605758 transitions. [2024-10-25 00:41:19,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-25 00:41:19,344 INFO L425 stractBuchiCegarLoop]: Abstraction has 424765 states and 605758 transitions. [2024-10-25 00:41:19,344 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-25 00:41:19,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 424765 states and 605758 transitions. [2024-10-25 00:41:21,414 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 423240 [2024-10-25 00:41:21,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-25 00:41:21,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-25 00:41:21,416 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:41:21,416 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-25 00:41:21,416 INFO L745 eck$LassoCheckResult]: Stem: 1430062#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1430063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 1431037#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1431038#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1432058#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 1430610#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1430611#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1430316#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1430317#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1431720#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1430919#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1430920#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1431549#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1430816#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1430817#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1430221#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1430222#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1430579#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1430767#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 1429810#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1429811#L1342 assume !(0 == ~M_E~0); 1429976#L1342-2 assume !(0 == ~T1_E~0); 1430545#L1347-1 assume !(0 == ~T2_E~0); 1431693#L1352-1 assume !(0 == ~T3_E~0); 1431431#L1357-1 assume !(0 == ~T4_E~0); 1430566#L1362-1 assume !(0 == ~T5_E~0); 1430567#L1367-1 assume !(0 == ~T6_E~0); 1430140#L1372-1 assume !(0 == ~T7_E~0); 1430141#L1377-1 assume !(0 == ~T8_E~0); 1430483#L1382-1 assume !(0 == ~T9_E~0); 1430484#L1387-1 assume !(0 == ~T10_E~0); 1431296#L1392-1 assume !(0 == ~T11_E~0); 1430527#L1397-1 assume !(0 == ~T12_E~0); 1430528#L1402-1 assume !(0 == ~T13_E~0); 1430160#L1407-1 assume !(0 == ~T14_E~0); 1430161#L1412-1 assume !(0 == ~E_1~0); 1431585#L1417-1 assume !(0 == ~E_2~0); 1431586#L1422-1 assume !(0 == ~E_3~0); 1431934#L1427-1 assume !(0 == ~E_4~0); 1430345#L1432-1 assume !(0 == ~E_5~0); 1430346#L1437-1 assume !(0 == ~E_6~0); 1431489#L1442-1 assume !(0 == ~E_7~0); 1431490#L1447-1 assume !(0 == ~E_8~0); 1431288#L1452-1 assume !(0 == ~E_9~0); 1429947#L1457-1 assume !(0 == ~E_10~0); 1429948#L1462-1 assume !(0 == ~E_11~0); 1431524#L1467-1 assume !(0 == ~E_12~0); 1431543#L1472-1 assume !(0 == ~E_13~0); 1431544#L1477-1 assume !(0 == ~E_14~0); 1431228#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1430130#L646 assume !(1 == ~m_pc~0); 1430131#L646-2 is_master_triggered_~__retres1~0#1 := 0; 1430848#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1430849#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1430223#L1666 assume !(0 != activate_threads_~tmp~1#1); 1430224#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1431975#L665 assume !(1 == ~t1_pc~0); 1430716#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1430717#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1431400#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1431401#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 1431089#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1431090#L684 assume !(1 == ~t2_pc~0); 1431138#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1431139#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1430211#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1430212#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 1431700#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1432001#L703 assume !(1 == ~t3_pc~0); 1430370#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1430371#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431385#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1429780#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 1429781#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1430255#L722 assume !(1 == ~t4_pc~0); 1430445#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1430446#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1429890#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1429891#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 1430873#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1429977#L741 assume !(1 == ~t5_pc~0); 1429978#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1431129#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1431130#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1431192#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 1431193#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1430546#L760 assume !(1 == ~t6_pc~0); 1430369#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1431023#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1431340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1431920#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 1430991#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1430992#L779 assume !(1 == ~t7_pc~0); 1431770#L779-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1429862#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1429863#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1431750#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 1430289#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1430290#L798 assume !(1 == ~t8_pc~0); 1431759#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1431642#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1431643#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1431891#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 1431977#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1429843#L817 assume 1 == ~t9_pc~0; 1429844#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1430647#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1430257#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1430258#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 1430234#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1430235#L836 assume !(1 == ~t10_pc~0); 1430259#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1430185#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1430186#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1430447#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 1430448#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1431659#L855 assume 1 == ~t11_pc~0; 1430842#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1430843#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1431517#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1431285#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 1431096#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1430123#L874 assume !(1 == ~t12_pc~0); 1430124#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1430299#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1429830#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1429831#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 1429818#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1429819#L893 assume 1 == ~t13_pc~0; 1431861#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1430163#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1430482#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1431780#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 1431767#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1431768#L912 assume 1 == ~t14_pc~0; 1431497#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1431498#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1431581#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1430060#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 1430061#L1778-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1430866#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 1431353#L1495-2 assume !(1 == ~T1_E~0); 1431354#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1431927#L1505-1 assume !(1 == ~T3_E~0); 1432052#L1510-1 assume !(1 == ~T4_E~0); 1432053#L1515-1 assume !(1 == ~T5_E~0); 1431961#L1520-1 assume !(1 == ~T6_E~0); 1431962#L1525-1 assume !(1 == ~T7_E~0); 1459203#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1459202#L1535-1 assume !(1 == ~T9_E~0); 1459201#L1540-1 assume !(1 == ~T10_E~0); 1459200#L1545-1 assume !(1 == ~T11_E~0); 1459199#L1550-1 assume !(1 == ~T12_E~0); 1459198#L1555-1 assume !(1 == ~T13_E~0); 1459197#L1560-1 assume !(1 == ~T14_E~0); 1459196#L1565-1 assume !(1 == ~E_1~0); 1459195#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1459194#L1575-1 assume !(1 == ~E_3~0); 1459193#L1580-1 assume !(1 == ~E_4~0); 1459192#L1585-1 assume !(1 == ~E_5~0); 1459191#L1590-1 assume !(1 == ~E_6~0); 1459190#L1595-1 assume !(1 == ~E_7~0); 1459189#L1600-1 assume !(1 == ~E_8~0); 1459187#L1605-1 assume !(1 == ~E_9~0); 1459188#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1475840#L1615-1 assume !(1 == ~E_11~0); 1475839#L1620-1 assume !(1 == ~E_12~0); 1475838#L1625-1 assume !(1 == ~E_13~0); 1475837#L1630-1 assume !(1 == ~E_14~0); 1459171#L1635-1 assume { :end_inline_reset_delta_events } true; 1459170#L2017-2 [2024-10-25 00:41:21,497 INFO L747 eck$LassoCheckResult]: Loop: 1459170#L2017-2 assume !false; 1458872#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1458873#L1316-1 assume !false; 1458868#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1458869#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1458777#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1458778#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1458750#L1115 assume !(0 != eval_~tmp~0#1); 1458752#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1477837#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1477832#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1477827#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1477822#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1477810#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1477805#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1477800#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1477796#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1477791#L1372-3 assume !(0 == ~T7_E~0); 1477788#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1477783#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1477777#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1477772#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1477768#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1477764#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1473599#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 1469356#L1412-3 assume !(0 == ~E_1~0); 1469350#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1469344#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1469339#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1469333#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1469327#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1469321#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1469315#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1469309#L1452-3 assume !(0 == ~E_9~0); 1469304#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1469300#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1469294#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1469289#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1469284#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 1469278#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1469274#L646-42 assume !(1 == ~m_pc~0); 1469269#L646-44 is_master_triggered_~__retres1~0#1 := 0; 1469265#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1469261#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1469256#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1469250#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1469243#L665-42 assume !(1 == ~t1_pc~0); 1469234#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1469227#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1469220#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1469213#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1469204#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1469197#L684-42 assume !(1 == ~t2_pc~0); 1469189#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1469181#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1469175#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1469167#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1469158#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1469150#L703-42 assume !(1 == ~t3_pc~0); 1469142#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1469133#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1469087#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1469076#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1469066#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1469055#L722-42 assume !(1 == ~t4_pc~0); 1469028#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1469018#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1469009#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1469001#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1468994#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1468993#L741-42 assume !(1 == ~t5_pc~0); 1468992#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1468991#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1468989#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1468988#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1468987#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1468986#L760-42 assume 1 == ~t6_pc~0; 1468984#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1468982#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1468980#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1468979#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 1468977#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1468976#L779-42 assume !(1 == ~t7_pc~0); 1468975#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1468974#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1468973#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1468972#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1468971#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1468968#L798-42 assume 1 == ~t8_pc~0; 1468964#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1468961#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1468958#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1468955#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1468952#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1468949#L817-42 assume 1 == ~t9_pc~0; 1468944#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1468940#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1468937#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1468934#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1468931#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1468928#L836-42 assume !(1 == ~t10_pc~0); 1468924#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1468921#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1468918#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1468915#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1468912#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1468909#L855-42 assume !(1 == ~t11_pc~0); 1468906#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1468902#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1468899#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1468896#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1468893#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1468890#L874-42 assume !(1 == ~t12_pc~0); 1468886#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1468883#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1468880#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1468877#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1468874#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1468871#L893-42 assume !(1 == ~t13_pc~0); 1468868#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1468864#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1468861#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1468858#L1770-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1468855#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1468852#L912-42 assume 1 == ~t14_pc~0; 1468848#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1468845#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1468843#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1468841#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 1468838#L1778-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1468836#L1495-3 assume !(1 == ~M_E~0); 1468834#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1468832#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1462303#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1468829#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1468827#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1468825#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1468823#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1462291#L1530-3 assume !(1 == ~T8_E~0); 1468822#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1468819#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1468816#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1468813#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1468810#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1468807#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 1468804#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1468801#L1570-3 assume !(1 == ~E_2~0); 1468797#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1468793#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1468790#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1468786#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1468787#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1468778#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1468779#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1468771#L1610-3 assume !(1 == ~E_10~0); 1468772#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1468763#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1468764#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1468704#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 1468705#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1468576#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1468566#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1468564#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1468561#L2036 assume !(0 == start_simulation_~tmp~3#1); 1468557#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1468549#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1468538#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1468536#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1468534#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1468531#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1468529#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1459169#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 1459170#L2017-2 [2024-10-25 00:41:21,498 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:41:21,498 INFO L85 PathProgramCache]: Analyzing trace with hash -1348886325, now seen corresponding path program 1 times [2024-10-25 00:41:21,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:41:21,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024159921] [2024-10-25 00:41:21,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:41:21,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:41:21,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:41:21,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:41:21,572 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:41:21,572 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024159921] [2024-10-25 00:41:21,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024159921] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:41:21,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:41:21,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-25 00:41:21,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485036860] [2024-10-25 00:41:21,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:41:21,573 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-25 00:41:21,574 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-25 00:41:21,574 INFO L85 PathProgramCache]: Analyzing trace with hash -1599703318, now seen corresponding path program 1 times [2024-10-25 00:41:21,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-25 00:41:21,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287599515] [2024-10-25 00:41:21,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-25 00:41:21,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-25 00:41:21,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-25 00:41:21,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-25 00:41:21,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-25 00:41:21,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287599515] [2024-10-25 00:41:21,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287599515] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-25 00:41:21,629 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-25 00:41:21,629 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-25 00:41:21,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348493913] [2024-10-25 00:41:21,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-25 00:41:21,629 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-25 00:41:21,629 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-25 00:41:21,630 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-25 00:41:21,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-25 00:41:21,630 INFO L87 Difference]: Start difference. First operand 424765 states and 605758 transitions. cyclomatic complexity: 181185 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-25 00:41:25,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-25 00:41:25,104 INFO L93 Difference]: Finished difference Result 815220 states and 1159651 transitions. [2024-10-25 00:41:25,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 815220 states and 1159651 transitions.