./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-crafted/Arrays03-ValueRestictsIndex-2.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-crafted/Arrays03-ValueRestictsIndex-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 302c18c494f9017ecbb07643194b1d54ba0a6bba467355d4f775638dea57e539 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:18:08,840 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:18:08,986 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-64bit-Automizer_Default.epf [2024-10-31 22:18:08,994 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:18:08,999 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:18:09,059 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:18:09,060 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:18:09,060 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:18:09,061 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:18:09,064 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:18:09,066 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:18:09,066 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:18:09,067 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:18:09,067 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:18:09,067 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:18:09,072 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:18:09,072 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:18:09,073 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:18:09,073 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:18:09,073 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:18:09,074 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:18:09,074 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:18:09,075 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:18:09,075 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:18:09,075 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:18:09,076 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:18:09,076 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:18:09,076 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:18:09,077 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:18:09,077 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:18:09,077 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:18:09,080 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:18:09,082 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:18:09,082 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:18:09,083 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:18:09,083 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:18:09,084 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 302c18c494f9017ecbb07643194b1d54ba0a6bba467355d4f775638dea57e539 [2024-10-31 22:18:09,440 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:18:09,505 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:18:09,509 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:18:09,511 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:18:09,513 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:18:09,514 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/termination-crafted/Arrays03-ValueRestictsIndex-2.c Unable to find full path for "g++" [2024-10-31 22:18:11,632 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:18:11,921 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:18:11,922 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/sv-benchmarks/c/termination-crafted/Arrays03-ValueRestictsIndex-2.c [2024-10-31 22:18:11,933 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/data/75a6ba14f/c5c8c32648c8453e9495eac577d6565c/FLAG2d2e0581e [2024-10-31 22:18:11,961 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/data/75a6ba14f/c5c8c32648c8453e9495eac577d6565c [2024-10-31 22:18:11,965 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:18:11,967 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:18:11,969 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:18:11,972 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:18:11,997 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:18:11,998 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:18:11" (1/1) ... [2024-10-31 22:18:11,999 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6d209a22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:11, skipping insertion in model container [2024-10-31 22:18:12,003 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:18:11" (1/1) ... [2024-10-31 22:18:12,033 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:18:12,345 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:12,355 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:18:12,380 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:12,414 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:18:12,415 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12 WrapperNode [2024-10-31 22:18:12,416 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:18:12,417 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:12,418 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:18:12,418 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:18:12,427 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,435 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,461 INFO L138 Inliner]: procedures = 8, calls = 8, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 48 [2024-10-31 22:18:12,463 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:12,463 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:18:12,465 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:18:12,465 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:18:12,480 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,480 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,491 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,511 INFO L175 MemorySlicer]: Split 3 memory accesses to 1 slices as follows [3]. 100 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0]. The 1 writes are split as follows [1]. [2024-10-31 22:18:12,515 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,516 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,525 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,532 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,533 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,534 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,536 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:18:12,538 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:18:12,538 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:18:12,538 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:18:12,539 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (1/1) ... [2024-10-31 22:18:12,547 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:12,564 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:12,582 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:18:12,589 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:18:12,628 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-10-31 22:18:12,629 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:18:12,630 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:18:12,631 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-10-31 22:18:12,631 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-10-31 22:18:12,631 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-10-31 22:18:12,732 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:18:12,738 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:18:12,955 INFO L? ?]: Removed 8 outVars from TransFormulas that were not future-live. [2024-10-31 22:18:12,956 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:18:12,970 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:18:12,971 INFO L316 CfgBuilder]: Removed 2 assume(true) statements. [2024-10-31 22:18:12,971 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:12 BoogieIcfgContainer [2024-10-31 22:18:12,971 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:18:12,973 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:18:12,973 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:18:12,978 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:18:12,979 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:12,980 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:18:11" (1/3) ... [2024-10-31 22:18:12,981 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@11b14f7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:12, skipping insertion in model container [2024-10-31 22:18:12,982 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:12,982 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:12" (2/3) ... [2024-10-31 22:18:12,983 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@11b14f7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:12, skipping insertion in model container [2024-10-31 22:18:12,983 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:12,983 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:12" (3/3) ... [2024-10-31 22:18:12,985 INFO L332 chiAutomizerObserver]: Analyzing ICFG Arrays03-ValueRestictsIndex-2.c [2024-10-31 22:18:13,055 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:18:13,056 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:18:13,056 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:18:13,056 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:18:13,056 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:18:13,057 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:18:13,057 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:18:13,057 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:18:13,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:13,079 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3 [2024-10-31 22:18:13,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:13,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:13,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-31 22:18:13,085 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:18:13,085 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:18:13,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:13,087 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3 [2024-10-31 22:18:13,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:13,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:13,088 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-31 22:18:13,088 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:18:13,095 INFO L745 eck$LassoCheckResult]: Stem: 11#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_#t~post2#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;havoc main_#t~nondet0#1;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 3#L15-3true [2024-10-31 22:18:13,095 INFO L747 eck$LassoCheckResult]: Loop: 3#L15-3true assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 7#L15-2true main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3#L15-3true [2024-10-31 22:18:13,101 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:13,101 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-10-31 22:18:13,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:13,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684148435] [2024-10-31 22:18:13,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:13,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:13,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:13,264 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:13,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:13,299 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:13,304 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:13,304 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2024-10-31 22:18:13,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:13,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227730529] [2024-10-31 22:18:13,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:13,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:13,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:13,326 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:13,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:13,338 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:13,340 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:13,341 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2024-10-31 22:18:13,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:13,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969944618] [2024-10-31 22:18:13,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:13,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:13,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:13,377 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:13,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:13,399 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:13,781 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:18:13,782 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:18:13,782 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:18:13,782 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:18:13,782 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-31 22:18:13,783 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:13,783 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:18:13,783 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:18:13,784 INFO L132 ssoRankerPreferences]: Filename of dumped script: Arrays03-ValueRestictsIndex-2.c_Iteration1_Lasso [2024-10-31 22:18:13,784 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:18:13,784 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:18:13,808 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:13,973 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:13,978 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:13,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:13,986 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:13,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:13,998 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:14,003 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:14,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:14,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:14,022 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:18:14,239 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:18:14,245 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-31 22:18:14,247 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:14,248 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:14,251 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:18:14,254 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-31 22:18:14,256 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:18:14,274 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:18:14,275 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:18:14,275 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:18:14,275 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:18:14,285 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:18:14,285 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:18:14,295 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:18:14,317 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2024-10-31 22:18:14,318 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:14,319 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:14,322 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:18:14,324 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-31 22:18:14,325 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:18:14,343 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:18:14,343 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:18:14,344 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:18:14,344 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:18:14,348 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:18:14,349 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:18:14,356 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:18:14,378 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-10-31 22:18:14,378 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:14,378 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:14,382 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:18:14,390 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-31 22:18:14,393 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:18:14,411 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:18:14,411 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:18:14,411 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:18:14,411 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:18:14,420 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:18:14,420 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:18:14,435 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-31 22:18:14,480 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2024-10-31 22:18:14,480 INFO L444 ModelExtractionUtils]: 0 out of 13 variables were initially zero. Simplification set additionally 10 variables to zero. [2024-10-31 22:18:14,482 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:14,483 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:14,493 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:18:14,496 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-31 22:18:14,497 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-31 22:18:14,515 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2024-10-31 22:18:14,515 INFO L474 LassoAnalysis]: Proved termination. [2024-10-31 22:18:14,516 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#a~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = 2095*v_rep(select #length ULTIMATE.start_main_~#a~0#1.base)_1 - 8*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2024-10-31 22:18:14,531 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-10-31 22:18:14,541 INFO L156 tatePredicateManager]: 1 out of 1 supporting invariants were superfluous and have been removed [2024-10-31 22:18:14,550 WARN L976 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2024-10-31 22:18:14,551 WARN L976 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2024-10-31 22:18:14,578 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:14,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:14,595 INFO L255 TraceCheckSpWp]: Trace formula consists of 19 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:18:14,597 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:18:14,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:14,616 INFO L255 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-10-31 22:18:14,618 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:18:14,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:14,728 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-10-31 22:18:14,732 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:14,792 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-10-31 22:18:14,830 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 26 states and 39 transitions. Complement of second has 6 states. [2024-10-31 22:18:14,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:18:14,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:14,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 19 transitions. [2024-10-31 22:18:14,842 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 19 transitions. Stem has 2 letters. Loop has 2 letters. [2024-10-31 22:18:14,843 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:18:14,844 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 19 transitions. Stem has 4 letters. Loop has 2 letters. [2024-10-31 22:18:14,844 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:18:14,844 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 19 transitions. Stem has 2 letters. Loop has 4 letters. [2024-10-31 22:18:14,844 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:18:14,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 39 transitions. [2024-10-31 22:18:14,850 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:14,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 10 states and 13 transitions. [2024-10-31 22:18:14,857 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2024-10-31 22:18:14,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-10-31 22:18:14,858 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 13 transitions. [2024-10-31 22:18:14,858 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:14,859 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10 states and 13 transitions. [2024-10-31 22:18:14,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 13 transitions. [2024-10-31 22:18:14,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2024-10-31 22:18:14,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.3) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:14,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 13 transitions. [2024-10-31 22:18:14,912 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 13 transitions. [2024-10-31 22:18:14,913 INFO L425 stractBuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2024-10-31 22:18:14,913 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:18:14,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 13 transitions. [2024-10-31 22:18:14,916 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:14,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:14,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:14,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:14,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:18:14,917 INFO L745 eck$LassoCheckResult]: Stem: 87#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 88#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_#t~post2#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;havoc main_#t~nondet0#1;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 82#L15-3 assume !(main_~i~0#1 < 1048); 80#L15-4 havoc main_~i~0#1; 81#L19 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 89#L20 assume !main_#t~short5#1; 85#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;havoc main_#t~nondet6#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 86#L22-2 [2024-10-31 22:18:14,918 INFO L747 eck$LassoCheckResult]: Loop: 86#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 86#L22-2 [2024-10-31 22:18:14,921 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:14,921 INFO L85 PathProgramCache]: Analyzing trace with hash 1807952492, now seen corresponding path program 1 times [2024-10-31 22:18:14,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:14,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164167366] [2024-10-31 22:18:14,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:14,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:14,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:15,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:15,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:15,064 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164167366] [2024-10-31 22:18:15,064 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164167366] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:15,065 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:15,065 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:15,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286609771] [2024-10-31 22:18:15,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:15,069 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:15,070 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:15,070 INFO L85 PathProgramCache]: Analyzing trace with hash 68, now seen corresponding path program 1 times [2024-10-31 22:18:15,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:15,071 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674821972] [2024-10-31 22:18:15,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:15,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:15,077 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:15,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:15,081 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:15,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:15,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:15,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:15,108 INFO L87 Difference]: Start difference. First operand 10 states and 13 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:15,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:15,125 INFO L93 Difference]: Finished difference Result 11 states and 13 transitions. [2024-10-31 22:18:15,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 13 transitions. [2024-10-31 22:18:15,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:15,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 13 transitions. [2024-10-31 22:18:15,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-10-31 22:18:15,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-10-31 22:18:15,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 13 transitions. [2024-10-31 22:18:15,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:15,128 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11 states and 13 transitions. [2024-10-31 22:18:15,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 13 transitions. [2024-10-31 22:18:15,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2024-10-31 22:18:15,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.2) internal successors, (12), 9 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:15,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 12 transitions. [2024-10-31 22:18:15,131 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 12 transitions. [2024-10-31 22:18:15,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:15,132 INFO L425 stractBuchiCegarLoop]: Abstraction has 10 states and 12 transitions. [2024-10-31 22:18:15,132 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:18:15,133 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 12 transitions. [2024-10-31 22:18:15,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:15,133 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:15,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:15,134 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:15,134 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:18:15,134 INFO L745 eck$LassoCheckResult]: Stem: 114#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 115#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_#t~post2#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;havoc main_#t~nondet0#1;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 109#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 110#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 111#L15-3 assume !(main_~i~0#1 < 1048); 107#L15-4 havoc main_~i~0#1; 108#L19 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 116#L20 assume !main_#t~short5#1; 112#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;havoc main_#t~nondet6#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 113#L22-2 [2024-10-31 22:18:15,135 INFO L747 eck$LassoCheckResult]: Loop: 113#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 113#L22-2 [2024-10-31 22:18:15,135 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:15,136 INFO L85 PathProgramCache]: Analyzing trace with hash -369324246, now seen corresponding path program 1 times [2024-10-31 22:18:15,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:15,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648548661] [2024-10-31 22:18:15,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:15,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:15,253 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:15,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:15,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648548661] [2024-10-31 22:18:15,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1648548661] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:18:15,255 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1300677034] [2024-10-31 22:18:15,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,255 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:18:15,256 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:15,258 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:18:15,260 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-10-31 22:18:15,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:15,321 INFO L255 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:18:15,322 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:18:15,340 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-10-31 22:18:15,340 INFO L307 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-10-31 22:18:15,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1300677034] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:15,342 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-10-31 22:18:15,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [4] total 5 [2024-10-31 22:18:15,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600209972] [2024-10-31 22:18:15,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:15,343 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:15,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:15,345 INFO L85 PathProgramCache]: Analyzing trace with hash 68, now seen corresponding path program 2 times [2024-10-31 22:18:15,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:15,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014245607] [2024-10-31 22:18:15,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:15,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:15,355 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:15,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:15,361 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:15,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:15,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:15,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:18:15,389 INFO L87 Difference]: Start difference. First operand 10 states and 12 transitions. cyclomatic complexity: 4 Second operand has 3 states, 2 states have (on average 4.5) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:15,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:15,405 INFO L93 Difference]: Finished difference Result 11 states and 12 transitions. [2024-10-31 22:18:15,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 12 transitions. [2024-10-31 22:18:15,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:15,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 10 states and 11 transitions. [2024-10-31 22:18:15,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-10-31 22:18:15,408 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-10-31 22:18:15,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 11 transitions. [2024-10-31 22:18:15,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:15,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10 states and 11 transitions. [2024-10-31 22:18:15,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 11 transitions. [2024-10-31 22:18:15,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2024-10-31 22:18:15,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.1) internal successors, (11), 9 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:15,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 11 transitions. [2024-10-31 22:18:15,413 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 11 transitions. [2024-10-31 22:18:15,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:15,415 INFO L425 stractBuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2024-10-31 22:18:15,416 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:18:15,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 11 transitions. [2024-10-31 22:18:15,417 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:15,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:15,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:15,419 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:15,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:18:15,420 INFO L745 eck$LassoCheckResult]: Stem: 167#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 168#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_#t~post2#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;havoc main_#t~nondet0#1;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 162#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 163#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 164#L15-3 assume !(main_~i~0#1 < 1048); 160#L15-4 havoc main_~i~0#1; 161#L19 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 169#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 165#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;havoc main_#t~nondet6#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 166#L22-2 [2024-10-31 22:18:15,420 INFO L747 eck$LassoCheckResult]: Loop: 166#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 166#L22-2 [2024-10-31 22:18:15,421 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:15,421 INFO L85 PathProgramCache]: Analyzing trace with hash -369324308, now seen corresponding path program 1 times [2024-10-31 22:18:15,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:15,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517581644] [2024-10-31 22:18:15,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:15,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:15,544 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:15,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:15,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517581644] [2024-10-31 22:18:15,545 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517581644] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:18:15,545 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1474811816] [2024-10-31 22:18:15,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,546 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:18:15,546 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:15,549 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:18:15,553 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-10-31 22:18:15,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:15,623 INFO L255 TraceCheckSpWp]: Trace formula consists of 50 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-10-31 22:18:15,625 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:18:15,648 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:15,648 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:18:15,690 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:15,693 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1474811816] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:18:15,693 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:18:15,693 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2024-10-31 22:18:15,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947520694] [2024-10-31 22:18:15,694 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:18:15,694 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:15,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:15,695 INFO L85 PathProgramCache]: Analyzing trace with hash 68, now seen corresponding path program 3 times [2024-10-31 22:18:15,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:15,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981669667] [2024-10-31 22:18:15,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:15,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:15,701 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:15,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:15,705 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:15,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:15,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-10-31 22:18:15,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2024-10-31 22:18:15,730 INFO L87 Difference]: Start difference. First operand 10 states and 11 transitions. cyclomatic complexity: 3 Second operand has 7 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 7 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:15,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:15,770 INFO L93 Difference]: Finished difference Result 16 states and 17 transitions. [2024-10-31 22:18:15,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 17 transitions. [2024-10-31 22:18:15,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:15,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 16 states and 17 transitions. [2024-10-31 22:18:15,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-10-31 22:18:15,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-10-31 22:18:15,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 17 transitions. [2024-10-31 22:18:15,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:15,772 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16 states and 17 transitions. [2024-10-31 22:18:15,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 17 transitions. [2024-10-31 22:18:15,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2024-10-31 22:18:15,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.0625) internal successors, (17), 15 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:15,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 17 transitions. [2024-10-31 22:18:15,775 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 17 transitions. [2024-10-31 22:18:15,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-10-31 22:18:15,776 INFO L425 stractBuchiCegarLoop]: Abstraction has 16 states and 17 transitions. [2024-10-31 22:18:15,777 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:18:15,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 17 transitions. [2024-10-31 22:18:15,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:15,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:15,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:15,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:15,779 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:18:15,779 INFO L745 eck$LassoCheckResult]: Stem: 252#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_#t~post2#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;havoc main_#t~nondet0#1;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 246#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 247#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 248#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 249#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 259#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 258#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 257#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 256#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 255#L15-3 assume !(main_~i~0#1 < 1048); 244#L15-4 havoc main_~i~0#1; 245#L19 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 254#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 250#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;havoc main_#t~nondet6#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 251#L22-2 [2024-10-31 22:18:15,779 INFO L747 eck$LassoCheckResult]: Loop: 251#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 251#L22-2 [2024-10-31 22:18:15,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:15,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1716187174, now seen corresponding path program 2 times [2024-10-31 22:18:15,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:15,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930088551] [2024-10-31 22:18:15,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:15,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:15,961 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:15,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:15,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930088551] [2024-10-31 22:18:15,964 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930088551] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:18:15,964 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [401557034] [2024-10-31 22:18:15,964 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-10-31 22:18:15,965 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:18:15,965 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:15,968 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:18:15,970 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-10-31 22:18:16,065 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-10-31 22:18:16,065 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:18:16,068 INFO L255 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-10-31 22:18:16,072 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:18:16,126 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:16,127 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:18:16,259 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:16,259 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [401557034] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:18:16,259 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:18:16,259 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2024-10-31 22:18:16,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527573416] [2024-10-31 22:18:16,260 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:18:16,260 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:16,265 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:16,265 INFO L85 PathProgramCache]: Analyzing trace with hash 68, now seen corresponding path program 4 times [2024-10-31 22:18:16,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:16,266 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819915678] [2024-10-31 22:18:16,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:16,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:16,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:16,272 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:16,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:16,279 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:16,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:16,314 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-10-31 22:18:16,314 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2024-10-31 22:18:16,315 INFO L87 Difference]: Start difference. First operand 16 states and 17 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 2.1538461538461537) internal successors, (28), 13 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:16,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:16,392 INFO L93 Difference]: Finished difference Result 28 states and 29 transitions. [2024-10-31 22:18:16,392 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28 states and 29 transitions. [2024-10-31 22:18:16,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:16,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28 states to 28 states and 29 transitions. [2024-10-31 22:18:16,394 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-10-31 22:18:16,398 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-10-31 22:18:16,398 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 29 transitions. [2024-10-31 22:18:16,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:16,399 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 29 transitions. [2024-10-31 22:18:16,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 29 transitions. [2024-10-31 22:18:16,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2024-10-31 22:18:16,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 27 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:16,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 29 transitions. [2024-10-31 22:18:16,404 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 29 transitions. [2024-10-31 22:18:16,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-10-31 22:18:16,405 INFO L425 stractBuchiCegarLoop]: Abstraction has 28 states and 29 transitions. [2024-10-31 22:18:16,405 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:18:16,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 29 transitions. [2024-10-31 22:18:16,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:16,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:16,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:16,407 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:16,407 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:18:16,407 INFO L745 eck$LassoCheckResult]: Stem: 396#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_#t~post2#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;havoc main_#t~nondet0#1;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 392#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 393#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 394#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 395#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 399#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 415#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 414#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 413#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 412#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 411#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 410#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 409#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 408#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 407#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 406#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 405#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 404#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 403#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 402#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 401#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 400#L15-3 assume !(main_~i~0#1 < 1048); 388#L15-4 havoc main_~i~0#1; 389#L19 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 398#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 390#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;havoc main_#t~nondet6#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 391#L22-2 [2024-10-31 22:18:16,408 INFO L747 eck$LassoCheckResult]: Loop: 391#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 391#L22-2 [2024-10-31 22:18:16,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:16,412 INFO L85 PathProgramCache]: Analyzing trace with hash 1328175130, now seen corresponding path program 3 times [2024-10-31 22:18:16,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:16,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753678543] [2024-10-31 22:18:16,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:16,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:16,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:16,947 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:16,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:16,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753678543] [2024-10-31 22:18:16,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753678543] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:18:16,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1919422701] [2024-10-31 22:18:16,948 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-31 22:18:16,948 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:18:16,949 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:16,953 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:18:16,955 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-10-31 22:18:17,113 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-10-31 22:18:17,113 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:18:17,115 INFO L255 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-10-31 22:18:17,118 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:18:17,214 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:17,214 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:18:17,605 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:17,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1919422701] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:18:17,606 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:18:17,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2024-10-31 22:18:17,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [828150294] [2024-10-31 22:18:17,607 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:18:17,607 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:17,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:17,608 INFO L85 PathProgramCache]: Analyzing trace with hash 68, now seen corresponding path program 5 times [2024-10-31 22:18:17,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:17,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718699337] [2024-10-31 22:18:17,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:17,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:17,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:17,614 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:17,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:17,618 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:17,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:17,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-10-31 22:18:17,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2024-10-31 22:18:17,644 INFO L87 Difference]: Start difference. First operand 28 states and 29 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 2.08) internal successors, (52), 25 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:17,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:17,813 INFO L93 Difference]: Finished difference Result 52 states and 53 transitions. [2024-10-31 22:18:17,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 53 transitions. [2024-10-31 22:18:17,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:17,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 52 states and 53 transitions. [2024-10-31 22:18:17,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-10-31 22:18:17,820 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-10-31 22:18:17,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 53 transitions. [2024-10-31 22:18:17,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:17,821 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 53 transitions. [2024-10-31 22:18:17,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 53 transitions. [2024-10-31 22:18:17,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2024-10-31 22:18:17,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 51 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:17,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 53 transitions. [2024-10-31 22:18:17,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 53 transitions. [2024-10-31 22:18:17,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-10-31 22:18:17,827 INFO L425 stractBuchiCegarLoop]: Abstraction has 52 states and 53 transitions. [2024-10-31 22:18:17,827 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:18:17,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 53 transitions. [2024-10-31 22:18:17,829 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:17,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:17,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:17,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:17,835 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:18:17,835 INFO L745 eck$LassoCheckResult]: Stem: 660#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 661#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_#t~post2#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;havoc main_#t~nondet0#1;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 654#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 655#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 656#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 657#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 663#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 703#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 702#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 701#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 700#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 699#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 698#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 697#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 696#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 695#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 694#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 693#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 692#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 691#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 690#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 689#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 688#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 687#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 686#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 685#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 684#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 683#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 682#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 681#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 680#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 679#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 678#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 677#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 676#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 675#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 674#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 673#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 672#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 671#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 670#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 669#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 668#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 667#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 666#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 665#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 664#L15-3 assume !(main_~i~0#1 < 1048); 652#L15-4 havoc main_~i~0#1; 653#L19 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 662#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 658#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;havoc main_#t~nondet6#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 659#L22-2 [2024-10-31 22:18:17,835 INFO L747 eck$LassoCheckResult]: Loop: 659#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 659#L22-2 [2024-10-31 22:18:17,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:17,836 INFO L85 PathProgramCache]: Analyzing trace with hash 1458388482, now seen corresponding path program 4 times [2024-10-31 22:18:17,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:17,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966810899] [2024-10-31 22:18:17,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:17,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:17,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:18,791 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:18,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:18,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966810899] [2024-10-31 22:18:18,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1966810899] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:18:18,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [374091241] [2024-10-31 22:18:18,792 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-10-31 22:18:18,792 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:18:18,793 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:18,796 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:18:18,797 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-10-31 22:18:18,926 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-10-31 22:18:18,927 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:18:18,929 INFO L255 TraceCheckSpWp]: Trace formula consists of 281 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-10-31 22:18:18,932 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:18:19,074 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:19,074 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:18:20,140 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:20,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [374091241] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:18:20,141 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:18:20,141 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 49 [2024-10-31 22:18:20,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403913476] [2024-10-31 22:18:20,142 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:18:20,142 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:20,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:20,143 INFO L85 PathProgramCache]: Analyzing trace with hash 68, now seen corresponding path program 6 times [2024-10-31 22:18:20,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:20,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002005325] [2024-10-31 22:18:20,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:20,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:20,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:20,150 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:20,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:20,152 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:20,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:20,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2024-10-31 22:18:20,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2024-10-31 22:18:20,170 INFO L87 Difference]: Start difference. First operand 52 states and 53 transitions. cyclomatic complexity: 3 Second operand has 49 states, 49 states have (on average 2.0408163265306123) internal successors, (100), 49 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:20,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:20,417 INFO L93 Difference]: Finished difference Result 100 states and 101 transitions. [2024-10-31 22:18:20,417 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 101 transitions. [2024-10-31 22:18:20,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:20,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 100 states and 101 transitions. [2024-10-31 22:18:20,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-10-31 22:18:20,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-10-31 22:18:20,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 101 transitions. [2024-10-31 22:18:20,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:20,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 101 transitions. [2024-10-31 22:18:20,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 101 transitions. [2024-10-31 22:18:20,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 100. [2024-10-31 22:18:20,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.01) internal successors, (101), 99 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:20,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 101 transitions. [2024-10-31 22:18:20,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 101 transitions. [2024-10-31 22:18:20,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-10-31 22:18:20,432 INFO L425 stractBuchiCegarLoop]: Abstraction has 100 states and 101 transitions. [2024-10-31 22:18:20,432 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:18:20,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 101 transitions. [2024-10-31 22:18:20,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:18:20,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:20,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:20,437 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:20,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:18:20,439 INFO L745 eck$LassoCheckResult]: Stem: 1164#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1165#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_#t~post2#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;havoc main_#t~nondet0#1;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 1158#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1159#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1160#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1161#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1167#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1255#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1254#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1253#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1252#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1251#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1250#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1249#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1248#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1247#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1246#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1245#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1244#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1243#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1242#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1241#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1240#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1239#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1238#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1237#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1236#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1235#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1234#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1233#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1232#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1231#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1230#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1229#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1228#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1227#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1226#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1225#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1224#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1223#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1222#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1221#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1220#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1219#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1218#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1217#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1216#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1215#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1214#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1213#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1212#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1211#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1210#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1209#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1208#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1207#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1206#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1205#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1204#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1203#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1202#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1201#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1200#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1199#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1198#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1197#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1196#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1195#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1194#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1193#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1192#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1191#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1190#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1189#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1188#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1187#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1186#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1185#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1184#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1183#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1182#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1181#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1180#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1179#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1178#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1177#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1176#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1175#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1174#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1173#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1172#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1171#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1170#L15-3 assume !!(main_~i~0#1 < 1048);havoc main_#t~nondet1#1;call write~int#0(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1169#L15-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1168#L15-3 assume !(main_~i~0#1 < 1048); 1156#L15-4 havoc main_~i~0#1; 1157#L19 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 1166#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int#0(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 1162#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;havoc main_#t~nondet6#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 1163#L22-2 [2024-10-31 22:18:20,439 INFO L747 eck$LassoCheckResult]: Loop: 1163#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 1163#L22-2 [2024-10-31 22:18:20,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:20,440 INFO L85 PathProgramCache]: Analyzing trace with hash 546267602, now seen corresponding path program 5 times [2024-10-31 22:18:20,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:20,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340589159] [2024-10-31 22:18:20,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:20,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:20,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:23,462 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:23,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:23,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340589159] [2024-10-31 22:18:23,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340589159] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:18:23,464 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [27833031] [2024-10-31 22:18:23,464 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-31 22:18:23,464 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:18:23,464 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:23,470 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:18:23,473 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9f76eb7-8e99-4e4e-9beb-99bdb12f044d/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-10-31 22:18:40,551 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-10-31 22:18:40,551 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:18:40,574 INFO L255 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 48 conjuncts are in the unsatisfiable core [2024-10-31 22:18:40,580 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:18:40,841 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:40,841 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:18:44,876 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:44,877 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [27833031] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:18:44,877 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:18:44,878 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 97 [2024-10-31 22:18:44,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1472666064] [2024-10-31 22:18:44,878 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:18:44,880 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:44,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:44,882 INFO L85 PathProgramCache]: Analyzing trace with hash 68, now seen corresponding path program 7 times [2024-10-31 22:18:44,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:44,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153955182] [2024-10-31 22:18:44,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:44,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:44,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:44,888 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:44,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:44,890 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:44,907 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:44,909 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2024-10-31 22:18:44,912 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2024-10-31 22:18:44,913 INFO L87 Difference]: Start difference. First operand 100 states and 101 transitions. cyclomatic complexity: 3 Second operand has 97 states, 97 states have (on average 2.020618556701031) internal successors, (196), 97 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)