./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:03:59,084 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:03:59,211 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-64bit-Automizer_Default.epf [2024-10-31 22:03:59,217 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:03:59,217 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:03:59,259 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:03:59,260 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:03:59,261 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:03:59,262 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:03:59,264 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:03:59,265 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:03:59,265 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:03:59,266 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:03:59,266 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:03:59,269 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:03:59,269 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:03:59,270 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:03:59,270 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:03:59,270 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:03:59,271 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:03:59,271 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:03:59,277 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:03:59,278 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:03:59,278 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:03:59,278 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:03:59,279 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:03:59,279 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:03:59,280 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:03:59,281 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:03:59,282 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:03:59,282 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:03:59,283 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:03:59,283 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:03:59,284 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:03:59,285 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:03:59,286 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:03:59,286 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 [2024-10-31 22:03:59,623 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:03:59,676 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:03:59,681 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:03:59,683 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:03:59,683 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:03:59,685 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c Unable to find full path for "g++" [2024-10-31 22:04:01,801 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:04:02,063 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:04:02,064 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2024-10-31 22:04:02,075 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/data/21c36f07f/1f45cc3008d148c1b23612aeb51689ac/FLAGa80a84aee [2024-10-31 22:04:02,406 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/data/21c36f07f/1f45cc3008d148c1b23612aeb51689ac [2024-10-31 22:04:02,409 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:04:02,413 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:04:02,415 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:04:02,416 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:04:02,423 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:04:02,424 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,428 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@51100c0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02, skipping insertion in model container [2024-10-31 22:04:02,429 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,455 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:04:02,670 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:04:02,676 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:04:02,689 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:04:02,705 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:04:02,706 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02 WrapperNode [2024-10-31 22:04:02,706 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:04:02,707 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:04:02,707 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:04:02,708 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:04:02,716 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,721 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,740 INFO L138 Inliner]: procedures = 4, calls = 2, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 19 [2024-10-31 22:04:02,743 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:04:02,745 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:04:02,745 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:04:02,749 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:04:02,767 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,771 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,772 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,784 INFO L175 MemorySlicer]: No memory access in input program. [2024-10-31 22:04:02,785 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,785 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,789 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,797 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,798 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,799 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,801 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:04:02,806 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:04:02,806 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:04:02,806 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:04:02,807 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (1/1) ... [2024-10-31 22:04:02,827 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:02,841 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:02,856 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:02,862 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:04:02,897 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:04:02,897 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:04:02,992 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:04:02,995 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:04:03,108 INFO L? ?]: Removed 4 outVars from TransFormulas that were not future-live. [2024-10-31 22:04:03,108 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:04:03,123 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:04:03,127 INFO L316 CfgBuilder]: Removed 1 assume(true) statements. [2024-10-31 22:04:03,127 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:04:03 BoogieIcfgContainer [2024-10-31 22:04:03,127 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:04:03,128 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:04:03,129 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:04:03,133 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:04:03,134 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:04:03,134 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:04:02" (1/3) ... [2024-10-31 22:04:03,136 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41fe9198 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:04:03, skipping insertion in model container [2024-10-31 22:04:03,137 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:04:03,138 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:02" (2/3) ... [2024-10-31 22:04:03,139 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41fe9198 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:04:03, skipping insertion in model container [2024-10-31 22:04:03,139 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:04:03,140 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:04:03" (3/3) ... [2024-10-31 22:04:03,141 INFO L332 chiAutomizerObserver]: Analyzing ICFG NarrowKonv.c [2024-10-31 22:04:03,219 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:04:03,220 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:04:03,220 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:04:03,220 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:04:03,222 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:04:03,222 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:04:03,224 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:04:03,224 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:04:03,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:03,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-10-31 22:04:03,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:03,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:03,264 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-31 22:04:03,264 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:03,265 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:04:03,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:03,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-10-31 22:04:03,268 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:03,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:03,269 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-31 22:04:03,269 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:03,277 INFO L745 eck$LassoCheckResult]: Stem: 6#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3#L12-1true [2024-10-31 22:04:03,278 INFO L747 eck$LassoCheckResult]: Loop: 3#L12-1true assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9#L12true assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3#L12-1true [2024-10-31 22:04:03,285 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:03,285 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-10-31 22:04:03,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:03,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590986587] [2024-10-31 22:04:03,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:03,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:03,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,402 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:03,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,424 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:03,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:03,428 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 1 times [2024-10-31 22:04:03,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:03,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625633127] [2024-10-31 22:04:03,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:03,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:03,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,445 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:03,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,453 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:03,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:03,457 INFO L85 PathProgramCache]: Analyzing trace with hash 925806, now seen corresponding path program 1 times [2024-10-31 22:04:03,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:03,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334396472] [2024-10-31 22:04:03,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:03,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:03,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:03,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:03,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:03,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334396472] [2024-10-31 22:04:03,599 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334396472] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:03,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:03,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:03,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164257479] [2024-10-31 22:04:03,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:03,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:03,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:03,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:03,718 INFO L87 Difference]: Start difference. First operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:03,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:03,779 INFO L93 Difference]: Finished difference Result 12 states and 16 transitions. [2024-10-31 22:04:03,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12 states and 16 transitions. [2024-10-31 22:04:03,782 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-10-31 22:04:03,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12 states to 8 states and 11 transitions. [2024-10-31 22:04:03,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-10-31 22:04:03,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-10-31 22:04:03,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 11 transitions. [2024-10-31 22:04:03,788 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:03,789 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2024-10-31 22:04:03,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 11 transitions. [2024-10-31 22:04:03,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 8. [2024-10-31 22:04:03,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.375) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:03,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 11 transitions. [2024-10-31 22:04:03,824 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2024-10-31 22:04:03,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:03,833 INFO L425 stractBuchiCegarLoop]: Abstraction has 8 states and 11 transitions. [2024-10-31 22:04:03,834 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:04:03,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 11 transitions. [2024-10-31 22:04:03,835 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-10-31 22:04:03,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:03,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:03,837 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-31 22:04:03,837 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:04:03,838 INFO L745 eck$LassoCheckResult]: Stem: 35#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 36#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 37#L12-1 [2024-10-31 22:04:03,838 INFO L747 eck$LassoCheckResult]: Loop: 37#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 38#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 39#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 37#L12-1 [2024-10-31 22:04:03,840 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:03,840 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2024-10-31 22:04:03,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:03,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67096687] [2024-10-31 22:04:03,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:03,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:03,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,853 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:03,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,858 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:03,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:03,859 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 1 times [2024-10-31 22:04:03,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:03,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486394699] [2024-10-31 22:04:03,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:03,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:03,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,882 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:03,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,894 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:03,895 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:03,895 INFO L85 PathProgramCache]: Analyzing trace with hash 28699757, now seen corresponding path program 1 times [2024-10-31 22:04:03,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:03,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492642346] [2024-10-31 22:04:03,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:03,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:03,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,910 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:03,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:03,917 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:04,008 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:04,009 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:04,010 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:04,010 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:04,010 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-31 22:04:04,010 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,010 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:04,011 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:04,011 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2024-10-31 22:04:04,011 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:04,011 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:04,034 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:04,049 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:04,058 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:04,206 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:04,207 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-31 22:04:04,211 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,211 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:04,214 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:04,216 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-31 22:04:04,219 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:04,219 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:04,249 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:04:04,250 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:04:04,277 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:04,277 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,277 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:04,279 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:04,282 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-31 22:04:04,284 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:04,285 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:04,311 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:04:04,311 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:04:04,331 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:04,331 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,331 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:04,333 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:04,336 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-31 22:04:04,337 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:04,338 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:04,376 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:04,376 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,377 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:04,379 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:04,381 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-31 22:04:04,382 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-31 22:04:04,382 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:04,447 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-31 22:04:04,450 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-10-31 22:04:04,450 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:04,450 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:04,450 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:04,450 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:04,451 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-31 22:04:04,451 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,451 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:04,451 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:04,451 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2024-10-31 22:04:04,451 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:04,451 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:04,453 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:04,459 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:04,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:04,564 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:04,568 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-31 22:04:04,570 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,570 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:04,572 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:04,574 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-10-31 22:04:04,575 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:04,590 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:04,591 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:04,591 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:04,591 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:04,597 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:04:04,598 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:04:04,606 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:04:04,624 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-10-31 22:04:04,625 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,625 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:04,627 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:04,629 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-10-31 22:04:04,630 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:04,645 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:04,645 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:04,645 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:04,645 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:04,649 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:04:04,649 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:04:04,660 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:04:04,678 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-10-31 22:04:04,679 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,679 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:04,681 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:04,682 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-10-31 22:04:04,684 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:04,698 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:04,699 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:04:04,699 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:04,700 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:04,700 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:04,703 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:04:04,703 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:04:04,709 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-31 22:04:04,713 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-31 22:04:04,713 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-31 22:04:04,715 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:04,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:04,723 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:04,725 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-10-31 22:04:04,726 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-31 22:04:04,726 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-31 22:04:04,727 INFO L474 LassoAnalysis]: Proved termination. [2024-10-31 22:04:04,727 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2024-10-31 22:04:04,744 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:04,748 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-31 22:04:04,797 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:04,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:04,807 INFO L255 TraceCheckSpWp]: Trace formula consists of 5 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:04:04,808 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:04,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:04,824 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-10-31 22:04:04,825 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:04,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:04,870 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-10-31 22:04:04,872 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:04,924 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5. Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 11 states and 15 transitions. Complement of second has 5 states. [2024-10-31 22:04:04,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:04:04,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:04,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 5 transitions. [2024-10-31 22:04:04,929 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 3 letters. [2024-10-31 22:04:04,929 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:04,929 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 5 letters. Loop has 3 letters. [2024-10-31 22:04:04,929 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:04,930 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 6 letters. [2024-10-31 22:04:04,930 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:04,930 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 15 transitions. [2024-10-31 22:04:04,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-10-31 22:04:04,931 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 15 transitions. [2024-10-31 22:04:04,931 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2024-10-31 22:04:04,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-10-31 22:04:04,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 15 transitions. [2024-10-31 22:04:04,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:04,932 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2024-10-31 22:04:04,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 15 transitions. [2024-10-31 22:04:04,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2024-10-31 22:04:04,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:04,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 15 transitions. [2024-10-31 22:04:04,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2024-10-31 22:04:04,935 INFO L425 stractBuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2024-10-31 22:04:04,936 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:04:04,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 15 transitions. [2024-10-31 22:04:04,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-10-31 22:04:04,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:04,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:04,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2024-10-31 22:04:04,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:04,938 INFO L745 eck$LassoCheckResult]: Stem: 93#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 94#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 95#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 90#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 91#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 86#L12-1 [2024-10-31 22:04:04,938 INFO L747 eck$LassoCheckResult]: Loop: 86#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 87#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 86#L12-1 [2024-10-31 22:04:04,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:04,939 INFO L85 PathProgramCache]: Analyzing trace with hash 28699755, now seen corresponding path program 1 times [2024-10-31 22:04:04,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:04,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996447404] [2024-10-31 22:04:04,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:04,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:04,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:04,946 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:04,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:04,951 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:04,952 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:04,952 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 2 times [2024-10-31 22:04:04,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:04,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478654071] [2024-10-31 22:04:04,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:04,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:04,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:04,956 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:04,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:04,959 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:04,960 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:04,960 INFO L85 PathProgramCache]: Analyzing trace with hash 1810661142, now seen corresponding path program 1 times [2024-10-31 22:04:04,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:04,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746686418] [2024-10-31 22:04:04,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:04,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:04,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:05,029 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:05,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:05,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746686418] [2024-10-31 22:04:05,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746686418] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:04:05,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [301036073] [2024-10-31 22:04:05,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:05,031 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:04:05,032 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:05,034 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:04:05,035 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-10-31 22:04:05,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:05,075 INFO L255 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-31 22:04:05,077 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:05,147 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:05,148 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:04:05,196 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:05,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [301036073] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:04:05,196 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:04:05,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2024-10-31 22:04:05,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034798358] [2024-10-31 22:04:05,197 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:04:05,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:05,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-10-31 22:04:05,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-10-31 22:04:05,232 INFO L87 Difference]: Start difference. First operand 11 states and 15 transitions. cyclomatic complexity: 6 Second operand has 7 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 7 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:05,357 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-10-31 22:04:05,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:05,412 INFO L93 Difference]: Finished difference Result 23 states and 28 transitions. [2024-10-31 22:04:05,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 28 transitions. [2024-10-31 22:04:05,413 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-10-31 22:04:05,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 23 states and 28 transitions. [2024-10-31 22:04:05,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2024-10-31 22:04:05,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2024-10-31 22:04:05,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 28 transitions. [2024-10-31 22:04:05,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:05,414 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2024-10-31 22:04:05,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 28 transitions. [2024-10-31 22:04:05,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2024-10-31 22:04:05,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.2173913043478262) internal successors, (28), 22 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:05,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 28 transitions. [2024-10-31 22:04:05,421 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2024-10-31 22:04:05,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-10-31 22:04:05,423 INFO L425 stractBuchiCegarLoop]: Abstraction has 23 states and 28 transitions. [2024-10-31 22:04:05,423 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:04:05,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 28 transitions. [2024-10-31 22:04:05,424 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-10-31 22:04:05,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:05,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:05,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1] [2024-10-31 22:04:05,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:04:05,425 INFO L745 eck$LassoCheckResult]: Stem: 178#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 174#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 181#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 170#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 171#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 176#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 191#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 184#L12-1 [2024-10-31 22:04:05,425 INFO L747 eck$LassoCheckResult]: Loop: 184#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 189#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 182#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 184#L12-1 [2024-10-31 22:04:05,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:05,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1805445589, now seen corresponding path program 1 times [2024-10-31 22:04:05,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:05,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584737340] [2024-10-31 22:04:05,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:05,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:05,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:05,444 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:05,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:05,461 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:05,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:05,462 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 2 times [2024-10-31 22:04:05,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:05,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209676456] [2024-10-31 22:04:05,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:05,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:05,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:05,470 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:05,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:05,479 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:05,479 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:05,480 INFO L85 PathProgramCache]: Analyzing trace with hash -154083067, now seen corresponding path program 2 times [2024-10-31 22:04:05,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:05,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246135741] [2024-10-31 22:04:05,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:05,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:05,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:05,493 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:05,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:05,501 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:05,549 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:05,549 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:05,550 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:05,550 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:05,550 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-31 22:04:05,550 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:05,550 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:05,551 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:05,551 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2024-10-31 22:04:05,551 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:05,551 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:05,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:05,559 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:05,565 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:05,649 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:05,649 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-31 22:04:05,649 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:05,649 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:05,651 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:05,653 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-10-31 22:04:05,654 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:05,654 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:05,679 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:04:05,680 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:04:05,698 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-10-31 22:04:05,699 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:05,699 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:05,700 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:05,701 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-10-31 22:04:05,703 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:05,704 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:05,728 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:04:05,729 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:04:05,758 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:05,758 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:05,758 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:05,759 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:05,760 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-10-31 22:04:05,761 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:05,761 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:05,811 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:05,811 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:05,811 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:05,812 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:05,814 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-10-31 22:04:05,815 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-31 22:04:05,815 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:05,892 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-31 22:04:05,897 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:05,897 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:05,897 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:05,898 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:05,898 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:05,898 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-31 22:04:05,898 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:05,898 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:05,898 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:05,898 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2024-10-31 22:04:05,898 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:05,898 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:05,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:05,907 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:05,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:05,991 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:05,991 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-31 22:04:05,992 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:05,992 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:05,994 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:05,996 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-10-31 22:04:05,997 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:06,012 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:06,012 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:06,012 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:06,012 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:06,015 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:04:06,015 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:04:06,019 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:04:06,039 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-10-31 22:04:06,040 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:06,040 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:06,042 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:06,044 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-10-31 22:04:06,047 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:06,063 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:06,063 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:04:06,063 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:06,063 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:06,063 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:06,067 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:04:06,067 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:04:06,070 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-31 22:04:06,078 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-31 22:04:06,079 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-31 22:04:06,079 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:06,079 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:06,081 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:06,086 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-10-31 22:04:06,088 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-31 22:04:06,088 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-31 22:04:06,088 INFO L474 LassoAnalysis]: Proved termination. [2024-10-31 22:04:06,089 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2024-10-31 22:04:06,109 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-10-31 22:04:06,112 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-31 22:04:06,137 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:06,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:06,149 INFO L255 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:04:06,149 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:06,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:06,179 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-10-31 22:04:06,180 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:06,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:06,221 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-10-31 22:04:06,221 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:06,256 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 50 transitions. Complement of second has 5 states. [2024-10-31 22:04:06,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:04:06,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:06,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2024-10-31 22:04:06,259 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 3 letters. [2024-10-31 22:04:06,259 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:06,260 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2024-10-31 22:04:06,260 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:06,260 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 6 letters. [2024-10-31 22:04:06,260 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:06,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 50 transitions. [2024-10-31 22:04:06,266 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-10-31 22:04:06,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 38 states and 44 transitions. [2024-10-31 22:04:06,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-10-31 22:04:06,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2024-10-31 22:04:06,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 44 transitions. [2024-10-31 22:04:06,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:06,267 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38 states and 44 transitions. [2024-10-31 22:04:06,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 44 transitions. [2024-10-31 22:04:06,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 34. [2024-10-31 22:04:06,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.1764705882352942) internal successors, (40), 33 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:06,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 40 transitions. [2024-10-31 22:04:06,276 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 40 transitions. [2024-10-31 22:04:06,276 INFO L425 stractBuchiCegarLoop]: Abstraction has 34 states and 40 transitions. [2024-10-31 22:04:06,276 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:04:06,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 40 transitions. [2024-10-31 22:04:06,278 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-10-31 22:04:06,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:06,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:06,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 1, 1, 1] [2024-10-31 22:04:06,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:04:06,279 INFO L745 eck$LassoCheckResult]: Stem: 308#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 309#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 310#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 302#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 332#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 301#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 303#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 311#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 299#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 300#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 304#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 305#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 330#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 328#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 321#L12-1 [2024-10-31 22:04:06,279 INFO L747 eck$LassoCheckResult]: Loop: 321#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 326#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 319#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 321#L12-1 [2024-10-31 22:04:06,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:06,279 INFO L85 PathProgramCache]: Analyzing trace with hash 1972849857, now seen corresponding path program 3 times [2024-10-31 22:04:06,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:06,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634893490] [2024-10-31 22:04:06,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:06,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:06,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:06,299 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:06,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:06,315 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:06,322 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:06,322 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 3 times [2024-10-31 22:04:06,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:06,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500270125] [2024-10-31 22:04:06,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:06,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:06,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:06,328 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:06,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:06,335 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:06,336 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:06,337 INFO L85 PathProgramCache]: Analyzing trace with hash 837622447, now seen corresponding path program 4 times [2024-10-31 22:04:06,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:06,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269961298] [2024-10-31 22:04:06,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:06,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:06,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:06,354 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:06,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:06,373 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:06,432 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:06,432 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:06,433 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:06,433 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:06,433 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-31 22:04:06,433 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:06,433 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:06,433 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:06,433 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2024-10-31 22:04:06,433 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:06,434 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:06,435 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:06,439 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:06,460 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:06,521 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:06,522 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-31 22:04:06,522 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:06,522 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:06,524 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:06,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-10-31 22:04:06,527 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:06,527 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:06,551 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:04:06,552 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_5=1} Honda state: {v_rep~unnamed0~0~true_5=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:04:06,565 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:06,565 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:06,565 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:06,566 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:06,567 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-10-31 22:04:06,568 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:06,569 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:06,600 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-10-31 22:04:06,601 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:06,601 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:06,603 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:06,608 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-10-31 22:04:06,609 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-31 22:04:06,609 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:06,682 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-31 22:04:06,686 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-10-31 22:04:06,686 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:06,686 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:06,687 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:06,687 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:06,687 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-31 22:04:06,687 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:06,687 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:06,687 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:06,687 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2024-10-31 22:04:06,687 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:06,687 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:06,688 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:06,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:06,707 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:06,765 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:06,765 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-31 22:04:06,765 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:06,765 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:06,767 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:06,769 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-10-31 22:04:06,770 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:06,784 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:06,784 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:04:06,784 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:06,784 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:06,784 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:06,785 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:04:06,786 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:04:06,789 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-31 22:04:06,793 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-31 22:04:06,793 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2024-10-31 22:04:06,793 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:06,793 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:06,797 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:06,798 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-10-31 22:04:06,799 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-31 22:04:06,800 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-31 22:04:06,800 INFO L474 LassoAnalysis]: Proved termination. [2024-10-31 22:04:06,800 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~range~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2024-10-31 22:04:06,819 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-10-31 22:04:06,820 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-31 22:04:06,844 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:06,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:06,857 INFO L255 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:04:06,858 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:06,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:06,902 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-10-31 22:04:06,902 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:06,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:06,935 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-10-31 22:04:06,935 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:06,966 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2024-10-31 22:04:06,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:04:06,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:06,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2024-10-31 22:04:06,968 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2024-10-31 22:04:06,968 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:06,968 INFO L682 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2024-10-31 22:04:06,989 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:07,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:07,003 INFO L255 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:04:07,003 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:07,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:07,040 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-10-31 22:04:07,040 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:07,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:07,068 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2024-10-31 22:04:07,068 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:07,096 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2024-10-31 22:04:07,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:04:07,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:07,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2024-10-31 22:04:07,100 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2024-10-31 22:04:07,100 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:07,100 INFO L682 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2024-10-31 22:04:07,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:07,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:07,129 INFO L255 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:04:07,130 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:07,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:07,159 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-10-31 22:04:07,159 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:07,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:07,188 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-10-31 22:04:07,188 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:07,218 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 57 states and 69 transitions. Complement of second has 4 states. [2024-10-31 22:04:07,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:04:07,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:07,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 13 transitions. [2024-10-31 22:04:07,221 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 3 letters. [2024-10-31 22:04:07,222 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:07,222 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 17 letters. Loop has 3 letters. [2024-10-31 22:04:07,222 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:07,222 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 6 letters. [2024-10-31 22:04:07,223 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:07,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 69 transitions. [2024-10-31 22:04:07,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 12 [2024-10-31 22:04:07,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 47 states and 58 transitions. [2024-10-31 22:04:07,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-10-31 22:04:07,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2024-10-31 22:04:07,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 58 transitions. [2024-10-31 22:04:07,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:07,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 58 transitions. [2024-10-31 22:04:07,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 58 transitions. [2024-10-31 22:04:07,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 31. [2024-10-31 22:04:07,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.2903225806451613) internal successors, (40), 30 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:07,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 40 transitions. [2024-10-31 22:04:07,229 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 40 transitions. [2024-10-31 22:04:07,229 INFO L425 stractBuchiCegarLoop]: Abstraction has 31 states and 40 transitions. [2024-10-31 22:04:07,230 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:04:07,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 40 transitions. [2024-10-31 22:04:07,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 11 [2024-10-31 22:04:07,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:07,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:07,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 3, 2, 1, 1] [2024-10-31 22:04:07,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 1, 1] [2024-10-31 22:04:07,232 INFO L745 eck$LassoCheckResult]: Stem: 669#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 670#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 671#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 664#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 690#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 660#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 661#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 665#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 666#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 672#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 667#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 668#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 688#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 684#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 681#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 680#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 678#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 676#L12-1 [2024-10-31 22:04:07,232 INFO L747 eck$LassoCheckResult]: Loop: 676#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 677#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 686#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 683#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 685#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 682#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 676#L12-1 [2024-10-31 22:04:07,232 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:07,232 INFO L85 PathProgramCache]: Analyzing trace with hash 1031341869, now seen corresponding path program 5 times [2024-10-31 22:04:07,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:07,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189671534] [2024-10-31 22:04:07,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:07,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:07,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:07,356 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:07,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:07,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189671534] [2024-10-31 22:04:07,356 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [189671534] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:04:07,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2063678112] [2024-10-31 22:04:07,357 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-31 22:04:07,357 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:04:07,357 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:07,359 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:04:07,361 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-10-31 22:04:07,403 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2024-10-31 22:04:07,403 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:04:07,405 INFO L255 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-10-31 22:04:07,406 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:07,523 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:07,523 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:04:07,620 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:07,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2063678112] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:04:07,620 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:04:07,620 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2024-10-31 22:04:07,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863791092] [2024-10-31 22:04:07,621 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:04:07,621 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:07,621 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:07,621 INFO L85 PathProgramCache]: Analyzing trace with hash 1215871107, now seen corresponding path program 1 times [2024-10-31 22:04:07,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:07,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46380110] [2024-10-31 22:04:07,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:07,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:07,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:07,632 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:07,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:07,636 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:07,720 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:07,721 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:07,721 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:07,721 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:07,721 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-31 22:04:07,721 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:07,721 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:07,721 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:07,722 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2024-10-31 22:04:07,722 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:07,722 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:07,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:07,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:07,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:07,837 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:07,837 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-31 22:04:07,837 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:07,838 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:07,840 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:07,841 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-10-31 22:04:07,842 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:07,842 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:07,877 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2024-10-31 22:04:07,877 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:07,878 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:07,880 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:07,881 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-10-31 22:04:07,882 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-31 22:04:07,882 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:08,013 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-31 22:04:08,018 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:08,019 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:08,019 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:08,019 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:08,019 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:08,019 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-31 22:04:08,020 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:08,020 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:08,020 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:08,020 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2024-10-31 22:04:08,020 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:08,020 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:08,021 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:08,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:08,074 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:08,076 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:08,114 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:08,172 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:08,173 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-31 22:04:08,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:08,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:08,175 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:08,177 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-10-31 22:04:08,178 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:08,192 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:08,193 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:04:08,193 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:08,194 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:08,194 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:08,197 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:04:08,197 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:04:08,201 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-31 22:04:08,207 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-31 22:04:08,208 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2024-10-31 22:04:08,208 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:08,208 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:08,210 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:08,211 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-10-31 22:04:08,212 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-31 22:04:08,212 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-31 22:04:08,212 INFO L474 LassoAnalysis]: Proved termination. [2024-10-31 22:04:08,213 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1) = 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2024-10-31 22:04:08,230 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:08,231 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-31 22:04:08,246 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:08,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:08,259 INFO L255 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:04:08,259 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:08,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:08,289 INFO L255 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-10-31 22:04:08,290 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:08,342 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:08,342 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-10-31 22:04:08,343 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:08,374 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 72 states and 96 transitions. Complement of second has 6 states. [2024-10-31 22:04:08,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2024-10-31 22:04:08,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:08,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 15 transitions. [2024-10-31 22:04:08,376 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 15 transitions. Stem has 17 letters. Loop has 6 letters. [2024-10-31 22:04:08,376 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:08,376 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 15 transitions. Stem has 23 letters. Loop has 6 letters. [2024-10-31 22:04:08,376 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:08,376 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 15 transitions. Stem has 17 letters. Loop has 12 letters. [2024-10-31 22:04:08,377 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:08,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 96 transitions. [2024-10-31 22:04:08,378 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-10-31 22:04:08,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 55 states and 73 transitions. [2024-10-31 22:04:08,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2024-10-31 22:04:08,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2024-10-31 22:04:08,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 73 transitions. [2024-10-31 22:04:08,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:08,380 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55 states and 73 transitions. [2024-10-31 22:04:08,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 73 transitions. [2024-10-31 22:04:08,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 47. [2024-10-31 22:04:08,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.3404255319148937) internal successors, (63), 46 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:08,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 63 transitions. [2024-10-31 22:04:08,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 63 transitions. [2024-10-31 22:04:08,386 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:08,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-10-31 22:04:08,387 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=96, Unknown=0, NotChecked=0, Total=156 [2024-10-31 22:04:08,387 INFO L87 Difference]: Start difference. First operand 47 states and 63 transitions. Second operand has 13 states, 13 states have (on average 3.076923076923077) internal successors, (40), 13 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:08,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:08,513 INFO L93 Difference]: Finished difference Result 89 states and 105 transitions. [2024-10-31 22:04:08,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 105 transitions. [2024-10-31 22:04:08,515 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-10-31 22:04:08,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 75 states and 91 transitions. [2024-10-31 22:04:08,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2024-10-31 22:04:08,516 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2024-10-31 22:04:08,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 91 transitions. [2024-10-31 22:04:08,516 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:08,516 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75 states and 91 transitions. [2024-10-31 22:04:08,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 91 transitions. [2024-10-31 22:04:08,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 71. [2024-10-31 22:04:08,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.2253521126760563) internal successors, (87), 70 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:08,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 87 transitions. [2024-10-31 22:04:08,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 71 states and 87 transitions. [2024-10-31 22:04:08,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-10-31 22:04:08,524 INFO L425 stractBuchiCegarLoop]: Abstraction has 71 states and 87 transitions. [2024-10-31 22:04:08,524 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:04:08,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 87 transitions. [2024-10-31 22:04:08,525 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-10-31 22:04:08,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:08,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:08,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 9, 2, 1, 1] [2024-10-31 22:04:08,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:08,526 INFO L745 eck$LassoCheckResult]: Stem: 1109#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 1110#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 1111#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1144#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1142#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1117#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1158#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1156#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1155#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1154#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1153#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1152#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1151#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1150#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1149#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1148#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1145#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1141#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1139#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1138#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1137#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1135#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1115#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1102#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1103#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1165#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1164#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1162#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1136#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1121#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1120#L12 [2024-10-31 22:04:08,526 INFO L747 eck$LassoCheckResult]: Loop: 1120#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1119#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1120#L12 [2024-10-31 22:04:08,526 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:08,526 INFO L85 PathProgramCache]: Analyzing trace with hash -566648130, now seen corresponding path program 6 times [2024-10-31 22:04:08,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:08,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972889660] [2024-10-31 22:04:08,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:08,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:08,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:08,717 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-10-31 22:04:08,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:08,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972889660] [2024-10-31 22:04:08,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972889660] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:04:08,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2089979059] [2024-10-31 22:04:08,718 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-10-31 22:04:08,718 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:04:08,718 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:08,720 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:04:08,723 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-10-31 22:04:08,780 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2024-10-31 22:04:08,781 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:04:08,782 INFO L255 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-10-31 22:04:08,783 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:08,986 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-10-31 22:04:08,987 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:04:09,192 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-10-31 22:04:09,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2089979059] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:04:09,193 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:04:09,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 25 [2024-10-31 22:04:09,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1831357602] [2024-10-31 22:04:09,194 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:04:09,194 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:09,194 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:09,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 3 times [2024-10-31 22:04:09,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:09,195 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615411818] [2024-10-31 22:04:09,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:09,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:09,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:09,201 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:09,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:09,203 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:09,222 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:09,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-10-31 22:04:09,223 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=356, Unknown=0, NotChecked=0, Total=600 [2024-10-31 22:04:09,224 INFO L87 Difference]: Start difference. First operand 71 states and 87 transitions. cyclomatic complexity: 22 Second operand has 25 states, 25 states have (on average 3.04) internal successors, (76), 25 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:09,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:09,491 INFO L93 Difference]: Finished difference Result 151 states and 167 transitions. [2024-10-31 22:04:09,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 167 transitions. [2024-10-31 22:04:09,493 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-10-31 22:04:09,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 123 states and 139 transitions. [2024-10-31 22:04:09,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2024-10-31 22:04:09,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2024-10-31 22:04:09,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 139 transitions. [2024-10-31 22:04:09,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:09,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 139 transitions. [2024-10-31 22:04:09,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 139 transitions. [2024-10-31 22:04:09,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 119. [2024-10-31 22:04:09,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119 states, 119 states have (on average 1.134453781512605) internal successors, (135), 118 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:09,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 135 transitions. [2024-10-31 22:04:09,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 119 states and 135 transitions. [2024-10-31 22:04:09,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2024-10-31 22:04:09,502 INFO L425 stractBuchiCegarLoop]: Abstraction has 119 states and 135 transitions. [2024-10-31 22:04:09,502 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:04:09,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119 states and 135 transitions. [2024-10-31 22:04:09,505 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-10-31 22:04:09,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:09,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:09,507 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 23, 21, 2, 1, 1] [2024-10-31 22:04:09,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:09,510 INFO L745 eck$LassoCheckResult]: Stem: 1583#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 1584#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 1585#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1591#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1580#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1581#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1634#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1635#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1576#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1577#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1670#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1669#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1668#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1667#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1666#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1665#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1664#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1663#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1662#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1661#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1660#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1659#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1658#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1657#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1656#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1655#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1654#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1653#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1652#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1651#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1650#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1649#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1648#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1647#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1646#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1645#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1644#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1643#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1642#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1641#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1640#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1639#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1638#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1637#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1636#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1611#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1614#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1610#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1609#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1608#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1607#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1589#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1590#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1633#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1632#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1631#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1630#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1629#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1628#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1627#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1626#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1625#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1624#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1623#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1622#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1621#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1620#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1618#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1619#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1615#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1612#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1592#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1593#L12 [2024-10-31 22:04:09,510 INFO L747 eck$LassoCheckResult]: Loop: 1593#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1595#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1593#L12 [2024-10-31 22:04:09,511 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:09,511 INFO L85 PathProgramCache]: Analyzing trace with hash 1262893886, now seen corresponding path program 7 times [2024-10-31 22:04:09,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:09,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210626692] [2024-10-31 22:04:09,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:09,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:09,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:09,658 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-10-31 22:04:10,116 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2024-10-31 22:04:10,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:10,117 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210626692] [2024-10-31 22:04:10,117 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210626692] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:04:10,117 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1467481986] [2024-10-31 22:04:10,117 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-31 22:04:10,118 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:04:10,118 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:10,120 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:04:10,121 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-10-31 22:04:10,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:10,182 INFO L255 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-10-31 22:04:10,184 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:10,662 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2024-10-31 22:04:10,662 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:04:11,100 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2024-10-31 22:04:11,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1467481986] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:04:11,103 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:04:11,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 38 [2024-10-31 22:04:11,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502549619] [2024-10-31 22:04:11,103 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:04:11,104 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:11,104 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:11,104 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 4 times [2024-10-31 22:04:11,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:11,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152500722] [2024-10-31 22:04:11,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:11,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:11,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:11,109 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:11,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:11,112 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:11,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:11,131 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2024-10-31 22:04:11,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=545, Invalid=861, Unknown=0, NotChecked=0, Total=1406 [2024-10-31 22:04:11,133 INFO L87 Difference]: Start difference. First operand 119 states and 135 transitions. cyclomatic complexity: 22 Second operand has 38 states, 38 states have (on average 3.0526315789473686) internal successors, (116), 38 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:11,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:11,508 INFO L93 Difference]: Finished difference Result 220 states and 236 transitions. [2024-10-31 22:04:11,508 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 220 states and 236 transitions. [2024-10-31 22:04:11,511 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-10-31 22:04:11,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 220 states to 186 states and 202 transitions. [2024-10-31 22:04:11,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2024-10-31 22:04:11,516 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2024-10-31 22:04:11,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 202 transitions. [2024-10-31 22:04:11,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:11,517 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 202 transitions. [2024-10-31 22:04:11,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 202 transitions. [2024-10-31 22:04:11,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 182. [2024-10-31 22:04:11,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 182 states have (on average 1.0879120879120878) internal successors, (198), 181 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:11,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 198 transitions. [2024-10-31 22:04:11,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 182 states and 198 transitions. [2024-10-31 22:04:11,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2024-10-31 22:04:11,538 INFO L425 stractBuchiCegarLoop]: Abstraction has 182 states and 198 transitions. [2024-10-31 22:04:11,539 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:04:11,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182 states and 198 transitions. [2024-10-31 22:04:11,540 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-10-31 22:04:11,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:11,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:11,545 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [37, 36, 34, 2, 1, 1] [2024-10-31 22:04:11,548 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:11,549 INFO L745 eck$LassoCheckResult]: Stem: 2397#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 2398#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 2399#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2420#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2524#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2391#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2394#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2395#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2521#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2520#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2518#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2517#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2516#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2515#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2514#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2513#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2512#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2511#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2510#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2509#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2508#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2507#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2506#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2505#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2504#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2503#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2502#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2501#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2500#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2499#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2498#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2497#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2496#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2495#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2494#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2493#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2492#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2491#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2490#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2489#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2488#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2487#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2486#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2485#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2484#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2483#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2482#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2481#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2480#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2479#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2478#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2477#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2476#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2475#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2474#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2473#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2472#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2427#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2428#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2426#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2425#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2424#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2422#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2403#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2404#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2471#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2470#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2469#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2468#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2467#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2466#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2465#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2464#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2463#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2462#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2461#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2460#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2459#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2458#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2457#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2456#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2455#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2454#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2453#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2452#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2451#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2450#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2449#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2448#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2447#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2446#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2445#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2444#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2443#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2442#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2441#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2440#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2439#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2438#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2437#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2436#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2435#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2434#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2432#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2433#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2429#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2421#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2405#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2406#L12 [2024-10-31 22:04:11,549 INFO L747 eck$LassoCheckResult]: Loop: 2406#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2408#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2406#L12 [2024-10-31 22:04:11,553 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:11,553 INFO L85 PathProgramCache]: Analyzing trace with hash -1287581916, now seen corresponding path program 8 times [2024-10-31 22:04:11,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:11,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41640104] [2024-10-31 22:04:11,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:11,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:11,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:11,603 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:11,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:11,644 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:11,648 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:11,648 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 5 times [2024-10-31 22:04:11,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:11,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851225575] [2024-10-31 22:04:11,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:11,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:11,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:11,655 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:11,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:11,658 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:11,659 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:11,659 INFO L85 PathProgramCache]: Analyzing trace with hash -415639335, now seen corresponding path program 1 times [2024-10-31 22:04:11,659 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:11,659 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948874906] [2024-10-31 22:04:11,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:11,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:11,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:11,765 INFO L134 CoverageAnalysis]: Checked inductivity of 1999 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 1820 trivial. 0 not checked. [2024-10-31 22:04:11,765 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:11,766 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948874906] [2024-10-31 22:04:11,766 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948874906] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:11,766 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:11,766 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-10-31 22:04:11,766 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385461047] [2024-10-31 22:04:11,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:11,787 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:11,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:11,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:11,788 INFO L87 Difference]: Start difference. First operand 182 states and 198 transitions. cyclomatic complexity: 22 Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:11,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:11,809 INFO L93 Difference]: Finished difference Result 180 states and 192 transitions. [2024-10-31 22:04:11,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 180 states and 192 transitions. [2024-10-31 22:04:11,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:11,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 180 states to 132 states and 140 transitions. [2024-10-31 22:04:11,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2024-10-31 22:04:11,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2024-10-31 22:04:11,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 140 transitions. [2024-10-31 22:04:11,813 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:11,813 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132 states and 140 transitions. [2024-10-31 22:04:11,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 140 transitions. [2024-10-31 22:04:11,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 129. [2024-10-31 22:04:11,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 129 states have (on average 1.062015503875969) internal successors, (137), 128 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:11,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 137 transitions. [2024-10-31 22:04:11,818 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129 states and 137 transitions. [2024-10-31 22:04:11,818 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:11,819 INFO L425 stractBuchiCegarLoop]: Abstraction has 129 states and 137 transitions. [2024-10-31 22:04:11,819 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:04:11,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129 states and 137 transitions. [2024-10-31 22:04:11,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:11,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:11,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:11,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [38, 37, 34, 3, 1, 1, 1] [2024-10-31 22:04:11,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:11,822 INFO L745 eck$LassoCheckResult]: Stem: 2767#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 2768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 2769#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2772#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2773#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2784#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2785#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2765#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2761#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2762#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2888#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2887#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2886#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2885#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2884#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2883#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2882#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2881#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2880#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2879#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2878#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2877#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2876#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2875#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2874#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2873#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2872#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2871#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2870#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2869#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2868#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2867#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2866#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2865#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2864#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2863#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2862#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2861#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2860#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2859#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2858#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2857#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2856#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2855#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2854#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2853#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2852#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2851#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2850#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2849#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2848#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2847#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2846#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2845#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2844#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2843#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2842#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2841#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2840#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2839#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2837#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2838#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2836#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2835#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2834#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2833#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2832#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2831#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2830#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2829#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2828#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2827#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2826#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2825#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2824#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2823#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2822#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2821#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2820#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2819#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2818#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2817#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2816#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2815#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2814#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2813#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2812#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2811#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2810#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2809#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2808#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2807#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2806#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2805#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2804#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2803#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2802#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2801#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2800#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2799#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2798#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2797#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2796#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2795#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2794#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2793#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2792#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2791#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2790#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2789#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2788#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2786#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2783#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2782#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2778#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2774#L12-1 [2024-10-31 22:04:11,823 INFO L747 eck$LassoCheckResult]: Loop: 2774#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2775#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2774#L12-1 [2024-10-31 22:04:11,823 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:11,823 INFO L85 PathProgramCache]: Analyzing trace with hash 2325394, now seen corresponding path program 2 times [2024-10-31 22:04:11,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:11,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226379012] [2024-10-31 22:04:11,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:11,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:11,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:12,429 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2024-10-31 22:04:12,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:12,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226379012] [2024-10-31 22:04:12,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226379012] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:04:12,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [607979886] [2024-10-31 22:04:12,430 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-10-31 22:04:12,430 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:04:12,430 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:12,432 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:04:12,434 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-10-31 22:04:12,506 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-10-31 22:04:12,506 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:04:12,508 INFO L255 TraceCheckSpWp]: Trace formula consists of 242 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-10-31 22:04:12,510 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:13,047 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2024-10-31 22:04:13,047 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:04:13,587 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2024-10-31 22:04:13,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [607979886] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:04:13,587 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:04:13,588 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 40 [2024-10-31 22:04:13,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1676913652] [2024-10-31 22:04:13,588 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:04:13,590 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:13,590 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:13,591 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 6 times [2024-10-31 22:04:13,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:13,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542206793] [2024-10-31 22:04:13,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:13,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:13,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:13,594 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:13,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:13,596 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:13,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:13,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2024-10-31 22:04:13,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=556, Invalid=1004, Unknown=0, NotChecked=0, Total=1560 [2024-10-31 22:04:13,616 INFO L87 Difference]: Start difference. First operand 129 states and 137 transitions. cyclomatic complexity: 12 Second operand has 40 states, 40 states have (on average 3.075) internal successors, (123), 40 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:15,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:15,030 INFO L93 Difference]: Finished difference Result 319 states and 329 transitions. [2024-10-31 22:04:15,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319 states and 329 transitions. [2024-10-31 22:04:15,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:15,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319 states to 251 states and 261 transitions. [2024-10-31 22:04:15,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2024-10-31 22:04:15,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2024-10-31 22:04:15,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 251 states and 261 transitions. [2024-10-31 22:04:15,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:15,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 251 states and 261 transitions. [2024-10-31 22:04:15,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states and 261 transitions. [2024-10-31 22:04:15,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 243. [2024-10-31 22:04:15,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 243 states, 243 states have (on average 1.0411522633744856) internal successors, (253), 242 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:15,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 253 transitions. [2024-10-31 22:04:15,042 INFO L240 hiAutomatonCegarLoop]: Abstraction has 243 states and 253 transitions. [2024-10-31 22:04:15,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2024-10-31 22:04:15,043 INFO L425 stractBuchiCegarLoop]: Abstraction has 243 states and 253 transitions. [2024-10-31 22:04:15,044 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:04:15,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 243 states and 253 transitions. [2024-10-31 22:04:15,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:15,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:15,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:15,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [76, 75, 70, 5, 1, 1, 1] [2024-10-31 22:04:15,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:15,049 INFO L745 eck$LassoCheckResult]: Stem: 4018#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 4019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 4020#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4023#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4024#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4036#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4037#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4016#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4012#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4013#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4253#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4252#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4251#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4250#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4249#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4247#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4246#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4245#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4244#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4243#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4242#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4241#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4240#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4238#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4237#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4234#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4231#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4230#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4229#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4228#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4227#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4226#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4225#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4224#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4223#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4222#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4220#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4219#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4218#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4217#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4216#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4215#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4214#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4213#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4210#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4209#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4208#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4207#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4206#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4205#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4204#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4202#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4203#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4201#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4200#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4199#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4198#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4197#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4196#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4195#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4190#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4189#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4185#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4181#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4179#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4178#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4177#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4174#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4173#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4172#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4171#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4169#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4168#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4167#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4166#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4165#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4163#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4162#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4161#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4160#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4158#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4157#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4156#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4151#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4150#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4149#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4148#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4147#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4144#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4142#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4141#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4139#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4138#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4137#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4136#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4135#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4134#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4133#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4132#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4131#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4130#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4129#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4128#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4127#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4126#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4125#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4124#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4123#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4122#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4121#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4120#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4119#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4117#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4116#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4115#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4114#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4113#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4112#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4111#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4110#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4109#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4108#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4107#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4105#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4103#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4102#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4101#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4100#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4099#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4098#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4097#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4096#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4094#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4093#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4091#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4092#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4090#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4089#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4088#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4087#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4086#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4085#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4084#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4083#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4082#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4081#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4080#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4079#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4078#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4077#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4076#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4075#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4074#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4073#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4072#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4071#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4070#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4069#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4068#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4067#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4066#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4065#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4064#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4063#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4062#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4061#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4060#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4059#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4058#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4057#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4056#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4055#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4054#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4053#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4052#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4051#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4050#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4049#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4048#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4047#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4046#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4045#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4044#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4043#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4042#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4039#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4040#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4038#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4035#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4034#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4033#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4029#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4025#L12-1 [2024-10-31 22:04:15,049 INFO L747 eck$LassoCheckResult]: Loop: 4025#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4026#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4025#L12-1 [2024-10-31 22:04:15,049 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:15,050 INFO L85 PathProgramCache]: Analyzing trace with hash 1383057750, now seen corresponding path program 3 times [2024-10-31 22:04:15,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:15,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376801839] [2024-10-31 22:04:15,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:15,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:15,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:15,424 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 0 proven. 6525 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2024-10-31 22:04:15,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:15,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376801839] [2024-10-31 22:04:15,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376801839] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:04:15,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1878029314] [2024-10-31 22:04:15,425 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-31 22:04:15,425 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:04:15,425 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:15,427 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:04:15,429 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-10-31 22:04:15,482 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2024-10-31 22:04:15,482 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:04:15,483 INFO L255 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-10-31 22:04:15,486 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:15,553 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2024-10-31 22:04:15,553 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:04:15,617 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2024-10-31 22:04:15,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1878029314] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:04:15,618 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:04:15,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5, 5] total 11 [2024-10-31 22:04:15,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107951603] [2024-10-31 22:04:15,618 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:04:15,619 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:15,619 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:15,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 7 times [2024-10-31 22:04:15,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:15,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873112036] [2024-10-31 22:04:15,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:15,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:15,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:15,622 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:15,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:15,624 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:15,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:15,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-10-31 22:04:15,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2024-10-31 22:04:15,643 INFO L87 Difference]: Start difference. First operand 243 states and 253 transitions. cyclomatic complexity: 16 Second operand has 12 states, 11 states have (on average 3.5454545454545454) internal successors, (39), 12 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:15,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:15,969 INFO L93 Difference]: Finished difference Result 267 states and 282 transitions. [2024-10-31 22:04:15,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 267 states and 282 transitions. [2024-10-31 22:04:15,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:15,972 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 267 states to 267 states and 282 transitions. [2024-10-31 22:04:15,973 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2024-10-31 22:04:15,973 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2024-10-31 22:04:15,973 INFO L73 IsDeterministic]: Start isDeterministic. Operand 267 states and 282 transitions. [2024-10-31 22:04:15,973 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:15,973 INFO L218 hiAutomatonCegarLoop]: Abstraction has 267 states and 282 transitions. [2024-10-31 22:04:15,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states and 282 transitions. [2024-10-31 22:04:15,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 256. [2024-10-31 22:04:15,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 256 states, 256 states have (on average 1.046875) internal successors, (268), 255 states have internal predecessors, (268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:15,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 268 transitions. [2024-10-31 22:04:15,979 INFO L240 hiAutomatonCegarLoop]: Abstraction has 256 states and 268 transitions. [2024-10-31 22:04:15,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-10-31 22:04:15,980 INFO L425 stractBuchiCegarLoop]: Abstraction has 256 states and 268 transitions. [2024-10-31 22:04:15,981 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:04:15,981 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 256 states and 268 transitions. [2024-10-31 22:04:15,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:15,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:15,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:15,988 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [78, 77, 71, 6, 1, 1, 1] [2024-10-31 22:04:15,988 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:15,989 INFO L745 eck$LassoCheckResult]: Stem: 5949#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 5950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 5951#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5965#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5961#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5956#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5955#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5947#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5943#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5944#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6196#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6195#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6190#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6189#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6185#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6181#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6179#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6178#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6177#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6174#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6173#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6172#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6171#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6169#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6168#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6167#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6166#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6165#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6163#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6162#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6161#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6160#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6158#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6157#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6156#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6151#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6150#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6149#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6148#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6147#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6144#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6142#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6141#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6139#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6138#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6137#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6136#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6135#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6134#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6133#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6132#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6131#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6130#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6129#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6128#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6127#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6126#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6125#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6124#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6123#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6122#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6121#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6120#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6119#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6117#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6116#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6115#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6114#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6113#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6112#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6111#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6110#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6109#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6108#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6107#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6105#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6103#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6102#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6101#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6100#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6099#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6098#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6097#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6096#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6094#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6093#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6092#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6091#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6090#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6088#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6089#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6087#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6086#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6085#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6084#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6083#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6082#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6081#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6080#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6079#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6078#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6077#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6076#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6075#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6074#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6073#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6072#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6071#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6070#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6069#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6068#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6067#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6066#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6065#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6064#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6063#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6062#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6061#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6060#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6059#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6058#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6057#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6056#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6055#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6054#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6053#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6052#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6051#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6050#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6049#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6048#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6047#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6046#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6045#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6044#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6043#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6042#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6041#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6040#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6039#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6038#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6037#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6036#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6034#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6035#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6033#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6032#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6031#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6030#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6029#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6028#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6027#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6026#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6025#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6024#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6023#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6022#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6021#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6020#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6019#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6018#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6017#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6016#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6015#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6014#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6013#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6012#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6011#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6010#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6009#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6008#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6007#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6006#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6005#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6004#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6003#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6002#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6001#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6000#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5999#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5998#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5997#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5996#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5995#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5994#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5993#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5992#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5991#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5990#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5989#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5988#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5987#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5986#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5985#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5983#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5984#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5982#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5981#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5980#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5979#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5978#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5973#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5972#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5976#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5967#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5966#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5962#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5959#L12-1 [2024-10-31 22:04:15,989 INFO L747 eck$LassoCheckResult]: Loop: 5959#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5960#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5959#L12-1 [2024-10-31 22:04:15,989 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:15,989 INFO L85 PathProgramCache]: Analyzing trace with hash -2031563884, now seen corresponding path program 4 times [2024-10-31 22:04:15,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:15,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23953069] [2024-10-31 22:04:15,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:15,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:16,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:16,508 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 154 proven. 6828 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2024-10-31 22:04:16,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:16,508 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23953069] [2024-10-31 22:04:16,508 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23953069] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:04:16,508 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [659101093] [2024-10-31 22:04:16,509 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-10-31 22:04:16,509 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:04:16,509 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:16,511 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:04:16,513 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-10-31 22:04:16,625 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-10-31 22:04:16,625 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:04:16,628 INFO L255 TraceCheckSpWp]: Trace formula consists of 489 conjuncts, 28 conjuncts are in the unsatisfiable core [2024-10-31 22:04:16,632 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:17,515 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2024-10-31 22:04:17,516 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:04:18,494 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2024-10-31 22:04:18,500 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [659101093] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:04:18,503 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:04:18,504 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 28, 28] total 50 [2024-10-31 22:04:18,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [976442688] [2024-10-31 22:04:18,510 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:04:18,511 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:18,516 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:18,520 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 8 times [2024-10-31 22:04:18,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:18,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086032231] [2024-10-31 22:04:18,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:18,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:18,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:18,541 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:18,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:18,543 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:18,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:18,563 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2024-10-31 22:04:18,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=683, Invalid=1767, Unknown=0, NotChecked=0, Total=2450 [2024-10-31 22:04:18,564 INFO L87 Difference]: Start difference. First operand 256 states and 268 transitions. cyclomatic complexity: 19 Second operand has 50 states, 50 states have (on average 3.18) internal successors, (159), 50 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:22,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:22,190 INFO L93 Difference]: Finished difference Result 1034 states and 1149 transitions. [2024-10-31 22:04:22,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1034 states and 1149 transitions. [2024-10-31 22:04:22,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:22,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1034 states to 986 states and 1101 transitions. [2024-10-31 22:04:22,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2024-10-31 22:04:22,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2024-10-31 22:04:22,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 986 states and 1101 transitions. [2024-10-31 22:04:22,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:22,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 986 states and 1101 transitions. [2024-10-31 22:04:22,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 986 states and 1101 transitions. [2024-10-31 22:04:22,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 986 to 693. [2024-10-31 22:04:22,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.1096681096681096) internal successors, (769), 692 states have internal predecessors, (769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:22,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 769 transitions. [2024-10-31 22:04:22,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 769 transitions. [2024-10-31 22:04:22,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 149 states. [2024-10-31 22:04:22,217 INFO L425 stractBuchiCegarLoop]: Abstraction has 693 states and 769 transitions. [2024-10-31 22:04:22,217 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:04:22,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 769 transitions. [2024-10-31 22:04:22,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:22,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:22,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:22,225 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 83, 11, 1, 1, 1] [2024-10-31 22:04:22,225 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:22,226 INFO L745 eck$LassoCheckResult]: Stem: 9116#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 9117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 9118#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9122#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9113#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9114#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9120#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9121#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9108#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9109#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9525#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9524#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9523#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9522#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9521#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9520#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9519#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9518#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9517#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9516#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9515#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9514#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9513#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9512#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9511#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9510#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9509#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9508#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9507#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9506#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9505#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9504#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9503#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9502#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9501#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9500#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9499#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9498#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9497#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9496#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9495#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9494#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9493#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9492#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9491#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9490#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9489#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9488#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9487#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9486#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9485#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9484#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9483#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9482#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9481#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9480#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9479#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9478#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9477#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9476#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9473#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9474#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9472#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9471#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9470#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9469#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9468#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9467#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9466#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9465#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9464#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9463#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9462#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9461#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9460#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9459#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9458#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9457#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9456#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9455#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9454#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9453#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9452#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9451#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9450#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9449#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9448#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9447#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9446#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9445#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9444#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9443#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9442#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9441#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9440#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9439#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9438#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9437#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9436#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9435#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9434#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9433#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9432#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9431#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9430#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9429#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9428#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9427#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9426#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9425#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9424#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9423#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9422#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9421#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9420#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9419#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9418#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9417#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9416#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9414#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9413#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9412#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9411#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9410#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9409#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9408#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9407#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9406#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9405#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9404#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9403#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9402#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9401#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9400#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9399#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9398#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9397#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9396#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9395#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9394#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9393#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9392#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9391#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9389#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9388#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9387#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9386#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9385#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9384#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9383#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9382#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9381#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9380#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9379#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9377#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9376#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9375#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9374#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9373#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9372#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9371#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9370#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9369#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9367#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9366#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9365#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9364#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9363#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9362#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9361#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9359#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9358#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9357#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9356#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9355#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9354#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9353#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9352#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9351#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9350#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9349#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9348#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9347#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9346#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9345#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9344#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9343#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9342#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9341#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9340#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9339#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9338#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9336#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9334#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9332#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9330#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9328#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9326#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9324#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9322#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9320#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9318#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9316#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9314#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9312#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9310#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9308#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9306#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9304#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9281#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9282#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9300#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9298#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9296#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9275#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9273#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9274#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9269#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9285#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9262#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9261#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9260#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9259#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9258#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9225#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9222#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9219#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9216#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9213#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9211#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9209#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9207#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9206#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9205#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9204#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9186#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9185#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9184#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9183#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9181#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9191#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9174#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9172#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9171#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9169#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9166#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9165#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9167#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9159#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9158#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9157#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9156#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9151#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9155#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9146#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9145#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9144#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9143#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9142#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9134#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9141#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9139#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9138#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9137#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9136#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9135#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9133#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9132#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9130#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9129#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9128#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9125#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9124#L12-1 [2024-10-31 22:04:22,226 INFO L747 eck$LassoCheckResult]: Loop: 9124#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9123#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9124#L12-1 [2024-10-31 22:04:22,226 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:22,226 INFO L85 PathProgramCache]: Analyzing trace with hash 2005033964, now seen corresponding path program 5 times [2024-10-31 22:04:22,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:22,227 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405836257] [2024-10-31 22:04:22,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:22,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:22,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:23,203 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 5787 proven. 5686 refuted. 0 times theorem prover too weak. 1828 trivial. 0 not checked. [2024-10-31 22:04:23,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:23,203 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405836257] [2024-10-31 22:04:23,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405836257] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:04:23,203 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [271627976] [2024-10-31 22:04:23,204 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-31 22:04:23,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:04:23,204 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:23,206 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:04:23,209 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2024-10-31 22:04:23,467 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 73 check-sat command(s) [2024-10-31 22:04:23,467 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:04:23,470 INFO L255 TraceCheckSpWp]: Trace formula consists of 455 conjuncts, 29 conjuncts are in the unsatisfiable core [2024-10-31 22:04:23,473 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:24,143 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7733 proven. 3749 refuted. 0 times theorem prover too weak. 1819 trivial. 0 not checked. [2024-10-31 22:04:24,144 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:04:24,755 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7733 proven. 3749 refuted. 0 times theorem prover too weak. 1819 trivial. 0 not checked. [2024-10-31 22:04:24,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [271627976] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:04:24,756 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:04:24,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 29, 29] total 48 [2024-10-31 22:04:24,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301341786] [2024-10-31 22:04:24,757 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:04:24,757 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:24,758 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:24,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 9 times [2024-10-31 22:04:24,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:24,758 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138983825] [2024-10-31 22:04:24,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:24,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:24,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:24,761 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:24,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:24,763 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:24,784 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:24,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2024-10-31 22:04:24,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=585, Invalid=1671, Unknown=0, NotChecked=0, Total=2256 [2024-10-31 22:04:24,786 INFO L87 Difference]: Start difference. First operand 693 states and 769 transitions. cyclomatic complexity: 82 Second operand has 48 states, 48 states have (on average 3.2291666666666665) internal successors, (155), 48 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:27,673 INFO L93 Difference]: Finished difference Result 1368 states and 1470 transitions. [2024-10-31 22:04:27,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1368 states and 1470 transitions. [2024-10-31 22:04:27,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:27,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1368 states to 1240 states and 1342 transitions. [2024-10-31 22:04:27,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2024-10-31 22:04:27,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2024-10-31 22:04:27,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1240 states and 1342 transitions. [2024-10-31 22:04:27,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:27,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1240 states and 1342 transitions. [2024-10-31 22:04:27,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1240 states and 1342 transitions. [2024-10-31 22:04:27,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1240 to 609. [2024-10-31 22:04:27,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 609 states, 609 states have (on average 1.083743842364532) internal successors, (660), 608 states have internal predecessors, (660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 609 states and 660 transitions. [2024-10-31 22:04:27,704 INFO L240 hiAutomatonCegarLoop]: Abstraction has 609 states and 660 transitions. [2024-10-31 22:04:27,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 135 states. [2024-10-31 22:04:27,705 INFO L425 stractBuchiCegarLoop]: Abstraction has 609 states and 660 transitions. [2024-10-31 22:04:27,705 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:04:27,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 609 states and 660 transitions. [2024-10-31 22:04:27,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-10-31 22:04:27,708 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:27,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:27,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [131, 130, 115, 15, 1, 1, 1] [2024-10-31 22:04:27,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:04:27,716 INFO L745 eck$LassoCheckResult]: Stem: 13188#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 13189#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 13190#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13185#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13181#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13677#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13676#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13675#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13674#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13673#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13672#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13671#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13670#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13669#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13668#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13667#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13666#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13665#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13664#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13663#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13662#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13661#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13660#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13659#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13658#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13657#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13656#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13655#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13654#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13653#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13652#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13651#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13650#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13649#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13648#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13647#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13646#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13645#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13644#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13643#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13642#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13641#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13640#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13639#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13638#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13637#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13636#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13635#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13634#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13633#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13632#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13631#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13630#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13629#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13628#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13626#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13627#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13625#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13624#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13623#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13622#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13621#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13620#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13619#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13618#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13617#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13616#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13615#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13614#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13613#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13612#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13611#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13610#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13609#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13608#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13607#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13606#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13605#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13604#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13603#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13602#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13601#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13600#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13599#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13598#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13597#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13596#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13595#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13594#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13593#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13592#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13591#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13590#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13589#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13588#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13587#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13586#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13585#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13584#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13583#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13582#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13581#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13580#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13579#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13578#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13577#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13576#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13575#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13574#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13573#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13572#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13571#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13569#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13570#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13568#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13567#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13566#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13565#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13564#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13563#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13562#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13561#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13560#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13559#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13558#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13557#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13556#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13555#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13554#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13553#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13552#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13551#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13550#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13549#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13548#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13547#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13546#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13545#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13544#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13543#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13542#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13541#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13540#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13539#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13538#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13537#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13536#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13535#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13534#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13533#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13532#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13531#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13530#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13529#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13528#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13527#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13526#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13525#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13524#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13523#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13521#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13520#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13518#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13517#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13516#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13515#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13513#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13512#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13511#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13510#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13509#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13508#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13507#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13506#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13505#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13504#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13503#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13502#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13501#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13500#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13499#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13498#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13497#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13496#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13495#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13494#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13493#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13491#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13489#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13487#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13485#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13483#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13481#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13479#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13477#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13475#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13473#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13471#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13469#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13467#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13465#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13463#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13460#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13457#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13454#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13451#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13448#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13445#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13442#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13439#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13436#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13433#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13430#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13427#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13424#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13422#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13415#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13414#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13413#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13412#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13411#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13410#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13409#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13408#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13407#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13406#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13405#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13404#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13403#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13402#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13401#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13400#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13399#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13398#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13396#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13394#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13392#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13388#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13386#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13384#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13382#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13380#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13376#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13374#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13372#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13338#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13369#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13370#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13366#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13365#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13364#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13363#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13362#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13361#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13360#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13359#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13358#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13349#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13348#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13346#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13345#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13344#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13343#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13341#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13339#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13340#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13336#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13335#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13334#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13333#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13332#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13331#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13330#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13329#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13328#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13327#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13326#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13320#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13319#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13317#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13315#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13314#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13312#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13313#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13309#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13308#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13307#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13306#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13305#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13304#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13303#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13302#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13301#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13300#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13299#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13298#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13297#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13296#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13292#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13290#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13288#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13289#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13285#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13284#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13283#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13282#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13281#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13280#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13279#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13278#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13277#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13276#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13275#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13274#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13273#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13272#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13269#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13267#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13268#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13264#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13263#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13262#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13261#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13260#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13259#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13258#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13257#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13256#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13255#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13254#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13253#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13252#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13251#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13250#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13249#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13247#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13246#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13245#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13244#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13243#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13242#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13241#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13240#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13239#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13238#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13237#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13236#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13235#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13234#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13232#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13230#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13229#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13228#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13227#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13226#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13225#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13224#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13223#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13222#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13220#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13219#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13218#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13217#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13216#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13215#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13214#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13206#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13213#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13211#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13210#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13209#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13208#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13207#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13205#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13204#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13202#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13201#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13200#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13195#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13196#L12-1 [2024-10-31 22:04:27,716 INFO L747 eck$LassoCheckResult]: Loop: 13196#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13199#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13196#L12-1 [2024-10-31 22:04:27,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:27,717 INFO L85 PathProgramCache]: Analyzing trace with hash -1703910940, now seen corresponding path program 6 times [2024-10-31 22:04:27,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:27,717 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742888925] [2024-10-31 22:04:27,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:27,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:27,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:29,310 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 12928 proven. 8663 refuted. 0 times theorem prover too weak. 3824 trivial. 0 not checked. [2024-10-31 22:04:29,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:29,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742888925] [2024-10-31 22:04:29,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [742888925] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:04:29,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1007998606] [2024-10-31 22:04:29,311 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-10-31 22:04:29,312 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:04:29,312 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:29,314 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:04:29,316 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a0f5635-2459-4279-a37f-7a6da11729ef/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2024-10-31 22:04:29,593 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 81 check-sat command(s) [2024-10-31 22:04:29,593 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:04:29,596 INFO L255 TraceCheckSpWp]: Trace formula consists of 521 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-10-31 22:04:29,601 INFO L278 TraceCheckSpWp]: Computing forward predicates...