./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_lcr.6.ufo.BOUNDED-12.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_lcr.6.ufo.BOUNDED-12.pals.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 65159196aa732cf84d788dcb31500c216d665703806e14a7c6f7047ab62d591b --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:10:47,679 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:10:47,774 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:10:47,782 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:10:47,783 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:10:47,815 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:10:47,818 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:10:47,818 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:10:47,819 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:10:47,822 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:10:47,822 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:10:47,824 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:10:47,825 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:10:47,825 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:10:47,825 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:10:47,827 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:10:47,828 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:10:47,828 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:10:47,828 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:10:47,829 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:10:47,829 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:10:47,833 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:10:47,834 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:10:47,834 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:10:47,834 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:10:47,834 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:10:47,835 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:10:47,835 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:10:47,835 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:10:47,835 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:10:47,836 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:10:47,836 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:10:47,836 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:10:47,836 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:10:47,837 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:10:47,837 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:10:47,837 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:10:47,838 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:10:47,838 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:10:47,838 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 65159196aa732cf84d788dcb31500c216d665703806e14a7c6f7047ab62d591b [2024-10-31 22:10:48,166 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:10:48,199 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:10:48,202 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:10:48,204 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:10:48,204 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:10:48,205 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/seq-mthreaded/pals_lcr.6.ufo.BOUNDED-12.pals.c Unable to find full path for "g++" [2024-10-31 22:10:50,190 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:10:50,453 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:10:50,454 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/sv-benchmarks/c/seq-mthreaded/pals_lcr.6.ufo.BOUNDED-12.pals.c [2024-10-31 22:10:50,468 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/data/15901eb47/8294b2a51faa40a39d228a58a4a4e937/FLAG2981c5260 [2024-10-31 22:10:50,489 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/data/15901eb47/8294b2a51faa40a39d228a58a4a4e937 [2024-10-31 22:10:50,492 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:10:50,493 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:10:50,494 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:10:50,495 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:10:50,500 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:10:50,501 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:50,502 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@f3c37ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50, skipping insertion in model container [2024-10-31 22:10:50,502 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:50,557 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:10:50,810 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:10:50,828 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:10:50,928 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:10:50,954 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:10:50,955 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50 WrapperNode [2024-10-31 22:10:50,955 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:10:50,956 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:10:50,957 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:10:50,957 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:10:50,966 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:50,982 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,022 INFO L138 Inliner]: procedures = 25, calls = 18, calls flagged for inlining = 13, calls inlined = 13, statements flattened = 378 [2024-10-31 22:10:51,023 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:10:51,024 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:10:51,024 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:10:51,024 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:10:51,039 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,039 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,043 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,060 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:10:51,060 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,061 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,069 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,074 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,077 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,078 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,086 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:10:51,091 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:10:51,091 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:10:51,091 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:10:51,092 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (1/1) ... [2024-10-31 22:10:51,105 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:10:51,130 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:10:51,158 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:10:51,166 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46447645-2c5f-41e0-a0a8-9db46999aae1/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:10:51,207 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:10:51,208 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:10:51,208 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:10:51,208 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:10:51,347 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:10:51,349 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:10:51,949 INFO L? ?]: Removed 45 outVars from TransFormulas that were not future-live. [2024-10-31 22:10:51,949 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:10:51,967 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:10:51,969 INFO L316 CfgBuilder]: Removed 1 assume(true) statements. [2024-10-31 22:10:51,969 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:10:51 BoogieIcfgContainer [2024-10-31 22:10:51,970 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:10:51,971 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:10:51,971 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:10:51,975 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:10:51,976 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:10:51,976 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:10:50" (1/3) ... [2024-10-31 22:10:51,977 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@78630374 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:10:51, skipping insertion in model container [2024-10-31 22:10:51,977 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:10:51,978 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:10:50" (2/3) ... [2024-10-31 22:10:51,978 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@78630374 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:10:51, skipping insertion in model container [2024-10-31 22:10:51,978 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:10:51,978 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:10:51" (3/3) ... [2024-10-31 22:10:51,980 INFO L332 chiAutomizerObserver]: Analyzing ICFG pals_lcr.6.ufo.BOUNDED-12.pals.c [2024-10-31 22:10:52,041 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:10:52,042 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:10:52,042 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:10:52,042 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:10:52,042 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:10:52,042 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:10:52,042 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:10:52,043 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:10:52,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 98 states, 97 states have (on average 1.7525773195876289) internal successors, (170), 97 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:10:52,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 48 [2024-10-31 22:10:52,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:10:52,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:10:52,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:52,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:52,082 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:10:52,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 98 states, 97 states have (on average 1.7525773195876289) internal successors, (170), 97 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:10:52,089 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 48 [2024-10-31 22:10:52,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:10:52,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:10:52,091 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:52,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:52,099 INFO L745 eck$LassoCheckResult]: Stem: 31#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(33, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0; 35#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~ret29#1, main_#t~ret30#1, main_#t~post31#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 64#L228true assume !(0 == ~r1~0);init_~tmp~0#1 := 0; 43#L228-1true init_#res#1 := init_~tmp~0#1; 66#init_returnLabel#1true main_#t~ret29#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret29#1;havoc main_#t~ret29#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 38#L22true assume !(0 == assume_abort_if_not_~cond#1); 69#L21true havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 74#L467-2true [2024-10-31 22:10:52,101 INFO L747 eck$LassoCheckResult]: Loop: 74#L467-2true assume !!(main_~i2~0#1 < 12);assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 19#L78true assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1; 39#L78-2true havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 17#L104true assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1; 95#L104-2true havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 81#L129true assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1; 10#L129-2true havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 68#L154true assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1; 96#L154-2true havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 85#L179true assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1; 21#L179-2true havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 78#L204true assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1; 70#L204-2true havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 87#L397true assume !(~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1);check_~tmp~1#1 := 0; 75#L397-1true check_#res#1 := check_~tmp~1#1; 15#check_returnLabel#1true main_#t~ret30#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret30#1;havoc main_#t~ret30#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 83#L500true assume !(0 == assert_~arg#1 % 256); 22#L495true havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;main_#t~post31#1 := main_~i2~0#1;main_~i2~0#1 := 1 + main_#t~post31#1;havoc main_#t~post31#1; 74#L467-2true [2024-10-31 22:10:52,108 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:10:52,108 INFO L85 PathProgramCache]: Analyzing trace with hash 2030119858, now seen corresponding path program 1 times [2024-10-31 22:10:52,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:10:52,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963297211] [2024-10-31 22:10:52,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:10:52,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:10:52,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:10:52,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:10:52,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:10:52,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963297211] [2024-10-31 22:10:52,623 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1963297211] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:10:52,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:10:52,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:10:52,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224393708] [2024-10-31 22:10:52,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:10:52,632 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:10:52,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:10:52,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1869415403, now seen corresponding path program 1 times [2024-10-31 22:10:52,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:10:52,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253326140] [2024-10-31 22:10:52,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:10:52,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:10:52,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:10:53,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:10:53,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:10:53,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253326140] [2024-10-31 22:10:53,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253326140] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:10:53,109 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:10:53,110 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:10:53,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [525598599] [2024-10-31 22:10:53,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:10:53,111 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:10:53,112 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:10:53,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:10:53,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:10:53,152 INFO L87 Difference]: Start difference. First operand has 98 states, 97 states have (on average 1.7525773195876289) internal successors, (170), 97 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:10:53,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:10:53,281 INFO L93 Difference]: Finished difference Result 100 states and 168 transitions. [2024-10-31 22:10:53,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 168 transitions. [2024-10-31 22:10:53,287 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 46 [2024-10-31 22:10:53,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 92 states and 121 transitions. [2024-10-31 22:10:53,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 92 [2024-10-31 22:10:53,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 92 [2024-10-31 22:10:53,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92 states and 121 transitions. [2024-10-31 22:10:53,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:10:53,295 INFO L218 hiAutomatonCegarLoop]: Abstraction has 92 states and 121 transitions. [2024-10-31 22:10:53,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states and 121 transitions. [2024-10-31 22:10:53,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 92. [2024-10-31 22:10:53,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.315217391304348) internal successors, (121), 91 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:10:53,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 121 transitions. [2024-10-31 22:10:53,327 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 121 transitions. [2024-10-31 22:10:53,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:10:53,332 INFO L425 stractBuchiCegarLoop]: Abstraction has 92 states and 121 transitions. [2024-10-31 22:10:53,332 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:10:53,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 121 transitions. [2024-10-31 22:10:53,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 46 [2024-10-31 22:10:53,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:10:53,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:10:53,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:53,336 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:53,337 INFO L745 eck$LassoCheckResult]: Stem: 284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(33, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0; 285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~ret29#1, main_#t~ret30#1, main_#t~post31#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 257#L228 assume 0 == ~r1~0; 258#L229 assume ~id1~0 >= 0; 228#L230 assume 0 == ~st1~0; 229#L231 assume ~send1~0 == ~id1~0; 242#L232 assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296); 302#L233 assume ~id2~0 >= 0; 218#L234 assume 0 == ~st2~0; 219#L235 assume ~send2~0 == ~id2~0; 293#L236 assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296); 288#L237 assume ~id3~0 >= 0; 274#L238 assume 0 == ~st3~0; 275#L239 assume ~send3~0 == ~id3~0; 272#L240 assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296); 273#L241 assume ~id4~0 >= 0; 277#L242 assume 0 == ~st4~0; 236#L243 assume ~send4~0 == ~id4~0; 230#L244 assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296); 231#L245 assume ~id5~0 >= 0; 276#L246 assume 0 == ~st5~0; 290#L247 assume ~send5~0 == ~id5~0; 291#L248 assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296); 220#L249 assume ~id6~0 >= 0; 221#L250 assume 0 == ~st6~0; 243#L251 assume ~send6~0 == ~id6~0; 244#L252 assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296); 248#L253 assume ~id1~0 != ~id2~0; 249#L254 assume ~id1~0 != ~id3~0; 250#L255 assume ~id1~0 != ~id4~0; 251#L256 assume ~id1~0 != ~id5~0; 297#L257 assume ~id1~0 != ~id6~0; 286#L258 assume ~id2~0 != ~id3~0; 212#L259 assume ~id2~0 != ~id4~0; 213#L260 assume ~id2~0 != ~id5~0; 303#L261 assume ~id2~0 != ~id6~0; 299#L262 assume ~id3~0 != ~id4~0; 300#L263 assume ~id3~0 != ~id5~0; 301#L264 assume ~id3~0 != ~id6~0; 216#L265 assume ~id4~0 != ~id5~0; 217#L266 assume ~id4~0 != ~id6~0; 237#L267 assume ~id5~0 != ~id6~0;init_~tmp~0#1 := 1; 271#L228-1 init_#res#1 := init_~tmp~0#1; 268#init_returnLabel#1 main_#t~ret29#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret29#1;havoc main_#t~ret29#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 269#L22 assume !(0 == assume_abort_if_not_~cond#1); 281#L21 havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 267#L467-2 [2024-10-31 22:10:53,337 INFO L747 eck$LassoCheckResult]: Loop: 267#L467-2 assume !!(main_~i2~0#1 < 12);assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 261#L78 assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1; 235#L78-2 havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 254#L104 assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1; 256#L104-2 havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 294#L129 assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1; 238#L129-2 havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 239#L154 assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1; 247#L154-2 havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 298#L179 assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1; 264#L179-2 havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 265#L204 assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1; 282#L204-2 havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 283#L397 assume !(~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1);check_~tmp~1#1 := 0; 233#L397-1 check_#res#1 := check_~tmp~1#1; 252#check_returnLabel#1 main_#t~ret30#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret30#1;havoc main_#t~ret30#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 253#L500 assume !(0 == assert_~arg#1 % 256); 266#L495 havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;main_#t~post31#1 := main_~i2~0#1;main_~i2~0#1 := 1 + main_#t~post31#1;havoc main_#t~post31#1; 267#L467-2 [2024-10-31 22:10:53,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:10:53,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1716035805, now seen corresponding path program 1 times [2024-10-31 22:10:53,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:10:53,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837303077] [2024-10-31 22:10:53,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:10:53,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:10:53,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:53,377 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:10:53,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:53,478 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:10:53,479 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:10:53,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1869415403, now seen corresponding path program 2 times [2024-10-31 22:10:53,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:10:53,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462076934] [2024-10-31 22:10:53,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:10:53,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:10:53,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:10:53,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:10:53,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:10:53,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462076934] [2024-10-31 22:10:53,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1462076934] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:10:53,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:10:53,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:10:53,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729838181] [2024-10-31 22:10:53,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:10:53,738 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:10:53,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:10:53,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:10:53,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:10:53,740 INFO L87 Difference]: Start difference. First operand 92 states and 121 transitions. cyclomatic complexity: 30 Second operand has 5 states, 5 states have (on average 3.6) internal successors, (18), 5 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:10:53,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:10:53,775 INFO L93 Difference]: Finished difference Result 95 states and 123 transitions. [2024-10-31 22:10:53,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95 states and 123 transitions. [2024-10-31 22:10:53,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 46 [2024-10-31 22:10:53,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95 states to 92 states and 118 transitions. [2024-10-31 22:10:53,779 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 92 [2024-10-31 22:10:53,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 92 [2024-10-31 22:10:53,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92 states and 118 transitions. [2024-10-31 22:10:53,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:10:53,783 INFO L218 hiAutomatonCegarLoop]: Abstraction has 92 states and 118 transitions. [2024-10-31 22:10:53,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states and 118 transitions. [2024-10-31 22:10:53,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 92. [2024-10-31 22:10:53,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.2826086956521738) internal successors, (118), 91 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:10:53,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 118 transitions. [2024-10-31 22:10:53,788 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 118 transitions. [2024-10-31 22:10:53,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:10:53,790 INFO L425 stractBuchiCegarLoop]: Abstraction has 92 states and 118 transitions. [2024-10-31 22:10:53,790 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:10:53,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 118 transitions. [2024-10-31 22:10:53,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 46 [2024-10-31 22:10:53,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:10:53,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:10:53,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:53,793 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:53,794 INFO L745 eck$LassoCheckResult]: Stem: 479#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(33, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0; 480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~ret29#1, main_#t~ret30#1, main_#t~post31#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 452#L228 assume 0 == ~r1~0; 453#L229 assume ~id1~0 >= 0; 423#L230 assume 0 == ~st1~0; 424#L231 assume ~send1~0 == ~id1~0; 437#L232 assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296); 497#L233 assume ~id2~0 >= 0; 413#L234 assume 0 == ~st2~0; 414#L235 assume ~send2~0 == ~id2~0; 488#L236 assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296); 483#L237 assume ~id3~0 >= 0; 469#L238 assume 0 == ~st3~0; 470#L239 assume ~send3~0 == ~id3~0; 467#L240 assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296); 468#L241 assume ~id4~0 >= 0; 475#L242 assume 0 == ~st4~0; 430#L243 assume ~send4~0 == ~id4~0; 427#L244 assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296); 428#L245 assume ~id5~0 >= 0; 471#L246 assume 0 == ~st5~0; 485#L247 assume ~send5~0 == ~id5~0; 486#L248 assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296); 418#L249 assume ~id6~0 >= 0; 419#L250 assume 0 == ~st6~0; 438#L251 assume ~send6~0 == ~id6~0; 439#L252 assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296); 445#L253 assume ~id1~0 != ~id2~0; 446#L254 assume ~id1~0 != ~id3~0; 447#L255 assume ~id1~0 != ~id4~0; 448#L256 assume ~id1~0 != ~id5~0; 492#L257 assume ~id1~0 != ~id6~0; 481#L258 assume ~id2~0 != ~id3~0; 407#L259 assume ~id2~0 != ~id4~0; 408#L260 assume ~id2~0 != ~id5~0; 498#L261 assume ~id2~0 != ~id6~0; 494#L262 assume ~id3~0 != ~id4~0; 495#L263 assume ~id3~0 != ~id5~0; 496#L264 assume ~id3~0 != ~id6~0; 411#L265 assume ~id4~0 != ~id5~0; 412#L266 assume ~id4~0 != ~id6~0; 431#L267 assume ~id5~0 != ~id6~0;init_~tmp~0#1 := 1; 466#L228-1 init_#res#1 := init_~tmp~0#1; 463#init_returnLabel#1 main_#t~ret29#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret29#1;havoc main_#t~ret29#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 464#L22 assume !(0 == assume_abort_if_not_~cond#1); 476#L21 havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 462#L467-2 [2024-10-31 22:10:53,794 INFO L747 eck$LassoCheckResult]: Loop: 462#L467-2 assume !!(main_~i2~0#1 < 12);assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 458#L78 assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1; 429#L78-2 havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 449#L104 assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1; 451#L104-2 havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 489#L129 assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1; 432#L129-2 havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 433#L154 assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1; 442#L154-2 havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 493#L179 assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1; 456#L179-2 havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 457#L204 assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1; 477#L204-2 havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 478#L397 assume ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1; 491#L398 assume ~r1~0 >= 6; 426#$Ultimate##208 assume ~r1~0 < 6;check_~tmp~1#1 := 1; 435#L397-1 check_#res#1 := check_~tmp~1#1; 443#check_returnLabel#1 main_#t~ret30#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret30#1;havoc main_#t~ret30#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 444#L500 assume !(0 == assert_~arg#1 % 256); 461#L495 havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;main_#t~post31#1 := main_~i2~0#1;main_~i2~0#1 := 1 + main_#t~post31#1;havoc main_#t~post31#1; 462#L467-2 [2024-10-31 22:10:53,794 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:10:53,795 INFO L85 PathProgramCache]: Analyzing trace with hash -1716035805, now seen corresponding path program 2 times [2024-10-31 22:10:53,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:10:53,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631287249] [2024-10-31 22:10:53,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:10:53,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:10:53,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:53,848 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:10:53,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:53,901 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:10:53,902 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:10:53,902 INFO L85 PathProgramCache]: Analyzing trace with hash -204006085, now seen corresponding path program 1 times [2024-10-31 22:10:53,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:10:53,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841910268] [2024-10-31 22:10:53,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:10:53,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:10:53,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:10:53,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:10:53,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:10:53,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841910268] [2024-10-31 22:10:53,962 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841910268] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:10:53,962 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:10:53,962 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:10:53,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723518322] [2024-10-31 22:10:53,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:10:53,963 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:10:53,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:10:53,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:10:53,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:10:53,964 INFO L87 Difference]: Start difference. First operand 92 states and 118 transitions. cyclomatic complexity: 27 Second operand has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 3 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:10:54,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:10:54,009 INFO L93 Difference]: Finished difference Result 132 states and 179 transitions. [2024-10-31 22:10:54,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132 states and 179 transitions. [2024-10-31 22:10:54,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 86 [2024-10-31 22:10:54,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132 states to 132 states and 179 transitions. [2024-10-31 22:10:54,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 132 [2024-10-31 22:10:54,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 132 [2024-10-31 22:10:54,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 179 transitions. [2024-10-31 22:10:54,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:10:54,023 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132 states and 179 transitions. [2024-10-31 22:10:54,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 179 transitions. [2024-10-31 22:10:54,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 132. [2024-10-31 22:10:54,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132 states, 132 states have (on average 1.356060606060606) internal successors, (179), 131 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:10:54,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 179 transitions. [2024-10-31 22:10:54,037 INFO L240 hiAutomatonCegarLoop]: Abstraction has 132 states and 179 transitions. [2024-10-31 22:10:54,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:10:54,039 INFO L425 stractBuchiCegarLoop]: Abstraction has 132 states and 179 transitions. [2024-10-31 22:10:54,042 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:10:54,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 132 states and 179 transitions. [2024-10-31 22:10:54,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 86 [2024-10-31 22:10:54,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:10:54,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:10:54,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:54,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:10:54,046 INFO L745 eck$LassoCheckResult]: Stem: 712#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(33, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0; 713#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~ret29#1, main_#t~ret30#1, main_#t~post31#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 682#L228 assume 0 == ~r1~0; 683#L229 assume ~id1~0 >= 0; 653#L230 assume 0 == ~st1~0; 654#L231 assume ~send1~0 == ~id1~0; 667#L232 assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296); 735#L233 assume ~id2~0 >= 0; 643#L234 assume 0 == ~st2~0; 644#L235 assume ~send2~0 == ~id2~0; 722#L236 assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296); 716#L237 assume ~id3~0 >= 0; 701#L238 assume 0 == ~st3~0; 702#L239 assume ~send3~0 == ~id3~0; 699#L240 assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296); 700#L241 assume ~id4~0 >= 0; 704#L242 assume 0 == ~st4~0; 660#L243 assume ~send4~0 == ~id4~0; 655#L244 assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296); 656#L245 assume ~id5~0 >= 0; 703#L246 assume 0 == ~st5~0; 719#L247 assume ~send5~0 == ~id5~0; 720#L248 assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296); 645#L249 assume ~id6~0 >= 0; 646#L250 assume 0 == ~st6~0; 668#L251 assume ~send6~0 == ~id6~0; 669#L252 assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296); 673#L253 assume ~id1~0 != ~id2~0; 674#L254 assume ~id1~0 != ~id3~0; 675#L255 assume ~id1~0 != ~id4~0; 676#L256 assume ~id1~0 != ~id5~0; 726#L257 assume ~id1~0 != ~id6~0; 714#L258 assume ~id2~0 != ~id3~0; 637#L259 assume ~id2~0 != ~id4~0; 638#L260 assume ~id2~0 != ~id5~0; 736#L261 assume ~id2~0 != ~id6~0; 730#L262 assume ~id3~0 != ~id4~0; 731#L263 assume ~id3~0 != ~id5~0; 733#L264 assume ~id3~0 != ~id6~0; 641#L265 assume ~id4~0 != ~id5~0; 642#L266 assume ~id4~0 != ~id6~0; 661#L267 assume ~id5~0 != ~id6~0;init_~tmp~0#1 := 1; 698#L228-1 init_#res#1 := init_~tmp~0#1; 694#init_returnLabel#1 main_#t~ret29#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret29#1;havoc main_#t~ret29#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 695#L22 assume !(0 == assume_abort_if_not_~cond#1); 708#L21 havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 709#L467-2 [2024-10-31 22:10:54,047 INFO L747 eck$LassoCheckResult]: Loop: 709#L467-2 assume !!(main_~i2~0#1 < 12);assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 764#L78 assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1; 659#L78-2 havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 760#L104 assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1; 758#L104-2 havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 755#L129 assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1; 754#L129-2 havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 697#L154 assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1; 672#L154-2 havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 737#L179 assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1; 690#L179-2 havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 691#L204 assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1; 710#L204-2 havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 711#L397 assume ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1; 729#L398 assume !(~r1~0 >= 6); 657#L401 assume 0 == ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0; 658#$Ultimate##208 assume ~r1~0 < 6;check_~tmp~1#1 := 1; 768#L397-1 check_#res#1 := check_~tmp~1#1; 767#check_returnLabel#1 main_#t~ret30#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret30#1;havoc main_#t~ret30#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 766#L500 assume !(0 == assert_~arg#1 % 256); 765#L495 havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;main_#t~post31#1 := main_~i2~0#1;main_~i2~0#1 := 1 + main_#t~post31#1;havoc main_#t~post31#1; 709#L467-2 [2024-10-31 22:10:54,047 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:10:54,047 INFO L85 PathProgramCache]: Analyzing trace with hash -1716035805, now seen corresponding path program 3 times [2024-10-31 22:10:54,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:10:54,048 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263654201] [2024-10-31 22:10:54,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:10:54,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:10:54,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:54,086 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:10:54,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:54,138 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:10:54,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:10:54,139 INFO L85 PathProgramCache]: Analyzing trace with hash -382651229, now seen corresponding path program 1 times [2024-10-31 22:10:54,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:10:54,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983359009] [2024-10-31 22:10:54,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:10:54,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:10:54,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:54,194 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:10:54,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:54,249 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:10:54,249 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:10:54,253 INFO L85 PathProgramCache]: Analyzing trace with hash -706871615, now seen corresponding path program 1 times [2024-10-31 22:10:54,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:10:54,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110316325] [2024-10-31 22:10:54,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:10:54,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:10:54,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:54,359 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:10:54,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:10:54,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:11:00,031 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:11:00,032 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:11:00,033 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:11:00,033 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:11:00,033 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-31 22:11:00,033 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:11:00,033 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:11:00,033 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:11:00,033 INFO L132 ssoRankerPreferences]: Filename of dumped script: pals_lcr.6.ufo.BOUNDED-12.pals.c_Iteration4_Loop [2024-10-31 22:11:00,034 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:11:00,034 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:11:00,083 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,095 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,102 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,105 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,108 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,112 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,115 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,117 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,120 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,128 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,130 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:00,133 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,754 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,767 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:02,776 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:11:05,591 WARN L137 XnfTransformerHelper]: expecting exponential blowup for input size 36