./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:18:55,952 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:18:56,096 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:18:56,108 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:18:56,108 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:18:56,132 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:18:56,133 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:18:56,133 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:18:56,134 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:18:56,134 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:18:56,135 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:18:56,136 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:18:56,136 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:18:56,137 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:18:56,137 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:18:56,137 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:18:56,138 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:18:56,138 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:18:56,139 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:18:56,139 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:18:56,140 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:18:56,140 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:18:56,141 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:18:56,141 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:18:56,142 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:18:56,142 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:18:56,143 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:18:56,143 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:18:56,143 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:18:56,144 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:18:56,144 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:18:56,145 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:18:56,145 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:18:56,145 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:18:56,146 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:18:56,146 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:18:56,147 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:18:56,147 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:18:56,148 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:18:56,148 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2024-10-31 22:18:56,468 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:18:56,503 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:18:56,506 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:18:56,508 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:18:56,509 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:18:56,510 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i Unable to find full path for "g++" [2024-10-31 22:18:58,605 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:18:58,936 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:18:58,938 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2024-10-31 22:18:58,954 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/data/e8b02a3cc/1e7c190a84b64096b571341c398f6d45/FLAGf842d2eaf [2024-10-31 22:18:59,191 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/data/e8b02a3cc/1e7c190a84b64096b571341c398f6d45 [2024-10-31 22:18:59,193 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:18:59,195 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:18:59,197 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:18:59,197 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:18:59,203 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:18:59,204 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,205 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@38f10898 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59, skipping insertion in model container [2024-10-31 22:18:59,206 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,229 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:18:59,432 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:59,443 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:18:59,464 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:59,480 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:18:59,481 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59 WrapperNode [2024-10-31 22:18:59,481 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:18:59,482 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:59,482 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:18:59,482 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:18:59,489 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,497 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,523 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 78 [2024-10-31 22:18:59,523 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:59,524 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:18:59,524 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:18:59,525 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:18:59,540 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,540 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,543 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,563 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [2, 5]. 71 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 1 writes are split as follows [0, 1]. [2024-10-31 22:18:59,563 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,564 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,568 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,572 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,574 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,575 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,581 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:18:59,582 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:18:59,582 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:18:59,582 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:18:59,583 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (1/1) ... [2024-10-31 22:18:59,595 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:59,610 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:59,623 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:18:59,626 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:18:59,655 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:18:59,655 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:18:59,655 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2024-10-31 22:18:59,656 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-10-31 22:18:59,656 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-10-31 22:18:59,656 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-10-31 22:18:59,656 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:18:59,658 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:18:59,658 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-10-31 22:18:59,658 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-10-31 22:18:59,658 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-10-31 22:18:59,736 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:18:59,738 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:18:59,923 INFO L? ?]: Removed 18 outVars from TransFormulas that were not future-live. [2024-10-31 22:18:59,923 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:18:59,934 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:18:59,934 INFO L316 CfgBuilder]: Removed 3 assume(true) statements. [2024-10-31 22:18:59,935 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:59 BoogieIcfgContainer [2024-10-31 22:18:59,935 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:18:59,936 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:18:59,936 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:18:59,941 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:18:59,941 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:59,942 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:18:59" (1/3) ... [2024-10-31 22:18:59,944 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@40923d22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:59, skipping insertion in model container [2024-10-31 22:18:59,944 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:59,945 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:59" (2/3) ... [2024-10-31 22:18:59,945 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@40923d22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:59, skipping insertion in model container [2024-10-31 22:18:59,945 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:59,945 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:59" (3/3) ... [2024-10-31 22:18:59,947 INFO L332 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2024-10-31 22:19:00,015 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:19:00,015 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:19:00,016 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:19:00,016 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:19:00,016 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:19:00,016 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:19:00,016 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:19:00,016 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:19:00,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:00,046 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2024-10-31 22:19:00,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:00,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:00,054 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-31 22:19:00,054 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:19:00,054 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:19:00,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:00,058 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2024-10-31 22:19:00,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:00,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:00,060 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-10-31 22:19:00,060 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:19:00,070 INFO L745 eck$LassoCheckResult]: Stem: 27#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 28#L27-3true [2024-10-31 22:19:00,070 INFO L747 eck$LassoCheckResult]: Loop: 28#L27-3true assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5#L27-2true main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 28#L27-3true [2024-10-31 22:19:00,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:00,079 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-10-31 22:19:00,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:00,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506540851] [2024-10-31 22:19:00,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:00,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:00,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:00,230 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:00,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:00,265 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:00,268 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:00,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2024-10-31 22:19:00,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:00,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169614893] [2024-10-31 22:19:00,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:00,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:00,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:00,285 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:00,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:00,302 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:00,317 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:00,317 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2024-10-31 22:19:00,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:00,318 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434599775] [2024-10-31 22:19:00,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:00,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:00,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:00,360 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:00,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:00,376 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:00,756 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:19:00,757 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:19:00,757 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:19:00,757 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:19:00,757 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-31 22:19:00,758 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:00,758 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:19:00,758 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:19:00,758 INFO L132 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2024-10-31 22:19:00,758 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:19:00,759 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:19:00,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:00,789 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:00,811 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:00,816 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:00,822 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:00,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:00,829 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:01,042 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:01,047 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:01,051 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:01,058 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:01,061 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:19:01,331 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:19:01,336 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-31 22:19:01,338 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,338 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,341 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,344 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-31 22:19:01,345 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:19:01,360 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:19:01,360 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:19:01,361 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:19:01,361 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:19:01,361 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:19:01,363 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:19:01,364 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:19:01,366 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:19:01,384 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-10-31 22:19:01,386 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,386 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,388 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,390 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-31 22:19:01,391 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:19:01,407 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:19:01,407 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:19:01,407 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:19:01,407 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:19:01,413 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:19:01,413 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:19:01,424 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:19:01,448 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-10-31 22:19:01,449 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,449 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,451 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,453 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-31 22:19:01,454 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:19:01,468 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:19:01,468 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:19:01,468 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:19:01,469 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:19:01,472 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:19:01,472 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:19:01,478 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:19:01,496 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-10-31 22:19:01,498 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,498 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,500 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,503 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-31 22:19:01,504 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:19:01,518 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:19:01,518 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:19:01,518 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:19:01,519 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:19:01,519 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:19:01,520 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:19:01,520 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:19:01,522 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:19:01,540 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-10-31 22:19:01,541 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,541 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,543 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,545 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-10-31 22:19:01,546 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:19:01,561 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:19:01,561 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:19:01,561 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:19:01,561 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:19:01,562 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:19:01,563 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:19:01,563 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:19:01,569 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:19:01,587 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-10-31 22:19:01,587 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,588 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,590 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,592 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-10-31 22:19:01,593 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:19:01,607 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:19:01,607 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:19:01,607 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:19:01,607 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:19:01,608 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:19:01,609 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:19:01,609 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:19:01,614 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:19:01,632 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-10-31 22:19:01,632 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,633 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,635 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,636 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-10-31 22:19:01,638 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:19:01,652 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:19:01,652 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:19:01,652 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:19:01,653 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:19:01,653 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:19:01,654 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:19:01,654 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:19:01,660 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:19:01,678 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-10-31 22:19:01,680 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,681 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,683 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,685 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-10-31 22:19:01,687 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:19:01,701 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:19:01,701 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:19:01,701 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:19:01,702 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:19:01,705 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:19:01,705 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:19:01,711 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:19:01,729 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-10-31 22:19:01,730 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,730 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,732 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,760 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-10-31 22:19:01,760 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:19:01,777 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:19:01,778 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:19:01,778 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:19:01,780 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:19:01,789 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-10-31 22:19:01,794 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-10-31 22:19:01,809 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-31 22:19:01,828 INFO L443 ModelExtractionUtils]: Simplification made 7 calls to the SMT solver. [2024-10-31 22:19:01,829 INFO L444 ModelExtractionUtils]: 5 out of 16 variables were initially zero. Simplification set additionally 7 variables to zero. [2024-10-31 22:19:01,831 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:19:01,831 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:01,842 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:19:01,844 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-10-31 22:19:01,845 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-31 22:19:01,860 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2024-10-31 22:19:01,860 INFO L474 LassoAnalysis]: Proved termination. [2024-10-31 22:19:01,861 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~#array~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~#array~0#1.offset Supporting invariants [] [2024-10-31 22:19:01,880 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2024-10-31 22:19:01,901 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2024-10-31 22:19:01,910 WARN L976 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2024-10-31 22:19:01,911 WARN L976 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2024-10-31 22:19:01,912 WARN L976 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: ~#array~0!offset [2024-10-31 22:19:01,940 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:01,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:01,958 INFO L255 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:19:01,959 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:01,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:01,979 INFO L255 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-31 22:19:01,979 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:02,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:02,047 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-10-31 22:19:02,050 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:02,096 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 54 states and 77 transitions. Complement of second has 6 states. [2024-10-31 22:19:02,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:19:02,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:02,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 38 transitions. [2024-10-31 22:19:02,105 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 38 transitions. Stem has 2 letters. Loop has 2 letters. [2024-10-31 22:19:02,105 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:19:02,105 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 38 transitions. Stem has 4 letters. Loop has 2 letters. [2024-10-31 22:19:02,105 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:19:02,105 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 38 transitions. Stem has 2 letters. Loop has 4 letters. [2024-10-31 22:19:02,105 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:19:02,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 77 transitions. [2024-10-31 22:19:02,109 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2024-10-31 22:19:02,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 25 states and 35 transitions. [2024-10-31 22:19:02,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2024-10-31 22:19:02,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2024-10-31 22:19:02,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 35 transitions. [2024-10-31 22:19:02,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:02,115 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2024-10-31 22:19:02,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 35 transitions. [2024-10-31 22:19:02,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2024-10-31 22:19:02,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.4) internal successors, (35), 24 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:02,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2024-10-31 22:19:02,145 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2024-10-31 22:19:02,146 INFO L425 stractBuchiCegarLoop]: Abstraction has 25 states and 35 transitions. [2024-10-31 22:19:02,146 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:19:02,146 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 35 transitions. [2024-10-31 22:19:02,147 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2024-10-31 22:19:02,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:02,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:02,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2024-10-31 22:19:02,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:02,148 INFO L745 eck$LassoCheckResult]: Stem: 157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 146#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 149#L27-4 main_~i~0#1 := 0; 150#L32-3 [2024-10-31 22:19:02,148 INFO L747 eck$LassoCheckResult]: Loop: 150#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 155#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 144#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 150#L32-3 [2024-10-31 22:19:02,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:02,148 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2024-10-31 22:19:02,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:02,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910785606] [2024-10-31 22:19:02,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:02,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:02,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:02,159 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:02,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:02,167 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:02,168 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:02,168 INFO L85 PathProgramCache]: Analyzing trace with hash 54361, now seen corresponding path program 1 times [2024-10-31 22:19:02,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:02,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300916489] [2024-10-31 22:19:02,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:02,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:02,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:02,182 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:02,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:02,199 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:02,200 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:02,200 INFO L85 PathProgramCache]: Analyzing trace with hash 1807958031, now seen corresponding path program 1 times [2024-10-31 22:19:02,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:02,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936425541] [2024-10-31 22:19:02,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:02,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:02,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:02,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:02,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:02,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936425541] [2024-10-31 22:19:02,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936425541] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:19:02,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:19:02,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:19:02,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139329486] [2024-10-31 22:19:02,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:19:02,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:02,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:19:02,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:19:02,482 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. cyclomatic complexity: 13 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:02,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:02,559 INFO L93 Difference]: Finished difference Result 44 states and 51 transitions. [2024-10-31 22:19:02,560 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 51 transitions. [2024-10-31 22:19:02,561 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:02,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 32 states and 38 transitions. [2024-10-31 22:19:02,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2024-10-31 22:19:02,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2024-10-31 22:19:02,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2024-10-31 22:19:02,563 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:02,563 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2024-10-31 22:19:02,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2024-10-31 22:19:02,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2024-10-31 22:19:02,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.2) internal successors, (24), 19 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:02,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2024-10-31 22:19:02,565 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 24 transitions. [2024-10-31 22:19:02,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:19:02,567 INFO L425 stractBuchiCegarLoop]: Abstraction has 20 states and 24 transitions. [2024-10-31 22:19:02,567 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:19:02,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 24 transitions. [2024-10-31 22:19:02,568 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:02,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:02,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:02,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:19:02,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:02,568 INFO L745 eck$LassoCheckResult]: Stem: 231#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 220#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 223#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 224#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 225#L27-4 main_~i~0#1 := 0; 226#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 230#L34 [2024-10-31 22:19:02,569 INFO L747 eck$LassoCheckResult]: Loop: 230#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 218#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 227#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 230#L34 [2024-10-31 22:19:02,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:02,569 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2024-10-31 22:19:02,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:02,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84688726] [2024-10-31 22:19:02,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:02,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:02,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:02,584 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:02,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:02,596 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:02,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:02,596 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 2 times [2024-10-31 22:19:02,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:02,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [939334136] [2024-10-31 22:19:02,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:02,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:02,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:02,608 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:02,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:02,628 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:02,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:02,631 INFO L85 PathProgramCache]: Analyzing trace with hash 1436021995, now seen corresponding path program 1 times [2024-10-31 22:19:02,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:02,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1133334965] [2024-10-31 22:19:02,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:02,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:02,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:02,772 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:02,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:02,773 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1133334965] [2024-10-31 22:19:02,773 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1133334965] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:02,773 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1534356580] [2024-10-31 22:19:02,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:02,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:02,774 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:02,776 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:02,777 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-10-31 22:19:02,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:02,832 INFO L255 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-10-31 22:19:02,833 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:02,910 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:02,911 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:02,966 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:02,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1534356580] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:02,966 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:02,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2024-10-31 22:19:02,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074261624] [2024-10-31 22:19:02,967 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:03,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:03,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-10-31 22:19:03,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2024-10-31 22:19:03,033 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. cyclomatic complexity: 7 Second operand has 11 states, 10 states have (on average 2.2) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:03,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:03,164 INFO L93 Difference]: Finished difference Result 62 states and 73 transitions. [2024-10-31 22:19:03,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 73 transitions. [2024-10-31 22:19:03,192 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:03,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 46 states and 54 transitions. [2024-10-31 22:19:03,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2024-10-31 22:19:03,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2024-10-31 22:19:03,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 54 transitions. [2024-10-31 22:19:03,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:03,194 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46 states and 54 transitions. [2024-10-31 22:19:03,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 54 transitions. [2024-10-31 22:19:03,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 28. [2024-10-31 22:19:03,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1785714285714286) internal successors, (33), 27 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:03,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2024-10-31 22:19:03,206 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-10-31 22:19:03,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-10-31 22:19:03,209 INFO L425 stractBuchiCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-10-31 22:19:03,209 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:19:03,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 33 transitions. [2024-10-31 22:19:03,210 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:03,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:03,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:03,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1] [2024-10-31 22:19:03,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:03,211 INFO L745 eck$LassoCheckResult]: Stem: 386#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 373#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 374#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 387#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 388#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 377#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 378#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 379#L27-4 main_~i~0#1 := 0; 380#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 392#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 381#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 382#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 385#L34 [2024-10-31 22:19:03,211 INFO L747 eck$LassoCheckResult]: Loop: 385#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 372#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 390#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 385#L34 [2024-10-31 22:19:03,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:03,212 INFO L85 PathProgramCache]: Analyzing trace with hash 780824429, now seen corresponding path program 2 times [2024-10-31 22:19:03,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:03,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995877549] [2024-10-31 22:19:03,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:03,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:03,244 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-10-31 22:19:03,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:03,250 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:03,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:03,276 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:03,276 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:03,277 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 3 times [2024-10-31 22:19:03,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:03,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177624788] [2024-10-31 22:19:03,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:03,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:03,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:03,283 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:03,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:03,294 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:03,294 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:03,294 INFO L85 PathProgramCache]: Analyzing trace with hash -2264087, now seen corresponding path program 3 times [2024-10-31 22:19:03,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:03,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789060745] [2024-10-31 22:19:03,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:03,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:03,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:03,468 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:03,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:03,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [789060745] [2024-10-31 22:19:03,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [789060745] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:03,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [670821283] [2024-10-31 22:19:03,469 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-31 22:19:03,469 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:03,469 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:03,471 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:03,472 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-10-31 22:19:03,543 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2024-10-31 22:19:03,543 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:19:03,546 INFO L255 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-10-31 22:19:03,547 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:03,669 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:03,669 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:03,764 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:03,765 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [670821283] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:03,765 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:03,765 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2024-10-31 22:19:03,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717804519] [2024-10-31 22:19:03,766 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:03,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:03,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2024-10-31 22:19:03,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2024-10-31 22:19:03,837 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. cyclomatic complexity: 8 Second operand has 14 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 14 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:04,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:04,051 INFO L93 Difference]: Finished difference Result 88 states and 103 transitions. [2024-10-31 22:19:04,051 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 103 transitions. [2024-10-31 22:19:04,053 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:04,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 60 states and 70 transitions. [2024-10-31 22:19:04,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2024-10-31 22:19:04,057 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2024-10-31 22:19:04,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 70 transitions. [2024-10-31 22:19:04,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:04,057 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 70 transitions. [2024-10-31 22:19:04,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 70 transitions. [2024-10-31 22:19:04,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 36. [2024-10-31 22:19:04,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.1666666666666667) internal successors, (42), 35 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:04,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 42 transitions. [2024-10-31 22:19:04,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 42 transitions. [2024-10-31 22:19:04,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-10-31 22:19:04,064 INFO L425 stractBuchiCegarLoop]: Abstraction has 36 states and 42 transitions. [2024-10-31 22:19:04,064 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:19:04,065 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 42 transitions. [2024-10-31 22:19:04,066 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:04,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:04,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:04,068 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1] [2024-10-31 22:19:04,069 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:04,069 INFO L745 eck$LassoCheckResult]: Stem: 610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 596#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 597#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 611#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 612#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 600#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 601#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 616#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 615#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 602#L27-4 main_~i~0#1 := 0; 603#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 624#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 604#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 605#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 609#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 618#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 623#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 608#L34 [2024-10-31 22:19:04,069 INFO L747 eck$LassoCheckResult]: Loop: 608#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 595#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 614#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 608#L34 [2024-10-31 22:19:04,069 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:04,069 INFO L85 PathProgramCache]: Analyzing trace with hash -79873369, now seen corresponding path program 4 times [2024-10-31 22:19:04,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:04,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854195071] [2024-10-31 22:19:04,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:04,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:04,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:04,097 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:04,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:04,127 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:04,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:04,127 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 4 times [2024-10-31 22:19:04,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:04,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801685618] [2024-10-31 22:19:04,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:04,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:04,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:04,136 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:04,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:04,144 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:04,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:04,145 INFO L85 PathProgramCache]: Analyzing trace with hash -95607185, now seen corresponding path program 5 times [2024-10-31 22:19:04,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:04,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149852727] [2024-10-31 22:19:04,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:04,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:04,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:04,400 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 5 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:04,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:04,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149852727] [2024-10-31 22:19:04,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149852727] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:04,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1680161198] [2024-10-31 22:19:04,401 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-31 22:19:04,401 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:04,401 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:04,410 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:04,413 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-10-31 22:19:04,517 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2024-10-31 22:19:04,518 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:19:04,519 INFO L255 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-10-31 22:19:04,521 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:04,677 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:04,677 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:04,790 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:04,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1680161198] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:04,791 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:04,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2024-10-31 22:19:04,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [51913180] [2024-10-31 22:19:04,792 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:04,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:04,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2024-10-31 22:19:04,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=197, Unknown=0, NotChecked=0, Total=272 [2024-10-31 22:19:04,868 INFO L87 Difference]: Start difference. First operand 36 states and 42 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.375) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:05,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:05,132 INFO L93 Difference]: Finished difference Result 114 states and 133 transitions. [2024-10-31 22:19:05,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114 states and 133 transitions. [2024-10-31 22:19:05,134 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:05,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114 states to 74 states and 86 transitions. [2024-10-31 22:19:05,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2024-10-31 22:19:05,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2024-10-31 22:19:05,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 86 transitions. [2024-10-31 22:19:05,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:05,139 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2024-10-31 22:19:05,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 86 transitions. [2024-10-31 22:19:05,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 44. [2024-10-31 22:19:05,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.1590909090909092) internal successors, (51), 43 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:05,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2024-10-31 22:19:05,143 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 51 transitions. [2024-10-31 22:19:05,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-10-31 22:19:05,144 INFO L425 stractBuchiCegarLoop]: Abstraction has 44 states and 51 transitions. [2024-10-31 22:19:05,145 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:19:05,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 51 transitions. [2024-10-31 22:19:05,146 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:05,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:05,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:05,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1] [2024-10-31 22:19:05,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:05,147 INFO L745 eck$LassoCheckResult]: Stem: 904#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 889#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 902#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 903#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 892#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 893#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 913#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 912#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 909#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 908#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 894#L27-4 main_~i~0#1 := 0; 895#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 900#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 887#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 897#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 923#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 921#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 920#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 917#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 915#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 907#L34 [2024-10-31 22:19:05,147 INFO L747 eck$LassoCheckResult]: Loop: 907#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 910#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 906#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 907#L34 [2024-10-31 22:19:05,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:05,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1712449137, now seen corresponding path program 6 times [2024-10-31 22:19:05,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:05,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162056555] [2024-10-31 22:19:05,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:05,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:05,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:05,175 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:05,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:05,199 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:05,200 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:05,200 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 5 times [2024-10-31 22:19:05,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:05,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268441643] [2024-10-31 22:19:05,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:05,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:05,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:05,205 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:05,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:05,210 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:05,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:05,211 INFO L85 PathProgramCache]: Analyzing trace with hash -49254811, now seen corresponding path program 7 times [2024-10-31 22:19:05,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:05,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814212327] [2024-10-31 22:19:05,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:05,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:05,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:05,440 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 12 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:05,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:05,441 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814212327] [2024-10-31 22:19:05,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814212327] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:05,441 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1035728845] [2024-10-31 22:19:05,441 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-31 22:19:05,442 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:05,442 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:05,444 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:05,446 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-10-31 22:19:05,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:05,521 INFO L255 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-10-31 22:19:05,523 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:05,709 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:05,710 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:05,855 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:05,855 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1035728845] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:05,855 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:05,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2024-10-31 22:19:05,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822698361] [2024-10-31 22:19:05,856 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:05,920 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:05,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2024-10-31 22:19:05,921 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=279, Unknown=0, NotChecked=0, Total=380 [2024-10-31 22:19:05,921 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. cyclomatic complexity: 10 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:06,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:06,226 INFO L93 Difference]: Finished difference Result 140 states and 163 transitions. [2024-10-31 22:19:06,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 163 transitions. [2024-10-31 22:19:06,227 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:06,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 88 states and 102 transitions. [2024-10-31 22:19:06,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2024-10-31 22:19:06,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2024-10-31 22:19:06,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 102 transitions. [2024-10-31 22:19:06,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:06,229 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88 states and 102 transitions. [2024-10-31 22:19:06,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 102 transitions. [2024-10-31 22:19:06,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 52. [2024-10-31 22:19:06,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1538461538461537) internal successors, (60), 51 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:06,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 60 transitions. [2024-10-31 22:19:06,232 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 60 transitions. [2024-10-31 22:19:06,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-10-31 22:19:06,233 INFO L425 stractBuchiCegarLoop]: Abstraction has 52 states and 60 transitions. [2024-10-31 22:19:06,234 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:19:06,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 60 transitions. [2024-10-31 22:19:06,234 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:06,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:06,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:06,235 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1] [2024-10-31 22:19:06,235 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:06,235 INFO L745 eck$LassoCheckResult]: Stem: 1264#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1250#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1265#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1266#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1253#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1254#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1277#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1276#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1275#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1274#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1271#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1270#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1255#L27-4 main_~i~0#1 := 0; 1256#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1261#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1248#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1258#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1263#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1291#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1290#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1287#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1285#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1284#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1281#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1279#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1278#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1269#L34 [2024-10-31 22:19:06,235 INFO L747 eck$LassoCheckResult]: Loop: 1269#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1272#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1268#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1269#L34 [2024-10-31 22:19:06,236 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:06,236 INFO L85 PathProgramCache]: Analyzing trace with hash -240296029, now seen corresponding path program 8 times [2024-10-31 22:19:06,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:06,236 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248885027] [2024-10-31 22:19:06,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:06,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:06,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:06,285 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:06,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:06,309 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:06,309 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:06,309 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 6 times [2024-10-31 22:19:06,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:06,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662018905] [2024-10-31 22:19:06,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:06,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:06,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:06,316 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:06,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:06,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:06,323 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:06,323 INFO L85 PathProgramCache]: Analyzing trace with hash 1051529203, now seen corresponding path program 9 times [2024-10-31 22:19:06,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:06,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612736198] [2024-10-31 22:19:06,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:06,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:06,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:06,625 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 22 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:06,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:06,625 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612736198] [2024-10-31 22:19:06,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1612736198] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:06,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1535169466] [2024-10-31 22:19:06,626 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-31 22:19:06,626 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:06,626 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:06,630 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:06,633 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-10-31 22:19:06,715 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2024-10-31 22:19:06,715 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:19:06,717 INFO L255 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjuncts are in the unsatisfiable core [2024-10-31 22:19:06,719 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:06,930 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:06,930 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:07,121 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:07,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1535169466] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:07,122 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:07,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2024-10-31 22:19:07,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964700220] [2024-10-31 22:19:07,122 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:07,181 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:07,182 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2024-10-31 22:19:07,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=375, Unknown=0, NotChecked=0, Total=506 [2024-10-31 22:19:07,183 INFO L87 Difference]: Start difference. First operand 52 states and 60 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.4545454545454546) internal successors, (54), 23 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:07,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:07,501 INFO L93 Difference]: Finished difference Result 166 states and 193 transitions. [2024-10-31 22:19:07,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 166 states and 193 transitions. [2024-10-31 22:19:07,503 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:07,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 166 states to 102 states and 118 transitions. [2024-10-31 22:19:07,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2024-10-31 22:19:07,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2024-10-31 22:19:07,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 118 transitions. [2024-10-31 22:19:07,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:07,505 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102 states and 118 transitions. [2024-10-31 22:19:07,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 118 transitions. [2024-10-31 22:19:07,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 60. [2024-10-31 22:19:07,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.15) internal successors, (69), 59 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:07,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 69 transitions. [2024-10-31 22:19:07,509 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 69 transitions. [2024-10-31 22:19:07,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-10-31 22:19:07,510 INFO L425 stractBuchiCegarLoop]: Abstraction has 60 states and 69 transitions. [2024-10-31 22:19:07,510 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:19:07,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 69 transitions. [2024-10-31 22:19:07,510 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:07,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:07,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:07,511 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1] [2024-10-31 22:19:07,511 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:07,511 INFO L745 eck$LassoCheckResult]: Stem: 1695#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1680#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1696#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1697#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1683#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1710#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1708#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1707#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1706#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1702#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1701#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1685#L27-4 main_~i~0#1 := 0; 1686#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1692#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1678#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1689#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1694#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1729#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1726#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1723#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1720#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1718#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1717#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1714#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1712#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1711#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1700#L34 [2024-10-31 22:19:07,511 INFO L747 eck$LassoCheckResult]: Loop: 1700#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 1703#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 1699#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1700#L34 [2024-10-31 22:19:07,512 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:07,512 INFO L85 PathProgramCache]: Analyzing trace with hash 1967863157, now seen corresponding path program 10 times [2024-10-31 22:19:07,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:07,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922217210] [2024-10-31 22:19:07,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:07,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:07,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:07,546 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:07,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:07,576 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:07,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:07,577 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 7 times [2024-10-31 22:19:07,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:07,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771882305] [2024-10-31 22:19:07,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:07,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:07,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:07,580 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:07,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:07,584 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:07,585 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:07,585 INFO L85 PathProgramCache]: Analyzing trace with hash -1692233503, now seen corresponding path program 11 times [2024-10-31 22:19:07,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:07,585 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024906438] [2024-10-31 22:19:07,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:07,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:07,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:07,952 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 35 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:07,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:07,953 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024906438] [2024-10-31 22:19:07,953 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024906438] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:07,953 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1872264888] [2024-10-31 22:19:07,953 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-31 22:19:07,953 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:07,953 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:07,956 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:07,959 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-10-31 22:19:08,126 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2024-10-31 22:19:08,126 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:19:08,128 INFO L255 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-10-31 22:19:08,130 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:08,396 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:08,396 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:08,600 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:08,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1872264888] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:08,601 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:08,601 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2024-10-31 22:19:08,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [5570177] [2024-10-31 22:19:08,601 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:08,662 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:08,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2024-10-31 22:19:08,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=485, Unknown=0, NotChecked=0, Total=650 [2024-10-31 22:19:08,663 INFO L87 Difference]: Start difference. First operand 60 states and 69 transitions. cyclomatic complexity: 12 Second operand has 26 states, 25 states have (on average 2.48) internal successors, (62), 26 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:09,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:09,144 INFO L93 Difference]: Finished difference Result 192 states and 223 transitions. [2024-10-31 22:19:09,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192 states and 223 transitions. [2024-10-31 22:19:09,145 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:09,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192 states to 116 states and 134 transitions. [2024-10-31 22:19:09,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2024-10-31 22:19:09,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2024-10-31 22:19:09,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 134 transitions. [2024-10-31 22:19:09,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:09,151 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 134 transitions. [2024-10-31 22:19:09,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 134 transitions. [2024-10-31 22:19:09,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 68. [2024-10-31 22:19:09,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1470588235294117) internal successors, (78), 67 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:09,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 78 transitions. [2024-10-31 22:19:09,156 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 78 transitions. [2024-10-31 22:19:09,157 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2024-10-31 22:19:09,158 INFO L425 stractBuchiCegarLoop]: Abstraction has 68 states and 78 transitions. [2024-10-31 22:19:09,158 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:19:09,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 78 transitions. [2024-10-31 22:19:09,159 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:09,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:09,159 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:09,160 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1] [2024-10-31 22:19:09,160 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:09,160 INFO L745 eck$LassoCheckResult]: Stem: 2194#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2178#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2179#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2195#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2196#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2182#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2183#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2211#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2210#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2209#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2208#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2207#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2206#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2205#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2204#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2201#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2200#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2184#L27-4 main_~i~0#1 := 0; 2185#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2191#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2177#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2188#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2193#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2236#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2235#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2233#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2230#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2229#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2227#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2224#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2223#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2221#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2219#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2218#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2215#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2213#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2212#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2199#L34 [2024-10-31 22:19:09,160 INFO L747 eck$LassoCheckResult]: Loop: 2199#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2202#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2198#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2199#L34 [2024-10-31 22:19:09,161 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:09,161 INFO L85 PathProgramCache]: Analyzing trace with hash -664171361, now seen corresponding path program 12 times [2024-10-31 22:19:09,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:09,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594366046] [2024-10-31 22:19:09,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:09,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:09,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:09,228 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:09,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:09,273 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:09,273 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:09,273 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 8 times [2024-10-31 22:19:09,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:09,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1475552775] [2024-10-31 22:19:09,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:09,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:09,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:09,277 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:09,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:09,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:09,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:09,282 INFO L85 PathProgramCache]: Analyzing trace with hash 585363831, now seen corresponding path program 13 times [2024-10-31 22:19:09,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:09,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916543665] [2024-10-31 22:19:09,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:09,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:09,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:09,825 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:09,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:09,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916543665] [2024-10-31 22:19:09,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1916543665] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:09,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [893900137] [2024-10-31 22:19:09,826 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-31 22:19:09,826 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:09,827 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:09,829 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:09,832 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-10-31 22:19:09,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:09,923 INFO L255 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-10-31 22:19:09,925 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:10,258 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:10,258 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:10,507 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:10,507 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [893900137] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:10,508 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:10,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2024-10-31 22:19:10,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854154019] [2024-10-31 22:19:10,508 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:10,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:10,567 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2024-10-31 22:19:10,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=609, Unknown=0, NotChecked=0, Total=812 [2024-10-31 22:19:10,568 INFO L87 Difference]: Start difference. First operand 68 states and 78 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 2.5) internal successors, (70), 29 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:10,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:10,997 INFO L93 Difference]: Finished difference Result 218 states and 253 transitions. [2024-10-31 22:19:10,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 253 transitions. [2024-10-31 22:19:10,999 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:11,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 130 states and 150 transitions. [2024-10-31 22:19:11,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2024-10-31 22:19:11,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2024-10-31 22:19:11,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 150 transitions. [2024-10-31 22:19:11,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:11,002 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130 states and 150 transitions. [2024-10-31 22:19:11,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 150 transitions. [2024-10-31 22:19:11,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 76. [2024-10-31 22:19:11,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.144736842105263) internal successors, (87), 75 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:11,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 87 transitions. [2024-10-31 22:19:11,009 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 87 transitions. [2024-10-31 22:19:11,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2024-10-31 22:19:11,011 INFO L425 stractBuchiCegarLoop]: Abstraction has 76 states and 87 transitions. [2024-10-31 22:19:11,011 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:19:11,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 87 transitions. [2024-10-31 22:19:11,012 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:11,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:11,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:11,013 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1] [2024-10-31 22:19:11,013 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:11,013 INFO L745 eck$LassoCheckResult]: Stem: 2762#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2746#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2747#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2763#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2764#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2750#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2751#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2781#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2780#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2779#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2778#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2777#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2776#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2775#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2774#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2773#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2772#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2769#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2768#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2752#L27-4 main_~i~0#1 := 0; 2753#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2759#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2745#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2756#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2761#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2812#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2811#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2809#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2806#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2805#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2803#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2800#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2799#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2797#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2794#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2791#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2789#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2788#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2785#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2783#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2782#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2767#L34 [2024-10-31 22:19:11,013 INFO L747 eck$LassoCheckResult]: Loop: 2767#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 2770#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 2766#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2767#L34 [2024-10-31 22:19:11,013 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:11,014 INFO L85 PathProgramCache]: Analyzing trace with hash -704996231, now seen corresponding path program 14 times [2024-10-31 22:19:11,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:11,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484264001] [2024-10-31 22:19:11,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:11,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:11,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:11,085 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:11,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:11,124 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:11,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:11,125 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 9 times [2024-10-31 22:19:11,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:11,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804441426] [2024-10-31 22:19:11,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:11,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:11,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:11,129 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:11,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:11,133 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:11,134 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:11,134 INFO L85 PathProgramCache]: Analyzing trace with hash -152593571, now seen corresponding path program 15 times [2024-10-31 22:19:11,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:11,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969242783] [2024-10-31 22:19:11,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:11,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:11,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:11,686 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 70 proven. 86 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:11,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:11,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969242783] [2024-10-31 22:19:11,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969242783] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:11,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2124107066] [2024-10-31 22:19:11,687 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-31 22:19:11,688 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:11,688 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:11,690 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:11,693 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-10-31 22:19:11,839 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2024-10-31 22:19:11,839 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:19:11,841 INFO L255 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-10-31 22:19:11,843 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:12,283 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:12,283 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:12,556 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:12,556 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2124107066] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:12,556 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:12,556 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2024-10-31 22:19:12,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063214179] [2024-10-31 22:19:12,557 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:12,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:12,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2024-10-31 22:19:12,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=747, Unknown=0, NotChecked=0, Total=992 [2024-10-31 22:19:12,644 INFO L87 Difference]: Start difference. First operand 76 states and 87 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 32 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:13,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:13,257 INFO L93 Difference]: Finished difference Result 244 states and 283 transitions. [2024-10-31 22:19:13,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244 states and 283 transitions. [2024-10-31 22:19:13,259 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:13,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244 states to 144 states and 166 transitions. [2024-10-31 22:19:13,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125 [2024-10-31 22:19:13,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125 [2024-10-31 22:19:13,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 166 transitions. [2024-10-31 22:19:13,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:13,261 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 166 transitions. [2024-10-31 22:19:13,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 166 transitions. [2024-10-31 22:19:13,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 84. [2024-10-31 22:19:13,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.1428571428571428) internal successors, (96), 83 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:13,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2024-10-31 22:19:13,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84 states and 96 transitions. [2024-10-31 22:19:13,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2024-10-31 22:19:13,268 INFO L425 stractBuchiCegarLoop]: Abstraction has 84 states and 96 transitions. [2024-10-31 22:19:13,268 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:19:13,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 96 transitions. [2024-10-31 22:19:13,269 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:13,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:13,270 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:13,271 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1] [2024-10-31 22:19:13,271 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:13,271 INFO L745 eck$LassoCheckResult]: Stem: 3399#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 3383#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 3384#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3400#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3401#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3387#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3388#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3420#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3419#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3418#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3417#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3416#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3415#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3414#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3413#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3412#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3411#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3410#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3409#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 3406#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3405#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 3389#L27-4 main_~i~0#1 := 0; 3390#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3396#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3382#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3398#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3457#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3456#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3454#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3451#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3450#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3448#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3445#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3444#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3442#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3439#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3438#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3436#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3433#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3432#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3430#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3428#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3427#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3424#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3422#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3421#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3404#L34 [2024-10-31 22:19:13,271 INFO L747 eck$LassoCheckResult]: Loop: 3404#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 3407#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 3403#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3404#L34 [2024-10-31 22:19:13,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:13,272 INFO L85 PathProgramCache]: Analyzing trace with hash -1850900069, now seen corresponding path program 16 times [2024-10-31 22:19:13,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:13,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547400787] [2024-10-31 22:19:13,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:13,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:13,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:13,343 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:13,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:13,408 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:13,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:13,412 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 10 times [2024-10-31 22:19:13,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:13,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446664617] [2024-10-31 22:19:13,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:13,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:13,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:13,420 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:13,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:13,428 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:13,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:13,430 INFO L85 PathProgramCache]: Analyzing trace with hash -1373762821, now seen corresponding path program 17 times [2024-10-31 22:19:13,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:13,431 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379767213] [2024-10-31 22:19:13,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:13,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:13,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:14,048 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 92 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:14,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:14,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [379767213] [2024-10-31 22:19:14,049 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [379767213] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:14,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1051378418] [2024-10-31 22:19:14,049 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-31 22:19:14,050 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:14,050 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:14,052 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:14,059 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-10-31 22:19:14,366 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2024-10-31 22:19:14,367 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:19:14,368 INFO L255 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-10-31 22:19:14,370 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:14,818 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:14,819 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:15,186 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:15,187 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1051378418] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:15,187 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:15,187 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2024-10-31 22:19:15,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402633894] [2024-10-31 22:19:15,187 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:15,254 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:15,255 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2024-10-31 22:19:15,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=899, Unknown=0, NotChecked=0, Total=1190 [2024-10-31 22:19:15,256 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.5294117647058822) internal successors, (86), 35 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:15,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:15,946 INFO L93 Difference]: Finished difference Result 270 states and 313 transitions. [2024-10-31 22:19:15,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 313 transitions. [2024-10-31 22:19:15,949 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:15,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 158 states and 182 transitions. [2024-10-31 22:19:15,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137 [2024-10-31 22:19:15,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2024-10-31 22:19:15,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 182 transitions. [2024-10-31 22:19:15,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:15,955 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 182 transitions. [2024-10-31 22:19:15,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 182 transitions. [2024-10-31 22:19:15,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 92. [2024-10-31 22:19:15,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.141304347826087) internal successors, (105), 91 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:15,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 105 transitions. [2024-10-31 22:19:15,968 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 105 transitions. [2024-10-31 22:19:15,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2024-10-31 22:19:15,972 INFO L425 stractBuchiCegarLoop]: Abstraction has 92 states and 105 transitions. [2024-10-31 22:19:15,973 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:19:15,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 105 transitions. [2024-10-31 22:19:15,974 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:15,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:15,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:15,975 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1] [2024-10-31 22:19:15,975 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:15,979 INFO L745 eck$LassoCheckResult]: Stem: 4105#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4090#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4106#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4107#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4093#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4094#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4128#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4127#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4126#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4125#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4124#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4123#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4122#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4121#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4120#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4119#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4118#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4117#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4116#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4115#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4112#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4111#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4095#L27-4 main_~i~0#1 := 0; 4096#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4102#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4088#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4099#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4104#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4171#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4170#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4168#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4165#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4164#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4162#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4159#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4158#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4156#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4153#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4152#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4150#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4147#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4146#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4144#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4141#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4138#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4136#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4135#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4132#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4130#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4129#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4110#L34 [2024-10-31 22:19:15,979 INFO L747 eck$LassoCheckResult]: Loop: 4110#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4113#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4109#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4110#L34 [2024-10-31 22:19:15,980 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:15,980 INFO L85 PathProgramCache]: Analyzing trace with hash -354133123, now seen corresponding path program 18 times [2024-10-31 22:19:15,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:15,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150041614] [2024-10-31 22:19:15,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:15,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:16,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:16,072 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:16,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:16,150 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:16,150 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:16,151 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 11 times [2024-10-31 22:19:16,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:16,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736137073] [2024-10-31 22:19:16,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:16,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:16,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:16,156 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:16,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:16,160 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:16,160 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:16,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1540141607, now seen corresponding path program 19 times [2024-10-31 22:19:16,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:16,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134793441] [2024-10-31 22:19:16,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:16,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:16,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:16,916 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 117 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:16,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:16,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134793441] [2024-10-31 22:19:16,916 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134793441] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:16,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2056281376] [2024-10-31 22:19:16,917 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-10-31 22:19:16,917 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:16,918 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:16,920 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:16,922 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-10-31 22:19:17,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:17,044 INFO L255 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-10-31 22:19:17,046 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:17,582 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:17,582 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:17,949 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:17,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2056281376] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:17,949 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:17,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2024-10-31 22:19:17,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788180502] [2024-10-31 22:19:17,949 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:18,011 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:18,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2024-10-31 22:19:18,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=1065, Unknown=0, NotChecked=0, Total=1406 [2024-10-31 22:19:18,013 INFO L87 Difference]: Start difference. First operand 92 states and 105 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.5405405405405403) internal successors, (94), 38 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:18,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:18,911 INFO L93 Difference]: Finished difference Result 296 states and 343 transitions. [2024-10-31 22:19:18,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 296 states and 343 transitions. [2024-10-31 22:19:18,913 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:18,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 296 states to 172 states and 198 transitions. [2024-10-31 22:19:18,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2024-10-31 22:19:18,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2024-10-31 22:19:18,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 198 transitions. [2024-10-31 22:19:18,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:18,916 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172 states and 198 transitions. [2024-10-31 22:19:18,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 198 transitions. [2024-10-31 22:19:18,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 100. [2024-10-31 22:19:18,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.14) internal successors, (114), 99 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:18,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 114 transitions. [2024-10-31 22:19:18,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 114 transitions. [2024-10-31 22:19:18,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2024-10-31 22:19:18,946 INFO L425 stractBuchiCegarLoop]: Abstraction has 100 states and 114 transitions. [2024-10-31 22:19:18,946 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:19:18,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 114 transitions. [2024-10-31 22:19:18,948 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:18,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:18,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:18,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1] [2024-10-31 22:19:18,954 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:18,954 INFO L745 eck$LassoCheckResult]: Stem: 4880#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4865#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4881#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4882#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4868#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4869#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4905#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4904#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4903#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4902#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4901#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4900#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4899#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4898#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4897#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4896#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4895#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4894#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4893#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4892#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4891#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4890#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 4887#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 4886#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4870#L27-4 main_~i~0#1 := 0; 4871#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4877#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4863#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4874#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4879#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4954#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4953#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4951#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4948#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4947#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4945#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4942#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4941#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4939#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4936#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4935#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4933#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4930#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4929#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4927#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4924#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4923#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4921#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4918#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4917#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4915#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4913#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4912#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4909#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4907#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4906#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4885#L34 [2024-10-31 22:19:18,955 INFO L747 eck$LassoCheckResult]: Loop: 4885#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 4888#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 4884#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4885#L34 [2024-10-31 22:19:18,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:18,955 INFO L85 PathProgramCache]: Analyzing trace with hash -726335849, now seen corresponding path program 20 times [2024-10-31 22:19:18,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:18,956 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595438686] [2024-10-31 22:19:18,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:18,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:19,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:19,055 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:19,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:19,116 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:19,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:19,117 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 12 times [2024-10-31 22:19:19,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:19,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686225020] [2024-10-31 22:19:19,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:19,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:19,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:19,121 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:19,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:19,126 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:19,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:19,127 INFO L85 PathProgramCache]: Analyzing trace with hash -225993601, now seen corresponding path program 21 times [2024-10-31 22:19:19,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:19,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861351908] [2024-10-31 22:19:19,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:19,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:19,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:19,864 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 145 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:19,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:19,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861351908] [2024-10-31 22:19:19,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861351908] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:19,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1629672675] [2024-10-31 22:19:19,865 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-31 22:19:19,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:19,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:19,868 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:19,869 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-10-31 22:19:20,171 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2024-10-31 22:19:20,172 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:19:20,175 INFO L255 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjuncts are in the unsatisfiable core [2024-10-31 22:19:20,177 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:20,696 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:20,696 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:21,074 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:21,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1629672675] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:21,075 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:21,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2024-10-31 22:19:21,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680819792] [2024-10-31 22:19:21,075 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:21,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:21,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2024-10-31 22:19:21,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=395, Invalid=1245, Unknown=0, NotChecked=0, Total=1640 [2024-10-31 22:19:21,131 INFO L87 Difference]: Start difference. First operand 100 states and 114 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.55) internal successors, (102), 41 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:21,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:21,743 INFO L93 Difference]: Finished difference Result 322 states and 373 transitions. [2024-10-31 22:19:21,743 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 373 transitions. [2024-10-31 22:19:21,745 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:21,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 186 states and 214 transitions. [2024-10-31 22:19:21,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161 [2024-10-31 22:19:21,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161 [2024-10-31 22:19:21,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 214 transitions. [2024-10-31 22:19:21,747 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:21,747 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 214 transitions. [2024-10-31 22:19:21,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 214 transitions. [2024-10-31 22:19:21,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 108. [2024-10-31 22:19:21,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1388888888888888) internal successors, (123), 107 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:21,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 123 transitions. [2024-10-31 22:19:21,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 123 transitions. [2024-10-31 22:19:21,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2024-10-31 22:19:21,759 INFO L425 stractBuchiCegarLoop]: Abstraction has 108 states and 123 transitions. [2024-10-31 22:19:21,759 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:19:21,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 123 transitions. [2024-10-31 22:19:21,760 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:21,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:21,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:21,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1] [2024-10-31 22:19:21,761 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:21,761 INFO L745 eck$LassoCheckResult]: Stem: 5726#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5708#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5724#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5725#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5712#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5713#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5751#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5749#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5748#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5747#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5745#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5744#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5743#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5742#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5741#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5740#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5739#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5738#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5737#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5736#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5735#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5734#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 5731#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 5730#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5714#L27-4 main_~i~0#1 := 0; 5715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5721#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5707#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5718#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5723#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5806#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5805#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5803#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5800#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5799#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5797#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5794#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5791#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5788#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5787#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5785#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5782#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5781#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5779#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5776#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5775#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5773#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5770#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5769#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5767#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5764#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5761#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5759#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5758#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5755#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5753#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5752#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5729#L34 [2024-10-31 22:19:21,761 INFO L747 eck$LassoCheckResult]: Loop: 5729#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 5732#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 5728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5729#L34 [2024-10-31 22:19:21,761 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:21,761 INFO L85 PathProgramCache]: Analyzing trace with hash -2083736959, now seen corresponding path program 22 times [2024-10-31 22:19:21,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:21,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674309670] [2024-10-31 22:19:21,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:21,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:21,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:21,860 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:21,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:21,920 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:21,921 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:21,921 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 13 times [2024-10-31 22:19:21,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:21,921 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671681661] [2024-10-31 22:19:21,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:21,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:21,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:21,925 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:21,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:21,929 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:21,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:21,931 INFO L85 PathProgramCache]: Analyzing trace with hash -1445369771, now seen corresponding path program 23 times [2024-10-31 22:19:21,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:21,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490179216] [2024-10-31 22:19:21,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:21,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:21,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:19:22,811 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 176 proven. 178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:22,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:19:22,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490179216] [2024-10-31 22:19:22,812 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490179216] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:19:22,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1217234127] [2024-10-31 22:19:22,812 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-31 22:19:22,813 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:19:22,813 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:19:22,818 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:19:22,819 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_758b1b88-0bbd-43bd-88d5-067bc6909731/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-10-31 22:19:23,305 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2024-10-31 22:19:23,305 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:19:23,310 INFO L255 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjuncts are in the unsatisfiable core [2024-10-31 22:19:23,314 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:19:23,947 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:23,948 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:19:24,425 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:19:24,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1217234127] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:19:24,425 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:19:24,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2024-10-31 22:19:24,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203052495] [2024-10-31 22:19:24,426 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:19:24,479 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:19:24,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2024-10-31 22:19:24,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=1439, Unknown=0, NotChecked=0, Total=1892 [2024-10-31 22:19:24,481 INFO L87 Difference]: Start difference. First operand 108 states and 123 transitions. cyclomatic complexity: 18 Second operand has 44 states, 43 states have (on average 2.558139534883721) internal successors, (110), 44 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:25,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:19:25,203 INFO L93 Difference]: Finished difference Result 348 states and 403 transitions. [2024-10-31 22:19:25,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 348 states and 403 transitions. [2024-10-31 22:19:25,206 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:25,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 348 states to 200 states and 230 transitions. [2024-10-31 22:19:25,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173 [2024-10-31 22:19:25,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173 [2024-10-31 22:19:25,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 230 transitions. [2024-10-31 22:19:25,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:25,209 INFO L218 hiAutomatonCegarLoop]: Abstraction has 200 states and 230 transitions. [2024-10-31 22:19:25,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 230 transitions. [2024-10-31 22:19:25,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 116. [2024-10-31 22:19:25,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1379310344827587) internal successors, (132), 115 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:19:25,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 132 transitions. [2024-10-31 22:19:25,214 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 132 transitions. [2024-10-31 22:19:25,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-10-31 22:19:25,217 INFO L425 stractBuchiCegarLoop]: Abstraction has 116 states and 132 transitions. [2024-10-31 22:19:25,217 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:19:25,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 132 transitions. [2024-10-31 22:19:25,218 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2024-10-31 22:19:25,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:19:25,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:19:25,219 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1] [2024-10-31 22:19:25,219 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-10-31 22:19:25,219 INFO L745 eck$LassoCheckResult]: Stem: 6637#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 6621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 6622#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6638#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6639#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6625#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6626#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6666#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6665#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6664#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6663#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6662#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6661#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6660#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6659#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6658#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6657#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6656#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6655#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6654#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6653#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6652#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6651#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6650#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6649#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6648#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6647#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 6644#L27-2 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 6643#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 6627#L27-4 main_~i~0#1 := 0; 6628#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6634#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6620#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6631#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6636#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6727#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6726#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6724#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6721#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6720#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6718#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6715#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6714#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6712#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6709#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6708#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6706#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6703#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6702#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6700#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6697#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6696#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6694#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6691#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6690#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6688#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6685#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6684#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6682#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6679#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6678#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6676#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6674#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6673#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6670#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6668#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6667#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6642#L34 [2024-10-31 22:19:25,220 INFO L747 eck$LassoCheckResult]: Loop: 6642#L34 assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1; 6645#L32-2 main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 6641#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6642#L34 [2024-10-31 22:19:25,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:25,223 INFO L85 PathProgramCache]: Analyzing trace with hash -1447312493, now seen corresponding path program 24 times [2024-10-31 22:19:25,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:25,225 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398344368] [2024-10-31 22:19:25,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:25,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:25,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:25,362 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:25,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:25,442 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:25,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:25,443 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 14 times [2024-10-31 22:19:25,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:25,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [661339810] [2024-10-31 22:19:25,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:25,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:25,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:25,449 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:19:25,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:19:25,453 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:19:25,454 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:19:25,454 INFO L85 PathProgramCache]: Analyzing trace with hash 290252291, now seen corresponding path program 25 times [2024-10-31 22:19:25,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:19:25,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165614515] [2024-10-31 22:19:25,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:19:25,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:19:25,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat