./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:13:39,309 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:13:39,403 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:13:39,410 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:13:39,411 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:13:39,446 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:13:39,449 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:13:39,449 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:13:39,450 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:13:39,452 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:13:39,453 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:13:39,453 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:13:39,454 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:13:39,454 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:13:39,456 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:13:39,457 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:13:39,457 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:13:39,457 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:13:39,457 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:13:39,458 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:13:39,458 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:13:39,459 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:13:39,459 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:13:39,459 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:13:39,460 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:13:39,460 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:13:39,460 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:13:39,460 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:13:39,461 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:13:39,461 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:13:39,461 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:13:39,462 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:13:39,462 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:13:39,462 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:13:39,462 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:13:39,463 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:13:39,463 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:13:39,463 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:13:39,464 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:13:39,464 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 [2024-10-31 22:13:39,810 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:13:39,845 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:13:39,848 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:13:39,850 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:13:39,851 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:13:39,852 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i Unable to find full path for "g++" [2024-10-31 22:13:41,942 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:13:42,167 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:13:42,171 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2024-10-31 22:13:42,181 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/data/34d39435c/466e4a539e454b9e9a8ece20cba66a5a/FLAGac3ef30bf [2024-10-31 22:13:42,523 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/data/34d39435c/466e4a539e454b9e9a8ece20cba66a5a [2024-10-31 22:13:42,526 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:13:42,527 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:13:42,529 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:13:42,529 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:13:42,535 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:13:42,536 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,537 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@55772ee3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42, skipping insertion in model container [2024-10-31 22:13:42,537 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,559 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:13:42,741 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:13:42,752 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:13:42,768 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:13:42,786 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:13:42,787 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42 WrapperNode [2024-10-31 22:13:42,787 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:13:42,788 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:13:42,788 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:13:42,788 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:13:42,796 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,802 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,821 INFO L138 Inliner]: procedures = 16, calls = 8, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 54 [2024-10-31 22:13:42,821 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:13:42,822 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:13:42,822 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:13:42,822 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:13:42,834 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,834 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,835 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,847 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:13:42,847 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,847 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,850 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,854 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,855 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,856 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,857 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:13:42,858 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:13:42,858 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:13:42,859 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:13:42,860 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (1/1) ... [2024-10-31 22:13:42,866 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:13:42,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:42,901 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:13:42,906 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:13:42,933 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:13:42,933 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:13:42,934 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:13:42,934 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:13:42,999 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:13:43,002 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:13:43,148 INFO L? ?]: Removed 9 outVars from TransFormulas that were not future-live. [2024-10-31 22:13:43,148 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:13:43,160 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:13:43,160 INFO L316 CfgBuilder]: Removed 2 assume(true) statements. [2024-10-31 22:13:43,161 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:13:43 BoogieIcfgContainer [2024-10-31 22:13:43,161 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:13:43,163 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:13:43,163 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:13:43,167 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:13:43,168 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:13:43,170 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:13:42" (1/3) ... [2024-10-31 22:13:43,171 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@340f066d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:13:43, skipping insertion in model container [2024-10-31 22:13:43,171 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:13:43,171 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:13:42" (2/3) ... [2024-10-31 22:13:43,173 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@340f066d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:13:43, skipping insertion in model container [2024-10-31 22:13:43,173 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:13:43,173 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:13:43" (3/3) ... [2024-10-31 22:13:43,174 INFO L332 chiAutomizerObserver]: Analyzing ICFG string_concat-noarr.i [2024-10-31 22:13:43,249 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:13:43,249 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:13:43,250 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:13:43,250 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:13:43,250 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:13:43,250 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:13:43,250 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:13:43,250 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:13:43,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:43,271 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2024-10-31 22:13:43,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:43,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:43,276 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2024-10-31 22:13:43,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:13:43,277 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:13:43,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:43,279 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2024-10-31 22:13:43,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:43,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:43,279 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2024-10-31 22:13:43,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-10-31 22:13:43,288 INFO L745 eck$LassoCheckResult]: Stem: 13#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5#L26true main_~i~0#1 := 0; 16#L29-2true [2024-10-31 22:13:43,288 INFO L747 eck$LassoCheckResult]: Loop: 16#L29-2true havoc main_#t~nondet1#1; 4#L29true assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16#L29-2true [2024-10-31 22:13:43,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:43,297 INFO L85 PathProgramCache]: Analyzing trace with hash 29857, now seen corresponding path program 1 times [2024-10-31 22:13:43,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:43,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136301928] [2024-10-31 22:13:43,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:43,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:43,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:43,422 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:43,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:43,458 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:43,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:43,462 INFO L85 PathProgramCache]: Analyzing trace with hash 1254, now seen corresponding path program 1 times [2024-10-31 22:13:43,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:43,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583131582] [2024-10-31 22:13:43,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:43,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:43,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:43,479 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:43,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:43,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:43,491 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:43,491 INFO L85 PathProgramCache]: Analyzing trace with hash 28692870, now seen corresponding path program 1 times [2024-10-31 22:13:43,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:43,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825381093] [2024-10-31 22:13:43,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:43,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:43,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:43,510 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:43,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:43,529 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:43,627 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:13:43,627 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:13:43,628 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:13:43,628 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:13:43,628 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-31 22:13:43,628 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:13:43,628 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:13:43,629 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:13:43,629 INFO L132 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2024-10-31 22:13:43,629 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:13:43,629 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:13:43,647 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:13:43,662 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:13:43,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:13:43,716 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:13:43,717 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-31 22:13:43,719 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:13:43,720 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:43,722 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:13:43,727 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-31 22:13:43,728 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:13:43,728 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:13:43,755 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-10-31 22:13:43,755 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:13:43,755 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:43,756 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:13:43,758 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-31 22:13:43,759 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-31 22:13:43,759 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:13:43,809 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-31 22:13:43,813 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-10-31 22:13:43,813 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:13:43,813 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:13:43,813 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:13:43,813 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:13:43,813 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-31 22:13:43,814 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:13:43,814 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:13:43,814 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:13:43,814 INFO L132 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2024-10-31 22:13:43,814 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:13:43,814 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:13:43,816 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:13:43,829 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:13:43,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:13:43,881 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:13:43,886 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-31 22:13:43,888 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:13:43,888 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:43,890 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:13:43,892 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-31 22:13:43,894 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:13:43,909 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:13:43,909 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:13:43,910 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:13:43,910 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:13:43,910 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:13:43,914 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:13:43,914 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:13:43,922 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-31 22:13:43,928 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-31 22:13:43,928 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-31 22:13:43,930 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:13:43,930 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:43,942 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:13:43,944 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-31 22:13:43,947 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-31 22:13:43,948 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-31 22:13:43,948 INFO L474 LassoAnalysis]: Proved termination. [2024-10-31 22:13:43,949 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = -2*ULTIMATE.start_main_~i~0#1 + 1999999 Supporting invariants [] [2024-10-31 22:13:43,970 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-10-31 22:13:43,978 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-31 22:13:44,051 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-10-31 22:13:44,062 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:44,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:44,083 INFO L255 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:13:44,084 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:44,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:44,109 WARN L253 TraceCheckSpWp]: Trace formula consists of 7 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-31 22:13:44,110 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:44,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:44,160 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2024-10-31 22:13:44,164 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:44,239 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 41 states and 58 transitions. Complement of second has 6 states. [2024-10-31 22:13:44,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:13:44,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:44,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 34 transitions. [2024-10-31 22:13:44,252 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 34 transitions. Stem has 3 letters. Loop has 2 letters. [2024-10-31 22:13:44,254 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:13:44,255 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 34 transitions. Stem has 5 letters. Loop has 2 letters. [2024-10-31 22:13:44,255 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:13:44,255 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 34 transitions. Stem has 3 letters. Loop has 4 letters. [2024-10-31 22:13:44,256 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:13:44,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 58 transitions. [2024-10-31 22:13:44,260 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2024-10-31 22:13:44,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 18 states and 23 transitions. [2024-10-31 22:13:44,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2024-10-31 22:13:44,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2024-10-31 22:13:44,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 23 transitions. [2024-10-31 22:13:44,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:44,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18 states and 23 transitions. [2024-10-31 22:13:44,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 23 transitions. [2024-10-31 22:13:44,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 16. [2024-10-31 22:13:44,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.3125) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:44,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 21 transitions. [2024-10-31 22:13:44,295 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 21 transitions. [2024-10-31 22:13:44,295 INFO L425 stractBuchiCegarLoop]: Abstraction has 16 states and 21 transitions. [2024-10-31 22:13:44,295 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:13:44,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 21 transitions. [2024-10-31 22:13:44,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:44,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:44,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:44,297 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2024-10-31 22:13:44,297 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:44,298 INFO L745 eck$LassoCheckResult]: Stem: 102#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 109#L26 main_~i~0#1 := 0; 110#L29-2 havoc main_#t~nondet1#1; 104#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 97#L29-3 assume main_~i~0#1 >= 100; 98#L32 [2024-10-31 22:13:44,298 INFO L747 eck$LassoCheckResult]: Loop: 98#L32 assume true; 98#L32 [2024-10-31 22:13:44,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:44,298 INFO L85 PathProgramCache]: Analyzing trace with hash 889478928, now seen corresponding path program 1 times [2024-10-31 22:13:44,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:44,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552723152] [2024-10-31 22:13:44,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:44,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:44,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:44,354 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:44,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552723152] [2024-10-31 22:13:44,355 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552723152] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:13:44,355 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:13:44,355 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:13:44,355 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059062325] [2024-10-31 22:13:44,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:13:44,358 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:44,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:44,358 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 1 times [2024-10-31 22:13:44,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:44,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725367936] [2024-10-31 22:13:44,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:44,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:44,361 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:44,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:44,363 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:44,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:44,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:13:44,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:13:44,370 INFO L87 Difference]: Start difference. First operand 16 states and 21 transitions. cyclomatic complexity: 8 Second operand has 3 states, 2 states have (on average 3.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:44,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:44,395 INFO L93 Difference]: Finished difference Result 26 states and 32 transitions. [2024-10-31 22:13:44,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 32 transitions. [2024-10-31 22:13:44,396 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2024-10-31 22:13:44,397 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 26 states and 32 transitions. [2024-10-31 22:13:44,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2024-10-31 22:13:44,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2024-10-31 22:13:44,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 32 transitions. [2024-10-31 22:13:44,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:44,397 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26 states and 32 transitions. [2024-10-31 22:13:44,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 32 transitions. [2024-10-31 22:13:44,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 18. [2024-10-31 22:13:44,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 17 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:44,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 23 transitions. [2024-10-31 22:13:44,399 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18 states and 23 transitions. [2024-10-31 22:13:44,400 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:13:44,401 INFO L425 stractBuchiCegarLoop]: Abstraction has 18 states and 23 transitions. [2024-10-31 22:13:44,401 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:13:44,401 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 23 transitions. [2024-10-31 22:13:44,401 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:44,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:44,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:44,402 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1] [2024-10-31 22:13:44,402 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:44,402 INFO L745 eck$LassoCheckResult]: Stem: 153#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 154#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 157#L26 main_~i~0#1 := 0; 158#L29-2 havoc main_#t~nondet1#1; 151#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 152#L29-2 havoc main_#t~nondet1#1; 149#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 150#L29-3 assume main_~i~0#1 >= 100; 159#L32 [2024-10-31 22:13:44,402 INFO L747 eck$LassoCheckResult]: Loop: 159#L32 assume true; 159#L32 [2024-10-31 22:13:44,403 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:44,403 INFO L85 PathProgramCache]: Analyzing trace with hash 90807307, now seen corresponding path program 1 times [2024-10-31 22:13:44,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:44,403 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618712906] [2024-10-31 22:13:44,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:44,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:44,467 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:44,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:44,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618712906] [2024-10-31 22:13:44,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618712906] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:13:44,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1774435439] [2024-10-31 22:13:44,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,468 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:13:44,468 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:44,472 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:13:44,478 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-10-31 22:13:44,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:44,530 INFO L255 TraceCheckSpWp]: Trace formula consists of 28 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-10-31 22:13:44,530 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:44,561 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:44,561 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:13:44,609 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:44,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1774435439] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:13:44,610 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:13:44,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2024-10-31 22:13:44,610 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [400211932] [2024-10-31 22:13:44,610 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:13:44,611 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:44,611 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:44,611 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 2 times [2024-10-31 22:13:44,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:44,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814058500] [2024-10-31 22:13:44,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:44,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:44,618 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:44,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:44,620 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:44,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:44,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-10-31 22:13:44,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2024-10-31 22:13:44,627 INFO L87 Difference]: Start difference. First operand 18 states and 23 transitions. cyclomatic complexity: 8 Second operand has 7 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 7 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:44,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:44,716 INFO L93 Difference]: Finished difference Result 60 states and 75 transitions. [2024-10-31 22:13:44,716 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 75 transitions. [2024-10-31 22:13:44,717 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2024-10-31 22:13:44,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 60 states and 75 transitions. [2024-10-31 22:13:44,721 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2024-10-31 22:13:44,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2024-10-31 22:13:44,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 75 transitions. [2024-10-31 22:13:44,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:44,723 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 75 transitions. [2024-10-31 22:13:44,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 75 transitions. [2024-10-31 22:13:44,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 24. [2024-10-31 22:13:44,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.4583333333333333) internal successors, (35), 23 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:44,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 35 transitions. [2024-10-31 22:13:44,727 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 35 transitions. [2024-10-31 22:13:44,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-10-31 22:13:44,730 INFO L425 stractBuchiCegarLoop]: Abstraction has 24 states and 35 transitions. [2024-10-31 22:13:44,730 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:13:44,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 35 transitions. [2024-10-31 22:13:44,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:44,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:44,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:44,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:13:44,732 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:44,734 INFO L745 eck$LassoCheckResult]: Stem: 282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 286#L26 main_~i~0#1 := 0; 287#L29-2 havoc main_#t~nondet1#1; 279#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 275#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 276#L35-2 havoc main_#t~nondet3#1; 284#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 289#L35-3 assume main_~j~0#1 >= 100; 288#L32 [2024-10-31 22:13:44,734 INFO L747 eck$LassoCheckResult]: Loop: 288#L32 assume true; 288#L32 [2024-10-31 22:13:44,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:44,735 INFO L85 PathProgramCache]: Analyzing trace with hash -1481354991, now seen corresponding path program 1 times [2024-10-31 22:13:44,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:44,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181185874] [2024-10-31 22:13:44,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:44,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:44,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:44,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:44,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181185874] [2024-10-31 22:13:44,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [181185874] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:13:44,809 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:13:44,809 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:13:44,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384887652] [2024-10-31 22:13:44,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:13:44,809 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:44,810 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:44,810 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 3 times [2024-10-31 22:13:44,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:44,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832767564] [2024-10-31 22:13:44,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:44,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:44,817 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:44,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:44,819 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:44,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:44,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:13:44,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:13:44,824 INFO L87 Difference]: Start difference. First operand 24 states and 35 transitions. cyclomatic complexity: 14 Second operand has 3 states, 2 states have (on average 4.5) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:44,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:44,836 INFO L93 Difference]: Finished difference Result 27 states and 37 transitions. [2024-10-31 22:13:44,836 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 37 transitions. [2024-10-31 22:13:44,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:44,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 22 states and 28 transitions. [2024-10-31 22:13:44,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-10-31 22:13:44,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-10-31 22:13:44,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 28 transitions. [2024-10-31 22:13:44,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:44,838 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 28 transitions. [2024-10-31 22:13:44,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 28 transitions. [2024-10-31 22:13:44,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2024-10-31 22:13:44,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:44,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2024-10-31 22:13:44,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2024-10-31 22:13:44,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:13:44,842 INFO L425 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2024-10-31 22:13:44,842 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:13:44,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2024-10-31 22:13:44,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:44,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:44,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:44,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:13:44,844 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:44,844 INFO L745 eck$LassoCheckResult]: Stem: 339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 342#L26 main_~i~0#1 := 0; 343#L29-2 havoc main_#t~nondet1#1; 337#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 334#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 335#L35-2 havoc main_#t~nondet3#1; 341#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 346#L35-2 havoc main_#t~nondet3#1; 345#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 344#L35-3 assume main_~j~0#1 >= 100; 333#L32 [2024-10-31 22:13:44,844 INFO L747 eck$LassoCheckResult]: Loop: 333#L32 assume true; 333#L32 [2024-10-31 22:13:44,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:44,845 INFO L85 PathProgramCache]: Analyzing trace with hash -1947921364, now seen corresponding path program 1 times [2024-10-31 22:13:44,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:44,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140463729] [2024-10-31 22:13:44,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:44,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:44,896 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:44,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:44,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140463729] [2024-10-31 22:13:44,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140463729] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:13:44,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [155487811] [2024-10-31 22:13:44,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,897 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:13:44,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:44,900 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:13:44,901 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-10-31 22:13:44,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:44,943 INFO L255 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-10-31 22:13:44,944 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:44,967 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:44,967 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:13:44,997 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:44,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [155487811] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:13:44,997 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:13:44,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2024-10-31 22:13:44,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342104735] [2024-10-31 22:13:44,998 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:13:44,998 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:44,998 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:44,999 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 4 times [2024-10-31 22:13:44,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:44,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584924775] [2024-10-31 22:13:44,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:44,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:45,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:45,002 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:45,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:45,003 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:45,006 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:45,006 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-10-31 22:13:45,006 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2024-10-31 22:13:45,007 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 7 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 7 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:45,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:45,028 INFO L93 Difference]: Finished difference Result 34 states and 40 transitions. [2024-10-31 22:13:45,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 40 transitions. [2024-10-31 22:13:45,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:45,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 28 states and 34 transitions. [2024-10-31 22:13:45,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-10-31 22:13:45,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-10-31 22:13:45,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2024-10-31 22:13:45,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:45,030 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 34 transitions. [2024-10-31 22:13:45,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2024-10-31 22:13:45,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2024-10-31 22:13:45,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:45,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2024-10-31 22:13:45,033 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2024-10-31 22:13:45,033 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-10-31 22:13:45,034 INFO L425 stractBuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2024-10-31 22:13:45,034 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:13:45,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2024-10-31 22:13:45,035 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:45,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:45,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:45,035 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1] [2024-10-31 22:13:45,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:45,035 INFO L745 eck$LassoCheckResult]: Stem: 461#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 462#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 468#L26 main_~i~0#1 := 0; 469#L29-2 havoc main_#t~nondet1#1; 464#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 465#L29-2 havoc main_#t~nondet1#1; 473#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 480#L29-2 havoc main_#t~nondet1#1; 479#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 478#L29-2 havoc main_#t~nondet1#1; 475#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 474#L29-2 havoc main_#t~nondet1#1; 463#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 457#L29-3 assume main_~i~0#1 >= 100; 458#L32 [2024-10-31 22:13:45,036 INFO L747 eck$LassoCheckResult]: Loop: 458#L32 assume true; 458#L32 [2024-10-31 22:13:45,036 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:45,036 INFO L85 PathProgramCache]: Analyzing trace with hash -957341060, now seen corresponding path program 2 times [2024-10-31 22:13:45,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:45,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21434111] [2024-10-31 22:13:45,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:45,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:45,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:45,147 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:45,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:45,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21434111] [2024-10-31 22:13:45,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21434111] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:13:45,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [875995282] [2024-10-31 22:13:45,148 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-10-31 22:13:45,149 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:13:45,149 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:45,152 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:13:45,155 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-10-31 22:13:45,206 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-10-31 22:13:45,206 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:13:45,207 INFO L255 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-10-31 22:13:45,208 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:45,255 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:45,256 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:13:45,370 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:45,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [875995282] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:13:45,373 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:13:45,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2024-10-31 22:13:45,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721588887] [2024-10-31 22:13:45,388 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:13:45,389 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:45,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:45,389 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 5 times [2024-10-31 22:13:45,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:45,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986124987] [2024-10-31 22:13:45,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:45,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:45,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:45,395 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:45,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:45,396 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:45,399 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:45,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-10-31 22:13:45,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2024-10-31 22:13:45,400 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 9 Second operand has 13 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 13 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:45,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:45,531 INFO L93 Difference]: Finished difference Result 152 states and 171 transitions. [2024-10-31 22:13:45,531 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152 states and 171 transitions. [2024-10-31 22:13:45,533 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2024-10-31 22:13:45,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152 states to 140 states and 159 transitions. [2024-10-31 22:13:45,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-10-31 22:13:45,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2024-10-31 22:13:45,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 140 states and 159 transitions. [2024-10-31 22:13:45,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:45,535 INFO L218 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2024-10-31 22:13:45,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states and 159 transitions. [2024-10-31 22:13:45,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 39. [2024-10-31 22:13:45,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.3076923076923077) internal successors, (51), 38 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:45,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 51 transitions. [2024-10-31 22:13:45,540 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2024-10-31 22:13:45,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-10-31 22:13:45,541 INFO L425 stractBuchiCegarLoop]: Abstraction has 39 states and 51 transitions. [2024-10-31 22:13:45,541 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:13:45,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 51 transitions. [2024-10-31 22:13:45,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:45,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:45,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:45,543 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:13:45,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:45,543 INFO L745 eck$LassoCheckResult]: Stem: 734#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 740#L26 main_~i~0#1 := 0; 741#L29-2 havoc main_#t~nondet1#1; 743#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 732#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 733#L35-2 havoc main_#t~nondet3#1; 739#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 746#L35-2 havoc main_#t~nondet3#1; 768#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 767#L35-2 havoc main_#t~nondet3#1; 766#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 765#L35-2 havoc main_#t~nondet3#1; 764#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 763#L35-2 havoc main_#t~nondet3#1; 745#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 742#L35-3 assume main_~j~0#1 >= 100; 731#L32 [2024-10-31 22:13:45,543 INFO L747 eck$LassoCheckResult]: Loop: 731#L32 assume true; 731#L32 [2024-10-31 22:13:45,543 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:45,544 INFO L85 PathProgramCache]: Analyzing trace with hash 606076157, now seen corresponding path program 2 times [2024-10-31 22:13:45,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:45,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83912255] [2024-10-31 22:13:45,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:45,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:45,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:45,682 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:45,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:45,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83912255] [2024-10-31 22:13:45,683 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83912255] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:13:45,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1406543091] [2024-10-31 22:13:45,683 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-10-31 22:13:45,683 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:13:45,683 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:45,686 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:13:45,687 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-10-31 22:13:45,732 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-10-31 22:13:45,732 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:13:45,733 INFO L255 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-10-31 22:13:45,734 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:45,772 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:45,773 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:13:45,859 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:45,859 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1406543091] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:13:45,859 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:13:45,860 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2024-10-31 22:13:45,860 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1161024305] [2024-10-31 22:13:45,860 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:13:45,860 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:45,861 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:45,861 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 6 times [2024-10-31 22:13:45,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:45,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670637474] [2024-10-31 22:13:45,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:45,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:45,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:45,863 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:45,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:45,864 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:45,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:45,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-10-31 22:13:45,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2024-10-31 22:13:45,867 INFO L87 Difference]: Start difference. First operand 39 states and 51 transitions. cyclomatic complexity: 15 Second operand has 13 states, 12 states have (on average 2.6666666666666665) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:45,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:45,897 INFO L93 Difference]: Finished difference Result 64 states and 76 transitions. [2024-10-31 22:13:45,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 76 transitions. [2024-10-31 22:13:45,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:45,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 52 states and 64 transitions. [2024-10-31 22:13:45,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-10-31 22:13:45,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-10-31 22:13:45,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 64 transitions. [2024-10-31 22:13:45,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:45,899 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 64 transitions. [2024-10-31 22:13:45,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 64 transitions. [2024-10-31 22:13:45,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2024-10-31 22:13:45,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.2352941176470589) internal successors, (63), 50 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:45,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 63 transitions. [2024-10-31 22:13:45,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 63 transitions. [2024-10-31 22:13:45,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-10-31 22:13:45,909 INFO L425 stractBuchiCegarLoop]: Abstraction has 51 states and 63 transitions. [2024-10-31 22:13:45,909 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:13:45,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 63 transitions. [2024-10-31 22:13:45,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:45,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:45,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:45,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1] [2024-10-31 22:13:45,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:45,912 INFO L745 eck$LassoCheckResult]: Stem: 952#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 953#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 956#L26 main_~i~0#1 := 0; 957#L29-2 havoc main_#t~nondet1#1; 950#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 951#L29-2 havoc main_#t~nondet1#1; 961#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 980#L29-2 havoc main_#t~nondet1#1; 979#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 978#L29-2 havoc main_#t~nondet1#1; 977#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 976#L29-2 havoc main_#t~nondet1#1; 975#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 974#L29-2 havoc main_#t~nondet1#1; 973#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 972#L29-2 havoc main_#t~nondet1#1; 971#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 970#L29-2 havoc main_#t~nondet1#1; 969#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 968#L29-2 havoc main_#t~nondet1#1; 967#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 966#L29-2 havoc main_#t~nondet1#1; 965#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 964#L29-2 havoc main_#t~nondet1#1; 949#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 945#L29-3 assume main_~i~0#1 >= 100; 946#L32 [2024-10-31 22:13:45,913 INFO L747 eck$LassoCheckResult]: Loop: 946#L32 assume true; 946#L32 [2024-10-31 22:13:45,914 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:45,914 INFO L85 PathProgramCache]: Analyzing trace with hash 777893150, now seen corresponding path program 3 times [2024-10-31 22:13:45,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:45,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493409268] [2024-10-31 22:13:45,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:45,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:45,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:46,166 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:46,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:46,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [493409268] [2024-10-31 22:13:46,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [493409268] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:13:46,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1125609779] [2024-10-31 22:13:46,167 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-31 22:13:46,167 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:13:46,167 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:46,175 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:13:46,177 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-10-31 22:13:46,234 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-10-31 22:13:46,234 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:13:46,235 INFO L255 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-10-31 22:13:46,237 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:46,322 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:46,322 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:13:46,650 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:46,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1125609779] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:13:46,650 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:13:46,650 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2024-10-31 22:13:46,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218731535] [2024-10-31 22:13:46,651 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:13:46,651 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:46,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:46,652 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 7 times [2024-10-31 22:13:46,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:46,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787723881] [2024-10-31 22:13:46,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:46,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:46,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:46,655 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:46,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:46,657 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:46,659 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:46,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-10-31 22:13:46,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2024-10-31 22:13:46,662 INFO L87 Difference]: Start difference. First operand 51 states and 63 transitions. cyclomatic complexity: 15 Second operand has 25 states, 24 states have (on average 2.2083333333333335) internal successors, (53), 25 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:46,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:46,943 INFO L93 Difference]: Finished difference Result 518 states and 555 transitions. [2024-10-31 22:13:46,944 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 555 transitions. [2024-10-31 22:13:46,949 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 13 [2024-10-31 22:13:46,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 494 states and 531 transitions. [2024-10-31 22:13:46,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2024-10-31 22:13:46,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2024-10-31 22:13:46,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 494 states and 531 transitions. [2024-10-31 22:13:46,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:46,955 INFO L218 hiAutomatonCegarLoop]: Abstraction has 494 states and 531 transitions. [2024-10-31 22:13:46,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states and 531 transitions. [2024-10-31 22:13:46,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 75. [2024-10-31 22:13:46,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.32) internal successors, (99), 74 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:46,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 99 transitions. [2024-10-31 22:13:46,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 99 transitions. [2024-10-31 22:13:46,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-10-31 22:13:46,965 INFO L425 stractBuchiCegarLoop]: Abstraction has 75 states and 99 transitions. [2024-10-31 22:13:46,965 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:13:46,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 99 transitions. [2024-10-31 22:13:46,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:46,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:46,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:46,967 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:13:46,968 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:46,968 INFO L745 eck$LassoCheckResult]: Stem: 1696#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1697#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1702#L26 main_~i~0#1 := 0; 1703#L29-2 havoc main_#t~nondet1#1; 1705#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1694#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 1695#L35-2 havoc main_#t~nondet3#1; 1701#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1708#L35-2 havoc main_#t~nondet3#1; 1766#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1765#L35-2 havoc main_#t~nondet3#1; 1764#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1763#L35-2 havoc main_#t~nondet3#1; 1762#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1761#L35-2 havoc main_#t~nondet3#1; 1760#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1759#L35-2 havoc main_#t~nondet3#1; 1758#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1757#L35-2 havoc main_#t~nondet3#1; 1756#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1755#L35-2 havoc main_#t~nondet3#1; 1754#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1753#L35-2 havoc main_#t~nondet3#1; 1752#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1751#L35-2 havoc main_#t~nondet3#1; 1750#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1749#L35-2 havoc main_#t~nondet3#1; 1707#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 1704#L35-3 assume main_~j~0#1 >= 100; 1693#L32 [2024-10-31 22:13:46,968 INFO L747 eck$LassoCheckResult]: Loop: 1693#L32 assume true; 1693#L32 [2024-10-31 22:13:46,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:46,969 INFO L85 PathProgramCache]: Analyzing trace with hash -2036695969, now seen corresponding path program 3 times [2024-10-31 22:13:46,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:46,969 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908775517] [2024-10-31 22:13:46,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:46,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:46,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:47,225 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:47,225 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:47,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908775517] [2024-10-31 22:13:47,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1908775517] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:13:47,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [800953727] [2024-10-31 22:13:47,226 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-10-31 22:13:47,226 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:13:47,226 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:47,229 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:13:47,231 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-10-31 22:13:47,291 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-10-31 22:13:47,292 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:13:47,293 INFO L255 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-10-31 22:13:47,295 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:47,370 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:47,370 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:13:47,665 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:47,666 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [800953727] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:13:47,666 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:13:47,667 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2024-10-31 22:13:47,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206972299] [2024-10-31 22:13:47,667 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:13:47,669 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:47,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:47,670 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 8 times [2024-10-31 22:13:47,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:47,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85471187] [2024-10-31 22:13:47,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:47,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:47,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:47,672 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:47,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:47,674 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:47,680 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:47,680 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-10-31 22:13:47,681 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2024-10-31 22:13:47,681 INFO L87 Difference]: Start difference. First operand 75 states and 99 transitions. cyclomatic complexity: 27 Second operand has 25 states, 24 states have (on average 2.3333333333333335) internal successors, (56), 25 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:47,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:47,726 INFO L93 Difference]: Finished difference Result 124 states and 148 transitions. [2024-10-31 22:13:47,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 148 transitions. [2024-10-31 22:13:47,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:47,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 100 states and 124 transitions. [2024-10-31 22:13:47,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-10-31 22:13:47,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-10-31 22:13:47,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 124 transitions. [2024-10-31 22:13:47,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:47,729 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 124 transitions. [2024-10-31 22:13:47,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 124 transitions. [2024-10-31 22:13:47,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2024-10-31 22:13:47,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.2424242424242424) internal successors, (123), 98 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:47,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 123 transitions. [2024-10-31 22:13:47,736 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 123 transitions. [2024-10-31 22:13:47,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-10-31 22:13:47,737 INFO L425 stractBuchiCegarLoop]: Abstraction has 99 states and 123 transitions. [2024-10-31 22:13:47,738 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:13:47,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 123 transitions. [2024-10-31 22:13:47,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:47,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:47,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:47,740 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1] [2024-10-31 22:13:47,740 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:47,740 INFO L745 eck$LassoCheckResult]: Stem: 2094#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2095#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2098#L26 main_~i~0#1 := 0; 2099#L29-2 havoc main_#t~nondet1#1; 2092#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2093#L29-2 havoc main_#t~nondet1#1; 2103#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2146#L29-2 havoc main_#t~nondet1#1; 2145#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2144#L29-2 havoc main_#t~nondet1#1; 2143#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2142#L29-2 havoc main_#t~nondet1#1; 2141#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2140#L29-2 havoc main_#t~nondet1#1; 2139#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2138#L29-2 havoc main_#t~nondet1#1; 2137#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2136#L29-2 havoc main_#t~nondet1#1; 2135#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2134#L29-2 havoc main_#t~nondet1#1; 2133#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2132#L29-2 havoc main_#t~nondet1#1; 2131#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2130#L29-2 havoc main_#t~nondet1#1; 2129#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2128#L29-2 havoc main_#t~nondet1#1; 2127#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2126#L29-2 havoc main_#t~nondet1#1; 2125#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2124#L29-2 havoc main_#t~nondet1#1; 2123#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2122#L29-2 havoc main_#t~nondet1#1; 2121#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2120#L29-2 havoc main_#t~nondet1#1; 2119#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2118#L29-2 havoc main_#t~nondet1#1; 2117#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2116#L29-2 havoc main_#t~nondet1#1; 2115#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2114#L29-2 havoc main_#t~nondet1#1; 2113#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2112#L29-2 havoc main_#t~nondet1#1; 2111#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2110#L29-2 havoc main_#t~nondet1#1; 2109#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2108#L29-2 havoc main_#t~nondet1#1; 2107#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2106#L29-2 havoc main_#t~nondet1#1; 2091#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2087#L29-3 assume main_~i~0#1 >= 100; 2088#L32 [2024-10-31 22:13:47,740 INFO L747 eck$LassoCheckResult]: Loop: 2088#L32 assume true; 2088#L32 [2024-10-31 22:13:47,741 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:47,741 INFO L85 PathProgramCache]: Analyzing trace with hash -439176862, now seen corresponding path program 4 times [2024-10-31 22:13:47,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:47,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876833435] [2024-10-31 22:13:47,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:47,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:47,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:48,328 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:48,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:48,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876833435] [2024-10-31 22:13:48,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876833435] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:13:48,329 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [656669780] [2024-10-31 22:13:48,329 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-10-31 22:13:48,329 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:13:48,329 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:48,335 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:13:48,344 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-10-31 22:13:48,408 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-10-31 22:13:48,409 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:13:48,410 INFO L255 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-10-31 22:13:48,414 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:48,546 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:48,546 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:13:49,588 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:49,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [656669780] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:13:49,588 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:13:49,588 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2024-10-31 22:13:49,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [279427406] [2024-10-31 22:13:49,589 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:13:49,589 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:49,590 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:49,590 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 9 times [2024-10-31 22:13:49,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:49,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140929593] [2024-10-31 22:13:49,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:49,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:49,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:49,593 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:49,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:49,594 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:49,598 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:49,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2024-10-31 22:13:49,600 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2024-10-31 22:13:49,601 INFO L87 Difference]: Start difference. First operand 99 states and 123 transitions. cyclomatic complexity: 27 Second operand has 49 states, 48 states have (on average 2.1041666666666665) internal successors, (101), 49 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:50,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:50,306 INFO L93 Difference]: Finished difference Result 1898 states and 1971 transitions. [2024-10-31 22:13:50,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1898 states and 1971 transitions. [2024-10-31 22:13:50,320 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2024-10-31 22:13:50,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1898 states to 1850 states and 1923 transitions. [2024-10-31 22:13:50,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81 [2024-10-31 22:13:50,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81 [2024-10-31 22:13:50,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1850 states and 1923 transitions. [2024-10-31 22:13:50,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:50,331 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1850 states and 1923 transitions. [2024-10-31 22:13:50,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1850 states and 1923 transitions. [2024-10-31 22:13:50,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1850 to 147. [2024-10-31 22:13:50,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 147 states have (on average 1.3265306122448979) internal successors, (195), 146 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:50,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 195 transitions. [2024-10-31 22:13:50,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147 states and 195 transitions. [2024-10-31 22:13:50,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-10-31 22:13:50,359 INFO L425 stractBuchiCegarLoop]: Abstraction has 147 states and 195 transitions. [2024-10-31 22:13:50,359 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:13:50,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147 states and 195 transitions. [2024-10-31 22:13:50,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:50,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:50,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:50,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:13:50,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:50,362 INFO L745 eck$LassoCheckResult]: Stem: 4437#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 4438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 4440#L26 main_~i~0#1 := 0; 4441#L29-2 havoc main_#t~nondet1#1; 4445#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 4432#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 4433#L35-2 havoc main_#t~nondet3#1; 4439#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4444#L35-2 havoc main_#t~nondet3#1; 4576#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4575#L35-2 havoc main_#t~nondet3#1; 4574#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4573#L35-2 havoc main_#t~nondet3#1; 4572#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4571#L35-2 havoc main_#t~nondet3#1; 4570#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4569#L35-2 havoc main_#t~nondet3#1; 4568#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4567#L35-2 havoc main_#t~nondet3#1; 4566#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4565#L35-2 havoc main_#t~nondet3#1; 4564#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4563#L35-2 havoc main_#t~nondet3#1; 4562#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4561#L35-2 havoc main_#t~nondet3#1; 4560#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4559#L35-2 havoc main_#t~nondet3#1; 4558#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4557#L35-2 havoc main_#t~nondet3#1; 4556#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4555#L35-2 havoc main_#t~nondet3#1; 4554#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4553#L35-2 havoc main_#t~nondet3#1; 4552#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4551#L35-2 havoc main_#t~nondet3#1; 4550#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4549#L35-2 havoc main_#t~nondet3#1; 4548#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4547#L35-2 havoc main_#t~nondet3#1; 4546#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4545#L35-2 havoc main_#t~nondet3#1; 4544#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4543#L35-2 havoc main_#t~nondet3#1; 4542#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4541#L35-2 havoc main_#t~nondet3#1; 4540#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4539#L35-2 havoc main_#t~nondet3#1; 4538#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4537#L35-2 havoc main_#t~nondet3#1; 4536#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4535#L35-2 havoc main_#t~nondet3#1; 4443#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 4442#L35-3 assume main_~j~0#1 >= 100; 4431#L32 [2024-10-31 22:13:50,362 INFO L747 eck$LassoCheckResult]: Loop: 4431#L32 assume true; 4431#L32 [2024-10-31 22:13:50,363 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:50,363 INFO L85 PathProgramCache]: Analyzing trace with hash -173936093, now seen corresponding path program 4 times [2024-10-31 22:13:50,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:50,363 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450496476] [2024-10-31 22:13:50,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:50,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:50,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:51,115 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:51,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:51,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450496476] [2024-10-31 22:13:51,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1450496476] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:13:51,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1627648549] [2024-10-31 22:13:51,116 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-10-31 22:13:51,116 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:13:51,116 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:51,119 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:13:51,121 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-10-31 22:13:51,198 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-10-31 22:13:51,198 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:13:51,200 INFO L255 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-10-31 22:13:51,203 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:51,330 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:51,330 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:13:52,536 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:52,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1627648549] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:13:52,537 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:13:52,541 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2024-10-31 22:13:52,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [807383182] [2024-10-31 22:13:52,541 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:13:52,542 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:52,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:52,542 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 10 times [2024-10-31 22:13:52,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:52,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329387204] [2024-10-31 22:13:52,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:52,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:52,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:52,549 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:52,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:52,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:52,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:52,560 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2024-10-31 22:13:52,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2024-10-31 22:13:52,564 INFO L87 Difference]: Start difference. First operand 147 states and 195 transitions. cyclomatic complexity: 51 Second operand has 49 states, 48 states have (on average 2.1666666666666665) internal successors, (104), 49 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:52,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:13:52,697 INFO L93 Difference]: Finished difference Result 244 states and 292 transitions. [2024-10-31 22:13:52,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244 states and 292 transitions. [2024-10-31 22:13:52,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:52,701 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244 states to 196 states and 244 transitions. [2024-10-31 22:13:52,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-10-31 22:13:52,701 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-10-31 22:13:52,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196 states and 244 transitions. [2024-10-31 22:13:52,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:13:52,702 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196 states and 244 transitions. [2024-10-31 22:13:52,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states and 244 transitions. [2024-10-31 22:13:52,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 195. [2024-10-31 22:13:52,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.2461538461538462) internal successors, (243), 194 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:13:52,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 243 transitions. [2024-10-31 22:13:52,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 243 transitions. [2024-10-31 22:13:52,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-10-31 22:13:52,709 INFO L425 stractBuchiCegarLoop]: Abstraction has 195 states and 243 transitions. [2024-10-31 22:13:52,709 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:13:52,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 243 transitions. [2024-10-31 22:13:52,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:13:52,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:13:52,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:13:52,716 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1] [2024-10-31 22:13:52,716 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:13:52,717 INFO L745 eck$LassoCheckResult]: Stem: 5192#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 5193#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5196#L26 main_~i~0#1 := 0; 5197#L29-2 havoc main_#t~nondet1#1; 5190#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5191#L29-2 havoc main_#t~nondet1#1; 5201#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5292#L29-2 havoc main_#t~nondet1#1; 5291#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5290#L29-2 havoc main_#t~nondet1#1; 5289#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5288#L29-2 havoc main_#t~nondet1#1; 5287#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5286#L29-2 havoc main_#t~nondet1#1; 5285#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5284#L29-2 havoc main_#t~nondet1#1; 5283#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5282#L29-2 havoc main_#t~nondet1#1; 5281#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5280#L29-2 havoc main_#t~nondet1#1; 5279#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5278#L29-2 havoc main_#t~nondet1#1; 5277#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5276#L29-2 havoc main_#t~nondet1#1; 5275#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5274#L29-2 havoc main_#t~nondet1#1; 5273#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5272#L29-2 havoc main_#t~nondet1#1; 5271#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5270#L29-2 havoc main_#t~nondet1#1; 5269#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5268#L29-2 havoc main_#t~nondet1#1; 5267#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5266#L29-2 havoc main_#t~nondet1#1; 5265#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5264#L29-2 havoc main_#t~nondet1#1; 5263#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5262#L29-2 havoc main_#t~nondet1#1; 5261#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5260#L29-2 havoc main_#t~nondet1#1; 5259#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5258#L29-2 havoc main_#t~nondet1#1; 5257#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5256#L29-2 havoc main_#t~nondet1#1; 5255#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5254#L29-2 havoc main_#t~nondet1#1; 5253#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5252#L29-2 havoc main_#t~nondet1#1; 5251#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5250#L29-2 havoc main_#t~nondet1#1; 5249#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5248#L29-2 havoc main_#t~nondet1#1; 5247#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5246#L29-2 havoc main_#t~nondet1#1; 5245#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5244#L29-2 havoc main_#t~nondet1#1; 5243#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5242#L29-2 havoc main_#t~nondet1#1; 5241#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5240#L29-2 havoc main_#t~nondet1#1; 5239#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5238#L29-2 havoc main_#t~nondet1#1; 5237#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5236#L29-2 havoc main_#t~nondet1#1; 5235#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5234#L29-2 havoc main_#t~nondet1#1; 5233#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5232#L29-2 havoc main_#t~nondet1#1; 5231#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5230#L29-2 havoc main_#t~nondet1#1; 5229#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5228#L29-2 havoc main_#t~nondet1#1; 5227#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5226#L29-2 havoc main_#t~nondet1#1; 5225#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5224#L29-2 havoc main_#t~nondet1#1; 5223#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5222#L29-2 havoc main_#t~nondet1#1; 5221#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5220#L29-2 havoc main_#t~nondet1#1; 5219#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5218#L29-2 havoc main_#t~nondet1#1; 5217#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5216#L29-2 havoc main_#t~nondet1#1; 5215#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5214#L29-2 havoc main_#t~nondet1#1; 5213#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5212#L29-2 havoc main_#t~nondet1#1; 5211#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5210#L29-2 havoc main_#t~nondet1#1; 5209#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5208#L29-2 havoc main_#t~nondet1#1; 5207#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5206#L29-2 havoc main_#t~nondet1#1; 5205#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5204#L29-2 havoc main_#t~nondet1#1; 5189#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 5185#L29-3 assume main_~i~0#1 >= 100; 5186#L32 [2024-10-31 22:13:52,717 INFO L747 eck$LassoCheckResult]: Loop: 5186#L32 assume true; 5186#L32 [2024-10-31 22:13:52,718 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:52,722 INFO L85 PathProgramCache]: Analyzing trace with hash -41810454, now seen corresponding path program 5 times [2024-10-31 22:13:52,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:52,722 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705154141] [2024-10-31 22:13:52,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:52,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:52,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:13:54,477 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:54,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:13:54,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [705154141] [2024-10-31 22:13:54,478 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [705154141] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:13:54,478 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1049091907] [2024-10-31 22:13:54,478 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-31 22:13:54,478 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:13:54,478 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:13:54,480 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:13:54,482 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-10-31 22:13:54,582 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-10-31 22:13:54,582 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:13:54,584 INFO L255 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 48 conjuncts are in the unsatisfiable core [2024-10-31 22:13:54,588 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:13:54,790 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:54,790 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:13:58,288 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:13:58,288 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1049091907] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:13:58,288 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:13:58,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2024-10-31 22:13:58,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245598123] [2024-10-31 22:13:58,289 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:13:58,289 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:13:58,290 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:13:58,290 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 11 times [2024-10-31 22:13:58,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:13:58,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850699605] [2024-10-31 22:13:58,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:13:58,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:13:58,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:58,292 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:13:58,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:13:58,293 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:13:58,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:13:58,302 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2024-10-31 22:13:58,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2024-10-31 22:13:58,306 INFO L87 Difference]: Start difference. First operand 195 states and 243 transitions. cyclomatic complexity: 51 Second operand has 97 states, 96 states have (on average 2.0520833333333335) internal successors, (197), 97 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:14:01,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:14:01,414 INFO L93 Difference]: Finished difference Result 7250 states and 7395 transitions. [2024-10-31 22:14:01,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7250 states and 7395 transitions. [2024-10-31 22:14:01,451 INFO L131 ngComponentsAnalysis]: Automaton has 49 accepting balls. 49 [2024-10-31 22:14:01,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7250 states to 7154 states and 7299 transitions. [2024-10-31 22:14:01,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153 [2024-10-31 22:14:01,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153 [2024-10-31 22:14:01,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7154 states and 7299 transitions. [2024-10-31 22:14:01,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:14:01,484 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7154 states and 7299 transitions. [2024-10-31 22:14:01,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7154 states and 7299 transitions. [2024-10-31 22:14:01,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7154 to 291. [2024-10-31 22:14:01,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 291 states, 291 states have (on average 1.3298969072164948) internal successors, (387), 290 states have internal predecessors, (387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:14:01,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 387 transitions. [2024-10-31 22:14:01,521 INFO L240 hiAutomatonCegarLoop]: Abstraction has 291 states and 387 transitions. [2024-10-31 22:14:01,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2024-10-31 22:14:01,523 INFO L425 stractBuchiCegarLoop]: Abstraction has 291 states and 387 transitions. [2024-10-31 22:14:01,523 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:14:01,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 387 transitions. [2024-10-31 22:14:01,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:14:01,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:14:01,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:14:01,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:14:01,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:14:01,527 INFO L745 eck$LassoCheckResult]: Stem: 13316#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 13317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 13322#L26 main_~i~0#1 := 0; 13323#L29-2 havoc main_#t~nondet1#1; 13325#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 13314#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 13315#L35-2 havoc main_#t~nondet3#1; 13321#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13328#L35-2 havoc main_#t~nondet3#1; 13602#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13601#L35-2 havoc main_#t~nondet3#1; 13600#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13599#L35-2 havoc main_#t~nondet3#1; 13598#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13597#L35-2 havoc main_#t~nondet3#1; 13596#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13595#L35-2 havoc main_#t~nondet3#1; 13594#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13593#L35-2 havoc main_#t~nondet3#1; 13592#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13591#L35-2 havoc main_#t~nondet3#1; 13590#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13589#L35-2 havoc main_#t~nondet3#1; 13588#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13587#L35-2 havoc main_#t~nondet3#1; 13586#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13585#L35-2 havoc main_#t~nondet3#1; 13584#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13583#L35-2 havoc main_#t~nondet3#1; 13582#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13581#L35-2 havoc main_#t~nondet3#1; 13580#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13579#L35-2 havoc main_#t~nondet3#1; 13578#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13577#L35-2 havoc main_#t~nondet3#1; 13576#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13575#L35-2 havoc main_#t~nondet3#1; 13574#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13573#L35-2 havoc main_#t~nondet3#1; 13572#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13571#L35-2 havoc main_#t~nondet3#1; 13570#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13569#L35-2 havoc main_#t~nondet3#1; 13568#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13567#L35-2 havoc main_#t~nondet3#1; 13566#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13565#L35-2 havoc main_#t~nondet3#1; 13564#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13563#L35-2 havoc main_#t~nondet3#1; 13562#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13561#L35-2 havoc main_#t~nondet3#1; 13560#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13559#L35-2 havoc main_#t~nondet3#1; 13558#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13557#L35-2 havoc main_#t~nondet3#1; 13556#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13555#L35-2 havoc main_#t~nondet3#1; 13554#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13553#L35-2 havoc main_#t~nondet3#1; 13552#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13551#L35-2 havoc main_#t~nondet3#1; 13550#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13549#L35-2 havoc main_#t~nondet3#1; 13548#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13547#L35-2 havoc main_#t~nondet3#1; 13546#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13545#L35-2 havoc main_#t~nondet3#1; 13544#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13543#L35-2 havoc main_#t~nondet3#1; 13542#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13541#L35-2 havoc main_#t~nondet3#1; 13540#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13539#L35-2 havoc main_#t~nondet3#1; 13538#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13537#L35-2 havoc main_#t~nondet3#1; 13536#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13535#L35-2 havoc main_#t~nondet3#1; 13534#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13533#L35-2 havoc main_#t~nondet3#1; 13532#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13531#L35-2 havoc main_#t~nondet3#1; 13530#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13529#L35-2 havoc main_#t~nondet3#1; 13528#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13527#L35-2 havoc main_#t~nondet3#1; 13526#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13525#L35-2 havoc main_#t~nondet3#1; 13524#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13523#L35-2 havoc main_#t~nondet3#1; 13522#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13521#L35-2 havoc main_#t~nondet3#1; 13520#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13519#L35-2 havoc main_#t~nondet3#1; 13518#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13517#L35-2 havoc main_#t~nondet3#1; 13516#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13515#L35-2 havoc main_#t~nondet3#1; 13514#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13513#L35-2 havoc main_#t~nondet3#1; 13327#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 13324#L35-3 assume main_~j~0#1 >= 100; 13313#L32 [2024-10-31 22:14:01,527 INFO L747 eck$LassoCheckResult]: Loop: 13313#L32 assume true; 13313#L32 [2024-10-31 22:14:01,528 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:14:01,528 INFO L85 PathProgramCache]: Analyzing trace with hash -174540373, now seen corresponding path program 5 times [2024-10-31 22:14:01,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:14:01,528 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610601053] [2024-10-31 22:14:01,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:14:01,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:14:01,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:14:03,561 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:14:03,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:14:03,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610601053] [2024-10-31 22:14:03,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610601053] provided 0 perfect and 1 imperfect interpolant sequences [2024-10-31 22:14:03,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2102166964] [2024-10-31 22:14:03,562 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-10-31 22:14:03,562 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-10-31 22:14:03,562 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:14:03,565 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-10-31 22:14:03,569 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a9be5ab-bd58-402a-95d7-30268771c10b/bin/uautomizer-verify-4GaUIPS5ZU/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-10-31 22:14:03,723 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-10-31 22:14:03,723 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-10-31 22:14:03,726 INFO L255 TraceCheckSpWp]: Trace formula consists of 350 conjuncts, 48 conjuncts are in the unsatisfiable core [2024-10-31 22:14:03,733 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:14:03,945 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:14:03,945 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-10-31 22:14:07,004 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:14:07,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2102166964] provided 0 perfect and 2 imperfect interpolant sequences [2024-10-31 22:14:07,005 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-10-31 22:14:07,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2024-10-31 22:14:07,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1571258633] [2024-10-31 22:14:07,006 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-10-31 22:14:07,006 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:14:07,007 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:14:07,007 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 12 times [2024-10-31 22:14:07,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:14:07,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743534211] [2024-10-31 22:14:07,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:14:07,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:14:07,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:14:07,010 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:14:07,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:14:07,011 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:14:07,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:14:07,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2024-10-31 22:14:07,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2024-10-31 22:14:07,021 INFO L87 Difference]: Start difference. First operand 291 states and 387 transitions. cyclomatic complexity: 99 Second operand has 97 states, 96 states have (on average 2.0833333333333335) internal successors, (200), 97 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:14:07,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:14:07,332 INFO L93 Difference]: Finished difference Result 484 states and 580 transitions. [2024-10-31 22:14:07,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 484 states and 580 transitions. [2024-10-31 22:14:07,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:14:07,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 484 states to 388 states and 484 transitions. [2024-10-31 22:14:07,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-10-31 22:14:07,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-10-31 22:14:07,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 388 states and 484 transitions. [2024-10-31 22:14:07,339 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:14:07,339 INFO L218 hiAutomatonCegarLoop]: Abstraction has 388 states and 484 transitions. [2024-10-31 22:14:07,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388 states and 484 transitions. [2024-10-31 22:14:07,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388 to 387. [2024-10-31 22:14:07,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 387 states, 387 states have (on average 1.248062015503876) internal successors, (483), 386 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:14:07,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 387 states to 387 states and 483 transitions. [2024-10-31 22:14:07,347 INFO L240 hiAutomatonCegarLoop]: Abstraction has 387 states and 483 transitions. [2024-10-31 22:14:07,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2024-10-31 22:14:07,350 INFO L425 stractBuchiCegarLoop]: Abstraction has 387 states and 483 transitions. [2024-10-31 22:14:07,352 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:14:07,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 387 states and 483 transitions. [2024-10-31 22:14:07,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-10-31 22:14:07,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:14:07,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:14:07,358 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 1, 1, 1, 1, 1] [2024-10-31 22:14:07,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-10-31 22:14:07,362 INFO L745 eck$LassoCheckResult]: Stem: 14794#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 14795#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 14798#L26 main_~i~0#1 := 0; 14799#L29-2 havoc main_#t~nondet1#1; 14792#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14793#L29-2 havoc main_#t~nondet1#1; 14803#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14990#L29-2 havoc main_#t~nondet1#1; 14989#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14988#L29-2 havoc main_#t~nondet1#1; 14987#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14986#L29-2 havoc main_#t~nondet1#1; 14985#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14984#L29-2 havoc main_#t~nondet1#1; 14983#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14982#L29-2 havoc main_#t~nondet1#1; 14981#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14980#L29-2 havoc main_#t~nondet1#1; 14979#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14978#L29-2 havoc main_#t~nondet1#1; 14977#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14976#L29-2 havoc main_#t~nondet1#1; 14975#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14974#L29-2 havoc main_#t~nondet1#1; 14973#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14972#L29-2 havoc main_#t~nondet1#1; 14971#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14970#L29-2 havoc main_#t~nondet1#1; 14969#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14968#L29-2 havoc main_#t~nondet1#1; 14967#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14966#L29-2 havoc main_#t~nondet1#1; 14965#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14964#L29-2 havoc main_#t~nondet1#1; 14963#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14962#L29-2 havoc main_#t~nondet1#1; 14961#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14960#L29-2 havoc main_#t~nondet1#1; 14959#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14958#L29-2 havoc main_#t~nondet1#1; 14957#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14956#L29-2 havoc main_#t~nondet1#1; 14955#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14954#L29-2 havoc main_#t~nondet1#1; 14953#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14952#L29-2 havoc main_#t~nondet1#1; 14951#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14950#L29-2 havoc main_#t~nondet1#1; 14949#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14948#L29-2 havoc main_#t~nondet1#1; 14947#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14946#L29-2 havoc main_#t~nondet1#1; 14945#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14944#L29-2 havoc main_#t~nondet1#1; 14943#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14942#L29-2 havoc main_#t~nondet1#1; 14941#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14940#L29-2 havoc main_#t~nondet1#1; 14939#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14938#L29-2 havoc main_#t~nondet1#1; 14937#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14936#L29-2 havoc main_#t~nondet1#1; 14935#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14934#L29-2 havoc main_#t~nondet1#1; 14933#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14932#L29-2 havoc main_#t~nondet1#1; 14931#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14930#L29-2 havoc main_#t~nondet1#1; 14929#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14928#L29-2 havoc main_#t~nondet1#1; 14927#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14926#L29-2 havoc main_#t~nondet1#1; 14925#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14924#L29-2 havoc main_#t~nondet1#1; 14923#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14922#L29-2 havoc main_#t~nondet1#1; 14921#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14920#L29-2 havoc main_#t~nondet1#1; 14919#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14918#L29-2 havoc main_#t~nondet1#1; 14917#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14916#L29-2 havoc main_#t~nondet1#1; 14915#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14914#L29-2 havoc main_#t~nondet1#1; 14913#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14912#L29-2 havoc main_#t~nondet1#1; 14911#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14910#L29-2 havoc main_#t~nondet1#1; 14909#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14908#L29-2 havoc main_#t~nondet1#1; 14907#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14906#L29-2 havoc main_#t~nondet1#1; 14905#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14904#L29-2 havoc main_#t~nondet1#1; 14903#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14902#L29-2 havoc main_#t~nondet1#1; 14901#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14900#L29-2 havoc main_#t~nondet1#1; 14899#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14898#L29-2 havoc main_#t~nondet1#1; 14897#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14896#L29-2 havoc main_#t~nondet1#1; 14895#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14894#L29-2 havoc main_#t~nondet1#1; 14893#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14892#L29-2 havoc main_#t~nondet1#1; 14891#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14890#L29-2 havoc main_#t~nondet1#1; 14889#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14888#L29-2 havoc main_#t~nondet1#1; 14887#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14886#L29-2 havoc main_#t~nondet1#1; 14885#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14884#L29-2 havoc main_#t~nondet1#1; 14883#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14882#L29-2 havoc main_#t~nondet1#1; 14881#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14880#L29-2 havoc main_#t~nondet1#1; 14879#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14878#L29-2 havoc main_#t~nondet1#1; 14877#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14876#L29-2 havoc main_#t~nondet1#1; 14875#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14874#L29-2 havoc main_#t~nondet1#1; 14873#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14872#L29-2 havoc main_#t~nondet1#1; 14871#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14870#L29-2 havoc main_#t~nondet1#1; 14869#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14868#L29-2 havoc main_#t~nondet1#1; 14867#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14866#L29-2 havoc main_#t~nondet1#1; 14865#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14864#L29-2 havoc main_#t~nondet1#1; 14863#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14862#L29-2 havoc main_#t~nondet1#1; 14861#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14860#L29-2 havoc main_#t~nondet1#1; 14859#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14858#L29-2 havoc main_#t~nondet1#1; 14857#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14856#L29-2 havoc main_#t~nondet1#1; 14855#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14854#L29-2 havoc main_#t~nondet1#1; 14853#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14852#L29-2 havoc main_#t~nondet1#1; 14851#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14850#L29-2 havoc main_#t~nondet1#1; 14849#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14848#L29-2 havoc main_#t~nondet1#1; 14847#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14846#L29-2 havoc main_#t~nondet1#1; 14845#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14844#L29-2 havoc main_#t~nondet1#1; 14843#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14842#L29-2 havoc main_#t~nondet1#1; 14841#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14840#L29-2 havoc main_#t~nondet1#1; 14839#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14838#L29-2 havoc main_#t~nondet1#1; 14837#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14836#L29-2 havoc main_#t~nondet1#1; 14835#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14834#L29-2 havoc main_#t~nondet1#1; 14833#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14832#L29-2 havoc main_#t~nondet1#1; 14831#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14830#L29-2 havoc main_#t~nondet1#1; 14829#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14828#L29-2 havoc main_#t~nondet1#1; 14827#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14826#L29-2 havoc main_#t~nondet1#1; 14825#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14824#L29-2 havoc main_#t~nondet1#1; 14823#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14822#L29-2 havoc main_#t~nondet1#1; 14821#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14820#L29-2 havoc main_#t~nondet1#1; 14819#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14818#L29-2 havoc main_#t~nondet1#1; 14817#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14816#L29-2 havoc main_#t~nondet1#1; 14815#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14814#L29-2 havoc main_#t~nondet1#1; 14813#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14812#L29-2 havoc main_#t~nondet1#1; 14811#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14810#L29-2 havoc main_#t~nondet1#1; 14809#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14808#L29-2 havoc main_#t~nondet1#1; 14807#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14806#L29-2 havoc main_#t~nondet1#1; 14791#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 14787#L29-3 assume main_~i~0#1 >= 100; 14788#L32 [2024-10-31 22:14:07,362 INFO L747 eck$LassoCheckResult]: Loop: 14788#L32 assume true; 14788#L32 [2024-10-31 22:14:07,363 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:14:07,363 INFO L85 PathProgramCache]: Analyzing trace with hash 1558585082, now seen corresponding path program 6 times [2024-10-31 22:14:07,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:14:07,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391313665] [2024-10-31 22:14:07,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:14:07,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:14:07,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat