./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:03:20,344 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:03:20,448 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:03:20,454 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:03:20,455 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:03:20,495 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:03:20,497 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:03:20,498 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:03:20,499 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:03:20,500 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:03:20,503 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:03:20,503 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:03:20,504 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:03:20,504 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:03:20,505 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:03:20,505 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:03:20,509 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:03:20,510 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:03:20,510 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:03:20,510 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:03:20,511 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:03:20,511 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:03:20,511 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:03:20,512 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:03:20,512 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:03:20,512 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:03:20,513 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:03:20,514 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:03:20,514 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:03:20,515 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:03:20,515 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:03:20,516 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:03:20,516 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:03:20,517 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:03:20,517 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:03:20,517 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:03:20,517 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:03:20,518 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:03:20,518 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:03:20,519 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea [2024-10-31 22:03:20,814 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:03:20,846 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:03:20,849 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:03:20,851 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:03:20,851 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:03:20,852 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c Unable to find full path for "g++" [2024-10-31 22:03:22,844 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:03:23,111 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:03:23,111 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2024-10-31 22:03:23,123 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/data/4e6eeb1a6/42384583f0304914beb4372578dd4785/FLAGd6c2fa4eb [2024-10-31 22:03:23,139 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/data/4e6eeb1a6/42384583f0304914beb4372578dd4785 [2024-10-31 22:03:23,144 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:03:23,146 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:03:23,150 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:03:23,150 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:03:23,157 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:03:23,158 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,162 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6788f6c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23, skipping insertion in model container [2024-10-31 22:03:23,162 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,200 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:03:23,464 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:03:23,481 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:03:23,541 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:03:23,570 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:03:23,570 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23 WrapperNode [2024-10-31 22:03:23,570 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:03:23,572 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:03:23,572 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:03:23,572 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:03:23,581 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,590 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,644 INFO L138 Inliner]: procedures = 36, calls = 45, calls flagged for inlining = 40, calls inlined = 80, statements flattened = 1087 [2024-10-31 22:03:23,645 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:03:23,646 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:03:23,646 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:03:23,646 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:03:23,667 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,667 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,677 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,714 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:03:23,718 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,718 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,746 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,772 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,774 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,780 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,796 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:03:23,797 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:03:23,797 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:03:23,797 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:03:23,798 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (1/1) ... [2024-10-31 22:03:23,807 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:03:23,820 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:03:23,848 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:03:23,851 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:03:23,887 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:03:23,888 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:03:23,888 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:03:23,888 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:03:24,007 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:03:24,009 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:03:25,245 INFO L? ?]: Removed 198 outVars from TransFormulas that were not future-live. [2024-10-31 22:03:25,247 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:03:25,272 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:03:25,272 INFO L316 CfgBuilder]: Removed 7 assume(true) statements. [2024-10-31 22:03:25,273 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:03:25 BoogieIcfgContainer [2024-10-31 22:03:25,273 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:03:25,274 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:03:25,274 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:03:25,281 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:03:25,282 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:03:25,282 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:03:23" (1/3) ... [2024-10-31 22:03:25,283 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@58c5df55 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:03:25, skipping insertion in model container [2024-10-31 22:03:25,283 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:03:25,283 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:03:23" (2/3) ... [2024-10-31 22:03:25,285 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@58c5df55 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:03:25, skipping insertion in model container [2024-10-31 22:03:25,286 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:03:25,286 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:03:25" (3/3) ... [2024-10-31 22:03:25,288 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2024-10-31 22:03:25,361 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:03:25,361 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:03:25,361 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:03:25,361 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:03:25,362 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:03:25,362 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:03:25,362 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:03:25,362 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:03:25,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:25,408 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2024-10-31 22:03:25,408 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:25,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:25,426 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:25,426 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:25,427 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:03:25,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:25,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2024-10-31 22:03:25,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:25,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:25,449 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:25,450 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:25,459 INFO L745 eck$LassoCheckResult]: Stem: 142#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 364#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 220#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 359#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49#L365true assume !(1 == ~m_i~0);~m_st~0 := 2; 334#L365-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 233#L370-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 187#L375-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 341#L380-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 213#L385-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 195#L526true assume !(0 == ~M_E~0); 421#L526-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 236#L531-1true assume !(0 == ~T2_E~0); 185#L536-1true assume !(0 == ~T3_E~0); 296#L541-1true assume !(0 == ~T4_E~0); 183#L546-1true assume !(0 == ~E_M~0); 248#L551-1true assume !(0 == ~E_1~0); 165#L556-1true assume !(0 == ~E_2~0); 192#L561-1true assume !(0 == ~E_3~0); 172#L566-1true assume 0 == ~E_4~0;~E_4~0 := 1; 376#L571-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168#L262true assume 1 == ~m_pc~0; 443#L263true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 380#L273true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 377#L649true assume !(0 != activate_threads_~tmp~1#1); 438#L649-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129#L281true assume !(1 == ~t1_pc~0); 394#L281-2true is_transmit1_triggered_~__retres1~1#1 := 0; 79#L292true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115#L657true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 361#L657-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175#L300true assume 1 == ~t2_pc~0; 308#L301true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 274#L311true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190#L665true assume !(0 != activate_threads_~tmp___1~0#1); 38#L665-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 445#L319true assume !(1 == ~t3_pc~0); 17#L319-2true is_transmit3_triggered_~__retres1~3#1 := 0; 277#L330true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141#L673true assume !(0 != activate_threads_~tmp___2~0#1); 27#L673-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278#L338true assume 1 == ~t4_pc~0; 112#L339true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73#L349true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 384#L681true assume !(0 != activate_threads_~tmp___3~0#1); 2#L681-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 374#L584true assume !(1 == ~M_E~0); 113#L584-2true assume !(1 == ~T1_E~0); 88#L589-1true assume !(1 == ~T2_E~0); 262#L594-1true assume !(1 == ~T3_E~0); 144#L599-1true assume !(1 == ~T4_E~0); 16#L604-1true assume !(1 == ~E_M~0); 9#L609-1true assume 1 == ~E_1~0;~E_1~0 := 2; 72#L614-1true assume !(1 == ~E_2~0); 125#L619-1true assume !(1 == ~E_3~0); 188#L624-1true assume !(1 == ~E_4~0); 401#L629-1true assume { :end_inline_reset_delta_events } true; 207#L815-2true [2024-10-31 22:03:25,461 INFO L747 eck$LassoCheckResult]: Loop: 207#L815-2true assume !false; 388#L816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 420#L501-1true assume false; 74#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 325#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145#L526-3true assume 0 == ~M_E~0;~M_E~0 := 1; 268#L526-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 75#L531-3true assume !(0 == ~T2_E~0); 395#L536-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 13#L541-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 189#L546-3true assume 0 == ~E_M~0;~E_M~0 := 1; 439#L551-3true assume 0 == ~E_1~0;~E_1~0 := 1; 154#L556-3true assume 0 == ~E_2~0;~E_2~0 := 1; 243#L561-3true assume 0 == ~E_3~0;~E_3~0 := 1; 318#L566-3true assume 0 == ~E_4~0;~E_4~0 := 1; 81#L571-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 267#L262-18true assume !(1 == ~m_pc~0); 137#L262-20true is_master_triggered_~__retres1~0#1 := 0; 292#L273-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149#is_master_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 373#L649-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20#L649-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163#L281-18true assume !(1 == ~t1_pc~0); 271#L281-20true is_transmit1_triggered_~__retres1~1#1 := 0; 178#L292-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 368#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 418#L657-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 293#L657-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 333#L300-18true assume !(1 == ~t2_pc~0); 14#L300-20true is_transmit2_triggered_~__retres1~2#1 := 0; 47#L311-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 217#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 255#L665-18true assume !(0 != activate_threads_~tmp___1~0#1); 319#L665-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80#L319-18true assume !(1 == ~t3_pc~0); 247#L319-20true is_transmit3_triggered_~__retres1~3#1 := 0; 96#L330-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 219#L673-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 204#L673-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128#L338-18true assume !(1 == ~t4_pc~0); 161#L338-20true is_transmit4_triggered_~__retres1~4#1 := 0; 106#L349-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29#L681-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 179#L681-20true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140#L584-3true assume 1 == ~M_E~0;~M_E~0 := 2; 290#L584-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 28#L589-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 135#L594-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 216#L599-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 156#L604-3true assume 1 == ~E_M~0;~E_M~0 := 2; 406#L609-3true assume 1 == ~E_1~0;~E_1~0 := 2; 203#L614-3true assume !(1 == ~E_2~0); 24#L619-3true assume 1 == ~E_3~0;~E_3~0 := 2; 214#L624-3true assume 1 == ~E_4~0;~E_4~0 := 2; 249#L629-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 257#L398-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68#L425-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 199#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 101#L834true assume !(0 == start_simulation_~tmp~3#1); 223#L834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 355#L398-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 218#L425-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 295#L789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 305#L796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 336#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 205#L847true assume !(0 != start_simulation_~tmp___0~1#1); 207#L815-2true [2024-10-31 22:03:25,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:25,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2024-10-31 22:03:25,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:25,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208841247] [2024-10-31 22:03:25,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:25,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:25,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:25,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:25,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:25,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208841247] [2024-10-31 22:03:25,786 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1208841247] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:25,786 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:25,786 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:25,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681125158] [2024-10-31 22:03:25,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:25,794 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:25,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:25,795 INFO L85 PathProgramCache]: Analyzing trace with hash 315649613, now seen corresponding path program 1 times [2024-10-31 22:03:25,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:25,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170005597] [2024-10-31 22:03:25,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:25,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:25,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:25,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:25,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:25,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170005597] [2024-10-31 22:03:25,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170005597] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:25,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:25,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:03:25,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640693412] [2024-10-31 22:03:25,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:25,867 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:25,868 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:25,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:25,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:25,900 INFO L87 Difference]: Start difference. First operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:25,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:25,958 INFO L93 Difference]: Finished difference Result 441 states and 657 transitions. [2024-10-31 22:03:25,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 441 states and 657 transitions. [2024-10-31 22:03:25,969 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:25,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 441 states to 435 states and 651 transitions. [2024-10-31 22:03:25,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-10-31 22:03:25,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-10-31 22:03:25,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 651 transitions. [2024-10-31 22:03:25,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:25,985 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 651 transitions. [2024-10-31 22:03:26,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 651 transitions. [2024-10-31 22:03:26,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-10-31 22:03:26,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4965517241379311) internal successors, (651), 434 states have internal predecessors, (651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:26,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 651 transitions. [2024-10-31 22:03:26,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 651 transitions. [2024-10-31 22:03:26,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:26,068 INFO L425 stractBuchiCegarLoop]: Abstraction has 435 states and 651 transitions. [2024-10-31 22:03:26,070 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:03:26,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 651 transitions. [2024-10-31 22:03:26,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:26,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:26,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:26,078 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:26,078 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:26,082 INFO L745 eck$LassoCheckResult]: Stem: 1142#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1143#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1235#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1236#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 992#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 993#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1244#L370-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1205#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1206#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1230#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1215#L526 assume !(0 == ~M_E~0); 1216#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1246#L531-1 assume !(0 == ~T2_E~0); 1201#L536-1 assume !(0 == ~T3_E~0); 1202#L541-1 assume !(0 == ~T4_E~0); 1197#L546-1 assume !(0 == ~E_M~0); 1198#L551-1 assume !(0 == ~E_1~0); 1173#L556-1 assume !(0 == ~E_2~0); 1174#L561-1 assume !(0 == ~E_3~0); 1184#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1185#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1178#L262 assume 1 == ~m_pc~0; 1179#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1324#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1112#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1113#L649 assume !(0 != activate_threads_~tmp~1#1); 1323#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1122#L281 assume !(1 == ~t1_pc~0); 1123#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1043#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 959#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 960#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1099#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1187#L300 assume 1 == ~t2_pc~0; 1188#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1277#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1238#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1209#L665 assume !(0 != activate_threads_~tmp___1~0#1); 972#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 973#L319 assume !(1 == ~t3_pc~0); 928#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 929#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 915#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 916#L673 assume !(0 != activate_threads_~tmp___2~0#1); 949#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 950#L338 assume 1 == ~t4_pc~0; 1095#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1018#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1023#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1024#L681 assume !(0 != activate_threads_~tmp___3~0#1); 895#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 896#L584 assume !(1 == ~M_E~0); 1096#L584-2 assume !(1 == ~T1_E~0); 1057#L589-1 assume !(1 == ~T2_E~0); 1058#L594-1 assume !(1 == ~T3_E~0); 1146#L599-1 assume !(1 == ~T4_E~0); 927#L604-1 assume !(1 == ~E_M~0); 913#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 914#L614-1 assume !(1 == ~E_2~0); 1032#L619-1 assume !(1 == ~E_3~0); 1114#L624-1 assume !(1 == ~E_4~0); 1207#L629-1 assume { :end_inline_reset_delta_events } true; 1226#L815-2 [2024-10-31 22:03:26,083 INFO L747 eck$LassoCheckResult]: Loop: 1226#L815-2 assume !false; 1227#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1104#L501-1 assume !false; 1320#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1321#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1038#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1251#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1252#L440 assume !(0 != eval_~tmp~0#1); 1033#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1034#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1147#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1148#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1035#L531-3 assume !(0 == ~T2_E~0); 1036#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 921#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 922#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1208#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1159#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1160#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1256#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1047#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1048#L262-18 assume 1 == ~m_pc~0; 1271#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1136#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1153#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1154#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 934#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 935#L281-18 assume 1 == ~t1_pc~0; 1170#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1190#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1191#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1322#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1293#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1294#L300-18 assume 1 == ~t2_pc~0; 1168#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 924#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 991#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1233#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 1262#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1044#L319-18 assume 1 == ~t3_pc~0; 1045#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1050#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1071#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1234#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1224#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1119#L338-18 assume !(1 == ~t4_pc~0); 1120#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1088#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1089#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 953#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 954#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1140#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1141#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 951#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 952#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1133#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1162#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1163#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1223#L614-3 assume !(1 == ~E_2~0); 943#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 944#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1231#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1260#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1026#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1027#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1078#L834 assume !(0 == start_simulation_~tmp~3#1); 1079#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1239#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1200#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 957#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 958#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1295#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1300#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1225#L847 assume !(0 != start_simulation_~tmp___0~1#1); 1226#L815-2 [2024-10-31 22:03:26,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:26,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2024-10-31 22:03:26,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:26,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156131911] [2024-10-31 22:03:26,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:26,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:26,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:26,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:26,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:26,195 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156131911] [2024-10-31 22:03:26,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156131911] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:26,196 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:26,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:26,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583606701] [2024-10-31 22:03:26,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:26,197 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:26,198 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:26,198 INFO L85 PathProgramCache]: Analyzing trace with hash -1098449818, now seen corresponding path program 1 times [2024-10-31 22:03:26,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:26,199 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195055116] [2024-10-31 22:03:26,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:26,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:26,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:26,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:26,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:26,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195055116] [2024-10-31 22:03:26,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195055116] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:26,316 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:26,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:26,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448049146] [2024-10-31 22:03:26,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:26,317 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:26,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:26,318 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:26,318 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:26,319 INFO L87 Difference]: Start difference. First operand 435 states and 651 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:26,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:26,344 INFO L93 Difference]: Finished difference Result 435 states and 650 transitions. [2024-10-31 22:03:26,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 650 transitions. [2024-10-31 22:03:26,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:26,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 650 transitions. [2024-10-31 22:03:26,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-10-31 22:03:26,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-10-31 22:03:26,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 650 transitions. [2024-10-31 22:03:26,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:26,355 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 650 transitions. [2024-10-31 22:03:26,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 650 transitions. [2024-10-31 22:03:26,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-10-31 22:03:26,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4942528735632183) internal successors, (650), 434 states have internal predecessors, (650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:26,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 650 transitions. [2024-10-31 22:03:26,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 650 transitions. [2024-10-31 22:03:26,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:26,371 INFO L425 stractBuchiCegarLoop]: Abstraction has 435 states and 650 transitions. [2024-10-31 22:03:26,372 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:03:26,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 650 transitions. [2024-10-31 22:03:26,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:26,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:26,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:26,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:26,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:26,378 INFO L745 eck$LassoCheckResult]: Stem: 2019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2112#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2113#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1869#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1870#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2121#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2082#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2083#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2107#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2092#L526 assume !(0 == ~M_E~0); 2093#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2123#L531-1 assume !(0 == ~T2_E~0); 2078#L536-1 assume !(0 == ~T3_E~0); 2079#L541-1 assume !(0 == ~T4_E~0); 2074#L546-1 assume !(0 == ~E_M~0); 2075#L551-1 assume !(0 == ~E_1~0); 2050#L556-1 assume !(0 == ~E_2~0); 2051#L561-1 assume !(0 == ~E_3~0); 2061#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2062#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2055#L262 assume 1 == ~m_pc~0; 2056#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2201#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1989#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1990#L649 assume !(0 != activate_threads_~tmp~1#1); 2200#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1999#L281 assume !(1 == ~t1_pc~0); 2000#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1920#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1836#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1837#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1976#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2064#L300 assume 1 == ~t2_pc~0; 2065#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2154#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2115#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2086#L665 assume !(0 != activate_threads_~tmp___1~0#1); 1849#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1850#L319 assume !(1 == ~t3_pc~0); 1805#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1806#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1792#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1793#L673 assume !(0 != activate_threads_~tmp___2~0#1); 1826#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1827#L338 assume 1 == ~t4_pc~0; 1972#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1895#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1900#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1901#L681 assume !(0 != activate_threads_~tmp___3~0#1); 1772#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1773#L584 assume !(1 == ~M_E~0); 1973#L584-2 assume !(1 == ~T1_E~0); 1934#L589-1 assume !(1 == ~T2_E~0); 1935#L594-1 assume !(1 == ~T3_E~0); 2023#L599-1 assume !(1 == ~T4_E~0); 1804#L604-1 assume !(1 == ~E_M~0); 1790#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1791#L614-1 assume !(1 == ~E_2~0); 1909#L619-1 assume !(1 == ~E_3~0); 1991#L624-1 assume !(1 == ~E_4~0); 2084#L629-1 assume { :end_inline_reset_delta_events } true; 2103#L815-2 [2024-10-31 22:03:26,378 INFO L747 eck$LassoCheckResult]: Loop: 2103#L815-2 assume !false; 2104#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1981#L501-1 assume !false; 2197#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2198#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1915#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2128#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2129#L440 assume !(0 != eval_~tmp~0#1); 1910#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1911#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2024#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2025#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1912#L531-3 assume !(0 == ~T2_E~0); 1913#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1798#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1799#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2085#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2036#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2037#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2133#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1924#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1925#L262-18 assume 1 == ~m_pc~0; 2148#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2013#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2030#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2031#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1811#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1812#L281-18 assume !(1 == ~t1_pc~0); 2048#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2067#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2068#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2199#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2170#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2171#L300-18 assume !(1 == ~t2_pc~0); 1800#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 1801#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1868#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2110#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 2139#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1921#L319-18 assume 1 == ~t3_pc~0; 1922#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1927#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1948#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2111#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2101#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1996#L338-18 assume !(1 == ~t4_pc~0); 1997#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1965#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1966#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1830#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1831#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2017#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2018#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1828#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1829#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2010#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2039#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2040#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2100#L614-3 assume !(1 == ~E_2~0); 1820#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1821#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2108#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2137#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1903#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1904#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1955#L834 assume !(0 == start_simulation_~tmp~3#1); 1956#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2116#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2077#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1835#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2172#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2177#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2102#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2103#L815-2 [2024-10-31 22:03:26,379 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:26,379 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2024-10-31 22:03:26,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:26,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362704029] [2024-10-31 22:03:26,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:26,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:26,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:26,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:26,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:26,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362704029] [2024-10-31 22:03:26,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362704029] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:26,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:26,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:26,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550382966] [2024-10-31 22:03:26,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:26,461 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:26,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:26,461 INFO L85 PathProgramCache]: Analyzing trace with hash 817900584, now seen corresponding path program 1 times [2024-10-31 22:03:26,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:26,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896440315] [2024-10-31 22:03:26,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:26,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:26,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:26,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:26,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:26,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896440315] [2024-10-31 22:03:26,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896440315] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:26,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:26,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:26,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900681853] [2024-10-31 22:03:26,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:26,560 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:26,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:26,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:26,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:26,561 INFO L87 Difference]: Start difference. First operand 435 states and 650 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:26,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:26,589 INFO L93 Difference]: Finished difference Result 435 states and 649 transitions. [2024-10-31 22:03:26,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 649 transitions. [2024-10-31 22:03:26,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:26,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 649 transitions. [2024-10-31 22:03:26,597 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-10-31 22:03:26,597 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-10-31 22:03:26,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 649 transitions. [2024-10-31 22:03:26,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:26,601 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 649 transitions. [2024-10-31 22:03:26,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 649 transitions. [2024-10-31 22:03:26,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-10-31 22:03:26,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4919540229885058) internal successors, (649), 434 states have internal predecessors, (649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:26,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 649 transitions. [2024-10-31 22:03:26,627 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 649 transitions. [2024-10-31 22:03:26,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:26,629 INFO L425 stractBuchiCegarLoop]: Abstraction has 435 states and 649 transitions. [2024-10-31 22:03:26,629 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:03:26,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 649 transitions. [2024-10-31 22:03:26,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:26,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:26,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:26,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:26,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:26,635 INFO L745 eck$LassoCheckResult]: Stem: 2896#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2989#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2990#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2746#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 2747#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2998#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2959#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2960#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2984#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2969#L526 assume !(0 == ~M_E~0); 2970#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3000#L531-1 assume !(0 == ~T2_E~0); 2955#L536-1 assume !(0 == ~T3_E~0); 2956#L541-1 assume !(0 == ~T4_E~0); 2951#L546-1 assume !(0 == ~E_M~0); 2952#L551-1 assume !(0 == ~E_1~0); 2927#L556-1 assume !(0 == ~E_2~0); 2928#L561-1 assume !(0 == ~E_3~0); 2938#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2939#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2932#L262 assume 1 == ~m_pc~0; 2933#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3078#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2866#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2867#L649 assume !(0 != activate_threads_~tmp~1#1); 3077#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2876#L281 assume !(1 == ~t1_pc~0); 2877#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2797#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2714#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2853#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2941#L300 assume 1 == ~t2_pc~0; 2942#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3031#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2963#L665 assume !(0 != activate_threads_~tmp___1~0#1); 2726#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2727#L319 assume !(1 == ~t3_pc~0); 2682#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2683#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2669#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2670#L673 assume !(0 != activate_threads_~tmp___2~0#1); 2703#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2704#L338 assume 1 == ~t4_pc~0; 2849#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2772#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2778#L681 assume !(0 != activate_threads_~tmp___3~0#1); 2649#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2650#L584 assume !(1 == ~M_E~0); 2850#L584-2 assume !(1 == ~T1_E~0); 2811#L589-1 assume !(1 == ~T2_E~0); 2812#L594-1 assume !(1 == ~T3_E~0); 2900#L599-1 assume !(1 == ~T4_E~0); 2681#L604-1 assume !(1 == ~E_M~0); 2667#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2668#L614-1 assume !(1 == ~E_2~0); 2786#L619-1 assume !(1 == ~E_3~0); 2868#L624-1 assume !(1 == ~E_4~0); 2961#L629-1 assume { :end_inline_reset_delta_events } true; 2980#L815-2 [2024-10-31 22:03:26,635 INFO L747 eck$LassoCheckResult]: Loop: 2980#L815-2 assume !false; 2981#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2858#L501-1 assume !false; 3074#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3075#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2792#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3005#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3006#L440 assume !(0 != eval_~tmp~0#1); 2787#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2788#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2901#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2902#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2789#L531-3 assume !(0 == ~T2_E~0); 2790#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2675#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2676#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2962#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2913#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2914#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3010#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2801#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2802#L262-18 assume 1 == ~m_pc~0; 3025#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2890#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2907#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2908#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2688#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2689#L281-18 assume 1 == ~t1_pc~0; 2924#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2944#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2945#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3076#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3047#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3048#L300-18 assume !(1 == ~t2_pc~0); 2677#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 2678#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2745#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2987#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 3016#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2798#L319-18 assume !(1 == ~t3_pc~0); 2800#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2804#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2825#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2988#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2978#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2873#L338-18 assume !(1 == ~t4_pc~0); 2874#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 2842#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2843#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2707#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2708#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2894#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2895#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2705#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2706#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2887#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2916#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2917#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2977#L614-3 assume !(1 == ~E_2~0); 2697#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2698#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2985#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3014#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2780#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2781#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2832#L834 assume !(0 == start_simulation_~tmp~3#1); 2833#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2993#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2954#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2712#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3049#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3054#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2979#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2980#L815-2 [2024-10-31 22:03:26,636 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:26,636 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2024-10-31 22:03:26,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:26,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248385189] [2024-10-31 22:03:26,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:26,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:26,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:26,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:26,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:26,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248385189] [2024-10-31 22:03:26,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248385189] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:26,718 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:26,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:26,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141475967] [2024-10-31 22:03:26,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:26,720 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:26,721 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:26,722 INFO L85 PathProgramCache]: Analyzing trace with hash -532175448, now seen corresponding path program 1 times [2024-10-31 22:03:26,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:26,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1976888815] [2024-10-31 22:03:26,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:26,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:26,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:26,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:26,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:26,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1976888815] [2024-10-31 22:03:26,815 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1976888815] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:26,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:26,816 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:26,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141362327] [2024-10-31 22:03:26,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:26,817 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:26,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:26,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:26,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:26,819 INFO L87 Difference]: Start difference. First operand 435 states and 649 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:26,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:26,863 INFO L93 Difference]: Finished difference Result 435 states and 648 transitions. [2024-10-31 22:03:26,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 648 transitions. [2024-10-31 22:03:26,866 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:26,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 648 transitions. [2024-10-31 22:03:26,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-10-31 22:03:26,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-10-31 22:03:26,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 648 transitions. [2024-10-31 22:03:26,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:26,873 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 648 transitions. [2024-10-31 22:03:26,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 648 transitions. [2024-10-31 22:03:26,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-10-31 22:03:26,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4896551724137932) internal successors, (648), 434 states have internal predecessors, (648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:26,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 648 transitions. [2024-10-31 22:03:26,887 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 648 transitions. [2024-10-31 22:03:26,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:26,888 INFO L425 stractBuchiCegarLoop]: Abstraction has 435 states and 648 transitions. [2024-10-31 22:03:26,888 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:03:26,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 648 transitions. [2024-10-31 22:03:26,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:26,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:26,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:26,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:26,898 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:26,898 INFO L745 eck$LassoCheckResult]: Stem: 3773#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3623#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 3624#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3875#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3836#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3837#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3861#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3846#L526 assume !(0 == ~M_E~0); 3847#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3877#L531-1 assume !(0 == ~T2_E~0); 3832#L536-1 assume !(0 == ~T3_E~0); 3833#L541-1 assume !(0 == ~T4_E~0); 3828#L546-1 assume !(0 == ~E_M~0); 3829#L551-1 assume !(0 == ~E_1~0); 3804#L556-1 assume !(0 == ~E_2~0); 3805#L561-1 assume !(0 == ~E_3~0); 3815#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3816#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3809#L262 assume 1 == ~m_pc~0; 3810#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3955#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3743#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3744#L649 assume !(0 != activate_threads_~tmp~1#1); 3954#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3753#L281 assume !(1 == ~t1_pc~0); 3754#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3674#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3590#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3591#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3730#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3818#L300 assume 1 == ~t2_pc~0; 3819#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3908#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3869#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3840#L665 assume !(0 != activate_threads_~tmp___1~0#1); 3603#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3604#L319 assume !(1 == ~t3_pc~0); 3559#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3560#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3546#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3547#L673 assume !(0 != activate_threads_~tmp___2~0#1); 3580#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3581#L338 assume 1 == ~t4_pc~0; 3726#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3649#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3654#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3655#L681 assume !(0 != activate_threads_~tmp___3~0#1); 3526#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3527#L584 assume !(1 == ~M_E~0); 3727#L584-2 assume !(1 == ~T1_E~0); 3688#L589-1 assume !(1 == ~T2_E~0); 3689#L594-1 assume !(1 == ~T3_E~0); 3777#L599-1 assume !(1 == ~T4_E~0); 3558#L604-1 assume !(1 == ~E_M~0); 3544#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3545#L614-1 assume !(1 == ~E_2~0); 3663#L619-1 assume !(1 == ~E_3~0); 3745#L624-1 assume !(1 == ~E_4~0); 3838#L629-1 assume { :end_inline_reset_delta_events } true; 3857#L815-2 [2024-10-31 22:03:26,898 INFO L747 eck$LassoCheckResult]: Loop: 3857#L815-2 assume !false; 3858#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3735#L501-1 assume !false; 3951#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3952#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3669#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3882#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3883#L440 assume !(0 != eval_~tmp~0#1); 3664#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3665#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3778#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3779#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3666#L531-3 assume !(0 == ~T2_E~0); 3667#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3552#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3553#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3839#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3790#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3791#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3887#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3678#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3679#L262-18 assume !(1 == ~m_pc~0); 3766#L262-20 is_master_triggered_~__retres1~0#1 := 0; 3767#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3784#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3785#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3565#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3566#L281-18 assume 1 == ~t1_pc~0; 3801#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3821#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3822#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3953#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3924#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3925#L300-18 assume !(1 == ~t2_pc~0); 3554#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 3555#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3622#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3864#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 3893#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3675#L319-18 assume 1 == ~t3_pc~0; 3676#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3681#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3702#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3865#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3855#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3750#L338-18 assume !(1 == ~t4_pc~0); 3751#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3719#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3720#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3584#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3585#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3771#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3772#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3582#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3583#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3764#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3793#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3794#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3854#L614-3 assume !(1 == ~E_2~0); 3574#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3575#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3862#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3891#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3657#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3658#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3709#L834 assume !(0 == start_simulation_~tmp~3#1); 3710#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3870#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3831#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3588#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3589#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3926#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3931#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3856#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3857#L815-2 [2024-10-31 22:03:26,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:26,899 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2024-10-31 22:03:26,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:26,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294859416] [2024-10-31 22:03:26,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:26,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:26,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:26,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:26,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:26,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294859416] [2024-10-31 22:03:26,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294859416] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:26,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:26,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:03:26,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [384900291] [2024-10-31 22:03:26,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:26,969 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:26,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:26,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1857403032, now seen corresponding path program 1 times [2024-10-31 22:03:26,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:26,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938796049] [2024-10-31 22:03:26,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:26,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:26,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:27,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:27,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:27,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938796049] [2024-10-31 22:03:27,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1938796049] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:27,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:27,034 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:27,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270270626] [2024-10-31 22:03:27,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:27,034 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:27,035 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:27,035 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:27,035 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:27,035 INFO L87 Difference]: Start difference. First operand 435 states and 648 transitions. cyclomatic complexity: 214 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:27,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:27,061 INFO L93 Difference]: Finished difference Result 435 states and 643 transitions. [2024-10-31 22:03:27,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 643 transitions. [2024-10-31 22:03:27,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:27,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 643 transitions. [2024-10-31 22:03:27,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-10-31 22:03:27,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-10-31 22:03:27,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 643 transitions. [2024-10-31 22:03:27,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:27,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 643 transitions. [2024-10-31 22:03:27,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 643 transitions. [2024-10-31 22:03:27,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-10-31 22:03:27,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4781609195402299) internal successors, (643), 434 states have internal predecessors, (643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:27,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 643 transitions. [2024-10-31 22:03:27,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 643 transitions. [2024-10-31 22:03:27,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:27,082 INFO L425 stractBuchiCegarLoop]: Abstraction has 435 states and 643 transitions. [2024-10-31 22:03:27,084 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:03:27,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 643 transitions. [2024-10-31 22:03:27,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-10-31 22:03:27,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:27,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:27,088 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:27,088 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:27,089 INFO L745 eck$LassoCheckResult]: Stem: 4650#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4743#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4744#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4500#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 4501#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4753#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4713#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4714#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4739#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4723#L526 assume !(0 == ~M_E~0); 4724#L526-2 assume !(0 == ~T1_E~0); 4755#L531-1 assume !(0 == ~T2_E~0); 4709#L536-1 assume !(0 == ~T3_E~0); 4710#L541-1 assume !(0 == ~T4_E~0); 4705#L546-1 assume !(0 == ~E_M~0); 4706#L551-1 assume !(0 == ~E_1~0); 4681#L556-1 assume !(0 == ~E_2~0); 4682#L561-1 assume !(0 == ~E_3~0); 4692#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4693#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4686#L262 assume 1 == ~m_pc~0; 4687#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4832#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4620#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4621#L649 assume !(0 != activate_threads_~tmp~1#1); 4831#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4630#L281 assume !(1 == ~t1_pc~0); 4631#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4551#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4467#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4468#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4607#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4695#L300 assume 1 == ~t2_pc~0; 4696#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4785#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4746#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4717#L665 assume !(0 != activate_threads_~tmp___1~0#1); 4480#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4481#L319 assume !(1 == ~t3_pc~0); 4436#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4437#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4424#L673 assume !(0 != activate_threads_~tmp___2~0#1); 4457#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4458#L338 assume 1 == ~t4_pc~0; 4603#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4526#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4532#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4533#L681 assume !(0 != activate_threads_~tmp___3~0#1); 4403#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4404#L584 assume !(1 == ~M_E~0); 4604#L584-2 assume !(1 == ~T1_E~0); 4565#L589-1 assume !(1 == ~T2_E~0); 4566#L594-1 assume !(1 == ~T3_E~0); 4654#L599-1 assume !(1 == ~T4_E~0); 4435#L604-1 assume !(1 == ~E_M~0); 4421#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4422#L614-1 assume !(1 == ~E_2~0); 4540#L619-1 assume !(1 == ~E_3~0); 4622#L624-1 assume !(1 == ~E_4~0); 4715#L629-1 assume { :end_inline_reset_delta_events } true; 4734#L815-2 [2024-10-31 22:03:27,093 INFO L747 eck$LassoCheckResult]: Loop: 4734#L815-2 assume !false; 4735#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4612#L501-1 assume !false; 4828#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4829#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4546#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4759#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4760#L440 assume !(0 != eval_~tmp~0#1); 4541#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4542#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4655#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4656#L526-5 assume !(0 == ~T1_E~0); 4543#L531-3 assume !(0 == ~T2_E~0); 4544#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4431#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4432#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4716#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4667#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4668#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4763#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4555#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4556#L262-18 assume !(1 == ~m_pc~0); 4642#L262-20 is_master_triggered_~__retres1~0#1 := 0; 4643#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4661#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4662#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4442#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4443#L281-18 assume 1 == ~t1_pc~0; 4678#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4698#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4699#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4830#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4801#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4802#L300-18 assume 1 == ~t2_pc~0; 4676#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4430#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4741#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 4770#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4552#L319-18 assume 1 == ~t3_pc~0; 4553#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4558#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4579#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4742#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4732#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4627#L338-18 assume !(1 == ~t4_pc~0); 4628#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 4596#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4597#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4461#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4462#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4648#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4649#L584-5 assume !(1 == ~T1_E~0); 4459#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4460#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4641#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4670#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4671#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4731#L614-3 assume !(1 == ~E_2~0); 4451#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4452#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4738#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4768#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4534#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4535#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4586#L834 assume !(0 == start_simulation_~tmp~3#1); 4587#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4747#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4708#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4465#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4466#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4803#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4808#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4733#L847 assume !(0 != start_simulation_~tmp___0~1#1); 4734#L815-2 [2024-10-31 22:03:27,093 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:27,094 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2024-10-31 22:03:27,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:27,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864086891] [2024-10-31 22:03:27,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:27,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:27,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:27,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:27,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:27,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864086891] [2024-10-31 22:03:27,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864086891] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:27,193 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:27,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:27,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1793641181] [2024-10-31 22:03:27,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:27,194 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:27,195 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:27,195 INFO L85 PathProgramCache]: Analyzing trace with hash -1570770201, now seen corresponding path program 1 times [2024-10-31 22:03:27,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:27,195 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102085569] [2024-10-31 22:03:27,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:27,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:27,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:27,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:27,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:27,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102085569] [2024-10-31 22:03:27,265 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102085569] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:27,265 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:27,265 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:27,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265850497] [2024-10-31 22:03:27,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:27,267 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:27,267 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:27,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:03:27,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:03:27,268 INFO L87 Difference]: Start difference. First operand 435 states and 643 transitions. cyclomatic complexity: 209 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:27,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:27,440 INFO L93 Difference]: Finished difference Result 730 states and 1076 transitions. [2024-10-31 22:03:27,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 730 states and 1076 transitions. [2024-10-31 22:03:27,446 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2024-10-31 22:03:27,450 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 730 states to 730 states and 1076 transitions. [2024-10-31 22:03:27,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 730 [2024-10-31 22:03:27,451 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 730 [2024-10-31 22:03:27,451 INFO L73 IsDeterministic]: Start isDeterministic. Operand 730 states and 1076 transitions. [2024-10-31 22:03:27,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:27,453 INFO L218 hiAutomatonCegarLoop]: Abstraction has 730 states and 1076 transitions. [2024-10-31 22:03:27,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 730 states and 1076 transitions. [2024-10-31 22:03:27,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 730 to 729. [2024-10-31 22:03:27,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.4746227709190671) internal successors, (1075), 728 states have internal predecessors, (1075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:27,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1075 transitions. [2024-10-31 22:03:27,489 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1075 transitions. [2024-10-31 22:03:27,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:03:27,494 INFO L425 stractBuchiCegarLoop]: Abstraction has 729 states and 1075 transitions. [2024-10-31 22:03:27,494 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:03:27,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 729 states and 1075 transitions. [2024-10-31 22:03:27,498 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2024-10-31 22:03:27,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:27,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:27,500 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:27,500 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:27,500 INFO L745 eck$LassoCheckResult]: Stem: 5825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5920#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5921#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5675#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 5676#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5930#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5888#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5889#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5915#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5899#L526 assume !(0 == ~M_E~0); 5900#L526-2 assume !(0 == ~T1_E~0); 5932#L531-1 assume !(0 == ~T2_E~0); 5884#L536-1 assume !(0 == ~T3_E~0); 5885#L541-1 assume !(0 == ~T4_E~0); 5880#L546-1 assume !(0 == ~E_M~0); 5881#L551-1 assume !(0 == ~E_1~0); 5856#L556-1 assume !(0 == ~E_2~0); 5857#L561-1 assume !(0 == ~E_3~0); 5867#L566-1 assume !(0 == ~E_4~0); 5868#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5861#L262 assume 1 == ~m_pc~0; 5862#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6011#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5795#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5796#L649 assume !(0 != activate_threads_~tmp~1#1); 6010#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5805#L281 assume !(1 == ~t1_pc~0); 5806#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5726#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5643#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5782#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5870#L300 assume 1 == ~t2_pc~0; 5871#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5963#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5923#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5892#L665 assume !(0 != activate_threads_~tmp___1~0#1); 5655#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5656#L319 assume !(1 == ~t3_pc~0); 5611#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5612#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5598#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5599#L673 assume !(0 != activate_threads_~tmp___2~0#1); 5632#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5633#L338 assume 1 == ~t4_pc~0; 5778#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5701#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5707#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5708#L681 assume !(0 != activate_threads_~tmp___3~0#1); 5578#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5579#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 6009#L584-2 assume !(1 == ~T1_E~0); 6279#L589-1 assume !(1 == ~T2_E~0); 6278#L594-1 assume !(1 == ~T3_E~0); 5829#L599-1 assume !(1 == ~T4_E~0); 5610#L604-1 assume !(1 == ~E_M~0); 5596#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5597#L614-1 assume !(1 == ~E_2~0); 5715#L619-1 assume !(1 == ~E_3~0); 5797#L624-1 assume !(1 == ~E_4~0); 5890#L629-1 assume { :end_inline_reset_delta_events } true; 5910#L815-2 [2024-10-31 22:03:27,500 INFO L747 eck$LassoCheckResult]: Loop: 5910#L815-2 assume !false; 5911#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5787#L501-1 assume !false; 6006#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6007#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5721#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5936#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5937#L440 assume !(0 != eval_~tmp~0#1); 6015#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6021#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6019#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6020#L526-5 assume !(0 == ~T1_E~0); 6306#L531-3 assume !(0 == ~T2_E~0); 6305#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6304#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6303#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6302#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6301#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6300#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6299#L566-3 assume !(0 == ~E_4~0); 6298#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6297#L262-18 assume 1 == ~m_pc~0; 6295#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6294#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6293#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6292#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6291#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6290#L281-18 assume !(1 == ~t1_pc~0); 6288#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6287#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6286#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6285#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6284#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6283#L300-18 assume 1 == ~t2_pc~0; 6281#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6280#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5917#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5918#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 5947#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5727#L319-18 assume 1 == ~t3_pc~0; 5728#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5733#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5754#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5919#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5908#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5802#L338-18 assume !(1 == ~t4_pc~0); 5803#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 5771#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5772#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5636#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5637#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5821#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5822#L584-5 assume !(1 == ~T1_E~0); 5634#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5635#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5816#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5844#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5845#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5907#L614-3 assume !(1 == ~E_2~0); 5626#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5627#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5914#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5945#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5709#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5710#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5761#L834 assume !(0 == start_simulation_~tmp~3#1); 5762#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5924#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5883#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5641#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5981#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5986#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5909#L847 assume !(0 != start_simulation_~tmp___0~1#1); 5910#L815-2 [2024-10-31 22:03:27,501 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:27,501 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2024-10-31 22:03:27,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:27,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639548804] [2024-10-31 22:03:27,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:27,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:27,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:27,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:27,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:27,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639548804] [2024-10-31 22:03:27,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1639548804] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:27,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:27,545 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:03:27,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277083608] [2024-10-31 22:03:27,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:27,545 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:27,546 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:27,546 INFO L85 PathProgramCache]: Analyzing trace with hash -1803648471, now seen corresponding path program 1 times [2024-10-31 22:03:27,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:27,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841334405] [2024-10-31 22:03:27,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:27,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:27,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:27,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:27,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:27,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841334405] [2024-10-31 22:03:27,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841334405] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:27,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:27,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:27,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093801651] [2024-10-31 22:03:27,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:27,597 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:27,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:27,598 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:27,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:27,598 INFO L87 Difference]: Start difference. First operand 729 states and 1075 transitions. cyclomatic complexity: 348 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:27,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:27,676 INFO L93 Difference]: Finished difference Result 1354 states and 1970 transitions. [2024-10-31 22:03:27,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1354 states and 1970 transitions. [2024-10-31 22:03:27,685 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1274 [2024-10-31 22:03:27,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1354 states to 1354 states and 1970 transitions. [2024-10-31 22:03:27,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1354 [2024-10-31 22:03:27,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1354 [2024-10-31 22:03:27,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1354 states and 1970 transitions. [2024-10-31 22:03:27,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:27,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1354 states and 1970 transitions. [2024-10-31 22:03:27,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1354 states and 1970 transitions. [2024-10-31 22:03:27,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1354 to 1286. [2024-10-31 22:03:27,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1286 states, 1286 states have (on average 1.4587869362363919) internal successors, (1876), 1285 states have internal predecessors, (1876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:27,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1286 states to 1286 states and 1876 transitions. [2024-10-31 22:03:27,730 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1286 states and 1876 transitions. [2024-10-31 22:03:27,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:27,733 INFO L425 stractBuchiCegarLoop]: Abstraction has 1286 states and 1876 transitions. [2024-10-31 22:03:27,733 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:03:27,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1286 states and 1876 transitions. [2024-10-31 22:03:27,740 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1206 [2024-10-31 22:03:27,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:27,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:27,741 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:27,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:27,742 INFO L745 eck$LassoCheckResult]: Stem: 7927#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7928#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8027#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7768#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 7769#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8040#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7993#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7994#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8021#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8005#L526 assume !(0 == ~M_E~0); 8006#L526-2 assume !(0 == ~T1_E~0); 8043#L531-1 assume !(0 == ~T2_E~0); 7989#L536-1 assume !(0 == ~T3_E~0); 7990#L541-1 assume !(0 == ~T4_E~0); 7985#L546-1 assume !(0 == ~E_M~0); 7986#L551-1 assume !(0 == ~E_1~0); 7961#L556-1 assume !(0 == ~E_2~0); 7962#L561-1 assume !(0 == ~E_3~0); 7971#L566-1 assume !(0 == ~E_4~0); 7972#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7966#L262 assume !(1 == ~m_pc~0); 7967#L262-2 is_master_triggered_~__retres1~0#1 := 0; 8157#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7896#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7897#L649 assume !(0 != activate_threads_~tmp~1#1); 8155#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7906#L281 assume !(1 == ~t1_pc~0); 7907#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7820#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7732#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7733#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7880#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7974#L300 assume 1 == ~t2_pc~0; 7975#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8082#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8031#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7997#L665 assume !(0 != activate_threads_~tmp___1~0#1); 7745#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7746#L319 assume !(1 == ~t3_pc~0); 7701#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7702#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7688#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7689#L673 assume !(0 != activate_threads_~tmp___2~0#1); 7722#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7723#L338 assume 1 == ~t4_pc~0; 7876#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7793#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7798#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7799#L681 assume !(0 != activate_threads_~tmp___3~0#1); 7668#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7669#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 7877#L584-2 assume !(1 == ~T1_E~0); 7834#L589-1 assume !(1 == ~T2_E~0); 7835#L594-1 assume !(1 == ~T3_E~0); 7931#L599-1 assume !(1 == ~T4_E~0); 7700#L604-1 assume !(1 == ~E_M~0); 7686#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7687#L614-1 assume !(1 == ~E_2~0); 7808#L619-1 assume !(1 == ~E_3~0); 7898#L624-1 assume !(1 == ~E_4~0); 7995#L629-1 assume { :end_inline_reset_delta_events } true; 8016#L815-2 [2024-10-31 22:03:27,742 INFO L747 eck$LassoCheckResult]: Loop: 8016#L815-2 assume !false; 8018#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7885#L501-1 assume !false; 8149#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8150#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7814#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8048#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8049#L440 assume !(0 != eval_~tmp~0#1); 8172#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8686#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8685#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8075#L526-5 assume !(0 == ~T1_E~0); 8076#L531-3 assume !(0 == ~T2_E~0); 8895#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8892#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8890#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8888#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8886#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8884#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8882#L566-3 assume !(0 == ~E_4~0); 8881#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8878#L262-18 assume !(1 == ~m_pc~0); 8876#L262-20 is_master_triggered_~__retres1~0#1 := 0; 8874#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8872#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8870#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8868#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8865#L281-18 assume !(1 == ~t1_pc~0); 8862#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 8860#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8858#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8856#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8854#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8851#L300-18 assume 1 == ~t2_pc~0; 8848#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8846#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8844#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8843#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 8842#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8841#L319-18 assume 1 == ~t3_pc~0; 8839#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8838#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8837#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8836#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8835#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8834#L338-18 assume !(1 == ~t4_pc~0); 7956#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 7868#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7869#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7726#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7727#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7925#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7926#L584-5 assume !(1 == ~T1_E~0); 7724#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7725#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7916#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7949#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7950#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8013#L614-3 assume !(1 == ~E_2~0); 7716#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7717#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8022#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8059#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7802#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 7858#L834 assume !(0 == start_simulation_~tmp~3#1); 7859#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8032#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7988#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7730#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7731#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8105#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8113#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 8015#L847 assume !(0 != start_simulation_~tmp___0~1#1); 8016#L815-2 [2024-10-31 22:03:27,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:27,743 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2024-10-31 22:03:27,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:27,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747818855] [2024-10-31 22:03:27,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:27,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:27,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:27,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:27,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:27,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747818855] [2024-10-31 22:03:27,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747818855] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:27,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:27,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:03:27,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476875238] [2024-10-31 22:03:27,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:27,824 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:27,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:27,824 INFO L85 PathProgramCache]: Analyzing trace with hash -2077426966, now seen corresponding path program 1 times [2024-10-31 22:03:27,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:27,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656797787] [2024-10-31 22:03:27,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:27,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:27,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:27,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:27,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:27,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [656797787] [2024-10-31 22:03:27,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [656797787] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:27,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:27,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:27,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841110183] [2024-10-31 22:03:27,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:27,872 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:27,872 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:27,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:03:27,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:03:27,873 INFO L87 Difference]: Start difference. First operand 1286 states and 1876 transitions. cyclomatic complexity: 594 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:28,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:28,100 INFO L93 Difference]: Finished difference Result 1355 states and 1945 transitions. [2024-10-31 22:03:28,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1355 states and 1945 transitions. [2024-10-31 22:03:28,111 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1272 [2024-10-31 22:03:28,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1355 states to 1355 states and 1945 transitions. [2024-10-31 22:03:28,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1355 [2024-10-31 22:03:28,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1355 [2024-10-31 22:03:28,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1355 states and 1945 transitions. [2024-10-31 22:03:28,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:28,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1355 states and 1945 transitions. [2024-10-31 22:03:28,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1355 states and 1945 transitions. [2024-10-31 22:03:28,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1355 to 1355. [2024-10-31 22:03:28,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1355 states, 1355 states have (on average 1.4354243542435425) internal successors, (1945), 1354 states have internal predecessors, (1945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:28,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1945 transitions. [2024-10-31 22:03:28,162 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1355 states and 1945 transitions. [2024-10-31 22:03:28,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:03:28,165 INFO L425 stractBuchiCegarLoop]: Abstraction has 1355 states and 1945 transitions. [2024-10-31 22:03:28,165 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:03:28,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1355 states and 1945 transitions. [2024-10-31 22:03:28,174 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1272 [2024-10-31 22:03:28,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:28,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:28,175 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:28,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:28,176 INFO L745 eck$LassoCheckResult]: Stem: 10579#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 10580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 10687#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10688#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10416#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 10417#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10704#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10651#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10652#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10680#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10663#L526 assume !(0 == ~M_E~0); 10664#L526-2 assume !(0 == ~T1_E~0); 10706#L531-1 assume !(0 == ~T2_E~0); 10647#L536-1 assume !(0 == ~T3_E~0); 10648#L541-1 assume !(0 == ~T4_E~0); 10643#L546-1 assume !(0 == ~E_M~0); 10644#L551-1 assume !(0 == ~E_1~0); 10616#L556-1 assume !(0 == ~E_2~0); 10617#L561-1 assume !(0 == ~E_3~0); 10626#L566-1 assume !(0 == ~E_4~0); 10627#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10621#L262 assume !(1 == ~m_pc~0); 10622#L262-2 is_master_triggered_~__retres1~0#1 := 0; 10841#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10545#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10546#L649 assume !(0 != activate_threads_~tmp~1#1); 10837#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10557#L281 assume !(1 == ~t1_pc~0); 10558#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10468#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10383#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10384#L657 assume !(0 != activate_threads_~tmp___0~0#1); 10532#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10631#L300 assume 1 == ~t2_pc~0; 10632#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10746#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10692#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10657#L665 assume !(0 != activate_threads_~tmp___1~0#1); 10396#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10397#L319 assume !(1 == ~t3_pc~0); 10352#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10353#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10338#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10339#L673 assume !(0 != activate_threads_~tmp___2~0#1); 10373#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10374#L338 assume 1 == ~t4_pc~0; 10527#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10441#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10446#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10447#L681 assume !(0 != activate_threads_~tmp___3~0#1); 10318#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10319#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 10528#L584-2 assume !(1 == ~T1_E~0); 10529#L589-1 assume !(1 == ~T2_E~0); 10732#L594-1 assume !(1 == ~T3_E~0); 10583#L599-1 assume !(1 == ~T4_E~0); 10350#L604-1 assume !(1 == ~E_M~0); 10351#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10455#L614-1 assume !(1 == ~E_2~0); 10456#L619-1 assume !(1 == ~E_3~0); 10653#L624-1 assume !(1 == ~E_4~0); 10654#L629-1 assume { :end_inline_reset_delta_events } true; 11606#L815-2 [2024-10-31 22:03:28,176 INFO L747 eck$LassoCheckResult]: Loop: 11606#L815-2 assume !false; 11435#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10866#L501-1 assume !false; 10867#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10875#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10462#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10711#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10712#L440 assume !(0 != eval_~tmp~0#1); 10457#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10458#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11575#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10736#L526-5 assume !(0 == ~T1_E~0); 10459#L531-3 assume !(0 == ~T2_E~0); 10460#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10850#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10655#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10656#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10600#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10601#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10717#L566-3 assume !(0 == ~E_4~0); 10472#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10473#L262-18 assume !(1 == ~m_pc~0); 10572#L262-20 is_master_triggered_~__retres1~0#1 := 0; 10573#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10595#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10596#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10358#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10359#L281-18 assume 1 == ~t1_pc~0; 10613#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10634#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10635#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10829#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10769#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10770#L300-18 assume 1 == ~t2_pc~0; 10610#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10347#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10415#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10683#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 10724#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10789#L319-18 assume 1 == ~t3_pc~0; 10476#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10477#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10501#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10715#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11639#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11638#L338-18 assume !(1 == ~t4_pc~0); 11636#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 11635#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11634#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11633#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11632#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10577#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10578#L584-5 assume !(1 == ~T1_E~0); 10768#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10568#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10569#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10603#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10604#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10673#L614-3 assume !(1 == ~E_2~0); 10369#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10370#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10681#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10721#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10449#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10450#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 10508#L834 assume !(0 == start_simulation_~tmp~3#1); 10509#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10823#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10646#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10381#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 10382#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10777#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10778#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 11607#L847 assume !(0 != start_simulation_~tmp___0~1#1); 11606#L815-2 [2024-10-31 22:03:28,176 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:28,177 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2024-10-31 22:03:28,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:28,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467218816] [2024-10-31 22:03:28,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:28,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:28,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:28,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:28,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:28,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [467218816] [2024-10-31 22:03:28,235 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [467218816] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:28,235 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:28,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:03:28,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268063883] [2024-10-31 22:03:28,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:28,236 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:28,236 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:28,236 INFO L85 PathProgramCache]: Analyzing trace with hash -183984791, now seen corresponding path program 1 times [2024-10-31 22:03:28,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:28,236 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243955475] [2024-10-31 22:03:28,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:28,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:28,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:28,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:28,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:28,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243955475] [2024-10-31 22:03:28,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243955475] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:28,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:28,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:28,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1601213057] [2024-10-31 22:03:28,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:28,273 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:28,273 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:28,274 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:28,274 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:28,274 INFO L87 Difference]: Start difference. First operand 1355 states and 1945 transitions. cyclomatic complexity: 594 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:28,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:28,345 INFO L93 Difference]: Finished difference Result 2450 states and 3494 transitions. [2024-10-31 22:03:28,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2450 states and 3494 transitions. [2024-10-31 22:03:28,361 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2356 [2024-10-31 22:03:28,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2450 states to 2450 states and 3494 transitions. [2024-10-31 22:03:28,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2450 [2024-10-31 22:03:28,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2450 [2024-10-31 22:03:28,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2450 states and 3494 transitions. [2024-10-31 22:03:28,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:28,381 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2450 states and 3494 transitions. [2024-10-31 22:03:28,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2450 states and 3494 transitions. [2024-10-31 22:03:28,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2450 to 2442. [2024-10-31 22:03:28,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2442 states, 2442 states have (on average 1.4275184275184276) internal successors, (3486), 2441 states have internal predecessors, (3486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:28,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2442 states to 2442 states and 3486 transitions. [2024-10-31 22:03:28,432 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2442 states and 3486 transitions. [2024-10-31 22:03:28,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:28,433 INFO L425 stractBuchiCegarLoop]: Abstraction has 2442 states and 3486 transitions. [2024-10-31 22:03:28,433 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:03:28,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2442 states and 3486 transitions. [2024-10-31 22:03:28,445 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2348 [2024-10-31 22:03:28,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:28,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:28,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:28,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:28,446 INFO L745 eck$LassoCheckResult]: Stem: 14384#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 14385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14487#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14488#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14225#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 14226#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14500#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14451#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14452#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14483#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14465#L526 assume !(0 == ~M_E~0); 14466#L526-2 assume !(0 == ~T1_E~0); 14503#L531-1 assume !(0 == ~T2_E~0); 14447#L536-1 assume !(0 == ~T3_E~0); 14448#L541-1 assume !(0 == ~T4_E~0); 14443#L546-1 assume !(0 == ~E_M~0); 14444#L551-1 assume !(0 == ~E_1~0); 14421#L556-1 assume !(0 == ~E_2~0); 14422#L561-1 assume !(0 == ~E_3~0); 14431#L566-1 assume !(0 == ~E_4~0); 14432#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14426#L262 assume !(1 == ~m_pc~0); 14427#L262-2 is_master_triggered_~__retres1~0#1 := 0; 14616#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14352#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14353#L649 assume !(0 != activate_threads_~tmp~1#1); 14615#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14362#L281 assume !(1 == ~t1_pc~0); 14363#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14279#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14192#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14193#L657 assume !(0 != activate_threads_~tmp___0~0#1); 14339#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14434#L300 assume !(1 == ~t2_pc~0); 14435#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14540#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14491#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14455#L665 assume !(0 != activate_threads_~tmp___1~0#1); 14205#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14206#L319 assume !(1 == ~t3_pc~0); 14161#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14162#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14149#L673 assume !(0 != activate_threads_~tmp___2~0#1); 14182#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14183#L338 assume 1 == ~t4_pc~0; 14335#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14253#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14259#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14260#L681 assume !(0 != activate_threads_~tmp___3~0#1); 14130#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14131#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 14611#L584-2 assume !(1 == ~T1_E~0); 16172#L589-1 assume !(1 == ~T2_E~0); 16170#L594-1 assume !(1 == ~T3_E~0); 16168#L599-1 assume !(1 == ~T4_E~0); 14160#L604-1 assume !(1 == ~E_M~0); 14146#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14147#L614-1 assume !(1 == ~E_2~0); 14267#L619-1 assume !(1 == ~E_3~0); 14354#L624-1 assume !(1 == ~E_4~0); 14453#L629-1 assume { :end_inline_reset_delta_events } true; 14627#L815-2 [2024-10-31 22:03:28,447 INFO L747 eck$LassoCheckResult]: Loop: 14627#L815-2 assume !false; 14932#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14930#L501-1 assume !false; 14927#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14925#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14919#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14917#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14914#L440 assume !(0 != eval_~tmp~0#1); 14915#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16287#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16286#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16285#L526-5 assume !(0 == ~T1_E~0); 16284#L531-3 assume !(0 == ~T2_E~0); 16283#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16282#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16281#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16280#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16279#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16278#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16277#L566-3 assume !(0 == ~E_4~0); 16276#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16275#L262-18 assume !(1 == ~m_pc~0); 16274#L262-20 is_master_triggered_~__retres1~0#1 := 0; 16273#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16271#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16270#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16269#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16268#L281-18 assume !(1 == ~t1_pc~0); 16266#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 16264#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16262#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16261#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 16259#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16258#L300-18 assume !(1 == ~t2_pc~0); 16257#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 16256#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16255#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16254#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 16253#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16252#L319-18 assume 1 == ~t3_pc~0; 16250#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16249#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16248#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16247#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16246#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16245#L338-18 assume !(1 == ~t4_pc~0); 15623#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 15620#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15618#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15616#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15614#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15612#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15610#L584-5 assume !(1 == ~T1_E~0); 15607#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15605#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15602#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15600#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15598#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15273#L614-3 assume !(1 == ~E_2~0); 14176#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14177#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14482#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14517#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14261#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14262#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 14316#L834 assume !(0 == start_simulation_~tmp~3#1); 14317#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14997#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14990#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14987#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 14986#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14985#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14984#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 14983#L847 assume !(0 != start_simulation_~tmp___0~1#1); 14627#L815-2 [2024-10-31 22:03:28,447 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:28,447 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2024-10-31 22:03:28,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:28,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316081673] [2024-10-31 22:03:28,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:28,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:28,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:28,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:28,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:28,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316081673] [2024-10-31 22:03:28,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316081673] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:28,497 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:28,497 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:03:28,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194032113] [2024-10-31 22:03:28,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:28,497 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:28,498 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:28,498 INFO L85 PathProgramCache]: Analyzing trace with hash 834972333, now seen corresponding path program 1 times [2024-10-31 22:03:28,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:28,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730998603] [2024-10-31 22:03:28,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:28,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:28,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:28,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:28,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:28,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [730998603] [2024-10-31 22:03:28,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [730998603] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:28,559 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:28,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:28,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123892089] [2024-10-31 22:03:28,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:28,560 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:28,560 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:28,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:28,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:28,561 INFO L87 Difference]: Start difference. First operand 2442 states and 3486 transitions. cyclomatic complexity: 1052 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:28,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:28,659 INFO L93 Difference]: Finished difference Result 4453 states and 6327 transitions. [2024-10-31 22:03:28,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4453 states and 6327 transitions. [2024-10-31 22:03:28,688 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4328 [2024-10-31 22:03:28,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4453 states to 4453 states and 6327 transitions. [2024-10-31 22:03:28,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4453 [2024-10-31 22:03:28,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4453 [2024-10-31 22:03:28,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4453 states and 6327 transitions. [2024-10-31 22:03:28,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:28,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4453 states and 6327 transitions. [2024-10-31 22:03:28,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4453 states and 6327 transitions. [2024-10-31 22:03:28,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4453 to 4437. [2024-10-31 22:03:28,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4437 states, 4437 states have (on average 1.422357448726617) internal successors, (6311), 4436 states have internal predecessors, (6311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:28,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4437 states to 4437 states and 6311 transitions. [2024-10-31 22:03:28,819 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4437 states and 6311 transitions. [2024-10-31 22:03:28,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:28,820 INFO L425 stractBuchiCegarLoop]: Abstraction has 4437 states and 6311 transitions. [2024-10-31 22:03:28,820 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:03:28,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4437 states and 6311 transitions. [2024-10-31 22:03:28,841 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4312 [2024-10-31 22:03:28,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:28,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:28,842 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:28,842 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:28,843 INFO L745 eck$LassoCheckResult]: Stem: 21286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 21287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 21385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21129#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 21130#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21396#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21349#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21350#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21380#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21360#L526 assume !(0 == ~M_E~0); 21361#L526-2 assume !(0 == ~T1_E~0); 21400#L531-1 assume !(0 == ~T2_E~0); 21345#L536-1 assume !(0 == ~T3_E~0); 21346#L541-1 assume !(0 == ~T4_E~0); 21341#L546-1 assume !(0 == ~E_M~0); 21342#L551-1 assume !(0 == ~E_1~0); 21319#L556-1 assume !(0 == ~E_2~0); 21320#L561-1 assume !(0 == ~E_3~0); 21329#L566-1 assume !(0 == ~E_4~0); 21330#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21324#L262 assume !(1 == ~m_pc~0); 21325#L262-2 is_master_triggered_~__retres1~0#1 := 0; 21510#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21256#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21257#L649 assume !(0 != activate_threads_~tmp~1#1); 21508#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21265#L281 assume !(1 == ~t1_pc~0); 21266#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21182#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21094#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21095#L657 assume !(0 != activate_threads_~tmp___0~0#1); 21238#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21332#L300 assume !(1 == ~t2_pc~0); 21333#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21432#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21389#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21354#L665 assume !(0 != activate_threads_~tmp___1~0#1); 21107#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21108#L319 assume !(1 == ~t3_pc~0); 21063#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21064#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21050#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21051#L673 assume !(0 != activate_threads_~tmp___2~0#1); 21084#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21085#L338 assume !(1 == ~t4_pc~0); 21153#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21154#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21159#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21160#L681 assume !(0 != activate_threads_~tmp___3~0#1); 21032#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21033#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 21507#L584-2 assume !(1 == ~T1_E~0); 23063#L589-1 assume !(1 == ~T2_E~0); 23062#L594-1 assume !(1 == ~T3_E~0); 23061#L599-1 assume !(1 == ~T4_E~0); 23060#L604-1 assume !(1 == ~E_M~0); 23059#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 23058#L614-1 assume !(1 == ~E_2~0); 23057#L619-1 assume !(1 == ~E_3~0); 23056#L624-1 assume !(1 == ~E_4~0); 21351#L629-1 assume { :end_inline_reset_delta_events } true; 21518#L815-2 [2024-10-31 22:03:28,843 INFO L747 eck$LassoCheckResult]: Loop: 21518#L815-2 assume !false; 23330#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23329#L501-1 assume !false; 23328#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23327#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23322#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23321#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23320#L440 assume !(0 != eval_~tmp~0#1); 23319#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23318#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23317#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23316#L526-5 assume !(0 == ~T1_E~0); 23315#L531-3 assume !(0 == ~T2_E~0); 23314#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23313#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23312#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23311#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23310#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23309#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23308#L566-3 assume !(0 == ~E_4~0); 23307#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23306#L262-18 assume !(1 == ~m_pc~0); 23305#L262-20 is_master_triggered_~__retres1~0#1 := 0; 23304#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23303#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23302#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23301#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23300#L281-18 assume 1 == ~t1_pc~0; 23298#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23296#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23294#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23292#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23291#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23290#L300-18 assume !(1 == ~t2_pc~0); 23289#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 23288#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23287#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23286#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 23285#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23284#L319-18 assume 1 == ~t3_pc~0; 23282#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23281#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23280#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23279#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23278#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23277#L338-18 assume !(1 == ~t4_pc~0); 23276#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 23275#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23274#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23273#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23272#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23271#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23170#L584-5 assume !(1 == ~T1_E~0); 23270#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23269#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23268#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23267#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23266#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23265#L614-3 assume !(1 == ~E_2~0); 23264#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23263#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23150#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23260#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23257#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23256#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 21218#L834 assume !(0 == start_simulation_~tmp~3#1); 21219#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23367#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23359#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23356#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 23352#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23348#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23344#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 23338#L847 assume !(0 != start_simulation_~tmp___0~1#1); 21518#L815-2 [2024-10-31 22:03:28,843 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:28,843 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2024-10-31 22:03:28,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:28,844 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532995592] [2024-10-31 22:03:28,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:28,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:28,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:28,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:28,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:28,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [532995592] [2024-10-31 22:03:28,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [532995592] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:28,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:28,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:03:28,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [324568978] [2024-10-31 22:03:28,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:28,898 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:28,902 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:28,903 INFO L85 PathProgramCache]: Analyzing trace with hash -669159510, now seen corresponding path program 1 times [2024-10-31 22:03:28,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:28,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697004100] [2024-10-31 22:03:28,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:28,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:28,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:28,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:28,954 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:28,954 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697004100] [2024-10-31 22:03:28,954 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697004100] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:28,954 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:28,954 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:28,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452294043] [2024-10-31 22:03:28,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:28,955 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:28,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:28,956 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:28,956 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:28,956 INFO L87 Difference]: Start difference. First operand 4437 states and 6311 transitions. cyclomatic complexity: 1890 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:29,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:29,063 INFO L93 Difference]: Finished difference Result 6648 states and 9441 transitions. [2024-10-31 22:03:29,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6648 states and 9441 transitions. [2024-10-31 22:03:29,103 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6508 [2024-10-31 22:03:29,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6648 states to 6648 states and 9441 transitions. [2024-10-31 22:03:29,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6648 [2024-10-31 22:03:29,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6648 [2024-10-31 22:03:29,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6648 states and 9441 transitions. [2024-10-31 22:03:29,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:29,161 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6648 states and 9441 transitions. [2024-10-31 22:03:29,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6648 states and 9441 transitions. [2024-10-31 22:03:29,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6648 to 4815. [2024-10-31 22:03:29,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4815 states, 4815 states have (on average 1.4188992731048806) internal successors, (6832), 4814 states have internal predecessors, (6832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:29,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4815 states to 4815 states and 6832 transitions. [2024-10-31 22:03:29,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4815 states and 6832 transitions. [2024-10-31 22:03:29,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:29,262 INFO L425 stractBuchiCegarLoop]: Abstraction has 4815 states and 6832 transitions. [2024-10-31 22:03:29,263 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:03:29,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4815 states and 6832 transitions. [2024-10-31 22:03:29,284 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4700 [2024-10-31 22:03:29,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:29,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:29,285 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:29,285 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:29,285 INFO L745 eck$LassoCheckResult]: Stem: 32373#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 32374#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 32470#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32471#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32219#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 32220#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32480#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32437#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32438#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32465#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32447#L526 assume !(0 == ~M_E~0); 32448#L526-2 assume !(0 == ~T1_E~0); 32482#L531-1 assume !(0 == ~T2_E~0); 32433#L536-1 assume !(0 == ~T3_E~0); 32434#L541-1 assume !(0 == ~T4_E~0); 32429#L546-1 assume !(0 == ~E_M~0); 32430#L551-1 assume !(0 == ~E_1~0); 32406#L556-1 assume !(0 == ~E_2~0); 32407#L561-1 assume !(0 == ~E_3~0); 32416#L566-1 assume !(0 == ~E_4~0); 32417#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32411#L262 assume !(1 == ~m_pc~0); 32412#L262-2 is_master_triggered_~__retres1~0#1 := 0; 32596#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32343#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32344#L649 assume !(0 != activate_threads_~tmp~1#1); 32593#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32353#L281 assume !(1 == ~t1_pc~0); 32354#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32270#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32186#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32187#L657 assume !(0 != activate_threads_~tmp___0~0#1); 32330#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32419#L300 assume !(1 == ~t2_pc~0); 32420#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32515#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32474#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32441#L665 assume !(0 != activate_threads_~tmp___1~0#1); 32199#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32200#L319 assume !(1 == ~t3_pc~0); 32155#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32156#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32142#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32143#L673 assume !(0 != activate_threads_~tmp___2~0#1); 32176#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32177#L338 assume !(1 == ~t4_pc~0); 32244#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32245#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32250#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32251#L681 assume !(0 != activate_threads_~tmp___3~0#1); 32124#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32125#L584 assume !(1 == ~M_E~0); 32327#L584-2 assume !(1 == ~T1_E~0); 32286#L589-1 assume !(1 == ~T2_E~0); 32287#L594-1 assume !(1 == ~T3_E~0); 32377#L599-1 assume !(1 == ~T4_E~0); 32154#L604-1 assume !(1 == ~E_M~0); 32140#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 32141#L614-1 assume !(1 == ~E_2~0); 32259#L619-1 assume !(1 == ~E_3~0); 32345#L624-1 assume !(1 == ~E_4~0); 32439#L629-1 assume { :end_inline_reset_delta_events } true; 32607#L815-2 [2024-10-31 22:03:29,286 INFO L747 eck$LassoCheckResult]: Loop: 32607#L815-2 assume !false; 34668#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34665#L501-1 assume !false; 34662#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34658#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34650#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34646#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34640#L440 assume !(0 != eval_~tmp~0#1); 34636#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34631#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34625#L526-3 assume !(0 == ~M_E~0); 34621#L526-5 assume !(0 == ~T1_E~0); 34617#L531-3 assume !(0 == ~T2_E~0); 34613#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34608#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34602#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34596#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34591#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34586#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34580#L566-3 assume !(0 == ~E_4~0); 34575#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34569#L262-18 assume !(1 == ~m_pc~0); 34562#L262-20 is_master_triggered_~__retres1~0#1 := 0; 34556#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34549#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34544#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34540#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34539#L281-18 assume !(1 == ~t1_pc~0); 34531#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 34530#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34526#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34524#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 34475#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34467#L300-18 assume !(1 == ~t2_pc~0); 34460#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 34451#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34432#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34431#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 34430#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34429#L319-18 assume 1 == ~t3_pc~0; 34427#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34425#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34379#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34376#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34374#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34372#L338-18 assume !(1 == ~t4_pc~0); 34370#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 34368#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34366#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34364#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34362#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34360#L584-3 assume !(1 == ~M_E~0); 34149#L584-5 assume !(1 == ~T1_E~0); 34356#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34354#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34352#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34350#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34348#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34346#L614-3 assume !(1 == ~E_2~0); 34344#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34342#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34340#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34320#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34313#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34308#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 32691#L834 assume !(0 == start_simulation_~tmp~3#1); 32692#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34766#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34761#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34759#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 34718#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34701#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34691#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 34682#L847 assume !(0 != start_simulation_~tmp___0~1#1); 32607#L815-2 [2024-10-31 22:03:29,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:29,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2024-10-31 22:03:29,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:29,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311693248] [2024-10-31 22:03:29,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:29,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:29,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:29,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:29,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:29,372 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [311693248] [2024-10-31 22:03:29,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [311693248] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:29,372 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:29,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:29,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141705383] [2024-10-31 22:03:29,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:29,373 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:29,373 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:29,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1024858899, now seen corresponding path program 1 times [2024-10-31 22:03:29,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:29,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509704032] [2024-10-31 22:03:29,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:29,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:29,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:29,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:29,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:29,411 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1509704032] [2024-10-31 22:03:29,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1509704032] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:29,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:29,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:29,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459248914] [2024-10-31 22:03:29,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:29,412 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:29,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:29,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:03:29,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:03:29,413 INFO L87 Difference]: Start difference. First operand 4815 states and 6832 transitions. cyclomatic complexity: 2025 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:29,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:29,616 INFO L93 Difference]: Finished difference Result 6567 states and 9149 transitions. [2024-10-31 22:03:29,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6567 states and 9149 transitions. [2024-10-31 22:03:29,649 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6350 [2024-10-31 22:03:29,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6567 states to 6567 states and 9149 transitions. [2024-10-31 22:03:29,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6567 [2024-10-31 22:03:29,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6567 [2024-10-31 22:03:29,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6567 states and 9149 transitions. [2024-10-31 22:03:29,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:29,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6567 states and 9149 transitions. [2024-10-31 22:03:29,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6567 states and 9149 transitions. [2024-10-31 22:03:29,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6567 to 5402. [2024-10-31 22:03:29,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5402 states, 5402 states have (on average 1.4009626064420584) internal successors, (7568), 5401 states have internal predecessors, (7568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:29,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5402 states to 5402 states and 7568 transitions. [2024-10-31 22:03:29,819 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5402 states and 7568 transitions. [2024-10-31 22:03:29,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:03:29,821 INFO L425 stractBuchiCegarLoop]: Abstraction has 5402 states and 7568 transitions. [2024-10-31 22:03:29,821 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:03:29,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5402 states and 7568 transitions. [2024-10-31 22:03:29,844 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5244 [2024-10-31 22:03:29,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:29,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:29,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:29,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:29,846 INFO L745 eck$LassoCheckResult]: Stem: 43770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 43771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 43868#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43869#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43612#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 43613#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43881#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43835#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43836#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43863#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43845#L526 assume !(0 == ~M_E~0); 43846#L526-2 assume !(0 == ~T1_E~0); 43884#L531-1 assume !(0 == ~T2_E~0); 43831#L536-1 assume !(0 == ~T3_E~0); 43832#L541-1 assume !(0 == ~T4_E~0); 43827#L546-1 assume !(0 == ~E_M~0); 43828#L551-1 assume 0 == ~E_1~0;~E_1~0 := 1; 43898#L556-1 assume !(0 == ~E_2~0); 44056#L561-1 assume !(0 == ~E_3~0); 44055#L566-1 assume !(0 == ~E_4~0); 43987#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43810#L262 assume !(1 == ~m_pc~0); 43811#L262-2 is_master_triggered_~__retres1~0#1 := 0; 43992#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43741#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43742#L649 assume !(0 != activate_threads_~tmp~1#1); 43988#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44049#L281 assume !(1 == ~t1_pc~0); 44048#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44047#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44046#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44041#L657 assume !(0 != activate_threads_~tmp___0~0#1); 44040#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44039#L300 assume !(1 == ~t2_pc~0); 44038#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44037#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44035#L665 assume !(0 != activate_threads_~tmp___1~0#1); 44034#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44033#L319 assume !(1 == ~t3_pc~0); 44031#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44030#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44029#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44028#L673 assume !(0 != activate_threads_~tmp___2~0#1); 44027#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44026#L338 assume !(1 == ~t4_pc~0); 44025#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44024#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44023#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44022#L681 assume !(0 != activate_threads_~tmp___3~0#1); 44021#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44020#L584 assume !(1 == ~M_E~0); 44019#L584-2 assume !(1 == ~T1_E~0); 44018#L589-1 assume !(1 == ~T2_E~0); 44017#L594-1 assume !(1 == ~T3_E~0); 44016#L599-1 assume !(1 == ~T4_E~0); 44015#L604-1 assume !(1 == ~E_M~0); 44014#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 43533#L614-1 assume !(1 == ~E_2~0); 43653#L619-1 assume !(1 == ~E_3~0); 43743#L624-1 assume !(1 == ~E_4~0); 43837#L629-1 assume { :end_inline_reset_delta_events } true; 43999#L815-2 [2024-10-31 22:03:29,847 INFO L747 eck$LassoCheckResult]: Loop: 43999#L815-2 assume !false; 48239#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48237#L501-1 assume !false; 48235#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 48234#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 48222#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 48217#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47858#L440 assume !(0 != eval_~tmp~0#1); 47859#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48810#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48808#L526-3 assume !(0 == ~M_E~0); 48806#L526-5 assume !(0 == ~T1_E~0); 48805#L531-3 assume !(0 == ~T2_E~0); 48803#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48801#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48799#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48796#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48795#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48794#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48793#L566-3 assume !(0 == ~E_4~0); 48792#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48791#L262-18 assume !(1 == ~m_pc~0); 48790#L262-20 is_master_triggered_~__retres1~0#1 := 0; 48789#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48788#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48787#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48786#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48785#L281-18 assume !(1 == ~t1_pc~0); 48784#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 48781#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48779#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 48777#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 48775#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48774#L300-18 assume !(1 == ~t2_pc~0); 48773#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 48772#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48771#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48770#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 48769#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48768#L319-18 assume 1 == ~t3_pc~0; 48766#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48765#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48764#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48763#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48762#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48761#L338-18 assume !(1 == ~t4_pc~0); 48760#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 48759#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48758#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48757#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48756#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48755#L584-3 assume !(1 == ~M_E~0); 47517#L584-5 assume !(1 == ~T1_E~0); 48754#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48753#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48752#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48751#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48749#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48747#L614-3 assume !(1 == ~E_2~0); 48745#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48743#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48741#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 48734#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 48731#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 48730#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 46537#L834 assume !(0 == start_simulation_~tmp~3#1); 46538#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 48266#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 48261#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 48258#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 48256#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48254#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48252#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 48250#L847 assume !(0 != start_simulation_~tmp___0~1#1); 43999#L815-2 [2024-10-31 22:03:29,869 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:29,869 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2024-10-31 22:03:29,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:29,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570724505] [2024-10-31 22:03:29,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:29,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:29,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:29,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:29,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:29,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570724505] [2024-10-31 22:03:29,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [570724505] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:29,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:29,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:29,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26728268] [2024-10-31 22:03:29,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:29,949 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:29,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:29,951 INFO L85 PathProgramCache]: Analyzing trace with hash -1024858899, now seen corresponding path program 2 times [2024-10-31 22:03:29,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:29,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983129057] [2024-10-31 22:03:29,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:29,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:29,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:30,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:30,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:30,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983129057] [2024-10-31 22:03:30,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983129057] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:30,014 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:30,014 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:30,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870140339] [2024-10-31 22:03:30,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:30,015 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:30,015 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:30,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:03:30,016 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:03:30,017 INFO L87 Difference]: Start difference. First operand 5402 states and 7568 transitions. cyclomatic complexity: 2174 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:30,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:30,142 INFO L93 Difference]: Finished difference Result 5518 states and 7683 transitions. [2024-10-31 22:03:30,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5518 states and 7683 transitions. [2024-10-31 22:03:30,180 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5382 [2024-10-31 22:03:30,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5518 states to 5518 states and 7683 transitions. [2024-10-31 22:03:30,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5518 [2024-10-31 22:03:30,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5518 [2024-10-31 22:03:30,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5518 states and 7683 transitions. [2024-10-31 22:03:30,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:30,230 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5518 states and 7683 transitions. [2024-10-31 22:03:30,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5518 states and 7683 transitions. [2024-10-31 22:03:30,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5518 to 4596. [2024-10-31 22:03:30,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4596 states, 4596 states have (on average 1.3962140992167102) internal successors, (6417), 4595 states have internal predecessors, (6417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:30,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4596 states to 4596 states and 6417 transitions. [2024-10-31 22:03:30,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4596 states and 6417 transitions. [2024-10-31 22:03:30,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:03:30,350 INFO L425 stractBuchiCegarLoop]: Abstraction has 4596 states and 6417 transitions. [2024-10-31 22:03:30,351 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:03:30,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4596 states and 6417 transitions. [2024-10-31 22:03:30,370 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4484 [2024-10-31 22:03:30,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:30,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:30,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:30,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:30,372 INFO L745 eck$LassoCheckResult]: Stem: 54695#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 54696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 54791#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54792#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54544#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 54545#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54802#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54758#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54759#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54787#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54770#L526 assume !(0 == ~M_E~0); 54771#L526-2 assume !(0 == ~T1_E~0); 54804#L531-1 assume !(0 == ~T2_E~0); 54754#L536-1 assume !(0 == ~T3_E~0); 54755#L541-1 assume !(0 == ~T4_E~0); 54750#L546-1 assume !(0 == ~E_M~0); 54751#L551-1 assume !(0 == ~E_1~0); 54728#L556-1 assume !(0 == ~E_2~0); 54729#L561-1 assume !(0 == ~E_3~0); 54738#L566-1 assume !(0 == ~E_4~0); 54739#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54733#L262 assume !(1 == ~m_pc~0); 54734#L262-2 is_master_triggered_~__retres1~0#1 := 0; 54903#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54664#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54665#L649 assume !(0 != activate_threads_~tmp~1#1); 54902#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54674#L281 assume !(1 == ~t1_pc~0); 54675#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54594#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54509#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54510#L657 assume !(0 != activate_threads_~tmp___0~0#1); 54649#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54741#L300 assume !(1 == ~t2_pc~0); 54742#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54837#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54762#L665 assume !(0 != activate_threads_~tmp___1~0#1); 54522#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54523#L319 assume !(1 == ~t3_pc~0); 54477#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54478#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54464#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54465#L673 assume !(0 != activate_threads_~tmp___2~0#1); 54499#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54500#L338 assume !(1 == ~t4_pc~0); 54567#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54568#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54574#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54575#L681 assume !(0 != activate_threads_~tmp___3~0#1); 54446#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54447#L584 assume !(1 == ~M_E~0); 54646#L584-2 assume !(1 == ~T1_E~0); 54609#L589-1 assume !(1 == ~T2_E~0); 54610#L594-1 assume !(1 == ~T3_E~0); 54701#L599-1 assume !(1 == ~T4_E~0); 54476#L604-1 assume !(1 == ~E_M~0); 54462#L609-1 assume !(1 == ~E_1~0); 54463#L614-1 assume !(1 == ~E_2~0); 54582#L619-1 assume !(1 == ~E_3~0); 54666#L624-1 assume !(1 == ~E_4~0); 54760#L629-1 assume { :end_inline_reset_delta_events } true; 54781#L815-2 [2024-10-31 22:03:30,372 INFO L747 eck$LassoCheckResult]: Loop: 54781#L815-2 assume !false; 57836#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57830#L501-1 assume !false; 57690#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 57110#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 57105#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 57104#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 57100#L440 assume !(0 != eval_~tmp~0#1); 57101#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57969#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57968#L526-3 assume !(0 == ~M_E~0); 57966#L526-5 assume !(0 == ~T1_E~0); 57964#L531-3 assume !(0 == ~T2_E~0); 57962#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57960#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57958#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57956#L551-3 assume !(0 == ~E_1~0); 57953#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57951#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57949#L566-3 assume !(0 == ~E_4~0); 57947#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57945#L262-18 assume !(1 == ~m_pc~0); 57943#L262-20 is_master_triggered_~__retres1~0#1 := 0; 57941#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57939#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 57937#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57935#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57933#L281-18 assume !(1 == ~t1_pc~0); 57930#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 57928#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57925#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57923#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 57921#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57919#L300-18 assume !(1 == ~t2_pc~0); 57917#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 57915#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57912#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57910#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 57908#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57906#L319-18 assume !(1 == ~t3_pc~0); 57904#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 57899#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57897#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57895#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57894#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57891#L338-18 assume !(1 == ~t4_pc~0); 57890#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 57889#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57886#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57882#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57878#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57873#L584-3 assume !(1 == ~M_E~0); 55972#L584-5 assume !(1 == ~T1_E~0); 57870#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57864#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57862#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57860#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57857#L609-3 assume !(1 == ~E_1~0); 57854#L614-3 assume !(1 == ~E_2~0); 57851#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57850#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57847#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 57833#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 57829#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 57691#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 56040#L834 assume !(0 == start_simulation_~tmp~3#1); 54683#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54796#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54753#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54507#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 54508#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54859#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54865#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 54780#L847 assume !(0 != start_simulation_~tmp___0~1#1); 54781#L815-2 [2024-10-31 22:03:30,373 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:30,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2024-10-31 22:03:30,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:30,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099477803] [2024-10-31 22:03:30,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:30,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:30,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:30,386 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:30,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:30,432 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:30,434 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:30,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1128028626, now seen corresponding path program 1 times [2024-10-31 22:03:30,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:30,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [923018227] [2024-10-31 22:03:30,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:30,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:30,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:30,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:30,475 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:30,475 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [923018227] [2024-10-31 22:03:30,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [923018227] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:30,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:30,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:30,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [843922202] [2024-10-31 22:03:30,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:30,477 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:30,477 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:30,477 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:30,477 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:30,478 INFO L87 Difference]: Start difference. First operand 4596 states and 6417 transitions. cyclomatic complexity: 1829 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:30,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:30,650 INFO L93 Difference]: Finished difference Result 6857 states and 9490 transitions. [2024-10-31 22:03:30,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6857 states and 9490 transitions. [2024-10-31 22:03:30,682 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6686 [2024-10-31 22:03:30,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6857 states to 6857 states and 9490 transitions. [2024-10-31 22:03:30,710 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6857 [2024-10-31 22:03:30,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6857 [2024-10-31 22:03:30,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6857 states and 9490 transitions. [2024-10-31 22:03:30,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:30,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6857 states and 9490 transitions. [2024-10-31 22:03:30,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6857 states and 9490 transitions. [2024-10-31 22:03:30,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6857 to 6849. [2024-10-31 22:03:30,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6849 states, 6849 states have (on average 1.384435684041466) internal successors, (9482), 6848 states have internal predecessors, (9482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:30,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6849 states to 6849 states and 9482 transitions. [2024-10-31 22:03:30,859 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6849 states and 9482 transitions. [2024-10-31 22:03:30,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:30,860 INFO L425 stractBuchiCegarLoop]: Abstraction has 6849 states and 9482 transitions. [2024-10-31 22:03:30,860 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:03:30,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6849 states and 9482 transitions. [2024-10-31 22:03:30,887 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6678 [2024-10-31 22:03:30,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:30,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:30,889 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:30,889 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:30,890 INFO L745 eck$LassoCheckResult]: Stem: 66166#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 66167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 66275#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66276#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66001#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 66002#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66295#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66235#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66236#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66268#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66247#L526 assume !(0 == ~M_E~0); 66248#L526-2 assume !(0 == ~T1_E~0); 66296#L531-1 assume !(0 == ~T2_E~0); 66231#L536-1 assume !(0 == ~T3_E~0); 66232#L541-1 assume !(0 == ~T4_E~0); 66227#L546-1 assume !(0 == ~E_M~0); 66228#L551-1 assume !(0 == ~E_1~0); 66203#L556-1 assume 0 == ~E_2~0;~E_2~0 := 1; 66204#L561-1 assume !(0 == ~E_3~0); 66245#L566-1 assume !(0 == ~E_4~0); 66427#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66428#L262 assume !(1 == ~m_pc~0); 66435#L262-2 is_master_triggered_~__retres1~0#1 := 0; 66436#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66473#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 66430#L649 assume !(0 != activate_threads_~tmp~1#1); 66431#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66472#L281 assume !(1 == ~t1_pc~0); 66439#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66440#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66470#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 66469#L657 assume !(0 != activate_threads_~tmp___0~0#1); 66419#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66420#L300 assume !(1 == ~t2_pc~0); 66383#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 66384#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66280#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66281#L665 assume !(0 != activate_threads_~tmp___1~0#1); 65981#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65982#L319 assume !(1 == ~t3_pc~0); 66459#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 66338#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66339#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66164#L673 assume !(0 != activate_threads_~tmp___2~0#1); 66165#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66340#L338 assume !(1 == ~t4_pc~0); 66025#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 66026#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66033#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66034#L681 assume !(0 != activate_threads_~tmp___3~0#1); 66466#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66425#L584 assume !(1 == ~M_E~0); 66426#L584-2 assume !(1 == ~T1_E~0); 66465#L589-1 assume !(1 == ~T2_E~0); 66464#L594-1 assume !(1 == ~T3_E~0); 66463#L599-1 assume !(1 == ~T4_E~0); 65936#L604-1 assume !(1 == ~E_M~0); 65922#L609-1 assume !(1 == ~E_1~0); 65923#L614-1 assume 1 == ~E_2~0;~E_2~0 := 2; 66043#L619-1 assume !(1 == ~E_3~0); 66135#L624-1 assume !(1 == ~E_4~0); 66237#L629-1 assume { :end_inline_reset_delta_events } true; 66443#L815-2 [2024-10-31 22:03:30,890 INFO L747 eck$LassoCheckResult]: Loop: 66443#L815-2 assume !false; 68485#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68376#L501-1 assume !false; 68484#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 68483#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68478#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 68477#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 68475#L440 assume !(0 != eval_~tmp~0#1); 68476#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68787#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68784#L526-3 assume !(0 == ~M_E~0); 68781#L526-5 assume !(0 == ~T1_E~0); 68778#L531-3 assume !(0 == ~T2_E~0); 68775#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68772#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68769#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68766#L551-3 assume !(0 == ~E_1~0); 68760#L556-3 assume !(0 == ~E_2~0); 68755#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68751#L566-3 assume !(0 == ~E_4~0); 68747#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68743#L262-18 assume !(1 == ~m_pc~0); 68739#L262-20 is_master_triggered_~__retres1~0#1 := 0; 68735#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68731#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68726#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68722#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68632#L281-18 assume !(1 == ~t1_pc~0); 68629#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 68627#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68625#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68623#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 68621#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68619#L300-18 assume !(1 == ~t2_pc~0); 68617#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 68615#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68613#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68611#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 68609#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68606#L319-18 assume 1 == ~t3_pc~0; 68603#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68601#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68599#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68597#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68595#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68593#L338-18 assume !(1 == ~t4_pc~0); 68591#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 68589#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68587#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68585#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68584#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68582#L584-3 assume !(1 == ~M_E~0); 68579#L584-5 assume !(1 == ~T1_E~0); 68578#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68577#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68574#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68568#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68566#L609-3 assume !(1 == ~E_1~0); 68543#L614-3 assume !(1 == ~E_2~0); 68541#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 68539#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68536#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 68529#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68525#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 68523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 68521#L834 assume !(0 == start_simulation_~tmp~3#1); 68518#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 68516#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68512#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 68499#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 68494#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68490#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68487#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 68486#L847 assume !(0 != start_simulation_~tmp___0~1#1); 66443#L815-2 [2024-10-31 22:03:30,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:30,891 INFO L85 PathProgramCache]: Analyzing trace with hash 652862409, now seen corresponding path program 1 times [2024-10-31 22:03:30,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:30,891 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151732784] [2024-10-31 22:03:30,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:30,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:30,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:30,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:30,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:30,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151732784] [2024-10-31 22:03:30,940 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151732784] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:30,940 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:30,940 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:03:30,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258416430] [2024-10-31 22:03:30,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:30,941 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:30,941 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:30,942 INFO L85 PathProgramCache]: Analyzing trace with hash -918560465, now seen corresponding path program 1 times [2024-10-31 22:03:30,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:30,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097333119] [2024-10-31 22:03:30,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:30,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:30,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:31,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:31,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:31,006 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097333119] [2024-10-31 22:03:31,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097333119] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:31,006 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:31,006 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:03:31,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385816427] [2024-10-31 22:03:31,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:31,007 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:31,007 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:31,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:31,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:31,009 INFO L87 Difference]: Start difference. First operand 6849 states and 9482 transitions. cyclomatic complexity: 2641 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:31,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:31,137 INFO L93 Difference]: Finished difference Result 4596 states and 6323 transitions. [2024-10-31 22:03:31,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4596 states and 6323 transitions. [2024-10-31 22:03:31,156 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4484 [2024-10-31 22:03:31,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4596 states to 4596 states and 6323 transitions. [2024-10-31 22:03:31,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4596 [2024-10-31 22:03:31,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4596 [2024-10-31 22:03:31,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4596 states and 6323 transitions. [2024-10-31 22:03:31,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:31,184 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4596 states and 6323 transitions. [2024-10-31 22:03:31,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4596 states and 6323 transitions. [2024-10-31 22:03:31,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4596 to 4596. [2024-10-31 22:03:31,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4596 states, 4596 states have (on average 1.3757615317667538) internal successors, (6323), 4595 states have internal predecessors, (6323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:31,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4596 states to 4596 states and 6323 transitions. [2024-10-31 22:03:31,268 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4596 states and 6323 transitions. [2024-10-31 22:03:31,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:31,270 INFO L425 stractBuchiCegarLoop]: Abstraction has 4596 states and 6323 transitions. [2024-10-31 22:03:31,271 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 22:03:31,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4596 states and 6323 transitions. [2024-10-31 22:03:31,288 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4484 [2024-10-31 22:03:31,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:31,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:31,290 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:31,290 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:31,290 INFO L745 eck$LassoCheckResult]: Stem: 77613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 77614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 77712#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77713#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77454#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 77455#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77724#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77674#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77675#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77706#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77687#L526 assume !(0 == ~M_E~0); 77688#L526-2 assume !(0 == ~T1_E~0); 77726#L531-1 assume !(0 == ~T2_E~0); 77670#L536-1 assume !(0 == ~T3_E~0); 77671#L541-1 assume !(0 == ~T4_E~0); 77666#L546-1 assume !(0 == ~E_M~0); 77667#L551-1 assume !(0 == ~E_1~0); 77644#L556-1 assume !(0 == ~E_2~0); 77645#L561-1 assume !(0 == ~E_3~0); 77654#L566-1 assume !(0 == ~E_4~0); 77655#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77649#L262 assume !(1 == ~m_pc~0); 77650#L262-2 is_master_triggered_~__retres1~0#1 := 0; 77837#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77582#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77583#L649 assume !(0 != activate_threads_~tmp~1#1); 77836#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77591#L281 assume !(1 == ~t1_pc~0); 77592#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 77507#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77421#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77422#L657 assume !(0 != activate_threads_~tmp___0~0#1); 77565#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77657#L300 assume !(1 == ~t2_pc~0); 77658#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77762#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77678#L665 assume !(0 != activate_threads_~tmp___1~0#1); 77434#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77435#L319 assume !(1 == ~t3_pc~0); 77390#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77391#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77377#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77378#L673 assume !(0 != activate_threads_~tmp___2~0#1); 77411#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77412#L338 assume !(1 == ~t4_pc~0); 77478#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 77479#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77485#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77486#L681 assume !(0 != activate_threads_~tmp___3~0#1); 77359#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77360#L584 assume !(1 == ~M_E~0); 77562#L584-2 assume !(1 == ~T1_E~0); 77524#L589-1 assume !(1 == ~T2_E~0); 77525#L594-1 assume !(1 == ~T3_E~0); 77619#L599-1 assume !(1 == ~T4_E~0); 77389#L604-1 assume !(1 == ~E_M~0); 77375#L609-1 assume !(1 == ~E_1~0); 77376#L614-1 assume !(1 == ~E_2~0); 77495#L619-1 assume !(1 == ~E_3~0); 77584#L624-1 assume !(1 == ~E_4~0); 77676#L629-1 assume { :end_inline_reset_delta_events } true; 77846#L815-2 [2024-10-31 22:03:31,291 INFO L747 eck$LassoCheckResult]: Loop: 77846#L815-2 assume !false; 80028#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78485#L501-1 assume !false; 80027#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 78475#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 78469#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 78467#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 78464#L440 assume !(0 != eval_~tmp~0#1); 78465#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81505#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81503#L526-3 assume !(0 == ~M_E~0); 81501#L526-5 assume !(0 == ~T1_E~0); 81499#L531-3 assume !(0 == ~T2_E~0); 81497#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 81495#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 81493#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 81491#L551-3 assume !(0 == ~E_1~0); 81489#L556-3 assume !(0 == ~E_2~0); 81487#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81484#L566-3 assume !(0 == ~E_4~0); 81482#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81480#L262-18 assume !(1 == ~m_pc~0); 81478#L262-20 is_master_triggered_~__retres1~0#1 := 0; 81476#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81474#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81472#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81470#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81468#L281-18 assume !(1 == ~t1_pc~0); 81465#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 81463#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81462#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81461#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 81460#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81459#L300-18 assume !(1 == ~t2_pc~0); 81458#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 81457#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81455#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81453#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 81451#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81448#L319-18 assume 1 == ~t3_pc~0; 81445#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81443#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81441#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81439#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81437#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81436#L338-18 assume !(1 == ~t4_pc~0); 81433#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 81431#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81429#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81427#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81425#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81423#L584-3 assume !(1 == ~M_E~0); 81419#L584-5 assume !(1 == ~T1_E~0); 81416#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81414#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81412#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81410#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81408#L609-3 assume !(1 == ~E_1~0); 81407#L614-3 assume !(1 == ~E_2~0); 81406#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81405#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81404#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 81401#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 81398#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 80586#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 80585#L834 assume !(0 == start_simulation_~tmp~3#1); 80583#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 80040#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 80036#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 80035#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 80034#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80033#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80032#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 80031#L847 assume !(0 != start_simulation_~tmp___0~1#1); 77846#L815-2 [2024-10-31 22:03:31,291 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:31,291 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2024-10-31 22:03:31,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:31,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240991947] [2024-10-31 22:03:31,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:31,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:31,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:31,304 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:31,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:31,325 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:31,326 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:31,326 INFO L85 PathProgramCache]: Analyzing trace with hash -918560465, now seen corresponding path program 2 times [2024-10-31 22:03:31,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:31,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1060212537] [2024-10-31 22:03:31,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:31,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:31,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:31,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:31,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:31,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1060212537] [2024-10-31 22:03:31,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1060212537] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:31,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:31,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:03:31,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531639730] [2024-10-31 22:03:31,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:31,388 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:31,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:31,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:03:31,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:03:31,389 INFO L87 Difference]: Start difference. First operand 4596 states and 6323 transitions. cyclomatic complexity: 1735 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:31,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:31,489 INFO L93 Difference]: Finished difference Result 4708 states and 6435 transitions. [2024-10-31 22:03:31,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4708 states and 6435 transitions. [2024-10-31 22:03:31,508 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4596 [2024-10-31 22:03:31,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4708 states to 4708 states and 6435 transitions. [2024-10-31 22:03:31,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4708 [2024-10-31 22:03:31,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4708 [2024-10-31 22:03:31,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4708 states and 6435 transitions. [2024-10-31 22:03:31,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:31,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4708 states and 6435 transitions. [2024-10-31 22:03:31,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4708 states and 6435 transitions. [2024-10-31 22:03:31,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4708 to 4644. [2024-10-31 22:03:31,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4644 states, 4644 states have (on average 1.3718776916451334) internal successors, (6371), 4643 states have internal predecessors, (6371), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:31,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4644 states to 4644 states and 6371 transitions. [2024-10-31 22:03:31,678 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4644 states and 6371 transitions. [2024-10-31 22:03:31,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:03:31,678 INFO L425 stractBuchiCegarLoop]: Abstraction has 4644 states and 6371 transitions. [2024-10-31 22:03:31,679 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-31 22:03:31,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4644 states and 6371 transitions. [2024-10-31 22:03:31,694 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4532 [2024-10-31 22:03:31,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:31,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:31,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:31,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:31,696 INFO L745 eck$LassoCheckResult]: Stem: 86933#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 86934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 87044#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87045#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86767#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 86768#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87063#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87001#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87002#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87035#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87012#L526 assume !(0 == ~M_E~0); 87013#L526-2 assume !(0 == ~T1_E~0); 87065#L531-1 assume !(0 == ~T2_E~0); 86997#L536-1 assume !(0 == ~T3_E~0); 86998#L541-1 assume !(0 == ~T4_E~0); 86993#L546-1 assume !(0 == ~E_M~0); 86994#L551-1 assume !(0 == ~E_1~0); 86970#L556-1 assume !(0 == ~E_2~0); 86971#L561-1 assume !(0 == ~E_3~0); 86980#L566-1 assume !(0 == ~E_4~0); 86981#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86975#L262 assume !(1 == ~m_pc~0); 86976#L262-2 is_master_triggered_~__retres1~0#1 := 0; 87230#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86900#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 86901#L649 assume !(0 != activate_threads_~tmp~1#1); 87225#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86910#L281 assume !(1 == ~t1_pc~0); 86911#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86820#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86733#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86734#L657 assume !(0 != activate_threads_~tmp___0~0#1); 86885#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86983#L300 assume !(1 == ~t2_pc~0); 86984#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 87112#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87048#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 87005#L665 assume !(0 != activate_threads_~tmp___1~0#1); 86746#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86747#L319 assume !(1 == ~t3_pc~0); 86702#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86703#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86689#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 86690#L673 assume !(0 != activate_threads_~tmp___2~0#1); 86723#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86724#L338 assume !(1 == ~t4_pc~0); 86793#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 86794#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86799#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 86800#L681 assume !(0 != activate_threads_~tmp___3~0#1); 86671#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86672#L584 assume !(1 == ~M_E~0); 86882#L584-2 assume !(1 == ~T1_E~0); 86836#L589-1 assume !(1 == ~T2_E~0); 86837#L594-1 assume !(1 == ~T3_E~0); 86937#L599-1 assume !(1 == ~T4_E~0); 86701#L604-1 assume !(1 == ~E_M~0); 86687#L609-1 assume !(1 == ~E_1~0); 86688#L614-1 assume !(1 == ~E_2~0); 86808#L619-1 assume !(1 == ~E_3~0); 86902#L624-1 assume !(1 == ~E_4~0); 87003#L629-1 assume { :end_inline_reset_delta_events } true; 87245#L815-2 [2024-10-31 22:03:31,696 INFO L747 eck$LassoCheckResult]: Loop: 87245#L815-2 assume !false; 89378#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89377#L501-1 assume !false; 89376#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 89375#L398 assume !(0 == ~m_st~0); 89372#L402 assume !(0 == ~t1_st~0); 89373#L406 assume !(0 == ~t2_st~0); 89374#L410 assume !(0 == ~t3_st~0); 89370#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 89371#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 89366#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 89367#L440 assume !(0 != eval_~tmp~0#1); 89605#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89603#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89601#L526-3 assume !(0 == ~M_E~0); 89599#L526-5 assume !(0 == ~T1_E~0); 89597#L531-3 assume !(0 == ~T2_E~0); 89595#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89593#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 89591#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 89589#L551-3 assume !(0 == ~E_1~0); 89587#L556-3 assume !(0 == ~E_2~0); 89585#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 89583#L566-3 assume !(0 == ~E_4~0); 89581#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89579#L262-18 assume !(1 == ~m_pc~0); 89577#L262-20 is_master_triggered_~__retres1~0#1 := 0; 89575#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89573#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 89571#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 89569#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89567#L281-18 assume !(1 == ~t1_pc~0); 89563#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 89561#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89559#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 89557#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 89555#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89553#L300-18 assume !(1 == ~t2_pc~0); 89551#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 89549#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89547#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 89545#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 89543#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89541#L319-18 assume !(1 == ~t3_pc~0); 89539#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 89535#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89533#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 89531#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89529#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89527#L338-18 assume !(1 == ~t4_pc~0); 89525#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 89523#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89521#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 89519#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89517#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89515#L584-3 assume !(1 == ~M_E~0); 89513#L584-5 assume !(1 == ~T1_E~0); 89511#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 89509#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89507#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89505#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 89503#L609-3 assume !(1 == ~E_1~0); 89501#L614-3 assume !(1 == ~E_2~0); 89499#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 89497#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89495#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 89491#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 89483#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 89461#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 86860#L834 assume !(0 == start_simulation_~tmp~3#1); 86861#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 89610#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 89606#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 89388#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 89387#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89386#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89385#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 89384#L847 assume !(0 != start_simulation_~tmp___0~1#1); 87245#L815-2 [2024-10-31 22:03:31,697 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:31,697 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2024-10-31 22:03:31,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:31,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039425218] [2024-10-31 22:03:31,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:31,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:31,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:31,708 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:31,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:31,731 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:31,732 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:31,732 INFO L85 PathProgramCache]: Analyzing trace with hash -978947036, now seen corresponding path program 1 times [2024-10-31 22:03:31,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:31,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014541891] [2024-10-31 22:03:31,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:31,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:31,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:31,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:31,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:31,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014541891] [2024-10-31 22:03:31,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014541891] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:31,825 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:31,825 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:03:31,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [756168431] [2024-10-31 22:03:31,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:31,826 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:31,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:31,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:03:31,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:03:31,827 INFO L87 Difference]: Start difference. First operand 4644 states and 6371 transitions. cyclomatic complexity: 1735 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:32,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:32,023 INFO L93 Difference]: Finished difference Result 4776 states and 6466 transitions. [2024-10-31 22:03:32,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4776 states and 6466 transitions. [2024-10-31 22:03:32,042 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4664 [2024-10-31 22:03:32,057 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4776 states to 4776 states and 6466 transitions. [2024-10-31 22:03:32,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4776 [2024-10-31 22:03:32,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4776 [2024-10-31 22:03:32,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4776 states and 6466 transitions. [2024-10-31 22:03:32,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:32,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4776 states and 6466 transitions. [2024-10-31 22:03:32,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4776 states and 6466 transitions. [2024-10-31 22:03:32,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4776 to 4776. [2024-10-31 22:03:32,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4776 states, 4776 states have (on average 1.353852596314908) internal successors, (6466), 4775 states have internal predecessors, (6466), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:32,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4776 states to 4776 states and 6466 transitions. [2024-10-31 22:03:32,309 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4776 states and 6466 transitions. [2024-10-31 22:03:32,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:03:32,310 INFO L425 stractBuchiCegarLoop]: Abstraction has 4776 states and 6466 transitions. [2024-10-31 22:03:32,310 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-31 22:03:32,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4776 states and 6466 transitions. [2024-10-31 22:03:32,326 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4664 [2024-10-31 22:03:32,327 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:32,327 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:32,328 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:32,328 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:32,329 INFO L745 eck$LassoCheckResult]: Stem: 96351#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 96352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 96446#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96447#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96194#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 96195#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96460#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96414#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96415#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96441#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96424#L526 assume !(0 == ~M_E~0); 96425#L526-2 assume !(0 == ~T1_E~0); 96463#L531-1 assume !(0 == ~T2_E~0); 96410#L536-1 assume !(0 == ~T3_E~0); 96411#L541-1 assume !(0 == ~T4_E~0); 96406#L546-1 assume !(0 == ~E_M~0); 96407#L551-1 assume !(0 == ~E_1~0); 96384#L556-1 assume !(0 == ~E_2~0); 96385#L561-1 assume !(0 == ~E_3~0); 96394#L566-1 assume !(0 == ~E_4~0); 96395#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96389#L262 assume !(1 == ~m_pc~0); 96390#L262-2 is_master_triggered_~__retres1~0#1 := 0; 96576#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96319#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 96320#L649 assume !(0 != activate_threads_~tmp~1#1); 96572#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96329#L281 assume !(1 == ~t1_pc~0); 96330#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 96245#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96160#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 96161#L657 assume !(0 != activate_threads_~tmp___0~0#1); 96303#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96397#L300 assume !(1 == ~t2_pc~0); 96398#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96498#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96450#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96418#L665 assume !(0 != activate_threads_~tmp___1~0#1); 96173#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96174#L319 assume !(1 == ~t3_pc~0); 96130#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96131#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96117#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 96118#L673 assume !(0 != activate_threads_~tmp___2~0#1); 96150#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96151#L338 assume !(1 == ~t4_pc~0); 96218#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96219#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96224#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96225#L681 assume !(0 != activate_threads_~tmp___3~0#1); 96099#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96100#L584 assume !(1 == ~M_E~0); 96300#L584-2 assume !(1 == ~T1_E~0); 96260#L589-1 assume !(1 == ~T2_E~0); 96261#L594-1 assume !(1 == ~T3_E~0); 96355#L599-1 assume !(1 == ~T4_E~0); 96129#L604-1 assume !(1 == ~E_M~0); 96115#L609-1 assume !(1 == ~E_1~0); 96116#L614-1 assume !(1 == ~E_2~0); 96233#L619-1 assume !(1 == ~E_3~0); 96321#L624-1 assume !(1 == ~E_4~0); 96416#L629-1 assume { :end_inline_reset_delta_events } true; 96588#L815-2 [2024-10-31 22:03:32,329 INFO L747 eck$LassoCheckResult]: Loop: 96588#L815-2 assume !false; 100254#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100005#L501-1 assume !false; 100253#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 100252#L398 assume !(0 == ~m_st~0); 100249#L402 assume !(0 == ~t1_st~0); 100250#L406 assume !(0 == ~t2_st~0); 100251#L410 assume !(0 == ~t3_st~0); 100247#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 100248#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 100842#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 100840#L440 assume !(0 != eval_~tmp~0#1); 100837#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100835#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100797#L526-3 assume !(0 == ~M_E~0); 100796#L526-5 assume !(0 == ~T1_E~0); 100795#L531-3 assume !(0 == ~T2_E~0); 100087#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100086#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100085#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100084#L551-3 assume !(0 == ~E_1~0); 100083#L556-3 assume !(0 == ~E_2~0); 100081#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100080#L566-3 assume !(0 == ~E_4~0); 100079#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100078#L262-18 assume !(1 == ~m_pc~0); 100077#L262-20 is_master_triggered_~__retres1~0#1 := 0; 100076#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100075#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 100071#L649-18 assume !(0 != activate_threads_~tmp~1#1); 100069#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100067#L281-18 assume !(1 == ~t1_pc~0); 100064#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 100061#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100059#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 100056#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 100054#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100052#L300-18 assume !(1 == ~t2_pc~0); 100050#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 100048#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100046#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100034#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 100033#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100031#L319-18 assume !(1 == ~t3_pc~0); 100029#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 100026#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100024#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100022#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100020#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100018#L338-18 assume !(1 == ~t4_pc~0); 100016#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 100014#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100012#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100010#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 99552#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99549#L584-3 assume !(1 == ~M_E~0); 99548#L584-5 assume !(1 == ~T1_E~0); 100350#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100349#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100348#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100347#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 100346#L609-3 assume !(1 == ~E_1~0); 100345#L614-3 assume !(1 == ~E_2~0); 100344#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 100343#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100342#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 98659#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 98650#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98638#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 98614#L834 assume !(0 == start_simulation_~tmp~3#1); 98615#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 100530#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 100526#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 100525#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 100524#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 100509#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 100508#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 100255#L847 assume !(0 != start_simulation_~tmp___0~1#1); 96588#L815-2 [2024-10-31 22:03:32,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:32,330 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2024-10-31 22:03:32,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:32,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574397496] [2024-10-31 22:03:32,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:32,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:32,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:32,346 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:32,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:32,366 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:32,366 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:32,367 INFO L85 PathProgramCache]: Analyzing trace with hash -994465754, now seen corresponding path program 1 times [2024-10-31 22:03:32,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:32,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483640493] [2024-10-31 22:03:32,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:32,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:32,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:32,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:32,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:32,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483640493] [2024-10-31 22:03:32,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483640493] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:32,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:32,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:32,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [535290980] [2024-10-31 22:03:32,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:32,425 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:03:32,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:32,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:32,426 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:32,427 INFO L87 Difference]: Start difference. First operand 4776 states and 6466 transitions. cyclomatic complexity: 1698 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:32,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:32,520 INFO L93 Difference]: Finished difference Result 7480 states and 9967 transitions. [2024-10-31 22:03:32,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7480 states and 9967 transitions. [2024-10-31 22:03:32,558 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7350 [2024-10-31 22:03:32,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7480 states to 7480 states and 9967 transitions. [2024-10-31 22:03:32,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7480 [2024-10-31 22:03:32,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7480 [2024-10-31 22:03:32,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7480 states and 9967 transitions. [2024-10-31 22:03:32,608 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:32,608 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7480 states and 9967 transitions. [2024-10-31 22:03:32,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7480 states and 9967 transitions. [2024-10-31 22:03:32,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7480 to 7224. [2024-10-31 22:03:32,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7224 states, 7224 states have (on average 1.33374861572536) internal successors, (9635), 7223 states have internal predecessors, (9635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:32,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7224 states to 7224 states and 9635 transitions. [2024-10-31 22:03:32,820 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7224 states and 9635 transitions. [2024-10-31 22:03:32,821 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:32,822 INFO L425 stractBuchiCegarLoop]: Abstraction has 7224 states and 9635 transitions. [2024-10-31 22:03:32,822 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-31 22:03:32,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7224 states and 9635 transitions. [2024-10-31 22:03:32,839 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7094 [2024-10-31 22:03:32,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:32,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:32,840 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:32,840 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:32,841 INFO L745 eck$LassoCheckResult]: Stem: 108619#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 108620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 108719#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 108720#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108458#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 108459#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 108733#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108682#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108683#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 108712#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108693#L526 assume !(0 == ~M_E~0); 108694#L526-2 assume !(0 == ~T1_E~0); 108736#L531-1 assume !(0 == ~T2_E~0); 108678#L536-1 assume !(0 == ~T3_E~0); 108679#L541-1 assume !(0 == ~T4_E~0); 108674#L546-1 assume !(0 == ~E_M~0); 108675#L551-1 assume !(0 == ~E_1~0); 108651#L556-1 assume !(0 == ~E_2~0); 108652#L561-1 assume !(0 == ~E_3~0); 108662#L566-1 assume !(0 == ~E_4~0); 108663#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108656#L262 assume !(1 == ~m_pc~0); 108657#L262-2 is_master_triggered_~__retres1~0#1 := 0; 108853#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108587#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 108588#L649 assume !(0 != activate_threads_~tmp~1#1); 108851#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108596#L281 assume !(1 == ~t1_pc~0); 108597#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 108514#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108423#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 108424#L657 assume !(0 != activate_threads_~tmp___0~0#1); 108571#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108665#L300 assume !(1 == ~t2_pc~0); 108666#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 108773#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 108686#L665 assume !(0 != activate_threads_~tmp___1~0#1); 108436#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108437#L319 assume !(1 == ~t3_pc~0); 108392#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 108393#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108379#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 108380#L673 assume !(0 != activate_threads_~tmp___2~0#1); 108413#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108414#L338 assume !(1 == ~t4_pc~0); 108485#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 108486#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108491#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 108492#L681 assume !(0 != activate_threads_~tmp___3~0#1); 108361#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108362#L584 assume !(1 == ~M_E~0); 108568#L584-2 assume !(1 == ~T1_E~0); 108528#L589-1 assume !(1 == ~T2_E~0); 108529#L594-1 assume !(1 == ~T3_E~0); 108623#L599-1 assume !(1 == ~T4_E~0); 108391#L604-1 assume !(1 == ~E_M~0); 108377#L609-1 assume !(1 == ~E_1~0); 108378#L614-1 assume !(1 == ~E_2~0); 108502#L619-1 assume !(1 == ~E_3~0); 108589#L624-1 assume !(1 == ~E_4~0); 108684#L629-1 assume { :end_inline_reset_delta_events } true; 108859#L815-2 assume !false; 110542#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 110523#L501-1 [2024-10-31 22:03:32,841 INFO L747 eck$LassoCheckResult]: Loop: 110523#L501-1 assume !false; 110524#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 110578#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 110577#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 110574#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 110575#L440 assume 0 != eval_~tmp~0#1; 110576#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 110572#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 110569#L448-2 havoc eval_~tmp_ndt_1~0#1; 110570#L445-1 assume !(0 == ~t1_st~0); 110874#L459-1 assume !(0 == ~t2_st~0); 110561#L473-1 assume !(0 == ~t3_st~0); 110544#L487-1 assume !(0 == ~t4_st~0); 110523#L501-1 [2024-10-31 22:03:32,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:32,842 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2024-10-31 22:03:32,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:32,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712386637] [2024-10-31 22:03:32,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:32,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:32,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:32,857 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:32,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:32,879 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:32,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:32,880 INFO L85 PathProgramCache]: Analyzing trace with hash -1697797356, now seen corresponding path program 1 times [2024-10-31 22:03:32,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:32,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721240966] [2024-10-31 22:03:32,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:32,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:32,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:32,886 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:32,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:32,891 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:32,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:32,892 INFO L85 PathProgramCache]: Analyzing trace with hash -1780226006, now seen corresponding path program 1 times [2024-10-31 22:03:32,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:32,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375398828] [2024-10-31 22:03:32,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:32,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:32,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:32,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:32,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:32,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1375398828] [2024-10-31 22:03:32,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1375398828] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:32,935 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:32,935 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:32,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443871723] [2024-10-31 22:03:32,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:33,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:33,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:33,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:33,030 INFO L87 Difference]: Start difference. First operand 7224 states and 9635 transitions. cyclomatic complexity: 2423 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:33,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:33,194 INFO L93 Difference]: Finished difference Result 11678 states and 15445 transitions. [2024-10-31 22:03:33,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11678 states and 15445 transitions. [2024-10-31 22:03:33,242 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11424 [2024-10-31 22:03:33,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11678 states to 11678 states and 15445 transitions. [2024-10-31 22:03:33,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11678 [2024-10-31 22:03:33,341 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11678 [2024-10-31 22:03:33,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11678 states and 15445 transitions. [2024-10-31 22:03:33,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:33,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11678 states and 15445 transitions. [2024-10-31 22:03:33,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11678 states and 15445 transitions. [2024-10-31 22:03:33,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11678 to 11678. [2024-10-31 22:03:33,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11678 states, 11678 states have (on average 1.3225723582805275) internal successors, (15445), 11677 states have internal predecessors, (15445), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:33,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11678 states to 11678 states and 15445 transitions. [2024-10-31 22:03:33,658 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11678 states and 15445 transitions. [2024-10-31 22:03:33,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:33,659 INFO L425 stractBuchiCegarLoop]: Abstraction has 11678 states and 15445 transitions. [2024-10-31 22:03:33,659 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-31 22:03:33,659 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11678 states and 15445 transitions. [2024-10-31 22:03:33,693 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11424 [2024-10-31 22:03:33,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:33,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:33,694 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:33,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:33,695 INFO L745 eck$LassoCheckResult]: Stem: 127525#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 127526#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 127629#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 127630#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 127367#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 127368#L365-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 127746#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132564#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132563#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132562#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132561#L526 assume !(0 == ~M_E~0); 132560#L526-2 assume !(0 == ~T1_E~0); 132559#L531-1 assume !(0 == ~T2_E~0); 132558#L536-1 assume !(0 == ~T3_E~0); 132557#L541-1 assume !(0 == ~T4_E~0); 132556#L546-1 assume !(0 == ~E_M~0); 132555#L551-1 assume !(0 == ~E_1~0); 132554#L556-1 assume !(0 == ~E_2~0); 132553#L561-1 assume !(0 == ~E_3~0); 132552#L566-1 assume !(0 == ~E_4~0); 132551#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132550#L262 assume !(1 == ~m_pc~0); 132549#L262-2 is_master_triggered_~__retres1~0#1 := 0; 132548#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132547#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 132546#L649 assume !(0 != activate_threads_~tmp~1#1); 132542#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 127504#L281 assume !(1 == ~t1_pc~0); 127505#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 127417#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 127332#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 127333#L657 assume !(0 != activate_threads_~tmp___0~0#1); 127479#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 127575#L300 assume !(1 == ~t2_pc~0); 127576#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 127686#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 127634#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 127599#L665 assume !(0 != activate_threads_~tmp___1~0#1); 127345#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127346#L319 assume !(1 == ~t3_pc~0); 127801#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 132524#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132523#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 132522#L673 assume !(0 != activate_threads_~tmp___2~0#1); 132521#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132520#L338 assume !(1 == ~t4_pc~0); 132519#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 132518#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132517#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 132516#L681 assume !(0 != activate_threads_~tmp___3~0#1); 132515#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132514#L584 assume !(1 == ~M_E~0); 132513#L584-2 assume !(1 == ~T1_E~0); 132512#L589-1 assume !(1 == ~T2_E~0); 132511#L594-1 assume !(1 == ~T3_E~0); 132510#L599-1 assume !(1 == ~T4_E~0); 132509#L604-1 assume !(1 == ~E_M~0); 132508#L609-1 assume !(1 == ~E_1~0); 132507#L614-1 assume !(1 == ~E_2~0); 132506#L619-1 assume !(1 == ~E_3~0); 132505#L624-1 assume !(1 == ~E_4~0); 132504#L629-1 assume { :end_inline_reset_delta_events } true; 132502#L815-2 assume !false; 132409#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 132407#L501-1 [2024-10-31 22:03:33,695 INFO L747 eck$LassoCheckResult]: Loop: 132407#L501-1 assume !false; 132405#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 132402#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 132400#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 132390#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 132383#L440 assume 0 != eval_~tmp~0#1; 132377#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 132375#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 132376#L448-2 havoc eval_~tmp_ndt_1~0#1; 133040#L445-1 assume !(0 == ~t1_st~0); 132544#L459-1 assume !(0 == ~t2_st~0); 132540#L473-1 assume !(0 == ~t3_st~0); 132411#L487-1 assume !(0 == ~t4_st~0); 132407#L501-1 [2024-10-31 22:03:33,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:33,696 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2024-10-31 22:03:33,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:33,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822583036] [2024-10-31 22:03:33,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:33,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:33,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:33,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:33,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:33,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822583036] [2024-10-31 22:03:33,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [822583036] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:33,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:33,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:33,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1610875604] [2024-10-31 22:03:33,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:33,724 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:03:33,724 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:33,724 INFO L85 PathProgramCache]: Analyzing trace with hash -1697797356, now seen corresponding path program 2 times [2024-10-31 22:03:33,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:33,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807777208] [2024-10-31 22:03:33,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:33,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:33,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:33,728 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:33,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:33,732 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:33,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:33,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:33,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:33,878 INFO L87 Difference]: Start difference. First operand 11678 states and 15445 transitions. cyclomatic complexity: 3779 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:33,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:33,915 INFO L93 Difference]: Finished difference Result 11618 states and 15367 transitions. [2024-10-31 22:03:33,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11618 states and 15367 transitions. [2024-10-31 22:03:33,961 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11424 [2024-10-31 22:03:34,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11618 states to 11618 states and 15367 transitions. [2024-10-31 22:03:34,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11618 [2024-10-31 22:03:34,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11618 [2024-10-31 22:03:34,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11618 states and 15367 transitions. [2024-10-31 22:03:34,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:34,023 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11618 states and 15367 transitions. [2024-10-31 22:03:34,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11618 states and 15367 transitions. [2024-10-31 22:03:34,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11618 to 11618. [2024-10-31 22:03:34,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11618 states, 11618 states have (on average 1.3226889309691858) internal successors, (15367), 11617 states have internal predecessors, (15367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:34,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11618 states to 11618 states and 15367 transitions. [2024-10-31 22:03:34,265 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11618 states and 15367 transitions. [2024-10-31 22:03:34,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:34,266 INFO L425 stractBuchiCegarLoop]: Abstraction has 11618 states and 15367 transitions. [2024-10-31 22:03:34,266 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-31 22:03:34,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11618 states and 15367 transitions. [2024-10-31 22:03:34,308 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11424 [2024-10-31 22:03:34,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:34,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:34,309 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:34,310 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:34,310 INFO L745 eck$LassoCheckResult]: Stem: 150824#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 150825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 150921#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 150922#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 150669#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 150670#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 150937#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 150888#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 150889#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 150916#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 150901#L526 assume !(0 == ~M_E~0); 150902#L526-2 assume !(0 == ~T1_E~0); 150939#L531-1 assume !(0 == ~T2_E~0); 150884#L536-1 assume !(0 == ~T3_E~0); 150885#L541-1 assume !(0 == ~T4_E~0); 150880#L546-1 assume !(0 == ~E_M~0); 150881#L551-1 assume !(0 == ~E_1~0); 150858#L556-1 assume !(0 == ~E_2~0); 150859#L561-1 assume !(0 == ~E_3~0); 150868#L566-1 assume !(0 == ~E_4~0); 150869#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150863#L262 assume !(1 == ~m_pc~0); 150864#L262-2 is_master_triggered_~__retres1~0#1 := 0; 151057#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150794#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 150795#L649 assume !(0 != activate_threads_~tmp~1#1); 151056#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 150803#L281 assume !(1 == ~t1_pc~0); 150804#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 150719#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150634#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 150635#L657 assume !(0 != activate_threads_~tmp___0~0#1); 150778#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 150871#L300 assume !(1 == ~t2_pc~0); 150872#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 150977#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 150926#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 150892#L665 assume !(0 != activate_threads_~tmp___1~0#1); 150647#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150648#L319 assume !(1 == ~t3_pc~0); 150604#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 150605#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 150591#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 150592#L673 assume !(0 != activate_threads_~tmp___2~0#1); 150624#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 150625#L338 assume !(1 == ~t4_pc~0); 150693#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 150694#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 150700#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 150701#L681 assume !(0 != activate_threads_~tmp___3~0#1); 150573#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150574#L584 assume !(1 == ~M_E~0); 150775#L584-2 assume !(1 == ~T1_E~0); 150734#L589-1 assume !(1 == ~T2_E~0); 150735#L594-1 assume !(1 == ~T3_E~0); 150830#L599-1 assume !(1 == ~T4_E~0); 150603#L604-1 assume !(1 == ~E_M~0); 150589#L609-1 assume !(1 == ~E_1~0); 150590#L614-1 assume !(1 == ~E_2~0); 150708#L619-1 assume !(1 == ~E_3~0); 150796#L624-1 assume !(1 == ~E_4~0); 150890#L629-1 assume { :end_inline_reset_delta_events } true; 151062#L815-2 assume !false; 153858#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 153855#L501-1 [2024-10-31 22:03:34,310 INFO L747 eck$LassoCheckResult]: Loop: 153855#L501-1 assume !false; 153853#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 153850#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 153847#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 153843#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 153839#L440 assume 0 != eval_~tmp~0#1; 153831#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 153827#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 153828#L448-2 havoc eval_~tmp_ndt_1~0#1; 153894#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 153884#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 153878#L462-2 havoc eval_~tmp_ndt_2~0#1; 153871#L459-1 assume !(0 == ~t2_st~0); 153865#L473-1 assume !(0 == ~t3_st~0); 153860#L487-1 assume !(0 == ~t4_st~0); 153855#L501-1 [2024-10-31 22:03:34,313 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:34,313 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2024-10-31 22:03:34,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:34,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010635073] [2024-10-31 22:03:34,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:34,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:34,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:34,398 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:34,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:34,417 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:34,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:34,418 INFO L85 PathProgramCache]: Analyzing trace with hash 201422285, now seen corresponding path program 1 times [2024-10-31 22:03:34,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:34,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872335631] [2024-10-31 22:03:34,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:34,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:34,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:34,423 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:34,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:34,428 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:34,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:34,429 INFO L85 PathProgramCache]: Analyzing trace with hash -1703099037, now seen corresponding path program 1 times [2024-10-31 22:03:34,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:34,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142347454] [2024-10-31 22:03:34,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:34,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:34,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:34,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:34,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:34,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142347454] [2024-10-31 22:03:34,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142347454] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:34,489 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:34,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:34,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254811978] [2024-10-31 22:03:34,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:34,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:34,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:34,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:34,579 INFO L87 Difference]: Start difference. First operand 11618 states and 15367 transitions. cyclomatic complexity: 3761 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:34,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:34,697 INFO L93 Difference]: Finished difference Result 13646 states and 17935 transitions. [2024-10-31 22:03:34,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13646 states and 17935 transitions. [2024-10-31 22:03:34,768 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13452 [2024-10-31 22:03:34,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13646 states to 13646 states and 17935 transitions. [2024-10-31 22:03:34,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13646 [2024-10-31 22:03:34,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13646 [2024-10-31 22:03:34,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13646 states and 17935 transitions. [2024-10-31 22:03:34,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:34,951 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13646 states and 17935 transitions. [2024-10-31 22:03:34,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13646 states and 17935 transitions. [2024-10-31 22:03:35,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13646 to 13156. [2024-10-31 22:03:35,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13156 states, 13156 states have (on average 1.3153694131955) internal successors, (17305), 13155 states have internal predecessors, (17305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:35,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13156 states to 13156 states and 17305 transitions. [2024-10-31 22:03:35,122 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13156 states and 17305 transitions. [2024-10-31 22:03:35,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:35,123 INFO L425 stractBuchiCegarLoop]: Abstraction has 13156 states and 17305 transitions. [2024-10-31 22:03:35,123 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-31 22:03:35,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13156 states and 17305 transitions. [2024-10-31 22:03:35,244 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12962 [2024-10-31 22:03:35,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:35,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:35,246 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:35,246 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:35,246 INFO L745 eck$LassoCheckResult]: Stem: 176098#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 176099#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 176203#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 176204#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 175939#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 175940#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 176219#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 176166#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 176167#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 176197#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 176180#L526 assume !(0 == ~M_E~0); 176181#L526-2 assume !(0 == ~T1_E~0); 176221#L531-1 assume !(0 == ~T2_E~0); 176162#L536-1 assume !(0 == ~T3_E~0); 176163#L541-1 assume !(0 == ~T4_E~0); 176158#L546-1 assume !(0 == ~E_M~0); 176159#L551-1 assume !(0 == ~E_1~0); 176134#L556-1 assume !(0 == ~E_2~0); 176135#L561-1 assume !(0 == ~E_3~0); 176144#L566-1 assume !(0 == ~E_4~0); 176145#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176139#L262 assume !(1 == ~m_pc~0); 176140#L262-2 is_master_triggered_~__retres1~0#1 := 0; 176343#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176067#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 176068#L649 assume !(0 != activate_threads_~tmp~1#1); 176342#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176077#L281 assume !(1 == ~t1_pc~0); 176078#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 175992#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 175906#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 175907#L657 assume !(0 != activate_threads_~tmp___0~0#1); 176048#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176147#L300 assume !(1 == ~t2_pc~0); 176148#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 176263#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176208#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176171#L665 assume !(0 != activate_threads_~tmp___1~0#1); 175919#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 175920#L319 assume !(1 == ~t3_pc~0); 175876#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 175877#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175863#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 175864#L673 assume !(0 != activate_threads_~tmp___2~0#1); 175896#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 175897#L338 assume !(1 == ~t4_pc~0); 175965#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 175966#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 175973#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 175974#L681 assume !(0 != activate_threads_~tmp___3~0#1); 175845#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175846#L584 assume !(1 == ~M_E~0); 176045#L584-2 assume !(1 == ~T1_E~0); 176007#L589-1 assume !(1 == ~T2_E~0); 176008#L594-1 assume !(1 == ~T3_E~0); 176104#L599-1 assume !(1 == ~T4_E~0); 175875#L604-1 assume !(1 == ~E_M~0); 175861#L609-1 assume !(1 == ~E_1~0); 175862#L614-1 assume !(1 == ~E_2~0); 175981#L619-1 assume !(1 == ~E_3~0); 176069#L624-1 assume !(1 == ~E_4~0); 176168#L629-1 assume { :end_inline_reset_delta_events } true; 176357#L815-2 assume !false; 179435#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 179434#L501-1 [2024-10-31 22:03:35,247 INFO L747 eck$LassoCheckResult]: Loop: 179434#L501-1 assume !false; 179433#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 179432#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 179427#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 179345#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 179346#L440 assume 0 != eval_~tmp~0#1; 179551#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 179546#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 179545#L448-2 havoc eval_~tmp_ndt_1~0#1; 179459#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 179456#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 179454#L462-2 havoc eval_~tmp_ndt_2~0#1; 179450#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 179447#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 179445#L476-2 havoc eval_~tmp_ndt_3~0#1; 179441#L473-1 assume !(0 == ~t3_st~0); 179437#L487-1 assume !(0 == ~t4_st~0); 179434#L501-1 [2024-10-31 22:03:35,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:35,247 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2024-10-31 22:03:35,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:35,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195587676] [2024-10-31 22:03:35,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:35,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:35,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:35,260 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:35,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:35,275 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:35,276 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:35,276 INFO L85 PathProgramCache]: Analyzing trace with hash 145011028, now seen corresponding path program 1 times [2024-10-31 22:03:35,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:35,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231179595] [2024-10-31 22:03:35,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:35,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:35,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:35,281 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:35,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:35,285 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:35,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:35,286 INFO L85 PathProgramCache]: Analyzing trace with hash -443911318, now seen corresponding path program 1 times [2024-10-31 22:03:35,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:35,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090982491] [2024-10-31 22:03:35,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:35,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:35,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:35,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:35,333 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:35,333 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090982491] [2024-10-31 22:03:35,333 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090982491] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:35,333 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:35,333 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:03:35,333 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864073152] [2024-10-31 22:03:35,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:35,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:35,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:35,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:35,415 INFO L87 Difference]: Start difference. First operand 13156 states and 17305 transitions. cyclomatic complexity: 4161 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:35,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:35,540 INFO L93 Difference]: Finished difference Result 23326 states and 30563 transitions. [2024-10-31 22:03:35,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23326 states and 30563 transitions. [2024-10-31 22:03:35,723 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 23004 [2024-10-31 22:03:35,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23326 states to 23326 states and 30563 transitions. [2024-10-31 22:03:35,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23326 [2024-10-31 22:03:35,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23326 [2024-10-31 22:03:35,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23326 states and 30563 transitions. [2024-10-31 22:03:35,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:35,817 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23326 states and 30563 transitions. [2024-10-31 22:03:35,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23326 states and 30563 transitions. [2024-10-31 22:03:36,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23326 to 22570. [2024-10-31 22:03:36,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22570 states, 22570 states have (on average 1.3142667257421357) internal successors, (29663), 22569 states have internal predecessors, (29663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:36,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22570 states to 22570 states and 29663 transitions. [2024-10-31 22:03:36,265 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22570 states and 29663 transitions. [2024-10-31 22:03:36,266 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:36,266 INFO L425 stractBuchiCegarLoop]: Abstraction has 22570 states and 29663 transitions. [2024-10-31 22:03:36,267 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-31 22:03:36,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22570 states and 29663 transitions. [2024-10-31 22:03:36,363 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22248 [2024-10-31 22:03:36,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:36,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:36,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:36,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:36,365 INFO L745 eck$LassoCheckResult]: Stem: 212593#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 212594#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 212701#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 212702#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 212432#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 212433#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 212717#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 212657#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 212658#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 212693#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 212672#L526 assume !(0 == ~M_E~0); 212673#L526-2 assume !(0 == ~T1_E~0); 212719#L531-1 assume !(0 == ~T2_E~0); 212653#L536-1 assume !(0 == ~T3_E~0); 212654#L541-1 assume !(0 == ~T4_E~0); 212649#L546-1 assume !(0 == ~E_M~0); 212650#L551-1 assume !(0 == ~E_1~0); 212626#L556-1 assume !(0 == ~E_2~0); 212627#L561-1 assume !(0 == ~E_3~0); 212637#L566-1 assume !(0 == ~E_4~0); 212638#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 212631#L262 assume !(1 == ~m_pc~0); 212632#L262-2 is_master_triggered_~__retres1~0#1 := 0; 212850#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 212562#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 212563#L649 assume !(0 != activate_threads_~tmp~1#1); 212849#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 212571#L281 assume !(1 == ~t1_pc~0); 212572#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 212485#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 212397#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 212398#L657 assume !(0 != activate_threads_~tmp___0~0#1); 212544#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 212640#L300 assume !(1 == ~t2_pc~0); 212641#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 212762#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 212706#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 212662#L665 assume !(0 != activate_threads_~tmp___1~0#1); 212410#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 212411#L319 assume !(1 == ~t3_pc~0); 212367#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 212368#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 212354#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 212355#L673 assume !(0 != activate_threads_~tmp___2~0#1); 212387#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 212388#L338 assume !(1 == ~t4_pc~0); 212458#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 212459#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 212466#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 212467#L681 assume !(0 != activate_threads_~tmp___3~0#1); 212335#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 212336#L584 assume !(1 == ~M_E~0); 212541#L584-2 assume !(1 == ~T1_E~0); 212501#L589-1 assume !(1 == ~T2_E~0); 212502#L594-1 assume !(1 == ~T3_E~0); 212599#L599-1 assume !(1 == ~T4_E~0); 212366#L604-1 assume !(1 == ~E_M~0); 212352#L609-1 assume !(1 == ~E_1~0); 212353#L614-1 assume !(1 == ~E_2~0); 212474#L619-1 assume !(1 == ~E_3~0); 212564#L624-1 assume !(1 == ~E_4~0); 212659#L629-1 assume { :end_inline_reset_delta_events } true; 212860#L815-2 assume !false; 218105#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 218103#L501-1 [2024-10-31 22:03:36,366 INFO L747 eck$LassoCheckResult]: Loop: 218103#L501-1 assume !false; 218101#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 218098#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 218095#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 218093#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 218091#L440 assume 0 != eval_~tmp~0#1; 218089#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 218087#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 218085#L448-2 havoc eval_~tmp_ndt_1~0#1; 218083#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 218064#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 218081#L462-2 havoc eval_~tmp_ndt_2~0#1; 218120#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 218117#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 218115#L476-2 havoc eval_~tmp_ndt_3~0#1; 218113#L473-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 216894#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 218110#L490-2 havoc eval_~tmp_ndt_4~0#1; 218107#L487-1 assume !(0 == ~t4_st~0); 218103#L501-1 [2024-10-31 22:03:36,366 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:36,367 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2024-10-31 22:03:36,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:36,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109693201] [2024-10-31 22:03:36,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:36,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:36,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:36,383 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:36,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:36,409 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:36,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:36,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1911902797, now seen corresponding path program 1 times [2024-10-31 22:03:36,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:36,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202664717] [2024-10-31 22:03:36,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:36,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:36,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:36,417 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:36,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:36,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:36,423 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:36,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1401755933, now seen corresponding path program 1 times [2024-10-31 22:03:36,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:36,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271461936] [2024-10-31 22:03:36,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:36,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:36,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:03:36,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:03:36,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:03:36,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271461936] [2024-10-31 22:03:36,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271461936] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:03:36,489 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:03:36,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:03:36,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [767621459] [2024-10-31 22:03:36,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:03:36,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:03:36,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:03:36,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:03:36,586 INFO L87 Difference]: Start difference. First operand 22570 states and 29663 transitions. cyclomatic complexity: 7105 Second operand has 3 states, 2 states have (on average 41.5) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:36,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:03:36,741 INFO L93 Difference]: Finished difference Result 26800 states and 35069 transitions. [2024-10-31 22:03:36,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26800 states and 35069 transitions. [2024-10-31 22:03:36,877 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 26470 [2024-10-31 22:03:36,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26800 states to 26800 states and 35069 transitions. [2024-10-31 22:03:36,981 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26800 [2024-10-31 22:03:36,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26800 [2024-10-31 22:03:37,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26800 states and 35069 transitions. [2024-10-31 22:03:37,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:03:37,021 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26800 states and 35069 transitions. [2024-10-31 22:03:37,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26800 states and 35069 transitions. [2024-10-31 22:03:37,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26800 to 26512. [2024-10-31 22:03:37,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26512 states, 26512 states have (on average 1.3118964996982498) internal successors, (34781), 26511 states have internal predecessors, (34781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:03:37,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26512 states to 26512 states and 34781 transitions. [2024-10-31 22:03:37,485 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26512 states and 34781 transitions. [2024-10-31 22:03:37,485 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:03:37,486 INFO L425 stractBuchiCegarLoop]: Abstraction has 26512 states and 34781 transitions. [2024-10-31 22:03:37,486 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-31 22:03:37,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26512 states and 34781 transitions. [2024-10-31 22:03:37,566 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 26182 [2024-10-31 22:03:37,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:03:37,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:03:37,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:37,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:03:37,568 INFO L745 eck$LassoCheckResult]: Stem: 261964#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 261965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 262071#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 262072#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 261812#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 261813#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 262089#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 262029#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 262030#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 262062#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 262040#L526 assume !(0 == ~M_E~0); 262041#L526-2 assume !(0 == ~T1_E~0); 262091#L531-1 assume !(0 == ~T2_E~0); 262025#L536-1 assume !(0 == ~T3_E~0); 262026#L541-1 assume !(0 == ~T4_E~0); 262021#L546-1 assume !(0 == ~E_M~0); 262022#L551-1 assume !(0 == ~E_1~0); 261996#L556-1 assume !(0 == ~E_2~0); 261997#L561-1 assume !(0 == ~E_3~0); 262007#L566-1 assume !(0 == ~E_4~0); 262008#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 262001#L262 assume !(1 == ~m_pc~0); 262002#L262-2 is_master_triggered_~__retres1~0#1 := 0; 262236#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 261932#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 261933#L649 assume !(0 != activate_threads_~tmp~1#1); 262232#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 261942#L281 assume !(1 == ~t1_pc~0); 261943#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 261862#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 261776#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 261777#L657 assume !(0 != activate_threads_~tmp___0~0#1); 261918#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 262010#L300 assume !(1 == ~t2_pc~0); 262011#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 262137#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 262076#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 262034#L665 assume !(0 != activate_threads_~tmp___1~0#1); 261789#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 261790#L319 assume !(1 == ~t3_pc~0); 261745#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 261746#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 261732#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 261733#L673 assume !(0 != activate_threads_~tmp___2~0#1); 261765#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 261766#L338 assume !(1 == ~t4_pc~0); 261836#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 261837#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 261842#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 261843#L681 assume !(0 != activate_threads_~tmp___3~0#1); 261713#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261714#L584 assume !(1 == ~M_E~0); 261915#L584-2 assume !(1 == ~T1_E~0); 261877#L589-1 assume !(1 == ~T2_E~0); 261878#L594-1 assume !(1 == ~T3_E~0); 261968#L599-1 assume !(1 == ~T4_E~0); 261744#L604-1 assume !(1 == ~E_M~0); 261730#L609-1 assume !(1 == ~E_1~0); 261731#L614-1 assume !(1 == ~E_2~0); 261851#L619-1 assume !(1 == ~E_3~0); 261934#L624-1 assume !(1 == ~E_4~0); 262031#L629-1 assume { :end_inline_reset_delta_events } true; 262248#L815-2 assume !false; 278992#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 278990#L501-1 [2024-10-31 22:03:37,569 INFO L747 eck$LassoCheckResult]: Loop: 278990#L501-1 assume !false; 278987#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 278984#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 278980#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 278978#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 278976#L440 assume 0 != eval_~tmp~0#1; 278974#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 278972#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 278971#L448-2 havoc eval_~tmp_ndt_1~0#1; 278970#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 269918#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 278968#L462-2 havoc eval_~tmp_ndt_2~0#1; 278966#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 278963#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 278961#L476-2 havoc eval_~tmp_ndt_3~0#1; 278959#L473-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 278895#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 278957#L490-2 havoc eval_~tmp_ndt_4~0#1; 278996#L487-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 278994#L504 assume !(0 != eval_~tmp_ndt_5~0#1); 278993#L504-2 havoc eval_~tmp_ndt_5~0#1; 278990#L501-1 [2024-10-31 22:03:37,570 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:37,570 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2024-10-31 22:03:37,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:37,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811977101] [2024-10-31 22:03:37,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:37,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:37,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:37,583 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:37,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:37,603 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:37,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:37,604 INFO L85 PathProgramCache]: Analyzing trace with hash -907526252, now seen corresponding path program 1 times [2024-10-31 22:03:37,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:37,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870653257] [2024-10-31 22:03:37,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:37,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:37,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:37,609 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:37,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:37,616 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:37,619 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:03:37,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1532167850, now seen corresponding path program 1 times [2024-10-31 22:03:37,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:03:37,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230736086] [2024-10-31 22:03:37,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:03:37,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:03:37,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:37,633 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:37,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:37,654 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:03:39,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:39,523 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:03:39,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:03:39,750 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 31.10 10:03:39 BoogieIcfgContainer [2024-10-31 22:03:39,750 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-10-31 22:03:39,750 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-10-31 22:03:39,750 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-10-31 22:03:39,750 INFO L274 PluginConnector]: Witness Printer initialized [2024-10-31 22:03:39,751 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:03:25" (3/4) ... [2024-10-31 22:03:39,755 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-10-31 22:03:39,858 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/witness.graphml [2024-10-31 22:03:39,859 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-10-31 22:03:39,859 INFO L158 Benchmark]: Toolchain (without parser) took 16713.85ms. Allocated memory was 121.6MB in the beginning and 5.3GB in the end (delta: 5.2GB). Free memory was 92.4MB in the beginning and 4.7GB in the end (delta: -4.6GB). Peak memory consumption was 559.5MB. Max. memory is 16.1GB. [2024-10-31 22:03:39,860 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 121.6MB. Free memory is still 79.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-10-31 22:03:39,860 INFO L158 Benchmark]: CACSL2BoogieTranslator took 421.37ms. Allocated memory is still 121.6MB. Free memory was 92.1MB in the beginning and 74.3MB in the end (delta: 17.7MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2024-10-31 22:03:39,860 INFO L158 Benchmark]: Boogie Procedure Inliner took 73.27ms. Allocated memory is still 121.6MB. Free memory was 74.3MB in the beginning and 69.9MB in the end (delta: 4.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-10-31 22:03:39,861 INFO L158 Benchmark]: Boogie Preprocessor took 150.27ms. Allocated memory is still 121.6MB. Free memory was 69.9MB in the beginning and 64.5MB in the end (delta: 5.4MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-10-31 22:03:39,861 INFO L158 Benchmark]: RCFGBuilder took 1476.48ms. Allocated memory was 121.6MB in the beginning and 153.1MB in the end (delta: 31.5MB). Free memory was 64.5MB in the beginning and 109.6MB in the end (delta: -45.1MB). Peak memory consumption was 20.0MB. Max. memory is 16.1GB. [2024-10-31 22:03:39,862 INFO L158 Benchmark]: BuchiAutomizer took 14475.91ms. Allocated memory was 153.1MB in the beginning and 5.3GB in the end (delta: 5.1GB). Free memory was 109.6MB in the beginning and 4.7GB in the end (delta: -4.6GB). Peak memory consumption was 534.6MB. Max. memory is 16.1GB. [2024-10-31 22:03:39,862 INFO L158 Benchmark]: Witness Printer took 108.66ms. Allocated memory is still 5.3GB. Free memory was 4.7GB in the beginning and 4.7GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-10-31 22:03:39,864 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 121.6MB. Free memory is still 79.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 421.37ms. Allocated memory is still 121.6MB. Free memory was 92.1MB in the beginning and 74.3MB in the end (delta: 17.7MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 73.27ms. Allocated memory is still 121.6MB. Free memory was 74.3MB in the beginning and 69.9MB in the end (delta: 4.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 150.27ms. Allocated memory is still 121.6MB. Free memory was 69.9MB in the beginning and 64.5MB in the end (delta: 5.4MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 1476.48ms. Allocated memory was 121.6MB in the beginning and 153.1MB in the end (delta: 31.5MB). Free memory was 64.5MB in the beginning and 109.6MB in the end (delta: -45.1MB). Peak memory consumption was 20.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 14475.91ms. Allocated memory was 153.1MB in the beginning and 5.3GB in the end (delta: 5.1GB). Free memory was 109.6MB in the beginning and 4.7GB in the end (delta: -4.6GB). Peak memory consumption was 534.6MB. Max. memory is 16.1GB. * Witness Printer took 108.66ms. Allocated memory is still 5.3GB. Free memory was 4.7GB in the beginning and 4.7GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 26512 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 14.2s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 5.7s. Construction of modules took 1.1s. Büchi inclusion checks took 6.5s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 3.1s AutomataMinimizationTime, 23 MinimizatonAttempts, 5875 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 1.4s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 12540 SdHoareTripleChecker+Valid, 1.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 12540 mSDsluCounter, 28217 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 12383 mSDsCounter, 245 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 750 IncrementalHoareTripleChecker+Invalid, 995 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 245 mSolverCounterUnsat, 15834 mSDtfsCounter, 750 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 435]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 435]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-10-31 22:03:39,900 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfb2c6b9-9ebe-4f3d-aa24-25e9faba891f/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)