./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:04:19,702 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:04:19,792 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:04:19,800 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:04:19,800 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:04:19,838 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:04:19,840 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:04:19,841 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:04:19,841 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:04:19,842 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:04:19,843 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:04:19,843 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:04:19,844 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:04:19,846 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:04:19,847 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:04:19,847 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:04:19,847 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:04:19,848 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:04:19,848 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:04:19,848 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:04:19,849 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:04:19,853 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:04:19,853 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:04:19,853 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:04:19,854 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:04:19,854 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:04:19,854 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:04:19,854 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:04:19,855 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:04:19,866 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:04:19,866 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:04:19,866 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:04:19,867 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:04:19,867 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:04:19,867 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:04:19,868 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:04:19,868 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:04:19,868 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:04:19,869 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:04:19,869 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 [2024-10-31 22:04:20,201 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:04:20,230 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:04:20,234 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:04:20,236 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:04:20,236 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:04:20,238 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c Unable to find full path for "g++" [2024-10-31 22:04:22,412 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:04:22,744 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:04:22,745 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2024-10-31 22:04:22,766 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/data/1062f931e/2eceb0c9cfd3428483032bd23e901a54/FLAGc92d1d86e [2024-10-31 22:04:23,025 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/data/1062f931e/2eceb0c9cfd3428483032bd23e901a54 [2024-10-31 22:04:23,028 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:04:23,030 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:04:23,031 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:04:23,031 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:04:23,039 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:04:23,040 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,041 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3ed170be and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23, skipping insertion in model container [2024-10-31 22:04:23,044 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,108 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:04:23,462 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:04:23,482 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:04:23,570 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:04:23,602 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:04:23,602 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23 WrapperNode [2024-10-31 22:04:23,603 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:04:23,604 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:04:23,604 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:04:23,605 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:04:23,614 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,629 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,711 INFO L138 Inliner]: procedures = 38, calls = 47, calls flagged for inlining = 42, calls inlined = 95, statements flattened = 1354 [2024-10-31 22:04:23,712 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:04:23,713 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:04:23,713 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:04:23,713 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:04:23,734 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,734 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,744 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,787 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:04:23,787 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,788 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,811 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,828 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,831 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,836 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,849 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:04:23,854 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:04:23,855 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:04:23,855 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:04:23,856 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (1/1) ... [2024-10-31 22:04:23,870 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:23,893 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:23,919 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:23,922 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:04:23,959 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:04:23,959 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:04:23,960 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:04:23,960 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:04:24,087 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:04:24,090 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:04:25,543 INFO L? ?]: Removed 252 outVars from TransFormulas that were not future-live. [2024-10-31 22:04:25,544 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:04:25,585 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:04:25,585 INFO L316 CfgBuilder]: Removed 8 assume(true) statements. [2024-10-31 22:04:25,586 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:04:25 BoogieIcfgContainer [2024-10-31 22:04:25,586 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:04:25,587 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:04:25,587 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:04:25,590 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:04:25,591 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:04:25,591 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:04:23" (1/3) ... [2024-10-31 22:04:25,592 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@768ba8f5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:04:25, skipping insertion in model container [2024-10-31 22:04:25,592 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:04:25,592 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:23" (2/3) ... [2024-10-31 22:04:25,593 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@768ba8f5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:04:25, skipping insertion in model container [2024-10-31 22:04:25,593 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:04:25,593 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:04:25" (3/3) ... [2024-10-31 22:04:25,595 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2024-10-31 22:04:25,664 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:04:25,664 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:04:25,664 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:04:25,664 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:04:25,664 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:04:25,665 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:04:25,665 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:04:25,665 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:04:25,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.521505376344086) internal successors, (849), 558 states have internal predecessors, (849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:25,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2024-10-31 22:04:25,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:25,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:25,730 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:25,730 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:25,730 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:04:25,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.521505376344086) internal successors, (849), 558 states have internal predecessors, (849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:25,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2024-10-31 22:04:25,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:25,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:25,766 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:25,767 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:25,775 INFO L745 eck$LassoCheckResult]: Stem: 172#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 464#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 267#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 460#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 551#L414true assume !(1 == ~m_i~0);~m_st~0 := 2; 222#L414-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 415#L419-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 414#L424-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 203#L429-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 406#L434-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 467#L439-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 201#L599true assume 0 == ~M_E~0;~M_E~0 := 1; 360#L599-2true assume !(0 == ~T1_E~0); 10#L604-1true assume !(0 == ~T2_E~0); 5#L609-1true assume !(0 == ~T3_E~0); 83#L614-1true assume !(0 == ~T4_E~0); 155#L619-1true assume !(0 == ~T5_E~0); 226#L624-1true assume !(0 == ~E_M~0); 506#L629-1true assume !(0 == ~E_1~0); 47#L634-1true assume 0 == ~E_2~0;~E_2~0 := 1; 327#L639-1true assume !(0 == ~E_3~0); 400#L644-1true assume !(0 == ~E_4~0); 351#L649-1true assume !(0 == ~E_5~0); 31#L654-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90#L292true assume !(1 == ~m_pc~0); 184#L292-2true is_master_triggered_~__retres1~0#1 := 0; 260#L303true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 486#L743true assume !(0 != activate_threads_~tmp~1#1); 62#L743-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 326#L311true assume 1 == ~t1_pc~0; 140#L312true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 231#L322true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19#L751true assume !(0 != activate_threads_~tmp___0~0#1); 427#L751-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329#L330true assume 1 == ~t2_pc~0; 157#L331true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 91#L341true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 454#L759true assume !(0 != activate_threads_~tmp___1~0#1); 468#L759-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84#L349true assume !(1 == ~t3_pc~0); 510#L349-2true is_transmit3_triggered_~__retres1~3#1 := 0; 298#L360true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 537#L767true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 444#L767-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 538#L368true assume 1 == ~t4_pc~0; 456#L369true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 388#L379true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 435#L775true assume !(0 != activate_threads_~tmp___3~0#1); 12#L775-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475#L387true assume !(1 == ~t5_pc~0); 242#L387-2true is_transmit5_triggered_~__retres1~5#1 := 0; 546#L398true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70#L783true assume !(0 != activate_threads_~tmp___4~0#1); 123#L783-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178#L667true assume !(1 == ~M_E~0); 335#L667-2true assume !(1 == ~T1_E~0); 342#L672-1true assume !(1 == ~T2_E~0); 147#L677-1true assume !(1 == ~T3_E~0); 309#L682-1true assume !(1 == ~T4_E~0); 402#L687-1true assume !(1 == ~T5_E~0); 469#L692-1true assume !(1 == ~E_M~0); 297#L697-1true assume 1 == ~E_1~0;~E_1~0 := 2; 527#L702-1true assume !(1 == ~E_2~0); 350#L707-1true assume !(1 == ~E_3~0); 215#L712-1true assume !(1 == ~E_4~0); 334#L717-1true assume !(1 == ~E_5~0); 316#L722-1true assume { :end_inline_reset_delta_events } true; 16#L928-2true [2024-10-31 22:04:25,777 INFO L747 eck$LassoCheckResult]: Loop: 16#L928-2true assume !false; 218#L929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 141#L574-1true assume !true; 85#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 398#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 257#L599-3true assume 0 == ~M_E~0;~M_E~0 := 1; 308#L599-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 190#L604-3true assume !(0 == ~T2_E~0); 515#L609-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 246#L614-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 20#L619-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 255#L624-3true assume 0 == ~E_M~0;~E_M~0 := 1; 305#L629-3true assume 0 == ~E_1~0;~E_1~0 := 1; 397#L634-3true assume 0 == ~E_2~0;~E_2~0 := 1; 317#L639-3true assume 0 == ~E_3~0;~E_3~0 := 1; 447#L644-3true assume !(0 == ~E_4~0); 517#L649-3true assume 0 == ~E_5~0;~E_5~0 := 1; 196#L654-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295#L292-21true assume 1 == ~m_pc~0; 262#L293-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53#L303-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106#is_master_triggered_returnLabel#8true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 428#L743-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 187#L743-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399#L311-21true assume !(1 == ~t1_pc~0); 136#L311-23true is_transmit1_triggered_~__retres1~1#1 := 0; 35#L322-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 465#L751-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89#L751-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282#L330-21true assume 1 == ~t2_pc~0; 480#L331-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 252#L341-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 272#L759-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58#L759-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213#L349-21true assume !(1 == ~t3_pc~0); 369#L349-23true is_transmit3_triggered_~__retres1~3#1 := 0; 385#L360-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 477#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 321#L767-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 452#L767-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101#L368-21true assume 1 == ~t4_pc~0; 42#L369-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 383#L379-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 438#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 362#L775-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8#L775-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37#L387-21true assume 1 == ~t5_pc~0; 241#L388-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 338#L398-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 248#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393#L783-21true assume !(0 != activate_threads_~tmp___4~0#1); 55#L783-23true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186#L667-3true assume 1 == ~M_E~0;~M_E~0 := 2; 49#L667-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 331#L672-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 88#L677-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 556#L682-3true assume !(1 == ~T4_E~0); 380#L687-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 114#L692-3true assume 1 == ~E_M~0;~E_M~0 := 2; 497#L697-3true assume 1 == ~E_1~0;~E_1~0 := 2; 165#L702-3true assume 1 == ~E_2~0;~E_2~0 := 2; 261#L707-3true assume 1 == ~E_3~0;~E_3~0 := 2; 294#L712-3true assume 1 == ~E_4~0;~E_4~0 := 2; 52#L717-3true assume 1 == ~E_5~0;~E_5~0 := 2; 287#L722-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 451#L452-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 387#L484-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 238#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 192#L947true assume !(0 == start_simulation_~tmp~3#1); 528#L947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 195#L452-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 323#L484-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 378#L902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 333#L909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 419#stop_simulation_returnLabel#1true start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 278#L960true assume !(0 != start_simulation_~tmp___0~1#1); 16#L928-2true [2024-10-31 22:04:25,783 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:25,784 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2024-10-31 22:04:25,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:25,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555598817] [2024-10-31 22:04:25,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:25,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:25,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:26,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:26,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:26,204 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555598817] [2024-10-31 22:04:26,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555598817] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:26,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:26,206 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:26,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293424886] [2024-10-31 22:04:26,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:26,212 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:26,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:26,213 INFO L85 PathProgramCache]: Analyzing trace with hash 1012277568, now seen corresponding path program 1 times [2024-10-31 22:04:26,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:26,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507214169] [2024-10-31 22:04:26,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:26,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:26,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:26,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:26,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:26,300 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507214169] [2024-10-31 22:04:26,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1507214169] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:26,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:26,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:26,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153989854] [2024-10-31 22:04:26,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:26,302 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:26,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:26,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:26,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:26,360 INFO L87 Difference]: Start difference. First operand has 559 states, 558 states have (on average 1.521505376344086) internal successors, (849), 558 states have internal predecessors, (849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:26,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:26,451 INFO L93 Difference]: Finished difference Result 557 states and 829 transitions. [2024-10-31 22:04:26,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 829 transitions. [2024-10-31 22:04:26,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:26,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 552 states and 824 transitions. [2024-10-31 22:04:26,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2024-10-31 22:04:26,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2024-10-31 22:04:26,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 824 transitions. [2024-10-31 22:04:26,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:26,488 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 824 transitions. [2024-10-31 22:04:26,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 824 transitions. [2024-10-31 22:04:26,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2024-10-31 22:04:26,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4927536231884058) internal successors, (824), 551 states have internal predecessors, (824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:26,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 824 transitions. [2024-10-31 22:04:26,558 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 824 transitions. [2024-10-31 22:04:26,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:26,568 INFO L425 stractBuchiCegarLoop]: Abstraction has 552 states and 824 transitions. [2024-10-31 22:04:26,568 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:04:26,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 824 transitions. [2024-10-31 22:04:26,576 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:26,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:26,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:26,579 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:26,580 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:26,580 INFO L745 eck$LassoCheckResult]: Stem: 1434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1666#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 1504#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1505#L419-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1650#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1479#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1480#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1646#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1477#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 1478#L599-2 assume !(0 == ~T1_E~0); 1142#L604-1 assume !(0 == ~T2_E~0); 1131#L609-1 assume !(0 == ~T3_E~0); 1132#L614-1 assume !(0 == ~T4_E~0); 1299#L619-1 assume !(0 == ~T5_E~0); 1413#L624-1 assume !(0 == ~E_M~0); 1508#L629-1 assume !(0 == ~E_1~0); 1221#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1222#L639-1 assume !(0 == ~E_3~0); 1609#L644-1 assume !(0 == ~E_4~0); 1624#L649-1 assume !(0 == ~E_5~0); 1185#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1186#L292 assume !(1 == ~m_pc~0); 1312#L292-2 is_master_triggered_~__retres1~0#1 := 0; 1450#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1409#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1410#L743 assume !(0 != activate_threads_~tmp~1#1); 1254#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1255#L311 assume 1 == ~t1_pc~0; 1386#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1387#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1179#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1158#L751 assume !(0 != activate_threads_~tmp___0~0#1); 1159#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1610#L330 assume 1 == ~t2_pc~0; 1415#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1314#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1315#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1559#L759 assume !(0 != activate_threads_~tmp___1~0#1); 1664#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1300#L349 assume !(1 == ~t3_pc~0); 1301#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1350#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1133#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1134#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1659#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1660#L368 assume 1 == ~t4_pc~0; 1665#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1377#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1285#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1286#L775 assume !(0 != activate_threads_~tmp___3~0#1); 1145#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1146#L387 assume !(1 == ~t5_pc~0); 1525#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1526#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1418#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1271#L783 assume !(0 != activate_threads_~tmp___4~0#1); 1272#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1365#L667 assume !(1 == ~M_E~0); 1442#L667-2 assume !(1 == ~T1_E~0); 1616#L672-1 assume !(1 == ~T2_E~0); 1400#L677-1 assume !(1 == ~T3_E~0); 1401#L682-1 assume !(1 == ~T4_E~0); 1593#L687-1 assume !(1 == ~T5_E~0); 1643#L692-1 assume !(1 == ~E_M~0); 1583#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1584#L702-1 assume !(1 == ~E_2~0); 1623#L707-1 assume !(1 == ~E_3~0); 1496#L712-1 assume !(1 == ~E_4~0); 1497#L717-1 assume !(1 == ~E_5~0); 1600#L722-1 assume { :end_inline_reset_delta_events } true; 1153#L928-2 [2024-10-31 22:04:26,581 INFO L747 eck$LassoCheckResult]: Loop: 1153#L928-2 assume !false; 1154#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1389#L574-1 assume !false; 1390#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1658#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1353#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1189#L499 assume !(0 != eval_~tmp~0#1); 1190#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1303#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1548#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1549#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1459#L604-3 assume !(0 == ~T2_E~0); 1460#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1534#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1160#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1161#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1543#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1590#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1601#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1602#L644-3 assume !(0 == ~E_4~0); 1662#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1469#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1470#L292-21 assume !(1 == ~m_pc~0); 1369#L292-23 is_master_triggered_~__retres1~0#1 := 0; 1236#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1237#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1339#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1453#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1454#L311-21 assume !(1 == ~t1_pc~0); 1381#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 1193#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1194#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1262#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1310#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1311#L330-21 assume !(1 == ~t2_pc~0); 1571#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1540#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1448#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1449#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1246#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1247#L349-21 assume 1 == ~t3_pc~0; 1493#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1633#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1638#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1604#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1605#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1329#L368-21 assume 1 == ~t4_pc~0; 1210#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1211#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1637#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1627#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1138#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1139#L387-21 assume !(1 == ~t5_pc~0); 1198#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 1524#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1532#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1533#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 1238#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1239#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1223#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1224#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1306#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1307#L682-3 assume !(1 == ~T4_E~0); 1636#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1348#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1349#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1423#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1424#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1550#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1230#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1231#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1575#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1168#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1521#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1462#L947 assume !(0 == start_simulation_~tmp~3#1); 1463#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1466#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1427#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1177#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 1178#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1614#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1615#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1563#L960 assume !(0 != start_simulation_~tmp___0~1#1); 1153#L928-2 [2024-10-31 22:04:26,582 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:26,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2024-10-31 22:04:26,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:26,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940245865] [2024-10-31 22:04:26,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:26,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:26,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:26,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:26,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:26,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940245865] [2024-10-31 22:04:26,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940245865] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:26,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:26,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:26,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [432989036] [2024-10-31 22:04:26,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:26,682 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:26,683 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:26,683 INFO L85 PathProgramCache]: Analyzing trace with hash -1923800974, now seen corresponding path program 1 times [2024-10-31 22:04:26,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:26,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781497474] [2024-10-31 22:04:26,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:26,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:26,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:26,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:26,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:26,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781497474] [2024-10-31 22:04:26,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1781497474] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:26,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:26,796 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:26,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620667087] [2024-10-31 22:04:26,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:26,797 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:26,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:26,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:26,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:26,798 INFO L87 Difference]: Start difference. First operand 552 states and 824 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:26,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:26,818 INFO L93 Difference]: Finished difference Result 552 states and 823 transitions. [2024-10-31 22:04:26,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 823 transitions. [2024-10-31 22:04:26,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:26,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 823 transitions. [2024-10-31 22:04:26,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2024-10-31 22:04:26,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2024-10-31 22:04:26,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 823 transitions. [2024-10-31 22:04:26,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:26,830 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 823 transitions. [2024-10-31 22:04:26,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 823 transitions. [2024-10-31 22:04:26,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2024-10-31 22:04:26,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4909420289855073) internal successors, (823), 551 states have internal predecessors, (823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:26,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 823 transitions. [2024-10-31 22:04:26,853 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 823 transitions. [2024-10-31 22:04:26,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:26,856 INFO L425 stractBuchiCegarLoop]: Abstraction has 552 states and 823 transitions. [2024-10-31 22:04:26,857 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:04:26,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 823 transitions. [2024-10-31 22:04:26,861 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:26,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:26,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:26,865 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:26,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:26,866 INFO L745 eck$LassoCheckResult]: Stem: 2545#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2665#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2666#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2777#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 2615#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2616#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2761#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2590#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2591#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2757#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2588#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 2589#L599-2 assume !(0 == ~T1_E~0); 2255#L604-1 assume !(0 == ~T2_E~0); 2242#L609-1 assume !(0 == ~T3_E~0); 2243#L614-1 assume !(0 == ~T4_E~0); 2410#L619-1 assume !(0 == ~T5_E~0); 2524#L624-1 assume !(0 == ~E_M~0); 2619#L629-1 assume !(0 == ~E_1~0); 2332#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2333#L639-1 assume !(0 == ~E_3~0); 2720#L644-1 assume !(0 == ~E_4~0); 2735#L649-1 assume !(0 == ~E_5~0); 2296#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2297#L292 assume !(1 == ~m_pc~0); 2423#L292-2 is_master_triggered_~__retres1~0#1 := 0; 2561#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2520#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2521#L743 assume !(0 != activate_threads_~tmp~1#1); 2365#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2366#L311 assume 1 == ~t1_pc~0; 2497#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2498#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2290#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2269#L751 assume !(0 != activate_threads_~tmp___0~0#1); 2270#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2721#L330 assume 1 == ~t2_pc~0; 2526#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2425#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2426#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2670#L759 assume !(0 != activate_threads_~tmp___1~0#1); 2775#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2411#L349 assume !(1 == ~t3_pc~0); 2412#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2461#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2246#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2247#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2770#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2771#L368 assume 1 == ~t4_pc~0; 2776#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2488#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2397#L775 assume !(0 != activate_threads_~tmp___3~0#1); 2256#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2257#L387 assume !(1 == ~t5_pc~0); 2636#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2637#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2529#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2382#L783 assume !(0 != activate_threads_~tmp___4~0#1); 2383#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2478#L667 assume !(1 == ~M_E~0); 2553#L667-2 assume !(1 == ~T1_E~0); 2727#L672-1 assume !(1 == ~T2_E~0); 2511#L677-1 assume !(1 == ~T3_E~0); 2512#L682-1 assume !(1 == ~T4_E~0); 2704#L687-1 assume !(1 == ~T5_E~0); 2754#L692-1 assume !(1 == ~E_M~0); 2694#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2695#L702-1 assume !(1 == ~E_2~0); 2734#L707-1 assume !(1 == ~E_3~0); 2607#L712-1 assume !(1 == ~E_4~0); 2608#L717-1 assume !(1 == ~E_5~0); 2711#L722-1 assume { :end_inline_reset_delta_events } true; 2264#L928-2 [2024-10-31 22:04:26,866 INFO L747 eck$LassoCheckResult]: Loop: 2264#L928-2 assume !false; 2265#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2500#L574-1 assume !false; 2501#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2769#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2464#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2687#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2300#L499 assume !(0 != eval_~tmp~0#1); 2301#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2414#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2659#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2660#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2570#L604-3 assume !(0 == ~T2_E~0); 2571#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2645#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2271#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2272#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2654#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2701#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2712#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2713#L644-3 assume !(0 == ~E_4~0); 2773#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2580#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2581#L292-21 assume !(1 == ~m_pc~0); 2480#L292-23 is_master_triggered_~__retres1~0#1 := 0; 2347#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2348#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2450#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2564#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2565#L311-21 assume 1 == ~t1_pc~0; 2753#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2304#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2305#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2373#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2421#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2422#L330-21 assume !(1 == ~t2_pc~0); 2682#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 2651#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2559#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2560#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2359#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2360#L349-21 assume 1 == ~t3_pc~0; 2604#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2743#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2749#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2715#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2716#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2440#L368-21 assume 1 == ~t4_pc~0; 2321#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2322#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2748#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2738#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2244#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2245#L387-21 assume !(1 == ~t5_pc~0); 2309#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 2635#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2643#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2644#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 2349#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2350#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2334#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2335#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2417#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2418#L682-3 assume !(1 == ~T4_E~0); 2747#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2459#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2460#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2534#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2535#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2661#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2343#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2344#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2686#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2279#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2632#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2573#L947 assume !(0 == start_simulation_~tmp~3#1); 2574#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2577#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2538#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 2289#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2725#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2726#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2674#L960 assume !(0 != start_simulation_~tmp___0~1#1); 2264#L928-2 [2024-10-31 22:04:26,867 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:26,867 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2024-10-31 22:04:26,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:26,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498364703] [2024-10-31 22:04:26,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:26,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:26,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:26,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:26,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:26,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498364703] [2024-10-31 22:04:26,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498364703] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:26,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:26,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:26,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [558552218] [2024-10-31 22:04:26,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:26,937 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:26,938 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:26,938 INFO L85 PathProgramCache]: Analyzing trace with hash -815672335, now seen corresponding path program 1 times [2024-10-31 22:04:26,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:26,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560583852] [2024-10-31 22:04:26,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:26,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:26,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:27,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:27,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:27,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1560583852] [2024-10-31 22:04:27,038 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1560583852] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:27,038 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:27,038 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:27,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016970396] [2024-10-31 22:04:27,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:27,039 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:27,039 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:27,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:27,040 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:27,040 INFO L87 Difference]: Start difference. First operand 552 states and 823 transitions. cyclomatic complexity: 272 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:27,059 INFO L93 Difference]: Finished difference Result 552 states and 822 transitions. [2024-10-31 22:04:27,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 822 transitions. [2024-10-31 22:04:27,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:27,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 822 transitions. [2024-10-31 22:04:27,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2024-10-31 22:04:27,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2024-10-31 22:04:27,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 822 transitions. [2024-10-31 22:04:27,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:27,071 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 822 transitions. [2024-10-31 22:04:27,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 822 transitions. [2024-10-31 22:04:27,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2024-10-31 22:04:27,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4891304347826086) internal successors, (822), 551 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 822 transitions. [2024-10-31 22:04:27,094 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 822 transitions. [2024-10-31 22:04:27,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:27,095 INFO L425 stractBuchiCegarLoop]: Abstraction has 552 states and 822 transitions. [2024-10-31 22:04:27,095 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:04:27,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 822 transitions. [2024-10-31 22:04:27,101 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:27,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:27,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:27,104 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:27,105 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:27,107 INFO L745 eck$LassoCheckResult]: Stem: 3656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3776#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3777#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3888#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 3726#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3727#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3872#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3703#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3704#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3868#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3699#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 3700#L599-2 assume !(0 == ~T1_E~0); 3366#L604-1 assume !(0 == ~T2_E~0); 3353#L609-1 assume !(0 == ~T3_E~0); 3354#L614-1 assume !(0 == ~T4_E~0); 3521#L619-1 assume !(0 == ~T5_E~0); 3635#L624-1 assume !(0 == ~E_M~0); 3730#L629-1 assume !(0 == ~E_1~0); 3443#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3444#L639-1 assume !(0 == ~E_3~0); 3831#L644-1 assume !(0 == ~E_4~0); 3846#L649-1 assume !(0 == ~E_5~0); 3407#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3408#L292 assume !(1 == ~m_pc~0); 3534#L292-2 is_master_triggered_~__retres1~0#1 := 0; 3672#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3631#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3632#L743 assume !(0 != activate_threads_~tmp~1#1); 3476#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3477#L311 assume 1 == ~t1_pc~0; 3608#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3609#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3401#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3380#L751 assume !(0 != activate_threads_~tmp___0~0#1); 3381#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3832#L330 assume 1 == ~t2_pc~0; 3637#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3536#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3537#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3781#L759 assume !(0 != activate_threads_~tmp___1~0#1); 3886#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3522#L349 assume !(1 == ~t3_pc~0); 3523#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3572#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3360#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3361#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3881#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3882#L368 assume 1 == ~t4_pc~0; 3887#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3599#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3507#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3508#L775 assume !(0 != activate_threads_~tmp___3~0#1); 3367#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3368#L387 assume !(1 == ~t5_pc~0); 3747#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3748#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3496#L783 assume !(0 != activate_threads_~tmp___4~0#1); 3497#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3589#L667 assume !(1 == ~M_E~0); 3664#L667-2 assume !(1 == ~T1_E~0); 3839#L672-1 assume !(1 == ~T2_E~0); 3622#L677-1 assume !(1 == ~T3_E~0); 3623#L682-1 assume !(1 == ~T4_E~0); 3815#L687-1 assume !(1 == ~T5_E~0); 3865#L692-1 assume !(1 == ~E_M~0); 3805#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3806#L702-1 assume !(1 == ~E_2~0); 3845#L707-1 assume !(1 == ~E_3~0); 3718#L712-1 assume !(1 == ~E_4~0); 3719#L717-1 assume !(1 == ~E_5~0); 3822#L722-1 assume { :end_inline_reset_delta_events } true; 3375#L928-2 [2024-10-31 22:04:27,108 INFO L747 eck$LassoCheckResult]: Loop: 3375#L928-2 assume !false; 3376#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3611#L574-1 assume !false; 3612#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3880#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3575#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3798#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3411#L499 assume !(0 != eval_~tmp~0#1); 3412#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3525#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3770#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3771#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3681#L604-3 assume !(0 == ~T2_E~0); 3682#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3757#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3382#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3383#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3765#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3812#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3823#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3824#L644-3 assume !(0 == ~E_4~0); 3884#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3691#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3692#L292-21 assume !(1 == ~m_pc~0); 3591#L292-23 is_master_triggered_~__retres1~0#1 := 0; 3458#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3459#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3561#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3675#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3676#L311-21 assume !(1 == ~t1_pc~0); 3602#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 3415#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3416#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3484#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3532#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3533#L330-21 assume 1 == ~t2_pc~0; 3792#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3762#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3669#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3670#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3465#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3466#L349-21 assume 1 == ~t3_pc~0; 3715#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3854#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3860#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3826#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3827#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3551#L368-21 assume 1 == ~t4_pc~0; 3432#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3433#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3859#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3849#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3358#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3359#L387-21 assume !(1 == ~t5_pc~0); 3420#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 3746#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3755#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3756#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 3460#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3461#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3448#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3449#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3528#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3529#L682-3 assume !(1 == ~T4_E~0); 3858#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3570#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3571#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3645#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3646#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3772#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3454#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3455#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3797#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3390#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3743#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3684#L947 assume !(0 == start_simulation_~tmp~3#1); 3685#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3688#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3649#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3399#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 3400#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3836#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3837#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3785#L960 assume !(0 != start_simulation_~tmp___0~1#1); 3375#L928-2 [2024-10-31 22:04:27,109 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:27,111 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2024-10-31 22:04:27,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:27,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182330231] [2024-10-31 22:04:27,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:27,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:27,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:27,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:27,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:27,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182330231] [2024-10-31 22:04:27,187 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [182330231] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:27,187 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:27,187 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:27,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708329146] [2024-10-31 22:04:27,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:27,188 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:27,188 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:27,189 INFO L85 PathProgramCache]: Analyzing trace with hash 902962993, now seen corresponding path program 1 times [2024-10-31 22:04:27,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:27,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853745898] [2024-10-31 22:04:27,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:27,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:27,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:27,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:27,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:27,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853745898] [2024-10-31 22:04:27,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [853745898] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:27,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:27,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:27,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1659106298] [2024-10-31 22:04:27,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:27,291 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:27,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:27,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:27,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:27,292 INFO L87 Difference]: Start difference. First operand 552 states and 822 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:27,312 INFO L93 Difference]: Finished difference Result 552 states and 821 transitions. [2024-10-31 22:04:27,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 821 transitions. [2024-10-31 22:04:27,316 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:27,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 821 transitions. [2024-10-31 22:04:27,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2024-10-31 22:04:27,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2024-10-31 22:04:27,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 821 transitions. [2024-10-31 22:04:27,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:27,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 821 transitions. [2024-10-31 22:04:27,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 821 transitions. [2024-10-31 22:04:27,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2024-10-31 22:04:27,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4873188405797102) internal successors, (821), 551 states have internal predecessors, (821), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 821 transitions. [2024-10-31 22:04:27,341 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 821 transitions. [2024-10-31 22:04:27,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:27,343 INFO L425 stractBuchiCegarLoop]: Abstraction has 552 states and 821 transitions. [2024-10-31 22:04:27,343 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:04:27,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 821 transitions. [2024-10-31 22:04:27,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:27,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:27,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:27,349 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:27,349 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:27,350 INFO L745 eck$LassoCheckResult]: Stem: 4767#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4887#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4888#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4999#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 4837#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4838#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4983#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4814#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4815#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4979#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4810#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 4811#L599-2 assume !(0 == ~T1_E~0); 4477#L604-1 assume !(0 == ~T2_E~0); 4464#L609-1 assume !(0 == ~T3_E~0); 4465#L614-1 assume !(0 == ~T4_E~0); 4632#L619-1 assume !(0 == ~T5_E~0); 4746#L624-1 assume !(0 == ~E_M~0); 4841#L629-1 assume !(0 == ~E_1~0); 4554#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4555#L639-1 assume !(0 == ~E_3~0); 4942#L644-1 assume !(0 == ~E_4~0); 4957#L649-1 assume !(0 == ~E_5~0); 4518#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4519#L292 assume !(1 == ~m_pc~0); 4645#L292-2 is_master_triggered_~__retres1~0#1 := 0; 4783#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4744#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4745#L743 assume !(0 != activate_threads_~tmp~1#1); 4587#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4588#L311 assume 1 == ~t1_pc~0; 4719#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4720#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4512#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4491#L751 assume !(0 != activate_threads_~tmp___0~0#1); 4492#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4943#L330 assume 1 == ~t2_pc~0; 4748#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4647#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4648#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4892#L759 assume !(0 != activate_threads_~tmp___1~0#1); 4997#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4633#L349 assume !(1 == ~t3_pc~0); 4634#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4683#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4471#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4472#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4992#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4993#L368 assume 1 == ~t4_pc~0; 4998#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4712#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4618#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4619#L775 assume !(0 != activate_threads_~tmp___3~0#1); 4478#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4479#L387 assume !(1 == ~t5_pc~0); 4858#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4859#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4751#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4607#L783 assume !(0 != activate_threads_~tmp___4~0#1); 4608#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4700#L667 assume !(1 == ~M_E~0); 4775#L667-2 assume !(1 == ~T1_E~0); 4950#L672-1 assume !(1 == ~T2_E~0); 4733#L677-1 assume !(1 == ~T3_E~0); 4734#L682-1 assume !(1 == ~T4_E~0); 4926#L687-1 assume !(1 == ~T5_E~0); 4976#L692-1 assume !(1 == ~E_M~0); 4916#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4917#L702-1 assume !(1 == ~E_2~0); 4956#L707-1 assume !(1 == ~E_3~0); 4829#L712-1 assume !(1 == ~E_4~0); 4830#L717-1 assume !(1 == ~E_5~0); 4933#L722-1 assume { :end_inline_reset_delta_events } true; 4486#L928-2 [2024-10-31 22:04:27,350 INFO L747 eck$LassoCheckResult]: Loop: 4486#L928-2 assume !false; 4487#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4722#L574-1 assume !false; 4723#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4991#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4686#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4909#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4522#L499 assume !(0 != eval_~tmp~0#1); 4523#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4636#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4881#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4882#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4793#L604-3 assume !(0 == ~T2_E~0); 4794#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4868#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4493#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4494#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4876#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4923#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4934#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4935#L644-3 assume !(0 == ~E_4~0); 4995#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4802#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4803#L292-21 assume 1 == ~m_pc~0; 4884#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4569#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4570#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4670#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4786#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4787#L311-21 assume !(1 == ~t1_pc~0); 4713#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 4526#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4527#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4595#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4643#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4644#L330-21 assume !(1 == ~t2_pc~0); 4903#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 4873#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4781#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4782#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4576#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4577#L349-21 assume 1 == ~t3_pc~0; 4826#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4965#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4971#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4937#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4938#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4662#L368-21 assume !(1 == ~t4_pc~0); 4545#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4544#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4970#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4960#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4469#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4470#L387-21 assume !(1 == ~t5_pc~0); 4531#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4857#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4866#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4867#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 4571#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4572#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4559#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4560#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4639#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4640#L682-3 assume !(1 == ~T4_E~0); 4969#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4681#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4682#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4756#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4757#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4883#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4565#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4566#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4908#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4501#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4854#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4795#L947 assume !(0 == start_simulation_~tmp~3#1); 4796#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4799#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4760#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4510#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 4511#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4947#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4948#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4896#L960 assume !(0 != start_simulation_~tmp___0~1#1); 4486#L928-2 [2024-10-31 22:04:27,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:27,351 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2024-10-31 22:04:27,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:27,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935436215] [2024-10-31 22:04:27,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:27,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:27,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:27,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:27,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:27,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935436215] [2024-10-31 22:04:27,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935436215] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:27,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:27,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:27,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479111614] [2024-10-31 22:04:27,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:27,413 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:27,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:27,414 INFO L85 PathProgramCache]: Analyzing trace with hash -1827073166, now seen corresponding path program 1 times [2024-10-31 22:04:27,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:27,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833084601] [2024-10-31 22:04:27,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:27,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:27,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:27,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:27,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:27,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833084601] [2024-10-31 22:04:27,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833084601] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:27,487 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:27,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:27,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747152672] [2024-10-31 22:04:27,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:27,488 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:27,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:27,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:27,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:27,489 INFO L87 Difference]: Start difference. First operand 552 states and 821 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:27,506 INFO L93 Difference]: Finished difference Result 552 states and 820 transitions. [2024-10-31 22:04:27,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 820 transitions. [2024-10-31 22:04:27,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:27,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 820 transitions. [2024-10-31 22:04:27,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2024-10-31 22:04:27,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2024-10-31 22:04:27,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 820 transitions. [2024-10-31 22:04:27,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:27,515 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 820 transitions. [2024-10-31 22:04:27,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 820 transitions. [2024-10-31 22:04:27,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2024-10-31 22:04:27,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4855072463768115) internal successors, (820), 551 states have internal predecessors, (820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 820 transitions. [2024-10-31 22:04:27,527 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 820 transitions. [2024-10-31 22:04:27,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:27,529 INFO L425 stractBuchiCegarLoop]: Abstraction has 552 states and 820 transitions. [2024-10-31 22:04:27,530 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:04:27,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 820 transitions. [2024-10-31 22:04:27,533 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2024-10-31 22:04:27,533 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:27,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:27,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:27,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:27,536 INFO L745 eck$LassoCheckResult]: Stem: 5879#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5998#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5999#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6110#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 5948#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5949#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6094#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5925#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5926#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6090#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5921#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 5922#L599-2 assume !(0 == ~T1_E~0); 5588#L604-1 assume !(0 == ~T2_E~0); 5575#L609-1 assume !(0 == ~T3_E~0); 5576#L614-1 assume !(0 == ~T4_E~0); 5743#L619-1 assume !(0 == ~T5_E~0); 5857#L624-1 assume !(0 == ~E_M~0); 5952#L629-1 assume !(0 == ~E_1~0); 5665#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5666#L639-1 assume !(0 == ~E_3~0); 6053#L644-1 assume !(0 == ~E_4~0); 6068#L649-1 assume !(0 == ~E_5~0); 5629#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5630#L292 assume !(1 == ~m_pc~0); 5756#L292-2 is_master_triggered_~__retres1~0#1 := 0; 5894#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5855#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5856#L743 assume !(0 != activate_threads_~tmp~1#1); 5698#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5699#L311 assume 1 == ~t1_pc~0; 5830#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5831#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5623#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5602#L751 assume !(0 != activate_threads_~tmp___0~0#1); 5603#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6056#L330 assume 1 == ~t2_pc~0; 5859#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5759#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5760#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6003#L759 assume !(0 != activate_threads_~tmp___1~0#1); 6108#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5744#L349 assume !(1 == ~t3_pc~0); 5745#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5794#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5582#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5583#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6103#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6104#L368 assume 1 == ~t4_pc~0; 6109#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5823#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5729#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5730#L775 assume !(0 != activate_threads_~tmp___3~0#1); 5589#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5590#L387 assume !(1 == ~t5_pc~0); 5969#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5970#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5862#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5718#L783 assume !(0 != activate_threads_~tmp___4~0#1); 5719#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5811#L667 assume !(1 == ~M_E~0); 5886#L667-2 assume !(1 == ~T1_E~0); 6061#L672-1 assume !(1 == ~T2_E~0); 5844#L677-1 assume !(1 == ~T3_E~0); 5845#L682-1 assume !(1 == ~T4_E~0); 6037#L687-1 assume !(1 == ~T5_E~0); 6087#L692-1 assume !(1 == ~E_M~0); 6027#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6028#L702-1 assume !(1 == ~E_2~0); 6067#L707-1 assume !(1 == ~E_3~0); 5940#L712-1 assume !(1 == ~E_4~0); 5941#L717-1 assume !(1 == ~E_5~0); 6044#L722-1 assume { :end_inline_reset_delta_events } true; 5597#L928-2 [2024-10-31 22:04:27,537 INFO L747 eck$LassoCheckResult]: Loop: 5597#L928-2 assume !false; 5598#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5833#L574-1 assume !false; 5834#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6102#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5797#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6020#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5633#L499 assume !(0 != eval_~tmp~0#1); 5634#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5992#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5993#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5903#L604-3 assume !(0 == ~T2_E~0); 5904#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5976#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5604#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5605#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5987#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6034#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6045#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6046#L644-3 assume !(0 == ~E_4~0); 6106#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5913#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5914#L292-21 assume !(1 == ~m_pc~0); 5813#L292-23 is_master_triggered_~__retres1~0#1 := 0; 5680#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5681#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5781#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5897#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5898#L311-21 assume !(1 == ~t1_pc~0); 5825#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 5637#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5638#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5706#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5754#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5755#L330-21 assume !(1 == ~t2_pc~0); 6014#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 5984#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5892#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5893#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5690#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5691#L349-21 assume 1 == ~t3_pc~0; 5937#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6077#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6082#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6048#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6049#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5773#L368-21 assume 1 == ~t4_pc~0; 5654#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5655#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6081#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6071#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5580#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5581#L387-21 assume !(1 == ~t5_pc~0); 5642#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5968#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5978#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5979#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 5682#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5683#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5670#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5671#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5752#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5753#L682-3 assume !(1 == ~T4_E~0); 6080#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5792#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5793#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5867#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5868#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5994#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5676#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5677#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6019#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5612#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5965#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5906#L947 assume !(0 == start_simulation_~tmp~3#1); 5907#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5910#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5871#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5621#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 5622#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6058#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6059#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6008#L960 assume !(0 != start_simulation_~tmp___0~1#1); 5597#L928-2 [2024-10-31 22:04:27,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:27,538 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2024-10-31 22:04:27,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:27,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [237992475] [2024-10-31 22:04:27,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:27,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:27,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:27,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:27,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:27,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [237992475] [2024-10-31 22:04:27,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [237992475] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:27,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:27,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:27,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090888694] [2024-10-31 22:04:27,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:27,620 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:27,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:27,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1923800974, now seen corresponding path program 2 times [2024-10-31 22:04:27,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:27,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156804638] [2024-10-31 22:04:27,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:27,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:27,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:27,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:27,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:27,691 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156804638] [2024-10-31 22:04:27,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [156804638] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:27,692 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:27,692 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:27,692 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [587651072] [2024-10-31 22:04:27,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:27,693 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:27,693 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:27,694 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:27,694 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:27,695 INFO L87 Difference]: Start difference. First operand 552 states and 820 transitions. cyclomatic complexity: 269 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:27,745 INFO L93 Difference]: Finished difference Result 981 states and 1451 transitions. [2024-10-31 22:04:27,745 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 981 states and 1451 transitions. [2024-10-31 22:04:27,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2024-10-31 22:04:27,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 981 states to 981 states and 1451 transitions. [2024-10-31 22:04:27,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 981 [2024-10-31 22:04:27,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 981 [2024-10-31 22:04:27,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 981 states and 1451 transitions. [2024-10-31 22:04:27,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:27,760 INFO L218 hiAutomatonCegarLoop]: Abstraction has 981 states and 1451 transitions. [2024-10-31 22:04:27,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 981 states and 1451 transitions. [2024-10-31 22:04:27,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 981 to 981. [2024-10-31 22:04:27,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981 states, 981 states have (on average 1.4791029561671762) internal successors, (1451), 980 states have internal predecessors, (1451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:27,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981 states to 981 states and 1451 transitions. [2024-10-31 22:04:27,785 INFO L240 hiAutomatonCegarLoop]: Abstraction has 981 states and 1451 transitions. [2024-10-31 22:04:27,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:27,789 INFO L425 stractBuchiCegarLoop]: Abstraction has 981 states and 1451 transitions. [2024-10-31 22:04:27,789 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:04:27,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981 states and 1451 transitions. [2024-10-31 22:04:27,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2024-10-31 22:04:27,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:27,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:27,799 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:27,799 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:27,799 INFO L745 eck$LassoCheckResult]: Stem: 7423#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7693#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 7501#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7502#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7670#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7473#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7474#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7664#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7469#L599 assume !(0 == ~M_E~0); 7470#L599-2 assume !(0 == ~T1_E~0); 7128#L604-1 assume !(0 == ~T2_E~0); 7115#L609-1 assume !(0 == ~T3_E~0); 7116#L614-1 assume !(0 == ~T4_E~0); 7284#L619-1 assume !(0 == ~T5_E~0); 7400#L624-1 assume !(0 == ~E_M~0); 7506#L629-1 assume !(0 == ~E_1~0); 7205#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7206#L639-1 assume !(0 == ~E_3~0); 7613#L644-1 assume !(0 == ~E_4~0); 7630#L649-1 assume !(0 == ~E_5~0); 7169#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7170#L292 assume !(1 == ~m_pc~0); 7297#L292-2 is_master_triggered_~__retres1~0#1 := 0; 7441#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7396#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7397#L743 assume !(0 != activate_threads_~tmp~1#1); 7238#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7239#L311 assume 1 == ~t1_pc~0; 7373#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7374#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7163#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7142#L751 assume !(0 != activate_threads_~tmp___0~0#1); 7143#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7614#L330 assume 1 == ~t2_pc~0; 7402#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7299#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7300#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7559#L759 assume !(0 != activate_threads_~tmp___1~0#1); 7691#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7285#L349 assume !(1 == ~t3_pc~0); 7286#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7333#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7117#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7118#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7684#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7685#L368 assume 1 == ~t4_pc~0; 7692#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7364#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7270#L775 assume !(0 != activate_threads_~tmp___3~0#1); 7129#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7130#L387 assume !(1 == ~t5_pc~0); 7525#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7526#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7405#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7255#L783 assume !(0 != activate_threads_~tmp___4~0#1); 7256#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7351#L667 assume !(1 == ~M_E~0); 7433#L667-2 assume !(1 == ~T1_E~0); 7620#L672-1 assume !(1 == ~T2_E~0); 7387#L677-1 assume !(1 == ~T3_E~0); 7388#L682-1 assume !(1 == ~T4_E~0); 7595#L687-1 assume !(1 == ~T5_E~0); 7659#L692-1 assume !(1 == ~E_M~0); 7583#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7584#L702-1 assume !(1 == ~E_2~0); 7629#L707-1 assume !(1 == ~E_3~0); 7490#L712-1 assume !(1 == ~E_4~0); 7491#L717-1 assume !(1 == ~E_5~0); 7602#L722-1 assume { :end_inline_reset_delta_events } true; 7137#L928-2 [2024-10-31 22:04:27,799 INFO L747 eck$LassoCheckResult]: Loop: 7137#L928-2 assume !false; 7138#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7376#L574-1 assume !false; 7377#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7683#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7338#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7770#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7768#L499 assume !(0 != eval_~tmp~0#1); 7767#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7656#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7546#L599-3 assume !(0 == ~M_E~0); 7547#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7451#L604-3 assume !(0 == ~T2_E~0); 7452#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7532#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7144#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7145#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7543#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7592#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7758#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7757#L644-3 assume !(0 == ~E_4~0); 7756#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7755#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7754#L292-21 assume !(1 == ~m_pc~0); 7752#L292-23 is_master_triggered_~__retres1~0#1 := 0; 7751#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7750#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7678#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7445#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7446#L311-21 assume 1 == ~t1_pc~0; 7747#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7746#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7745#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7744#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7743#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7742#L330-21 assume 1 == ~t2_pc~0; 7699#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7540#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7439#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7440#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7230#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7231#L349-21 assume !(1 == ~t3_pc~0); 7488#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7643#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7650#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7607#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7608#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7689#L368-21 assume !(1 == ~t4_pc~0); 7729#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7728#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7682#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7636#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7122#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7123#L387-21 assume !(1 == ~t5_pc~0); 7182#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 7524#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7534#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7535#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 7222#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7223#L667-3 assume !(1 == ~M_E~0); 7444#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7969#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7968#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7967#L682-3 assume !(1 == ~T4_E~0); 7966#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7965#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7964#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7963#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7962#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7961#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7960#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7959#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7947#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7943#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7941#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7940#L947 assume !(0 == start_simulation_~tmp~3#1); 7938#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7934#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7931#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7930#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 7929#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7618#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7619#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7564#L960 assume !(0 != start_simulation_~tmp___0~1#1); 7137#L928-2 [2024-10-31 22:04:27,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:27,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2024-10-31 22:04:27,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:27,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197297963] [2024-10-31 22:04:27,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:27,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:27,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:27,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:27,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:27,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197297963] [2024-10-31 22:04:27,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197297963] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:27,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:27,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:27,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [356252596] [2024-10-31 22:04:27,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:27,887 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:27,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:27,887 INFO L85 PathProgramCache]: Analyzing trace with hash 1767686066, now seen corresponding path program 1 times [2024-10-31 22:04:27,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:27,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264197766] [2024-10-31 22:04:27,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:27,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:27,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:27,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:27,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:27,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264197766] [2024-10-31 22:04:27,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264197766] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:27,949 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:27,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:27,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316810163] [2024-10-31 22:04:27,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:27,949 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:27,950 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:27,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:27,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:27,951 INFO L87 Difference]: Start difference. First operand 981 states and 1451 transitions. cyclomatic complexity: 471 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:28,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:28,012 INFO L93 Difference]: Finished difference Result 981 states and 1429 transitions. [2024-10-31 22:04:28,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 981 states and 1429 transitions. [2024-10-31 22:04:28,019 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2024-10-31 22:04:28,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 981 states to 981 states and 1429 transitions. [2024-10-31 22:04:28,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 981 [2024-10-31 22:04:28,026 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 981 [2024-10-31 22:04:28,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 981 states and 1429 transitions. [2024-10-31 22:04:28,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:28,028 INFO L218 hiAutomatonCegarLoop]: Abstraction has 981 states and 1429 transitions. [2024-10-31 22:04:28,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 981 states and 1429 transitions. [2024-10-31 22:04:28,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 981 to 981. [2024-10-31 22:04:28,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981 states, 981 states have (on average 1.4566768603465852) internal successors, (1429), 980 states have internal predecessors, (1429), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:28,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981 states to 981 states and 1429 transitions. [2024-10-31 22:04:28,047 INFO L240 hiAutomatonCegarLoop]: Abstraction has 981 states and 1429 transitions. [2024-10-31 22:04:28,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:28,050 INFO L425 stractBuchiCegarLoop]: Abstraction has 981 states and 1429 transitions. [2024-10-31 22:04:28,050 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:04:28,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981 states and 1429 transitions. [2024-10-31 22:04:28,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2024-10-31 22:04:28,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:28,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:28,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:28,058 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:28,058 INFO L745 eck$LassoCheckResult]: Stem: 9387#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9641#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 9457#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9458#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9617#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9433#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9434#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9612#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9429#L599 assume !(0 == ~M_E~0); 9430#L599-2 assume !(0 == ~T1_E~0); 9097#L604-1 assume !(0 == ~T2_E~0); 9084#L609-1 assume !(0 == ~T3_E~0); 9085#L614-1 assume !(0 == ~T4_E~0); 9252#L619-1 assume !(0 == ~T5_E~0); 9365#L624-1 assume !(0 == ~E_M~0); 9461#L629-1 assume !(0 == ~E_1~0); 9174#L634-1 assume !(0 == ~E_2~0); 9175#L639-1 assume !(0 == ~E_3~0); 9566#L644-1 assume !(0 == ~E_4~0); 9583#L649-1 assume !(0 == ~E_5~0); 9138#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9139#L292 assume !(1 == ~m_pc~0); 9265#L292-2 is_master_triggered_~__retres1~0#1 := 0; 9402#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9363#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9364#L743 assume !(0 != activate_threads_~tmp~1#1); 9207#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9208#L311 assume 1 == ~t1_pc~0; 9339#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9340#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9132#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9111#L751 assume !(0 != activate_threads_~tmp___0~0#1); 9112#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9569#L330 assume !(1 == ~t2_pc~0); 9368#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9268#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9269#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9514#L759 assume !(0 != activate_threads_~tmp___1~0#1); 9639#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9254#L349 assume !(1 == ~t3_pc~0); 9255#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9303#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9091#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9092#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9633#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9634#L368 assume 1 == ~t4_pc~0; 9640#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9332#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9238#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9239#L775 assume !(0 != activate_threads_~tmp___3~0#1); 9098#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9099#L387 assume !(1 == ~t5_pc~0); 9479#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9480#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9370#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9227#L783 assume !(0 != activate_threads_~tmp___4~0#1); 9228#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9320#L667 assume !(1 == ~M_E~0); 9394#L667-2 assume !(1 == ~T1_E~0); 9575#L672-1 assume !(1 == ~T2_E~0); 9352#L677-1 assume !(1 == ~T3_E~0); 9353#L682-1 assume !(1 == ~T4_E~0); 9549#L687-1 assume !(1 == ~T5_E~0); 9607#L692-1 assume !(1 == ~E_M~0); 9538#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9539#L702-1 assume !(1 == ~E_2~0); 9582#L707-1 assume !(1 == ~E_3~0); 9448#L712-1 assume !(1 == ~E_4~0); 9449#L717-1 assume !(1 == ~E_5~0); 9556#L722-1 assume { :end_inline_reset_delta_events } true; 9106#L928-2 [2024-10-31 22:04:28,058 INFO L747 eck$LassoCheckResult]: Loop: 9106#L928-2 assume !false; 9107#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9718#L574-1 assume !false; 9717#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9713#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9615#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9531#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9142#L499 assume !(0 != eval_~tmp~0#1); 9144#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9253#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9707#L599-3 assume !(0 == ~M_E~0); 9706#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9705#L604-3 assume !(0 == ~T2_E~0); 9704#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9703#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9702#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9701#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9700#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9602#L634-3 assume !(0 == ~E_2~0); 9557#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9558#L644-3 assume !(0 == ~E_4~0); 9636#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9653#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9696#L292-21 assume !(1 == ~m_pc~0); 9694#L292-23 is_master_triggered_~__retres1~0#1 := 0; 9693#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9692#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9626#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9406#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9407#L311-21 assume 1 == ~t1_pc~0; 9689#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9688#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9687#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9686#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9685#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9683#L330-21 assume !(1 == ~t2_pc~0); 9618#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9494#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9400#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9401#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9199#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9200#L349-21 assume 1 == ~t3_pc~0; 9445#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9593#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9598#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9560#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9561#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9638#L368-21 assume !(1 == ~t4_pc~0); 9670#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 9669#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9631#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9587#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9089#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9090#L387-21 assume !(1 == ~t5_pc~0); 9152#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9478#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9488#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9489#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 9191#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9192#L667-3 assume !(1 == ~M_E~0); 9405#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9841#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9839#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9837#L682-3 assume !(1 == ~T4_E~0); 9835#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9834#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9833#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9832#L702-3 assume !(1 == ~E_2~0); 9831#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9829#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9827#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9825#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9816#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9812#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9810#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9809#L947 assume !(0 == start_simulation_~tmp~3#1); 9807#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9782#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9775#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9771#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 9749#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9742#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9621#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9519#L960 assume !(0 != start_simulation_~tmp___0~1#1); 9106#L928-2 [2024-10-31 22:04:28,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:28,059 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2024-10-31 22:04:28,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:28,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925801997] [2024-10-31 22:04:28,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:28,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:28,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:28,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:28,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:28,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925801997] [2024-10-31 22:04:28,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925801997] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:28,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:28,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:28,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973557366] [2024-10-31 22:04:28,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:28,143 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:28,143 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:28,143 INFO L85 PathProgramCache]: Analyzing trace with hash -982956238, now seen corresponding path program 1 times [2024-10-31 22:04:28,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:28,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673517597] [2024-10-31 22:04:28,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:28,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:28,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:28,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:28,215 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:28,215 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673517597] [2024-10-31 22:04:28,215 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673517597] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:28,215 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:28,215 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:28,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140475625] [2024-10-31 22:04:28,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:28,216 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:28,216 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:28,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:28,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:28,217 INFO L87 Difference]: Start difference. First operand 981 states and 1429 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:28,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:28,316 INFO L93 Difference]: Finished difference Result 1779 states and 2571 transitions. [2024-10-31 22:04:28,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1779 states and 2571 transitions. [2024-10-31 22:04:28,331 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1697 [2024-10-31 22:04:28,341 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1779 states to 1779 states and 2571 transitions. [2024-10-31 22:04:28,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1779 [2024-10-31 22:04:28,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1779 [2024-10-31 22:04:28,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1779 states and 2571 transitions. [2024-10-31 22:04:28,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:28,346 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1779 states and 2571 transitions. [2024-10-31 22:04:28,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1779 states and 2571 transitions. [2024-10-31 22:04:28,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1779 to 1775. [2024-10-31 22:04:28,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1775 states, 1775 states have (on average 1.4461971830985916) internal successors, (2567), 1774 states have internal predecessors, (2567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:28,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1775 states to 1775 states and 2567 transitions. [2024-10-31 22:04:28,384 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1775 states and 2567 transitions. [2024-10-31 22:04:28,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:28,386 INFO L425 stractBuchiCegarLoop]: Abstraction has 1775 states and 2567 transitions. [2024-10-31 22:04:28,386 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:04:28,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1775 states and 2567 transitions. [2024-10-31 22:04:28,396 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1693 [2024-10-31 22:04:28,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:28,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:28,398 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:28,398 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:28,398 INFO L745 eck$LassoCheckResult]: Stem: 12160#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12289#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12438#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 12235#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12236#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12417#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12208#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12209#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12411#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12204#L599 assume !(0 == ~M_E~0); 12205#L599-2 assume !(0 == ~T1_E~0); 11862#L604-1 assume !(0 == ~T2_E~0); 11851#L609-1 assume !(0 == ~T3_E~0); 11852#L614-1 assume !(0 == ~T4_E~0); 12019#L619-1 assume !(0 == ~T5_E~0); 12137#L624-1 assume !(0 == ~E_M~0); 12240#L629-1 assume !(0 == ~E_1~0); 11941#L634-1 assume !(0 == ~E_2~0); 11942#L639-1 assume !(0 == ~E_3~0); 12358#L644-1 assume !(0 == ~E_4~0); 12378#L649-1 assume !(0 == ~E_5~0); 11906#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11907#L292 assume !(1 == ~m_pc~0); 12033#L292-2 is_master_triggered_~__retres1~0#1 := 0; 12176#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12133#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12134#L743 assume !(0 != activate_threads_~tmp~1#1); 11975#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11976#L311 assume !(1 == ~t1_pc~0); 12357#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12247#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11900#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11879#L751 assume !(0 != activate_threads_~tmp___0~0#1); 11880#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12359#L330 assume !(1 == ~t2_pc~0); 12140#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12035#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12295#L759 assume !(0 != activate_threads_~tmp___1~0#1); 12436#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12020#L349 assume !(1 == ~t3_pc~0); 12021#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12069#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11853#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11854#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12431#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12432#L368 assume 1 == ~t4_pc~0; 12437#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12101#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12005#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12006#L775 assume !(0 != activate_threads_~tmp___3~0#1); 11865#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11866#L387 assume !(1 == ~t5_pc~0); 12260#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12261#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12142#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11991#L783 assume !(0 != activate_threads_~tmp___4~0#1); 11992#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12086#L667 assume !(1 == ~M_E~0); 12168#L667-2 assume !(1 == ~T1_E~0); 12365#L672-1 assume !(1 == ~T2_E~0); 12123#L677-1 assume !(1 == ~T3_E~0); 12124#L682-1 assume !(1 == ~T4_E~0); 12339#L687-1 assume !(1 == ~T5_E~0); 12406#L692-1 assume !(1 == ~E_M~0); 12326#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12327#L702-1 assume !(1 == ~E_2~0); 12377#L707-1 assume !(1 == ~E_3~0); 12226#L712-1 assume !(1 == ~E_4~0); 12227#L717-1 assume !(1 == ~E_5~0); 12346#L722-1 assume { :end_inline_reset_delta_events } true; 12347#L928-2 [2024-10-31 22:04:28,398 INFO L747 eck$LassoCheckResult]: Loop: 12347#L928-2 assume !false; 12847#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12845#L574-1 assume !false; 12844#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12840#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12416#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12313#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11910#L499 assume !(0 != eval_~tmp~0#1); 11912#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12834#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12831#L599-3 assume !(0 == ~M_E~0); 12832#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13168#L604-3 assume !(0 == ~T2_E~0); 13167#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13166#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13165#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13164#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13163#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13162#L634-3 assume !(0 == ~E_2~0); 13161#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13160#L644-3 assume !(0 == ~E_4~0); 13159#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13158#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13157#L292-21 assume !(1 == ~m_pc~0); 13155#L292-23 is_master_triggered_~__retres1~0#1 := 0; 13154#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13153#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13152#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12732#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12403#L311-21 assume !(1 == ~t1_pc~0); 12404#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 13222#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13221#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13220#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13219#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13217#L330-21 assume !(1 == ~t2_pc~0); 13216#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 13215#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13214#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13213#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13212#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13211#L349-21 assume 1 == ~t3_pc~0; 13209#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13208#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13207#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13206#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13205#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13204#L368-21 assume !(1 == ~t4_pc~0); 13202#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 13201#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13200#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13199#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13198#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13197#L387-21 assume 1 == ~t5_pc~0; 13195#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13194#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13193#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13192#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 13191#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13190#L667-3 assume !(1 == ~M_E~0); 13074#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13189#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13188#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13187#L682-3 assume !(1 == ~T4_E~0); 13186#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13185#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13184#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13183#L702-3 assume !(1 == ~E_2~0); 13182#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13181#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13180#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13179#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13175#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13172#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13171#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 12190#L947 assume !(0 == start_simulation_~tmp~3#1); 12191#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12462#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13010#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12876#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 12875#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12873#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12863#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 12856#L960 assume !(0 != start_simulation_~tmp___0~1#1); 12347#L928-2 [2024-10-31 22:04:28,399 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:28,399 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2024-10-31 22:04:28,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:28,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455999336] [2024-10-31 22:04:28,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:28,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:28,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:28,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:28,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:28,490 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455999336] [2024-10-31 22:04:28,490 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455999336] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:28,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:28,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:04:28,491 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691557196] [2024-10-31 22:04:28,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:28,491 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:28,492 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:28,492 INFO L85 PathProgramCache]: Analyzing trace with hash -319613902, now seen corresponding path program 1 times [2024-10-31 22:04:28,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:28,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369374661] [2024-10-31 22:04:28,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:28,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:28,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:28,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:28,572 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:28,573 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369374661] [2024-10-31 22:04:28,573 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369374661] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:28,573 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:28,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:28,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831755632] [2024-10-31 22:04:28,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:28,574 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:28,574 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:28,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:04:28,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:04:28,575 INFO L87 Difference]: Start difference. First operand 1775 states and 2567 transitions. cyclomatic complexity: 794 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:28,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:28,832 INFO L93 Difference]: Finished difference Result 1862 states and 2654 transitions. [2024-10-31 22:04:28,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1862 states and 2654 transitions. [2024-10-31 22:04:28,847 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1777 [2024-10-31 22:04:28,858 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1862 states to 1862 states and 2654 transitions. [2024-10-31 22:04:28,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1862 [2024-10-31 22:04:28,861 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1862 [2024-10-31 22:04:28,861 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1862 states and 2654 transitions. [2024-10-31 22:04:28,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:28,864 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1862 states and 2654 transitions. [2024-10-31 22:04:28,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1862 states and 2654 transitions. [2024-10-31 22:04:28,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1862 to 1862. [2024-10-31 22:04:28,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1862 states, 1862 states have (on average 1.4253490870032224) internal successors, (2654), 1861 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:28,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1862 states to 1862 states and 2654 transitions. [2024-10-31 22:04:28,911 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1862 states and 2654 transitions. [2024-10-31 22:04:28,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:04:28,912 INFO L425 stractBuchiCegarLoop]: Abstraction has 1862 states and 2654 transitions. [2024-10-31 22:04:28,912 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:04:28,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1862 states and 2654 transitions. [2024-10-31 22:04:28,921 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1777 [2024-10-31 22:04:28,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:28,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:28,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:28,923 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:28,923 INFO L745 eck$LassoCheckResult]: Stem: 15801#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 15802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15928#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15929#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16073#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 15873#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15874#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16048#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15848#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15849#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16044#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15844#L599 assume !(0 == ~M_E~0); 15845#L599-2 assume !(0 == ~T1_E~0); 15508#L604-1 assume !(0 == ~T2_E~0); 15497#L609-1 assume !(0 == ~T3_E~0); 15498#L614-1 assume !(0 == ~T4_E~0); 15664#L619-1 assume !(0 == ~T5_E~0); 15778#L624-1 assume !(0 == ~E_M~0); 15878#L629-1 assume !(0 == ~E_1~0); 15585#L634-1 assume !(0 == ~E_2~0); 15586#L639-1 assume !(0 == ~E_3~0); 15993#L644-1 assume !(0 == ~E_4~0); 16013#L649-1 assume !(0 == ~E_5~0); 15551#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15552#L292 assume !(1 == ~m_pc~0); 15677#L292-2 is_master_triggered_~__retres1~0#1 := 0; 15817#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15774#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15775#L743 assume !(0 != activate_threads_~tmp~1#1); 15619#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15620#L311 assume !(1 == ~t1_pc~0); 15992#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15885#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15545#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15524#L751 assume !(0 != activate_threads_~tmp___0~0#1); 15525#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15995#L330 assume !(1 == ~t2_pc~0); 15781#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15679#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15680#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15934#L759 assume !(0 != activate_threads_~tmp___1~0#1); 16070#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15665#L349 assume !(1 == ~t3_pc~0); 15666#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15960#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15499#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15500#L767 assume !(0 != activate_threads_~tmp___2~0#1); 16065#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16066#L368 assume 1 == ~t4_pc~0; 16071#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15745#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15651#L775 assume !(0 != activate_threads_~tmp___3~0#1); 15511#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15512#L387 assume !(1 == ~t5_pc~0); 15898#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15899#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15783#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15636#L783 assume !(0 != activate_threads_~tmp___4~0#1); 15637#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15730#L667 assume !(1 == ~M_E~0); 15809#L667-2 assume !(1 == ~T1_E~0); 16001#L672-1 assume !(1 == ~T2_E~0); 15765#L677-1 assume !(1 == ~T3_E~0); 15766#L682-1 assume !(1 == ~T4_E~0); 15972#L687-1 assume !(1 == ~T5_E~0); 16040#L692-1 assume !(1 == ~E_M~0); 15958#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15959#L702-1 assume !(1 == ~E_2~0); 16012#L707-1 assume !(1 == ~E_3~0); 15865#L712-1 assume !(1 == ~E_4~0); 15866#L717-1 assume !(1 == ~E_5~0); 15981#L722-1 assume { :end_inline_reset_delta_events } true; 15519#L928-2 [2024-10-31 22:04:28,923 INFO L747 eck$LassoCheckResult]: Loop: 15519#L928-2 assume !false; 15520#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15754#L574-1 assume !false; 15755#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16063#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 15718#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 15951#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15555#L499 assume !(0 != eval_~tmp~0#1); 15556#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15668#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15919#L599-3 assume !(0 == ~M_E~0); 15920#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15827#L604-3 assume !(0 == ~T2_E~0); 15828#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15905#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15526#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15527#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15916#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15969#L634-3 assume !(0 == ~E_2~0); 16399#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16397#L644-3 assume !(0 == ~E_4~0); 16395#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16393#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16391#L292-21 assume !(1 == ~m_pc~0); 16388#L292-23 is_master_triggered_~__retres1~0#1 := 0; 16385#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16383#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16382#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16381#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16039#L311-21 assume !(1 == ~t1_pc~0); 15748#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 15559#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15560#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15627#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15675#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15676#L330-21 assume !(1 == ~t2_pc~0); 15945#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 15913#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15815#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15816#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15611#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15612#L349-21 assume 1 == ~t3_pc~0; 15862#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16102#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17253#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17252#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15987#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15694#L368-21 assume 1 == ~t4_pc~0; 15575#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15576#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16031#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16016#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15504#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15505#L387-21 assume !(1 == ~t5_pc~0); 15564#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 15897#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15907#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15908#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 15603#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15604#L667-3 assume !(1 == ~M_E~0); 15820#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17227#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17225#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17223#L682-3 assume !(1 == ~T4_E~0); 17222#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17221#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17220#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17219#L702-3 assume !(1 == ~E_2~0); 17218#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17217#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17216#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17215#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 17211#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 17208#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 15894#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 15830#L947 assume !(0 == start_simulation_~tmp~3#1); 15831#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 15835#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 15792#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 15543#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 15544#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15999#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16000#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 15939#L960 assume !(0 != start_simulation_~tmp___0~1#1); 15519#L928-2 [2024-10-31 22:04:28,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:28,924 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2024-10-31 22:04:28,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:28,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285974387] [2024-10-31 22:04:28,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:28,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:28,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:28,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:28,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:28,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285974387] [2024-10-31 22:04:28,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285974387] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:28,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:28,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:28,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272703974] [2024-10-31 22:04:28,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:28,973 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:28,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:28,973 INFO L85 PathProgramCache]: Analyzing trace with hash 1078622450, now seen corresponding path program 1 times [2024-10-31 22:04:28,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:28,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707299333] [2024-10-31 22:04:28,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:28,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:28,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:29,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:29,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:29,027 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707299333] [2024-10-31 22:04:29,027 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [707299333] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:29,027 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:29,027 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:29,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777454927] [2024-10-31 22:04:29,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:29,028 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:29,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:29,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:29,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:29,029 INFO L87 Difference]: Start difference. First operand 1862 states and 2654 transitions. cyclomatic complexity: 794 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:29,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:29,131 INFO L93 Difference]: Finished difference Result 3428 states and 4858 transitions. [2024-10-31 22:04:29,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3428 states and 4858 transitions. [2024-10-31 22:04:29,154 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3332 [2024-10-31 22:04:29,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3428 states to 3428 states and 4858 transitions. [2024-10-31 22:04:29,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3428 [2024-10-31 22:04:29,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3428 [2024-10-31 22:04:29,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3428 states and 4858 transitions. [2024-10-31 22:04:29,180 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:29,180 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3428 states and 4858 transitions. [2024-10-31 22:04:29,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3428 states and 4858 transitions. [2024-10-31 22:04:29,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3428 to 3420. [2024-10-31 22:04:29,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3420 states, 3420 states have (on average 1.4181286549707601) internal successors, (4850), 3419 states have internal predecessors, (4850), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:29,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3420 states to 3420 states and 4850 transitions. [2024-10-31 22:04:29,243 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3420 states and 4850 transitions. [2024-10-31 22:04:29,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:29,244 INFO L425 stractBuchiCegarLoop]: Abstraction has 3420 states and 4850 transitions. [2024-10-31 22:04:29,244 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:04:29,244 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3420 states and 4850 transitions. [2024-10-31 22:04:29,258 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3324 [2024-10-31 22:04:29,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:29,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:29,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:29,259 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:29,260 INFO L745 eck$LassoCheckResult]: Stem: 21102#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21230#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21231#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21368#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 21174#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21175#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21340#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21148#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21149#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21335#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21144#L599 assume !(0 == ~M_E~0); 21145#L599-2 assume !(0 == ~T1_E~0); 20805#L604-1 assume !(0 == ~T2_E~0); 20794#L609-1 assume !(0 == ~T3_E~0); 20795#L614-1 assume !(0 == ~T4_E~0); 20962#L619-1 assume !(0 == ~T5_E~0); 21079#L624-1 assume !(0 == ~E_M~0); 21180#L629-1 assume !(0 == ~E_1~0); 20883#L634-1 assume !(0 == ~E_2~0); 20884#L639-1 assume !(0 == ~E_3~0); 21289#L644-1 assume !(0 == ~E_4~0); 21304#L649-1 assume !(0 == ~E_5~0); 20848#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20849#L292 assume !(1 == ~m_pc~0); 20976#L292-2 is_master_triggered_~__retres1~0#1 := 0; 21117#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21075#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21076#L743 assume !(0 != activate_threads_~tmp~1#1); 20916#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20917#L311 assume !(1 == ~t1_pc~0); 21288#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21187#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20842#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20821#L751 assume !(0 != activate_threads_~tmp___0~0#1); 20822#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21290#L330 assume !(1 == ~t2_pc~0); 21083#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20978#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20979#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21235#L759 assume !(0 != activate_threads_~tmp___1~0#1); 21367#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20963#L349 assume !(1 == ~t3_pc~0); 20964#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21397#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21418#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21407#L767 assume !(0 != activate_threads_~tmp___2~0#1); 21361#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21362#L368 assume !(1 == ~t4_pc~0); 21045#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21046#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20947#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20948#L775 assume !(0 != activate_threads_~tmp___3~0#1); 20808#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20809#L387 assume !(1 == ~t5_pc~0); 21200#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21201#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21085#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20933#L783 assume !(0 != activate_threads_~tmp___4~0#1); 20934#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21032#L667 assume !(1 == ~M_E~0); 21110#L667-2 assume !(1 == ~T1_E~0); 21296#L672-1 assume !(1 == ~T2_E~0); 21066#L677-1 assume !(1 == ~T3_E~0); 21067#L682-1 assume !(1 == ~T4_E~0); 21271#L687-1 assume !(1 == ~T5_E~0); 21330#L692-1 assume !(1 == ~E_M~0); 21259#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21260#L702-1 assume !(1 == ~E_2~0); 21303#L707-1 assume !(1 == ~E_3~0); 21166#L712-1 assume !(1 == ~E_4~0); 21167#L717-1 assume !(1 == ~E_5~0); 21278#L722-1 assume { :end_inline_reset_delta_events } true; 20816#L928-2 [2024-10-31 22:04:29,260 INFO L747 eck$LassoCheckResult]: Loop: 20816#L928-2 assume !false; 20817#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21055#L574-1 assume !false; 21056#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 21360#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 21020#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 21252#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20852#L499 assume !(0 != eval_~tmp~0#1); 20853#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21329#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21221#L599-3 assume !(0 == ~M_E~0); 21222#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21126#L604-3 assume !(0 == ~T2_E~0); 21127#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21207#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20823#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20824#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21218#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21268#L634-3 assume !(0 == ~E_2~0); 21279#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21280#L644-3 assume !(0 == ~E_4~0); 21364#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21136#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21137#L292-21 assume 1 == ~m_pc~0; 21227#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20896#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20897#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21003#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21120#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21121#L311-21 assume !(1 == ~t1_pc~0); 21049#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 20856#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20857#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23835#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23834#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23832#L330-21 assume !(1 == ~t2_pc~0); 23831#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 21215#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21115#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21116#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20908#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20909#L349-21 assume 1 == ~t3_pc~0; 21163#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21411#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21378#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21379#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21284#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20994#L368-21 assume !(1 == ~t4_pc~0); 20995#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 21306#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21322#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21311#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20798#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20799#L387-21 assume !(1 == ~t5_pc~0); 20861#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 21199#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21209#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21210#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 20901#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20902#L667-3 assume !(1 == ~M_E~0); 20888#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20889#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20972#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20973#L682-3 assume !(1 == ~T4_E~0); 21321#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21016#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21017#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21090#L702-3 assume !(1 == ~E_2~0); 21091#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21226#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20894#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20895#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 21251#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 20831#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 21195#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 21129#L947 assume !(0 == start_simulation_~tmp~3#1); 21130#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 21134#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 21095#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 20840#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 20841#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21294#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21295#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 21240#L960 assume !(0 != start_simulation_~tmp___0~1#1); 20816#L928-2 [2024-10-31 22:04:29,260 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:29,261 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2024-10-31 22:04:29,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:29,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141305958] [2024-10-31 22:04:29,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:29,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:29,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:29,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:29,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:29,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141305958] [2024-10-31 22:04:29,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141305958] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:29,346 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:29,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:29,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1362194353] [2024-10-31 22:04:29,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:29,347 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:29,348 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:29,348 INFO L85 PathProgramCache]: Analyzing trace with hash 1175350258, now seen corresponding path program 1 times [2024-10-31 22:04:29,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:29,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840267597] [2024-10-31 22:04:29,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:29,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:29,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:29,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:29,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:29,388 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840267597] [2024-10-31 22:04:29,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1840267597] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:29,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:29,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:29,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655949793] [2024-10-31 22:04:29,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:29,390 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:29,390 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:29,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:29,390 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:29,390 INFO L87 Difference]: Start difference. First operand 3420 states and 4850 transitions. cyclomatic complexity: 1434 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:29,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:29,556 INFO L93 Difference]: Finished difference Result 5429 states and 7639 transitions. [2024-10-31 22:04:29,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5429 states and 7639 transitions. [2024-10-31 22:04:29,585 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5244 [2024-10-31 22:04:29,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5429 states to 5429 states and 7639 transitions. [2024-10-31 22:04:29,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5429 [2024-10-31 22:04:29,614 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5429 [2024-10-31 22:04:29,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5429 states and 7639 transitions. [2024-10-31 22:04:29,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:29,621 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5429 states and 7639 transitions. [2024-10-31 22:04:29,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5429 states and 7639 transitions. [2024-10-31 22:04:29,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5429 to 3932. [2024-10-31 22:04:29,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3932 states, 3932 states have (on average 1.4109867751780265) internal successors, (5548), 3931 states have internal predecessors, (5548), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:29,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3932 states to 3932 states and 5548 transitions. [2024-10-31 22:04:29,698 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3932 states and 5548 transitions. [2024-10-31 22:04:29,698 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:29,698 INFO L425 stractBuchiCegarLoop]: Abstraction has 3932 states and 5548 transitions. [2024-10-31 22:04:29,699 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:04:29,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3932 states and 5548 transitions. [2024-10-31 22:04:29,714 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3780 [2024-10-31 22:04:29,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:29,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:29,716 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:29,716 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:29,717 INFO L745 eck$LassoCheckResult]: Stem: 29955#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 29956#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 30090#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30091#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30228#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 30031#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30032#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30207#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30006#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30007#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30205#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30002#L599 assume !(0 == ~M_E~0); 30003#L599-2 assume !(0 == ~T1_E~0); 29666#L604-1 assume !(0 == ~T2_E~0); 29653#L609-1 assume !(0 == ~T3_E~0); 29654#L614-1 assume !(0 == ~T4_E~0); 29817#L619-1 assume !(0 == ~T5_E~0); 29931#L624-1 assume !(0 == ~E_M~0); 30035#L629-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30246#L634-1 assume !(0 == ~E_2~0); 30155#L639-1 assume !(0 == ~E_3~0); 30156#L644-1 assume !(0 == ~E_4~0); 30172#L649-1 assume !(0 == ~E_5~0); 30173#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29830#L292 assume !(1 == ~m_pc~0); 29831#L292-2 is_master_triggered_~__retres1~0#1 := 0; 30085#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30086#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30298#L743 assume !(0 != activate_threads_~tmp~1#1); 30296#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30295#L311 assume !(1 == ~t1_pc~0); 30294#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30293#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30292#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29680#L751 assume !(0 != activate_threads_~tmp___0~0#1); 29681#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30159#L330 assume !(1 == ~t2_pc~0); 29934#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30288#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30095#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30096#L759 assume !(0 != activate_threads_~tmp___1~0#1); 30224#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29819#L349 assume !(1 == ~t3_pc~0); 29820#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30125#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29660#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29661#L767 assume !(0 != activate_threads_~tmp___2~0#1); 30219#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30220#L368 assume !(1 == ~t4_pc~0); 29899#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29900#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30191#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30274#L775 assume !(0 != activate_threads_~tmp___3~0#1); 30273#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30272#L387 assume !(1 == ~t5_pc~0); 30270#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30255#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29936#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29937#L783 assume !(0 != activate_threads_~tmp___4~0#1); 30268#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30267#L667 assume !(1 == ~M_E~0); 30266#L667-2 assume !(1 == ~T1_E~0); 30265#L672-1 assume !(1 == ~T2_E~0); 30264#L677-1 assume !(1 == ~T3_E~0); 30263#L682-1 assume !(1 == ~T4_E~0); 30262#L687-1 assume !(1 == ~T5_E~0); 30261#L692-1 assume !(1 == ~E_M~0); 30260#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 30124#L702-1 assume !(1 == ~E_2~0); 30171#L707-1 assume !(1 == ~E_3~0); 30022#L712-1 assume !(1 == ~E_4~0); 30023#L717-1 assume !(1 == ~E_5~0); 30144#L722-1 assume { :end_inline_reset_delta_events } true; 30145#L928-2 [2024-10-31 22:04:29,717 INFO L747 eck$LassoCheckResult]: Loop: 30145#L928-2 assume !false; 31861#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31858#L574-1 assume !false; 31856#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31851#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31847#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31844#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31841#L499 assume !(0 != eval_~tmp~0#1); 31839#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31837#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31835#L599-3 assume !(0 == ~M_E~0); 31833#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31832#L604-3 assume !(0 == ~T2_E~0); 31830#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31828#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31826#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31824#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31821#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31820#L634-3 assume !(0 == ~E_2~0); 31819#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31818#L644-3 assume !(0 == ~E_4~0); 31817#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31816#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31815#L292-21 assume !(1 == ~m_pc~0); 31813#L292-23 is_master_triggered_~__retres1~0#1 := 0; 31812#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31811#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31810#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31809#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31808#L311-21 assume !(1 == ~t1_pc~0); 31807#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 31806#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31805#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31804#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31803#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31801#L330-21 assume !(1 == ~t2_pc~0); 31800#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 31799#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31798#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31797#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31796#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31795#L349-21 assume 1 == ~t3_pc~0; 31793#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31791#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31789#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31787#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31786#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31785#L368-21 assume !(1 == ~t4_pc~0); 31784#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 31783#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31782#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31781#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31780#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31779#L387-21 assume 1 == ~t5_pc~0; 31777#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31776#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31775#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31774#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 31773#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31772#L667-3 assume !(1 == ~M_E~0); 31205#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31771#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31770#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31769#L682-3 assume !(1 == ~T4_E~0); 31768#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31767#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31765#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31764#L702-3 assume !(1 == ~E_2~0); 31763#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31762#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31761#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31760#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31756#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31753#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31752#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 30336#L947 assume !(0 == start_simulation_~tmp~3#1); 30338#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31907#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31903#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31901#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 31899#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31886#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31878#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 31872#L960 assume !(0 != start_simulation_~tmp___0~1#1); 30145#L928-2 [2024-10-31 22:04:29,717 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:29,717 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2024-10-31 22:04:29,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:29,717 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456435297] [2024-10-31 22:04:29,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:29,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:29,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:29,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:29,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:29,775 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1456435297] [2024-10-31 22:04:29,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1456435297] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:29,775 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:29,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:29,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168720048] [2024-10-31 22:04:29,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:29,776 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:29,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:29,776 INFO L85 PathProgramCache]: Analyzing trace with hash -319613902, now seen corresponding path program 2 times [2024-10-31 22:04:29,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:29,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927450055] [2024-10-31 22:04:29,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:29,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:29,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:29,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:29,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:29,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927450055] [2024-10-31 22:04:29,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927450055] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:29,818 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:29,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:29,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256815639] [2024-10-31 22:04:29,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:29,819 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:29,819 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:29,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:29,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:29,820 INFO L87 Difference]: Start difference. First operand 3932 states and 5548 transitions. cyclomatic complexity: 1620 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:29,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:29,956 INFO L93 Difference]: Finished difference Result 4766 states and 6689 transitions. [2024-10-31 22:04:29,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4766 states and 6689 transitions. [2024-10-31 22:04:29,979 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4642 [2024-10-31 22:04:30,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4766 states to 4766 states and 6689 transitions. [2024-10-31 22:04:30,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4766 [2024-10-31 22:04:30,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4766 [2024-10-31 22:04:30,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4766 states and 6689 transitions. [2024-10-31 22:04:30,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:30,010 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4766 states and 6689 transitions. [2024-10-31 22:04:30,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4766 states and 6689 transitions. [2024-10-31 22:04:30,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4766 to 3420. [2024-10-31 22:04:30,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3420 states, 3420 states have (on average 1.4035087719298245) internal successors, (4800), 3419 states have internal predecessors, (4800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:30,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3420 states to 3420 states and 4800 transitions. [2024-10-31 22:04:30,079 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3420 states and 4800 transitions. [2024-10-31 22:04:30,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:30,080 INFO L425 stractBuchiCegarLoop]: Abstraction has 3420 states and 4800 transitions. [2024-10-31 22:04:30,080 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:04:30,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3420 states and 4800 transitions. [2024-10-31 22:04:30,094 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3324 [2024-10-31 22:04:30,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:30,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:30,095 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,096 INFO L745 eck$LassoCheckResult]: Stem: 38660#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 38661#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 38793#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38794#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38938#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 38735#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38736#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38911#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38708#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38709#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38907#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38704#L599 assume !(0 == ~M_E~0); 38705#L599-2 assume !(0 == ~T1_E~0); 38372#L604-1 assume !(0 == ~T2_E~0); 38361#L609-1 assume !(0 == ~T3_E~0); 38362#L614-1 assume !(0 == ~T4_E~0); 38524#L619-1 assume !(0 == ~T5_E~0); 38637#L624-1 assume !(0 == ~E_M~0); 38740#L629-1 assume !(0 == ~E_1~0); 38449#L634-1 assume !(0 == ~E_2~0); 38450#L639-1 assume !(0 == ~E_3~0); 38859#L644-1 assume !(0 == ~E_4~0); 38879#L649-1 assume !(0 == ~E_5~0); 38415#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38416#L292 assume !(1 == ~m_pc~0); 38537#L292-2 is_master_triggered_~__retres1~0#1 := 0; 38676#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38633#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38634#L743 assume !(0 != activate_threads_~tmp~1#1); 38481#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38482#L311 assume !(1 == ~t1_pc~0); 38858#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38747#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38409#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38388#L751 assume !(0 != activate_threads_~tmp___0~0#1); 38389#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38861#L330 assume !(1 == ~t2_pc~0); 38640#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38539#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38540#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38798#L759 assume !(0 != activate_threads_~tmp___1~0#1); 38935#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38525#L349 assume !(1 == ~t3_pc~0); 38526#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38966#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38985#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38976#L767 assume !(0 != activate_threads_~tmp___2~0#1); 38929#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38930#L368 assume !(1 == ~t4_pc~0); 38603#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 38604#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38511#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38512#L775 assume !(0 != activate_threads_~tmp___3~0#1); 38375#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38376#L387 assume !(1 == ~t5_pc~0); 38762#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 38763#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38642#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38498#L783 assume !(0 != activate_threads_~tmp___4~0#1); 38499#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38592#L667 assume !(1 == ~M_E~0); 38668#L667-2 assume !(1 == ~T1_E~0); 38867#L672-1 assume !(1 == ~T2_E~0); 38624#L677-1 assume !(1 == ~T3_E~0); 38625#L682-1 assume !(1 == ~T4_E~0); 38838#L687-1 assume !(1 == ~T5_E~0); 38903#L692-1 assume !(1 == ~E_M~0); 38826#L697-1 assume !(1 == ~E_1~0); 38827#L702-1 assume !(1 == ~E_2~0); 38878#L707-1 assume !(1 == ~E_3~0); 38726#L712-1 assume !(1 == ~E_4~0); 38727#L717-1 assume !(1 == ~E_5~0); 38845#L722-1 assume { :end_inline_reset_delta_events } true; 38846#L928-2 [2024-10-31 22:04:30,096 INFO L747 eck$LassoCheckResult]: Loop: 38846#L928-2 assume !false; 39646#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39644#L574-1 assume !false; 39643#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 39639#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 39636#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 39635#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 39633#L499 assume !(0 != eval_~tmp~0#1); 39632#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39631#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39630#L599-3 assume !(0 == ~M_E~0); 39629#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39628#L604-3 assume !(0 == ~T2_E~0); 39627#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39626#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39625#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39624#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39623#L629-3 assume !(0 == ~E_1~0); 39622#L634-3 assume !(0 == ~E_2~0); 39621#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39620#L644-3 assume !(0 == ~E_4~0); 39619#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39618#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39617#L292-21 assume 1 == ~m_pc~0; 39616#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39614#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39613#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39612#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39611#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39610#L311-21 assume !(1 == ~t1_pc~0); 39609#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 39608#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39607#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39606#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39605#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39603#L330-21 assume !(1 == ~t2_pc~0); 39602#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 39601#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39600#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39599#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39598#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39597#L349-21 assume 1 == ~t3_pc~0; 39595#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39593#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39591#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39589#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39588#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39587#L368-21 assume !(1 == ~t4_pc~0); 39586#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 39585#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39584#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39583#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39582#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39581#L387-21 assume 1 == ~t5_pc~0; 39579#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39578#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39577#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39576#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 39575#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39217#L667-3 assume !(1 == ~M_E~0); 39214#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39207#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39205#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39203#L682-3 assume !(1 == ~T4_E~0); 39200#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39198#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 39195#L697-3 assume !(1 == ~E_1~0); 39193#L702-3 assume !(1 == ~E_2~0); 39191#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39189#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39187#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39185#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 39175#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 39170#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 39087#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 39021#L947 assume !(0 == start_simulation_~tmp~3#1); 39023#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 39753#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 39746#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 39732#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 39680#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39670#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39661#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 39655#L960 assume !(0 != start_simulation_~tmp___0~1#1); 38846#L928-2 [2024-10-31 22:04:30,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:30,097 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2024-10-31 22:04:30,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:30,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656996770] [2024-10-31 22:04:30,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:30,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:30,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:30,110 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:30,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:30,149 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:30,150 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:30,150 INFO L85 PathProgramCache]: Analyzing trace with hash -263477199, now seen corresponding path program 1 times [2024-10-31 22:04:30,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:30,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248478080] [2024-10-31 22:04:30,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:30,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:30,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:30,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:30,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:30,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248478080] [2024-10-31 22:04:30,195 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248478080] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:30,195 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:30,195 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:30,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964577998] [2024-10-31 22:04:30,195 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:30,196 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:30,196 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:30,196 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:30,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:30,197 INFO L87 Difference]: Start difference. First operand 3420 states and 4800 transitions. cyclomatic complexity: 1384 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:30,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:30,242 INFO L93 Difference]: Finished difference Result 3932 states and 5517 transitions. [2024-10-31 22:04:30,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3932 states and 5517 transitions. [2024-10-31 22:04:30,260 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3780 [2024-10-31 22:04:30,275 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3932 states to 3932 states and 5517 transitions. [2024-10-31 22:04:30,275 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3932 [2024-10-31 22:04:30,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3932 [2024-10-31 22:04:30,279 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3932 states and 5517 transitions. [2024-10-31 22:04:30,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:30,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3932 states and 5517 transitions. [2024-10-31 22:04:30,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3932 states and 5517 transitions. [2024-10-31 22:04:30,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3932 to 3932. [2024-10-31 22:04:30,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3932 states, 3932 states have (on average 1.4031027466937944) internal successors, (5517), 3931 states have internal predecessors, (5517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:30,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3932 states to 3932 states and 5517 transitions. [2024-10-31 22:04:30,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3932 states and 5517 transitions. [2024-10-31 22:04:30,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:30,356 INFO L425 stractBuchiCegarLoop]: Abstraction has 3932 states and 5517 transitions. [2024-10-31 22:04:30,356 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:04:30,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3932 states and 5517 transitions. [2024-10-31 22:04:30,371 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3780 [2024-10-31 22:04:30,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:30,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:30,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,373 INFO L745 eck$LassoCheckResult]: Stem: 46023#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 46024#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 46157#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46158#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46303#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 46099#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46100#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46285#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46072#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46073#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46279#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46068#L599 assume !(0 == ~M_E~0); 46069#L599-2 assume !(0 == ~T1_E~0); 45730#L604-1 assume !(0 == ~T2_E~0); 45719#L609-1 assume !(0 == ~T3_E~0); 45720#L614-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45882#L619-1 assume !(0 == ~T5_E~0); 46001#L624-1 assume !(0 == ~E_M~0); 46412#L629-1 assume !(0 == ~E_1~0); 45808#L634-1 assume !(0 == ~E_2~0); 45809#L639-1 assume !(0 == ~E_3~0); 46273#L644-1 assume !(0 == ~E_4~0); 46243#L649-1 assume !(0 == ~E_5~0); 45774#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45775#L292 assume !(1 == ~m_pc~0); 45897#L292-2 is_master_triggered_~__retres1~0#1 := 0; 46038#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46152#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46315#L743 assume !(0 != activate_threads_~tmp~1#1); 45840#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45841#L311 assume !(1 == ~t1_pc~0); 46225#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46112#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45767#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45768#L751 assume !(0 != activate_threads_~tmp___0~0#1); 46388#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46383#L330 assume !(1 == ~t2_pc~0); 46181#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45899#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45900#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46380#L759 assume !(0 != activate_threads_~tmp___1~0#1); 46379#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46378#L349 assume !(1 == ~t3_pc~0); 46376#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46374#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46372#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46367#L767 assume !(0 != activate_threads_~tmp___2~0#1); 46366#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46342#L368 assume !(1 == ~t4_pc~0); 46343#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46364#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45869#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45870#L775 assume !(0 != activate_threads_~tmp___3~0#1); 45733#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45734#L387 assume !(1 == ~t5_pc~0); 46124#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46125#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46357#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45856#L783 assume !(0 != activate_threads_~tmp___4~0#1); 45857#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45953#L667 assume !(1 == ~M_E~0); 46031#L667-2 assume !(1 == ~T1_E~0); 46235#L672-1 assume !(1 == ~T2_E~0); 45987#L677-1 assume !(1 == ~T3_E~0); 45988#L682-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46206#L687-1 assume !(1 == ~T5_E~0); 46274#L692-1 assume !(1 == ~E_M~0); 46192#L697-1 assume !(1 == ~E_1~0); 46193#L702-1 assume !(1 == ~E_2~0); 46242#L707-1 assume !(1 == ~E_3~0); 46090#L712-1 assume !(1 == ~E_4~0); 46091#L717-1 assume !(1 == ~E_5~0); 46214#L722-1 assume { :end_inline_reset_delta_events } true; 46215#L928-2 [2024-10-31 22:04:30,373 INFO L747 eck$LassoCheckResult]: Loop: 46215#L928-2 assume !false; 48662#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48646#L574-1 assume !false; 48601#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 47762#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 47758#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 47756#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 47754#L499 assume !(0 != eval_~tmp~0#1); 45887#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45888#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46147#L599-3 assume !(0 == ~M_E~0); 46148#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46048#L604-3 assume !(0 == ~T2_E~0); 46049#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46131#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45748#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45749#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46144#L629-3 assume !(0 == ~E_1~0); 46203#L634-3 assume !(0 == ~E_2~0); 46216#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46217#L644-3 assume !(0 == ~E_4~0); 46299#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46058#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46059#L292-21 assume !(1 == ~m_pc~0); 45958#L292-23 is_master_triggered_~__retres1~0#1 := 0; 45821#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45822#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45924#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46041#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46042#L311-21 assume !(1 == ~t1_pc~0); 45970#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 45782#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45783#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45848#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45895#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45896#L330-21 assume !(1 == ~t2_pc~0); 46175#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 46286#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49533#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49532#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49531#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49530#L349-21 assume !(1 == ~t3_pc~0); 49528#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 49526#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49524#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49523#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 49521#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49520#L368-21 assume !(1 == ~t4_pc~0); 46246#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 46247#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46266#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46252#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45723#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45724#L387-21 assume !(1 == ~t5_pc~0); 45787#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 46123#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46134#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46135#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 45825#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45826#L667-3 assume !(1 == ~M_E~0); 45813#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45814#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46231#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46350#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46265#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45937#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45938#L697-3 assume !(1 == ~E_1~0); 46012#L702-3 assume !(1 == ~E_2~0); 46013#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46153#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46191#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49209#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 46300#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 45756#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 46120#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 46051#L947 assume !(0 == start_simulation_~tmp~3#1); 46052#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 48720#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 48712#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 48706#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 48698#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48688#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48681#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 48673#L960 assume !(0 != start_simulation_~tmp___0~1#1); 46215#L928-2 [2024-10-31 22:04:30,374 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:30,374 INFO L85 PathProgramCache]: Analyzing trace with hash -113006587, now seen corresponding path program 1 times [2024-10-31 22:04:30,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:30,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052353456] [2024-10-31 22:04:30,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:30,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:30,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:30,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:30,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:30,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052353456] [2024-10-31 22:04:30,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052353456] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:30,462 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:30,463 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:30,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [807050254] [2024-10-31 22:04:30,463 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:30,463 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:30,464 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:30,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1375954700, now seen corresponding path program 1 times [2024-10-31 22:04:30,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:30,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265550032] [2024-10-31 22:04:30,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:30,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:30,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:30,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:30,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:30,528 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265550032] [2024-10-31 22:04:30,529 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265550032] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:30,529 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:30,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:04:30,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510455347] [2024-10-31 22:04:30,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:30,530 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:30,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:30,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:30,530 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:30,531 INFO L87 Difference]: Start difference. First operand 3932 states and 5517 transitions. cyclomatic complexity: 1589 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:30,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:30,627 INFO L93 Difference]: Finished difference Result 4958 states and 6933 transitions. [2024-10-31 22:04:30,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4958 states and 6933 transitions. [2024-10-31 22:04:30,649 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4846 [2024-10-31 22:04:30,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4958 states to 4958 states and 6933 transitions. [2024-10-31 22:04:30,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4958 [2024-10-31 22:04:30,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4958 [2024-10-31 22:04:30,670 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4958 states and 6933 transitions. [2024-10-31 22:04:30,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:30,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4958 states and 6933 transitions. [2024-10-31 22:04:30,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4958 states and 6933 transitions. [2024-10-31 22:04:30,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4958 to 3420. [2024-10-31 22:04:30,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3420 states, 3420 states have (on average 1.4008771929824562) internal successors, (4791), 3419 states have internal predecessors, (4791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:30,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3420 states to 3420 states and 4791 transitions. [2024-10-31 22:04:30,747 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3420 states and 4791 transitions. [2024-10-31 22:04:30,747 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:30,748 INFO L425 stractBuchiCegarLoop]: Abstraction has 3420 states and 4791 transitions. [2024-10-31 22:04:30,748 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:04:30,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3420 states and 4791 transitions. [2024-10-31 22:04:30,761 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3324 [2024-10-31 22:04:30,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:30,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:30,763 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,763 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,763 INFO L745 eck$LassoCheckResult]: Stem: 54930#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 54931#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 55062#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55063#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55202#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 55005#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55006#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55181#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54978#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54979#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55176#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54974#L599 assume !(0 == ~M_E~0); 54975#L599-2 assume !(0 == ~T1_E~0); 54632#L604-1 assume !(0 == ~T2_E~0); 54621#L609-1 assume !(0 == ~T3_E~0); 54622#L614-1 assume !(0 == ~T4_E~0); 54786#L619-1 assume !(0 == ~T5_E~0); 54906#L624-1 assume !(0 == ~E_M~0); 55009#L629-1 assume !(0 == ~E_1~0); 54711#L634-1 assume !(0 == ~E_2~0); 54712#L639-1 assume !(0 == ~E_3~0); 55129#L644-1 assume !(0 == ~E_4~0); 55146#L649-1 assume !(0 == ~E_5~0); 54675#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54676#L292 assume !(1 == ~m_pc~0); 54800#L292-2 is_master_triggered_~__retres1~0#1 := 0; 54945#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54902#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54903#L743 assume !(0 != activate_threads_~tmp~1#1); 54743#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54744#L311 assume !(1 == ~t1_pc~0); 55128#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55016#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54669#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54648#L751 assume !(0 != activate_threads_~tmp___0~0#1); 54649#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55130#L330 assume !(1 == ~t2_pc~0); 54909#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54802#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54803#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55067#L759 assume !(0 != activate_threads_~tmp___1~0#1); 55197#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54787#L349 assume !(1 == ~t3_pc~0); 54788#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55098#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54623#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54624#L767 assume !(0 != activate_threads_~tmp___2~0#1); 55192#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55193#L368 assume !(1 == ~t4_pc~0); 54870#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54871#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54773#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54774#L775 assume !(0 != activate_threads_~tmp___3~0#1); 54635#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54636#L387 assume !(1 == ~t5_pc~0); 55031#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 55032#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54911#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54760#L783 assume !(0 != activate_threads_~tmp___4~0#1); 54761#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54859#L667 assume !(1 == ~M_E~0); 54938#L667-2 assume !(1 == ~T1_E~0); 55138#L672-1 assume !(1 == ~T2_E~0); 54892#L677-1 assume !(1 == ~T3_E~0); 54893#L682-1 assume !(1 == ~T4_E~0); 55111#L687-1 assume !(1 == ~T5_E~0); 55172#L692-1 assume !(1 == ~E_M~0); 55096#L697-1 assume !(1 == ~E_1~0); 55097#L702-1 assume !(1 == ~E_2~0); 55145#L707-1 assume !(1 == ~E_3~0); 54996#L712-1 assume !(1 == ~E_4~0); 54997#L717-1 assume !(1 == ~E_5~0); 55118#L722-1 assume { :end_inline_reset_delta_events } true; 54643#L928-2 [2024-10-31 22:04:30,764 INFO L747 eck$LassoCheckResult]: Loop: 54643#L928-2 assume !false; 54644#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54881#L574-1 assume !false; 54882#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55191#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57848#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 57845#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 57842#L499 assume !(0 != eval_~tmp~0#1); 57843#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58021#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58020#L599-3 assume !(0 == ~M_E~0); 58019#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 58018#L604-3 assume !(0 == ~T2_E~0); 57991#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57990#L614-3 assume !(0 == ~T4_E~0); 57989#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57988#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57987#L629-3 assume !(0 == ~E_1~0); 57986#L634-3 assume !(0 == ~E_2~0); 57985#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57984#L644-3 assume !(0 == ~E_4~0); 57983#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57982#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57981#L292-21 assume !(1 == ~m_pc~0); 57979#L292-23 is_master_triggered_~__retres1~0#1 := 0; 57978#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57977#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 57976#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57975#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57974#L311-21 assume !(1 == ~t1_pc~0); 57972#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 57970#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57969#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57968#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57967#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57965#L330-21 assume !(1 == ~t2_pc~0); 57964#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 57963#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57962#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57961#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54735#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54736#L349-21 assume 1 == ~t3_pc~0; 54992#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55238#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58017#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 58016#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55124#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54818#L368-21 assume !(1 == ~t4_pc~0); 54819#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 55149#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55164#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55153#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54625#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54626#L387-21 assume !(1 == ~t5_pc~0); 54688#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 55030#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55041#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55042#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 55169#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57786#L667-3 assume !(1 == ~M_E~0); 56927#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55133#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55134#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57685#L682-3 assume !(1 == ~T4_E~0); 55404#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55403#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55402#L697-3 assume !(1 == ~E_1~0); 55401#L702-3 assume !(1 == ~E_2~0); 55400#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55399#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55393#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55391#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55347#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55338#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55329#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 55323#L947 assume !(0 == start_simulation_~tmp~3#1); 55229#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54962#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54921#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54667#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 54668#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55136#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55137#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 55075#L960 assume !(0 != start_simulation_~tmp___0~1#1); 54643#L928-2 [2024-10-31 22:04:30,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:30,764 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2024-10-31 22:04:30,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:30,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924533643] [2024-10-31 22:04:30,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:30,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:30,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:30,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:30,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:30,800 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:30,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:30,801 INFO L85 PathProgramCache]: Analyzing trace with hash 902041777, now seen corresponding path program 1 times [2024-10-31 22:04:30,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:30,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887437467] [2024-10-31 22:04:30,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:30,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:30,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:30,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:30,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:30,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887437467] [2024-10-31 22:04:30,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887437467] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:30,865 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:30,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:04:30,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029809476] [2024-10-31 22:04:30,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:30,866 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:30,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:30,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:04:30,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:04:30,868 INFO L87 Difference]: Start difference. First operand 3420 states and 4791 transitions. cyclomatic complexity: 1375 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:30,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:30,956 INFO L93 Difference]: Finished difference Result 3476 states and 4847 transitions. [2024-10-31 22:04:30,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3476 states and 4847 transitions. [2024-10-31 22:04:30,972 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3380 [2024-10-31 22:04:30,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3476 states to 3476 states and 4847 transitions. [2024-10-31 22:04:30,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3476 [2024-10-31 22:04:31,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3476 [2024-10-31 22:04:31,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3476 states and 4847 transitions. [2024-10-31 22:04:31,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:31,019 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3476 states and 4847 transitions. [2024-10-31 22:04:31,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3476 states and 4847 transitions. [2024-10-31 22:04:31,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3476 to 3444. [2024-10-31 22:04:31,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3444 states, 3444 states have (on average 1.3980836236933798) internal successors, (4815), 3443 states have internal predecessors, (4815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:31,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3444 states to 3444 states and 4815 transitions. [2024-10-31 22:04:31,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3444 states and 4815 transitions. [2024-10-31 22:04:31,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:04:31,106 INFO L425 stractBuchiCegarLoop]: Abstraction has 3444 states and 4815 transitions. [2024-10-31 22:04:31,106 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 22:04:31,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3444 states and 4815 transitions. [2024-10-31 22:04:31,121 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3348 [2024-10-31 22:04:31,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:31,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:31,123 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:31,123 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:31,124 INFO L745 eck$LassoCheckResult]: Stem: 61838#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 61839#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 61986#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61987#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62180#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 61927#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61928#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62139#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61895#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61896#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62130#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61891#L599 assume !(0 == ~M_E~0); 61892#L599-2 assume !(0 == ~T1_E~0); 61536#L604-1 assume !(0 == ~T2_E~0); 61525#L609-1 assume !(0 == ~T3_E~0); 61526#L614-1 assume !(0 == ~T4_E~0); 61689#L619-1 assume !(0 == ~T5_E~0); 61814#L624-1 assume !(0 == ~E_M~0); 61931#L629-1 assume !(0 == ~E_1~0); 61614#L634-1 assume !(0 == ~E_2~0); 61615#L639-1 assume !(0 == ~E_3~0); 62058#L644-1 assume !(0 == ~E_4~0); 62082#L649-1 assume !(0 == ~E_5~0); 61580#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61581#L292 assume !(1 == ~m_pc~0); 61703#L292-2 is_master_triggered_~__retres1~0#1 := 0; 61859#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61810#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 61811#L743 assume !(0 != activate_threads_~tmp~1#1); 61646#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61647#L311 assume !(1 == ~t1_pc~0); 62057#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61939#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61574#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61553#L751 assume !(0 != activate_threads_~tmp___0~0#1); 61554#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62061#L330 assume !(1 == ~t2_pc~0); 61818#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61705#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61706#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61992#L759 assume !(0 != activate_threads_~tmp___1~0#1); 62176#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61690#L349 assume !(1 == ~t3_pc~0); 61691#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62212#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62248#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 62230#L767 assume !(0 != activate_threads_~tmp___2~0#1); 62166#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62167#L368 assume !(1 == ~t4_pc~0); 61777#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61778#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61675#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 61676#L775 assume !(0 != activate_threads_~tmp___3~0#1); 61539#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61540#L387 assume !(1 == ~t5_pc~0); 61955#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 61956#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61821#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61662#L783 assume !(0 != activate_threads_~tmp___4~0#1); 61663#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61762#L667 assume !(1 == ~M_E~0); 61851#L667-2 assume !(1 == ~T1_E~0); 62067#L672-1 assume !(1 == ~T2_E~0); 61800#L677-1 assume !(1 == ~T3_E~0); 61801#L682-1 assume !(1 == ~T4_E~0); 62036#L687-1 assume !(1 == ~T5_E~0); 62123#L692-1 assume !(1 == ~E_M~0); 62020#L697-1 assume !(1 == ~E_1~0); 62021#L702-1 assume !(1 == ~E_2~0); 62081#L707-1 assume !(1 == ~E_3~0); 61915#L712-1 assume !(1 == ~E_4~0); 61916#L717-1 assume !(1 == ~E_5~0); 62043#L722-1 assume { :end_inline_reset_delta_events } true; 62044#L928-2 [2024-10-31 22:04:31,124 INFO L747 eck$LassoCheckResult]: Loop: 62044#L928-2 assume !false; 62843#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 62842#L574-1 assume !false; 62837#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 62838#L452 assume !(0 == ~m_st~0); 63943#L456 assume !(0 == ~t1_st~0); 63945#L460 assume !(0 == ~t2_st~0); 63940#L464 assume !(0 == ~t3_st~0); 63942#L468 assume !(0 == ~t4_st~0); 63944#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 63938#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 63936#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 63937#L499 assume !(0 != eval_~tmp~0#1); 64941#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64940#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64939#L599-3 assume !(0 == ~M_E~0); 62035#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 61872#L604-3 assume !(0 == ~T2_E~0); 61873#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61962#L614-3 assume !(0 == ~T4_E~0); 61555#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61556#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 61974#L629-3 assume !(0 == ~E_1~0); 62031#L634-3 assume !(0 == ~E_2~0); 62045#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62046#L644-3 assume !(0 == ~E_4~0); 62170#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 61882#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61883#L292-21 assume !(1 == ~m_pc~0); 61766#L292-23 is_master_triggered_~__retres1~0#1 := 0; 61627#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61628#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 64922#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61864#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61865#L311-21 assume !(1 == ~t1_pc~0); 61781#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 61587#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61588#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61654#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62185#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64913#L330-21 assume !(1 == ~t2_pc~0); 62140#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 61970#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61971#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64907#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64905#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64903#L349-21 assume !(1 == ~t3_pc~0); 64900#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 64897#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64894#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64893#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 62173#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61722#L368-21 assume !(1 == ~t4_pc~0); 61723#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 64887#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64885#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64883#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64880#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64877#L387-21 assume 1 == ~t5_pc~0; 64874#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62070#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62071#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 64869#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 64867#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64865#L667-3 assume !(1 == ~M_E~0); 64863#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64862#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64861#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64860#L682-3 assume !(1 == ~T4_E~0); 63317#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63318#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 63311#L697-3 assume !(1 == ~E_1~0); 63312#L702-3 assume !(1 == ~E_2~0); 63305#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 63306#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63299#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63300#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 63281#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 63279#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 62397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 62398#L947 assume !(0 == start_simulation_~tmp~3#1); 64080#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 64076#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 64073#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 63152#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 63147#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63141#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63142#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 63946#L960 assume !(0 != start_simulation_~tmp___0~1#1); 62044#L928-2 [2024-10-31 22:04:31,125 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:31,125 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2024-10-31 22:04:31,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:31,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884251205] [2024-10-31 22:04:31,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:31,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:31,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:31,140 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:31,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:31,170 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:31,171 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:31,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1677399618, now seen corresponding path program 1 times [2024-10-31 22:04:31,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:31,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814635737] [2024-10-31 22:04:31,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:31,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:31,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:31,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:31,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:31,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814635737] [2024-10-31 22:04:31,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814635737] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:31,264 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:31,265 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:04:31,265 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997055414] [2024-10-31 22:04:31,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:31,265 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:31,265 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:31,266 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:04:31,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:04:31,266 INFO L87 Difference]: Start difference. First operand 3444 states and 4815 transitions. cyclomatic complexity: 1375 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:31,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:31,498 INFO L93 Difference]: Finished difference Result 3603 states and 4974 transitions. [2024-10-31 22:04:31,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3603 states and 4974 transitions. [2024-10-31 22:04:31,514 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3504 [2024-10-31 22:04:31,526 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3603 states to 3603 states and 4974 transitions. [2024-10-31 22:04:31,526 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3603 [2024-10-31 22:04:31,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3603 [2024-10-31 22:04:31,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3603 states and 4974 transitions. [2024-10-31 22:04:31,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:31,534 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3603 states and 4974 transitions. [2024-10-31 22:04:31,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3603 states and 4974 transitions. [2024-10-31 22:04:31,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3603 to 3603. [2024-10-31 22:04:31,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3603 states, 3603 states have (on average 1.3805162364696086) internal successors, (4974), 3602 states have internal predecessors, (4974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:31,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3603 states to 3603 states and 4974 transitions. [2024-10-31 22:04:31,595 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3603 states and 4974 transitions. [2024-10-31 22:04:31,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:04:31,596 INFO L425 stractBuchiCegarLoop]: Abstraction has 3603 states and 4974 transitions. [2024-10-31 22:04:31,596 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-31 22:04:31,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3603 states and 4974 transitions. [2024-10-31 22:04:31,609 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3504 [2024-10-31 22:04:31,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:31,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:31,610 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:31,610 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:31,611 INFO L745 eck$LassoCheckResult]: Stem: 68884#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 68885#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 69018#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69019#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69160#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 68959#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68960#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69135#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68933#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68934#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69129#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68929#L599 assume !(0 == ~M_E~0); 68930#L599-2 assume !(0 == ~T1_E~0); 68593#L604-1 assume !(0 == ~T2_E~0); 68580#L609-1 assume !(0 == ~T3_E~0); 68581#L614-1 assume !(0 == ~T4_E~0); 68743#L619-1 assume !(0 == ~T5_E~0); 68859#L624-1 assume !(0 == ~E_M~0); 68965#L629-1 assume !(0 == ~E_1~0); 68669#L634-1 assume !(0 == ~E_2~0); 68670#L639-1 assume !(0 == ~E_3~0); 69087#L644-1 assume !(0 == ~E_4~0); 69102#L649-1 assume !(0 == ~E_5~0); 68634#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68635#L292 assume !(1 == ~m_pc~0); 68757#L292-2 is_master_triggered_~__retres1~0#1 := 0; 68899#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68857#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68858#L743 assume !(0 != activate_threads_~tmp~1#1); 68701#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68702#L311 assume !(1 == ~t1_pc~0); 69086#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68973#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68628#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68607#L751 assume !(0 != activate_threads_~tmp___0~0#1); 68608#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69090#L330 assume !(1 == ~t2_pc~0); 68862#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68760#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68761#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 69023#L759 assume !(0 != activate_threads_~tmp___1~0#1); 69159#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68746#L349 assume !(1 == ~t3_pc~0); 68747#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69187#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68587#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68588#L767 assume !(0 != activate_threads_~tmp___2~0#1); 69150#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69151#L368 assume !(1 == ~t4_pc~0); 68826#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68827#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68730#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68731#L775 assume !(0 != activate_threads_~tmp___3~0#1); 68594#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68595#L387 assume !(1 == ~t5_pc~0); 68987#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68988#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69213#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69212#L783 assume !(0 != activate_threads_~tmp___4~0#1); 68721#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68814#L667 assume !(1 == ~M_E~0); 68891#L667-2 assume !(1 == ~T1_E~0); 69096#L672-1 assume !(1 == ~T2_E~0); 68845#L677-1 assume !(1 == ~T3_E~0); 68846#L682-1 assume !(1 == ~T4_E~0); 69065#L687-1 assume !(1 == ~T5_E~0); 69123#L692-1 assume !(1 == ~E_M~0); 69050#L697-1 assume !(1 == ~E_1~0); 69051#L702-1 assume !(1 == ~E_2~0); 69101#L707-1 assume !(1 == ~E_3~0); 68950#L712-1 assume !(1 == ~E_4~0); 68951#L717-1 assume !(1 == ~E_5~0); 69075#L722-1 assume { :end_inline_reset_delta_events } true; 69076#L928-2 [2024-10-31 22:04:31,611 INFO L747 eck$LassoCheckResult]: Loop: 69076#L928-2 assume !false; 70371#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70369#L574-1 assume !false; 70368#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 70363#L452 assume !(0 == ~m_st~0); 70364#L456 assume !(0 == ~t1_st~0); 70366#L460 assume !(0 == ~t2_st~0); 70361#L464 assume !(0 == ~t3_st~0); 70362#L468 assume !(0 == ~t4_st~0); 70365#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 70367#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 70355#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 70356#L499 assume !(0 != eval_~tmp~0#1); 70948#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70946#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70943#L599-3 assume !(0 == ~M_E~0); 70941#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 70939#L604-3 assume !(0 == ~T2_E~0); 70937#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70935#L614-3 assume !(0 == ~T4_E~0); 70933#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70931#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 70929#L629-3 assume !(0 == ~E_1~0); 70927#L634-3 assume !(0 == ~E_2~0); 70925#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70923#L644-3 assume !(0 == ~E_4~0); 70920#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70918#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70916#L292-21 assume !(1 == ~m_pc~0); 70913#L292-23 is_master_triggered_~__retres1~0#1 := 0; 70911#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70908#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 70905#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70901#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70897#L311-21 assume !(1 == ~t1_pc~0); 70893#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 70889#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70886#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 70883#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70880#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70875#L330-21 assume !(1 == ~t2_pc~0); 70846#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 70845#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70843#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 70840#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70837#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70835#L349-21 assume !(1 == ~t3_pc~0); 70833#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 70830#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70827#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70769#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 70766#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70764#L368-21 assume !(1 == ~t4_pc~0); 70761#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 70758#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70754#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 70658#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70657#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70656#L387-21 assume !(1 == ~t5_pc~0); 70653#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 70651#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70650#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70626#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 70624#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70510#L667-3 assume !(1 == ~M_E~0); 70506#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70504#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70502#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70499#L682-3 assume !(1 == ~T4_E~0); 70497#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70494#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70492#L697-3 assume !(1 == ~E_1~0); 70490#L702-3 assume !(1 == ~E_2~0); 70488#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70486#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70484#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70482#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 69362#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 69360#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 69349#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 69350#L947 assume !(0 == start_simulation_~tmp~3#1); 70428#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 70418#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 70410#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 70404#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 70399#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70394#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70386#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 70380#L960 assume !(0 != start_simulation_~tmp___0~1#1); 69076#L928-2 [2024-10-31 22:04:31,611 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:31,612 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2024-10-31 22:04:31,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:31,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53278950] [2024-10-31 22:04:31,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:31,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:31,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:31,628 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:31,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:31,661 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:31,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:31,664 INFO L85 PathProgramCache]: Analyzing trace with hash 846096703, now seen corresponding path program 1 times [2024-10-31 22:04:31,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:31,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142681383] [2024-10-31 22:04:31,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:31,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:31,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:31,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:31,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:31,750 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142681383] [2024-10-31 22:04:31,750 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [142681383] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:31,750 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:31,750 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:04:31,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025379638] [2024-10-31 22:04:31,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:31,751 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:31,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:31,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:04:31,752 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:04:31,752 INFO L87 Difference]: Start difference. First operand 3603 states and 4974 transitions. cyclomatic complexity: 1375 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:31,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:31,986 INFO L93 Difference]: Finished difference Result 3762 states and 5133 transitions. [2024-10-31 22:04:31,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3762 states and 5133 transitions. [2024-10-31 22:04:32,002 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3660 [2024-10-31 22:04:32,013 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3762 states to 3762 states and 5133 transitions. [2024-10-31 22:04:32,014 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3762 [2024-10-31 22:04:32,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3762 [2024-10-31 22:04:32,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3762 states and 5133 transitions. [2024-10-31 22:04:32,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:32,021 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3762 states and 5133 transitions. [2024-10-31 22:04:32,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3762 states and 5133 transitions. [2024-10-31 22:04:32,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3762 to 3762. [2024-10-31 22:04:32,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3762 states, 3762 states have (on average 1.3644338118022328) internal successors, (5133), 3761 states have internal predecessors, (5133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3762 states to 3762 states and 5133 transitions. [2024-10-31 22:04:32,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3762 states and 5133 transitions. [2024-10-31 22:04:32,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:04:32,083 INFO L425 stractBuchiCegarLoop]: Abstraction has 3762 states and 5133 transitions. [2024-10-31 22:04:32,083 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-31 22:04:32,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3762 states and 5133 transitions. [2024-10-31 22:04:32,096 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3660 [2024-10-31 22:04:32,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:32,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:32,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,098 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,098 INFO L745 eck$LassoCheckResult]: Stem: 76265#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 76266#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 76404#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76405#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76577#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 76344#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76345#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76544#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76315#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76316#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76539#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76311#L599 assume !(0 == ~M_E~0); 76312#L599-2 assume !(0 == ~T1_E~0); 75966#L604-1 assume !(0 == ~T2_E~0); 75953#L609-1 assume !(0 == ~T3_E~0); 75954#L614-1 assume !(0 == ~T4_E~0); 76117#L619-1 assume !(0 == ~T5_E~0); 76238#L624-1 assume !(0 == ~E_M~0); 76349#L629-1 assume !(0 == ~E_1~0); 76041#L634-1 assume !(0 == ~E_2~0); 76042#L639-1 assume !(0 == ~E_3~0); 76475#L644-1 assume !(0 == ~E_4~0); 76498#L649-1 assume !(0 == ~E_5~0); 76007#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76008#L292 assume !(1 == ~m_pc~0); 76131#L292-2 is_master_triggered_~__retres1~0#1 := 0; 76281#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76628#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 76589#L743 assume !(0 != activate_threads_~tmp~1#1); 76073#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76074#L311 assume !(1 == ~t1_pc~0); 76473#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76356#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76001#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75980#L751 assume !(0 != activate_threads_~tmp___0~0#1); 75981#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76478#L330 assume !(1 == ~t2_pc~0); 76241#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76134#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76135#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76409#L759 assume !(0 != activate_threads_~tmp___1~0#1); 76576#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76120#L349 assume !(1 == ~t3_pc~0); 76121#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76603#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75960#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 75961#L767 assume !(0 != activate_threads_~tmp___2~0#1); 76566#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76567#L368 assume !(1 == ~t4_pc~0); 76203#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76204#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76103#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76104#L775 assume !(0 != activate_threads_~tmp___3~0#1); 75967#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75968#L387 assume !(1 == ~t5_pc~0); 76368#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76369#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76629#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76627#L783 assume !(0 != activate_threads_~tmp___4~0#1); 76094#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76191#L667 assume !(1 == ~M_E~0); 76274#L667-2 assume !(1 == ~T1_E~0); 76486#L672-1 assume !(1 == ~T2_E~0); 76225#L677-1 assume !(1 == ~T3_E~0); 76226#L682-1 assume !(1 == ~T4_E~0); 76454#L687-1 assume !(1 == ~T5_E~0); 76534#L692-1 assume !(1 == ~E_M~0); 76438#L697-1 assume !(1 == ~E_1~0); 76439#L702-1 assume !(1 == ~E_2~0); 76497#L707-1 assume !(1 == ~E_3~0); 76335#L712-1 assume !(1 == ~E_4~0); 76336#L717-1 assume !(1 == ~E_5~0); 76461#L722-1 assume { :end_inline_reset_delta_events } true; 76462#L928-2 [2024-10-31 22:04:32,099 INFO L747 eck$LassoCheckResult]: Loop: 76462#L928-2 assume !false; 78191#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78188#L574-1 assume !false; 78186#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 78157#L452 assume !(0 == ~m_st~0); 78158#L456 assume !(0 == ~t1_st~0); 78160#L460 assume !(0 == ~t2_st~0); 78155#L464 assume !(0 == ~t3_st~0); 78156#L468 assume !(0 == ~t4_st~0); 78159#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 78161#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 78149#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 78150#L499 assume !(0 != eval_~tmp~0#1); 78478#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78476#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78474#L599-3 assume !(0 == ~M_E~0); 78472#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78470#L604-3 assume !(0 == ~T2_E~0); 78468#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78466#L614-3 assume !(0 == ~T4_E~0); 78464#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78462#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 78460#L629-3 assume !(0 == ~E_1~0); 78458#L634-3 assume !(0 == ~E_2~0); 78456#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78454#L644-3 assume !(0 == ~E_4~0); 78452#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78450#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78448#L292-21 assume 1 == ~m_pc~0; 78445#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 78441#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78437#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 78433#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78430#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78428#L311-21 assume !(1 == ~t1_pc~0); 78426#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 78424#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78422#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 78420#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78418#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78415#L330-21 assume !(1 == ~t2_pc~0); 78412#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 78409#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78406#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 78404#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78400#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78396#L349-21 assume 1 == ~t3_pc~0; 78393#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78388#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78384#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 78379#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78376#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78374#L368-21 assume !(1 == ~t4_pc~0); 78372#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 78370#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78363#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 78359#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78355#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78352#L387-21 assume !(1 == ~t5_pc~0); 78347#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 78341#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78335#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 78329#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 78324#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78318#L667-3 assume !(1 == ~M_E~0); 78312#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78309#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78306#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78302#L682-3 assume !(1 == ~T4_E~0); 78299#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78295#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78292#L697-3 assume !(1 == ~E_1~0); 78287#L702-3 assume !(1 == ~E_2~0); 78283#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78281#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78280#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78279#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 76570#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 75990#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 76525#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 78255#L947 assume !(0 == start_simulation_~tmp~3#1); 78249#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 78236#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 78228#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 78222#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 78215#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78210#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78204#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 78200#L960 assume !(0 != start_simulation_~tmp___0~1#1); 76462#L928-2 [2024-10-31 22:04:32,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2024-10-31 22:04:32,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835292435] [2024-10-31 22:04:32,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:32,111 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:32,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:32,129 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:32,129 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,130 INFO L85 PathProgramCache]: Analyzing trace with hash -235598597, now seen corresponding path program 1 times [2024-10-31 22:04:32,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042664224] [2024-10-31 22:04:32,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,213 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042664224] [2024-10-31 22:04:32,213 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2042664224] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,213 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,213 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:04:32,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989922486] [2024-10-31 22:04:32,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,214 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:32,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:32,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:04:32,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:04:32,215 INFO L87 Difference]: Start difference. First operand 3762 states and 5133 transitions. cyclomatic complexity: 1375 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:32,382 INFO L93 Difference]: Finished difference Result 3774 states and 5096 transitions. [2024-10-31 22:04:32,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3774 states and 5096 transitions. [2024-10-31 22:04:32,397 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3672 [2024-10-31 22:04:32,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3774 states to 3774 states and 5096 transitions. [2024-10-31 22:04:32,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3774 [2024-10-31 22:04:32,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3774 [2024-10-31 22:04:32,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3774 states and 5096 transitions. [2024-10-31 22:04:32,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:32,414 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3774 states and 5096 transitions. [2024-10-31 22:04:32,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3774 states and 5096 transitions. [2024-10-31 22:04:32,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3774 to 3774. [2024-10-31 22:04:32,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3774 states, 3774 states have (on average 1.3502914679385267) internal successors, (5096), 3773 states have internal predecessors, (5096), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3774 states to 3774 states and 5096 transitions. [2024-10-31 22:04:32,470 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3774 states and 5096 transitions. [2024-10-31 22:04:32,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:04:32,471 INFO L425 stractBuchiCegarLoop]: Abstraction has 3774 states and 5096 transitions. [2024-10-31 22:04:32,471 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-31 22:04:32,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3774 states and 5096 transitions. [2024-10-31 22:04:32,482 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3672 [2024-10-31 22:04:32,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:32,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:32,484 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,484 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,484 INFO L745 eck$LassoCheckResult]: Stem: 83805#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 83806#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 83947#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 83948#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84120#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 83885#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83886#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84092#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83859#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83860#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84087#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 83853#L599 assume !(0 == ~M_E~0); 83854#L599-2 assume !(0 == ~T1_E~0); 83510#L604-1 assume !(0 == ~T2_E~0); 83497#L609-1 assume !(0 == ~T3_E~0); 83498#L614-1 assume !(0 == ~T4_E~0); 83658#L619-1 assume !(0 == ~T5_E~0); 83779#L624-1 assume !(0 == ~E_M~0); 83891#L629-1 assume !(0 == ~E_1~0); 83584#L634-1 assume !(0 == ~E_2~0); 83585#L639-1 assume !(0 == ~E_3~0); 84014#L644-1 assume !(0 == ~E_4~0); 84040#L649-1 assume !(0 == ~E_5~0); 83551#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83552#L292 assume !(1 == ~m_pc~0); 83672#L292-2 is_master_triggered_~__retres1~0#1 := 0; 83823#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84172#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 84135#L743 assume !(0 != activate_threads_~tmp~1#1); 83616#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83617#L311 assume !(1 == ~t1_pc~0); 84013#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83899#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83545#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 83524#L751 assume !(0 != activate_threads_~tmp___0~0#1); 83525#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84017#L330 assume !(1 == ~t2_pc~0); 83783#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83675#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 83952#L759 assume !(0 != activate_threads_~tmp___1~0#1); 84118#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83661#L349 assume !(1 == ~t3_pc~0); 83662#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84154#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83504#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 83505#L767 assume !(0 != activate_threads_~tmp___2~0#1); 84109#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84110#L368 assume !(1 == ~t4_pc~0); 83744#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 83745#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83645#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 83646#L775 assume !(0 != activate_threads_~tmp___3~0#1); 83511#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83512#L387 assume !(1 == ~t5_pc~0); 83911#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 83912#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84173#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84171#L783 assume !(0 != activate_threads_~tmp___4~0#1); 83636#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83732#L667 assume !(1 == ~M_E~0); 83815#L667-2 assume !(1 == ~T1_E~0); 84027#L672-1 assume !(1 == ~T2_E~0); 83764#L677-1 assume !(1 == ~T3_E~0); 83765#L682-1 assume !(1 == ~T4_E~0); 83992#L687-1 assume !(1 == ~T5_E~0); 84081#L692-1 assume !(1 == ~E_M~0); 83978#L697-1 assume !(1 == ~E_1~0); 83979#L702-1 assume !(1 == ~E_2~0); 84037#L707-1 assume !(1 == ~E_3~0); 83876#L712-1 assume !(1 == ~E_4~0); 83877#L717-1 assume !(1 == ~E_5~0); 83999#L722-1 assume { :end_inline_reset_delta_events } true; 84000#L928-2 [2024-10-31 22:04:32,485 INFO L747 eck$LassoCheckResult]: Loop: 84000#L928-2 assume !false; 84795#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84789#L574-1 assume !false; 84787#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 84785#L452 assume !(0 == ~m_st~0); 84783#L456 assume !(0 == ~t1_st~0); 84781#L460 assume !(0 == ~t2_st~0); 84779#L464 assume !(0 == ~t3_st~0); 84777#L468 assume !(0 == ~t4_st~0); 84774#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 84771#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 84769#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 84767#L499 assume !(0 != eval_~tmp~0#1); 84764#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 84762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 84760#L599-3 assume !(0 == ~M_E~0); 84758#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 84756#L604-3 assume !(0 == ~T2_E~0); 84754#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 84752#L614-3 assume !(0 == ~T4_E~0); 84750#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 84748#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 84746#L629-3 assume !(0 == ~E_1~0); 84744#L634-3 assume !(0 == ~E_2~0); 84742#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84740#L644-3 assume !(0 == ~E_4~0); 84738#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 84736#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84734#L292-21 assume 1 == ~m_pc~0; 84731#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 84727#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84723#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 84719#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 84716#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84714#L311-21 assume !(1 == ~t1_pc~0); 84712#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 84710#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84708#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 84706#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 84704#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84701#L330-21 assume !(1 == ~t2_pc~0); 84698#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 84696#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84694#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84692#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 84690#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84688#L349-21 assume 1 == ~t3_pc~0; 84685#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 84681#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84677#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 84673#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 84670#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84668#L368-21 assume !(1 == ~t4_pc~0); 84666#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 84664#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84662#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 84660#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 84658#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84656#L387-21 assume !(1 == ~t5_pc~0); 84653#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 84649#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84645#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84641#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 84638#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84636#L667-3 assume !(1 == ~M_E~0); 84633#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84632#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84630#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84627#L682-3 assume !(1 == ~T4_E~0); 84628#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 85099#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84618#L697-3 assume !(1 == ~E_1~0); 84610#L702-3 assume !(1 == ~E_2~0); 84611#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85093#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85091#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 84585#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 84586#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 84564#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 84565#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 84984#L947 assume !(0 == start_simulation_~tmp~3#1); 84977#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 84891#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 84887#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 84878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 84817#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 84813#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 84811#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 84809#L960 assume !(0 != start_simulation_~tmp___0~1#1); 84000#L928-2 [2024-10-31 22:04:32,485 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,485 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2024-10-31 22:04:32,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,486 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697302788] [2024-10-31 22:04:32,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:32,497 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:32,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:32,514 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:32,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,515 INFO L85 PathProgramCache]: Analyzing trace with hash 2030782589, now seen corresponding path program 1 times [2024-10-31 22:04:32,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302939496] [2024-10-31 22:04:32,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302939496] [2024-10-31 22:04:32,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302939496] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:04:32,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116172282] [2024-10-31 22:04:32,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,616 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:32,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:32,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:04:32,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:04:32,617 INFO L87 Difference]: Start difference. First operand 3774 states and 5096 transitions. cyclomatic complexity: 1326 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:32,772 INFO L93 Difference]: Finished difference Result 3786 states and 5059 transitions. [2024-10-31 22:04:32,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3786 states and 5059 transitions. [2024-10-31 22:04:32,785 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3684 [2024-10-31 22:04:32,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3786 states to 3786 states and 5059 transitions. [2024-10-31 22:04:32,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3786 [2024-10-31 22:04:32,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3786 [2024-10-31 22:04:32,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3786 states and 5059 transitions. [2024-10-31 22:04:32,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:32,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3786 states and 5059 transitions. [2024-10-31 22:04:32,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3786 states and 5059 transitions. [2024-10-31 22:04:32,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3786 to 3786. [2024-10-31 22:04:32,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3786 states, 3786 states have (on average 1.3362387744321182) internal successors, (5059), 3785 states have internal predecessors, (5059), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3786 states to 3786 states and 5059 transitions. [2024-10-31 22:04:32,856 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3786 states and 5059 transitions. [2024-10-31 22:04:32,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:04:32,857 INFO L425 stractBuchiCegarLoop]: Abstraction has 3786 states and 5059 transitions. [2024-10-31 22:04:32,857 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-31 22:04:32,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3786 states and 5059 transitions. [2024-10-31 22:04:32,867 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3684 [2024-10-31 22:04:32,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:32,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:32,869 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,869 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,869 INFO L745 eck$LassoCheckResult]: Stem: 91375#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 91376#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 91512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 91513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91690#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 91452#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91453#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91659#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91427#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91428#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91648#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91421#L599 assume !(0 == ~M_E~0); 91422#L599-2 assume !(0 == ~T1_E~0); 91078#L604-1 assume !(0 == ~T2_E~0); 91065#L609-1 assume !(0 == ~T3_E~0); 91066#L614-1 assume !(0 == ~T4_E~0); 91228#L619-1 assume !(0 == ~T5_E~0); 91351#L624-1 assume !(0 == ~E_M~0); 91457#L629-1 assume !(0 == ~E_1~0); 91152#L634-1 assume !(0 == ~E_2~0); 91153#L639-1 assume !(0 == ~E_3~0); 91586#L644-1 assume !(0 == ~E_4~0); 91608#L649-1 assume !(0 == ~E_5~0); 91119#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91120#L292 assume !(1 == ~m_pc~0); 91242#L292-2 is_master_triggered_~__retres1~0#1 := 0; 91393#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91746#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 91702#L743 assume !(0 != activate_threads_~tmp~1#1); 91184#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91185#L311 assume !(1 == ~t1_pc~0); 91585#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 91465#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91113#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 91092#L751 assume !(0 != activate_threads_~tmp___0~0#1); 91093#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91587#L330 assume !(1 == ~t2_pc~0); 91354#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 91245#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91246#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 91517#L759 assume !(0 != activate_threads_~tmp___1~0#1); 91689#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91229#L349 assume !(1 == ~t3_pc~0); 91230#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 91721#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91072#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 91073#L767 assume !(0 != activate_threads_~tmp___2~0#1); 91680#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91681#L368 assume !(1 == ~t4_pc~0); 91315#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 91316#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91214#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 91215#L775 assume !(0 != activate_threads_~tmp___3~0#1); 91079#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 91080#L387 assume !(1 == ~t5_pc~0); 91478#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 91479#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 91747#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 91745#L783 assume !(0 != activate_threads_~tmp___4~0#1); 91205#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91301#L667 assume !(1 == ~M_E~0); 91384#L667-2 assume !(1 == ~T1_E~0); 91598#L672-1 assume !(1 == ~T2_E~0); 91336#L677-1 assume !(1 == ~T3_E~0); 91337#L682-1 assume !(1 == ~T4_E~0); 91565#L687-1 assume !(1 == ~T5_E~0); 91644#L692-1 assume !(1 == ~E_M~0); 91549#L697-1 assume !(1 == ~E_1~0); 91550#L702-1 assume !(1 == ~E_2~0); 91606#L707-1 assume !(1 == ~E_3~0); 91444#L712-1 assume !(1 == ~E_4~0); 91445#L717-1 assume !(1 == ~E_5~0); 91572#L722-1 assume { :end_inline_reset_delta_events } true; 91573#L928-2 [2024-10-31 22:04:32,869 INFO L747 eck$LassoCheckResult]: Loop: 91573#L928-2 assume !false; 94617#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 94615#L574-1 assume !false; 94614#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 94609#L452 assume !(0 == ~m_st~0); 94610#L456 assume !(0 == ~t1_st~0); 94612#L460 assume !(0 == ~t2_st~0); 94607#L464 assume !(0 == ~t3_st~0); 94608#L468 assume !(0 == ~t4_st~0); 94611#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 94613#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 94755#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 94753#L499 assume !(0 != eval_~tmp~0#1); 94751#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94749#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94748#L599-3 assume !(0 == ~M_E~0); 94745#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94744#L604-3 assume !(0 == ~T2_E~0); 94743#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 94735#L614-3 assume !(0 == ~T4_E~0); 94734#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94733#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 94731#L629-3 assume !(0 == ~E_1~0); 94730#L634-3 assume !(0 == ~E_2~0); 94729#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 94727#L644-3 assume !(0 == ~E_4~0); 94725#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94724#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94723#L292-21 assume !(1 == ~m_pc~0); 94720#L292-23 is_master_triggered_~__retres1~0#1 := 0; 94718#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94717#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 94715#L743-21 assume !(0 != activate_threads_~tmp~1#1); 94714#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94601#L311-21 assume !(1 == ~t1_pc~0); 94602#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 94795#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94793#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94791#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 94790#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94788#L330-21 assume !(1 == ~t2_pc~0); 94785#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 94783#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94781#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 94780#L759-21 assume !(0 != activate_threads_~tmp___1~0#1); 94778#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91439#L349-21 assume !(1 == ~t3_pc~0); 91441#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 91623#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91634#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 91579#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 91580#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91260#L368-21 assume !(1 == ~t4_pc~0); 91261#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 91610#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91632#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 91616#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 91070#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 91071#L387-21 assume !(1 == ~t5_pc~0); 91131#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 94523#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94524#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94516#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 91640#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91396#L667-3 assume !(1 == ~M_E~0); 91157#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 91158#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 91236#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 91237#L682-3 assume !(1 == ~T4_E~0); 92127#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 92116#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 92117#L697-3 assume !(1 == ~E_1~0); 92105#L702-3 assume !(1 == ~E_2~0); 92106#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 92091#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 92092#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 92080#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 92081#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 94650#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 94649#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 94648#L947 assume !(0 == start_simulation_~tmp~3#1); 94646#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 94638#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 94634#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 94632#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 94629#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 94627#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 94624#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 94622#L960 assume !(0 != start_simulation_~tmp___0~1#1); 91573#L928-2 [2024-10-31 22:04:32,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,870 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2024-10-31 22:04:32,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968546991] [2024-10-31 22:04:32,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:32,880 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:32,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:32,896 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:32,897 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,897 INFO L85 PathProgramCache]: Analyzing trace with hash 971914181, now seen corresponding path program 1 times [2024-10-31 22:04:32,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655175247] [2024-10-31 22:04:32,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,942 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1655175247] [2024-10-31 22:04:32,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1655175247] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:32,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923998720] [2024-10-31 22:04:32,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,943 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:32,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:32,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:32,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:32,944 INFO L87 Difference]: Start difference. First operand 3786 states and 5059 transitions. cyclomatic complexity: 1277 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:33,018 INFO L93 Difference]: Finished difference Result 7022 states and 9239 transitions. [2024-10-31 22:04:33,018 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7022 states and 9239 transitions. [2024-10-31 22:04:33,042 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6904 [2024-10-31 22:04:33,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7022 states to 7022 states and 9239 transitions. [2024-10-31 22:04:33,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7022 [2024-10-31 22:04:33,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7022 [2024-10-31 22:04:33,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7022 states and 9239 transitions. [2024-10-31 22:04:33,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:33,074 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7022 states and 9239 transitions. [2024-10-31 22:04:33,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7022 states and 9239 transitions. [2024-10-31 22:04:33,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7022 to 6674. [2024-10-31 22:04:33,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6674 states, 6674 states have (on average 1.3195984417141144) internal successors, (8807), 6673 states have internal predecessors, (8807), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6674 states to 6674 states and 8807 transitions. [2024-10-31 22:04:33,165 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6674 states and 8807 transitions. [2024-10-31 22:04:33,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:33,165 INFO L425 stractBuchiCegarLoop]: Abstraction has 6674 states and 8807 transitions. [2024-10-31 22:04:33,165 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-31 22:04:33,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6674 states and 8807 transitions. [2024-10-31 22:04:33,220 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6556 [2024-10-31 22:04:33,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:33,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:33,222 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,222 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,222 INFO L745 eck$LassoCheckResult]: Stem: 102189#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 102190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 102337#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 102338#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102498#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 102272#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102273#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102473#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102242#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102243#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 102465#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102238#L599 assume !(0 == ~M_E~0); 102239#L599-2 assume !(0 == ~T1_E~0); 101892#L604-1 assume !(0 == ~T2_E~0); 101879#L609-1 assume !(0 == ~T3_E~0); 101880#L614-1 assume !(0 == ~T4_E~0); 102042#L619-1 assume !(0 == ~T5_E~0); 102163#L624-1 assume !(0 == ~E_M~0); 102278#L629-1 assume !(0 == ~E_1~0); 101967#L634-1 assume !(0 == ~E_2~0); 101968#L639-1 assume !(0 == ~E_3~0); 102406#L644-1 assume !(0 == ~E_4~0); 102428#L649-1 assume !(0 == ~E_5~0); 101933#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101934#L292 assume !(1 == ~m_pc~0); 102056#L292-2 is_master_triggered_~__retres1~0#1 := 0; 102208#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102330#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102509#L743 assume !(0 != activate_threads_~tmp~1#1); 101999#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102000#L311 assume !(1 == ~t1_pc~0); 102405#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102287#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101927#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 101906#L751 assume !(0 != activate_threads_~tmp___0~0#1); 101907#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102409#L330 assume !(1 == ~t2_pc~0); 102167#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 102059#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102060#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 102342#L759 assume !(0 != activate_threads_~tmp___1~0#1); 102495#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102045#L349 assume !(1 == ~t3_pc~0); 102046#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102371#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102372#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 102536#L767 assume !(0 != activate_threads_~tmp___2~0#1); 102487#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102488#L368 assume !(1 == ~t4_pc~0); 102129#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 102130#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102028#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 102029#L775 assume !(0 != activate_threads_~tmp___3~0#1); 101893#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101894#L387 assume !(1 == ~t5_pc~0); 102301#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 102302#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102169#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 102170#L783 assume !(0 != activate_threads_~tmp___4~0#1); 102019#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102114#L667 assume !(1 == ~M_E~0); 102198#L667-2 assume !(1 == ~T1_E~0); 102416#L672-1 assume !(1 == ~T2_E~0); 102149#L677-1 assume !(1 == ~T3_E~0); 102150#L682-1 assume !(1 == ~T4_E~0); 102384#L687-1 assume !(1 == ~T5_E~0); 102458#L692-1 assume !(1 == ~E_M~0); 102369#L697-1 assume !(1 == ~E_1~0); 102370#L702-1 assume !(1 == ~E_2~0); 102426#L707-1 assume !(1 == ~E_3~0); 102260#L712-1 assume !(1 == ~E_4~0); 102261#L717-1 assume !(1 == ~E_5~0); 102391#L722-1 assume { :end_inline_reset_delta_events } true; 102392#L928-2 [2024-10-31 22:04:33,223 INFO L747 eck$LassoCheckResult]: Loop: 102392#L928-2 assume !false; 105746#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105743#L574-1 assume !false; 105741#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105737#L452 assume !(0 == ~m_st~0); 105738#L456 assume !(0 == ~t1_st~0); 105824#L460 assume !(0 == ~t2_st~0); 105822#L464 assume !(0 == ~t3_st~0); 105819#L468 assume !(0 == ~t4_st~0); 105816#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 105814#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 105811#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 105808#L499 assume !(0 != eval_~tmp~0#1); 105806#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105805#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 105803#L599-3 assume !(0 == ~M_E~0); 105801#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 105799#L604-3 assume !(0 == ~T2_E~0); 105797#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 105795#L614-3 assume !(0 == ~T4_E~0); 105793#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 105791#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 105789#L629-3 assume !(0 == ~E_1~0); 105787#L634-3 assume !(0 == ~E_2~0); 105785#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 105783#L644-3 assume !(0 == ~E_4~0); 105773#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 105772#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105759#L292-21 assume 1 == ~m_pc~0; 105749#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 105744#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105742#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 105739#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 105736#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105734#L311-21 assume !(1 == ~t1_pc~0); 105732#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 105730#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105727#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105725#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 105723#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105719#L330-21 assume !(1 == ~t2_pc~0); 105715#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 105713#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105711#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105709#L759-21 assume !(0 != activate_threads_~tmp___1~0#1); 105707#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105706#L349-21 assume !(1 == ~t3_pc~0); 105702#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 105700#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105698#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105696#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 105693#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105691#L368-21 assume !(1 == ~t4_pc~0); 105674#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 105670#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105665#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105659#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 105656#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105652#L387-21 assume !(1 == ~t5_pc~0); 105647#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 105667#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105662#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 105631#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 105629#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105627#L667-3 assume !(1 == ~M_E~0); 105165#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 105624#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 105622#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 105618#L682-3 assume !(1 == ~T4_E~0); 105615#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 105613#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 105611#L697-3 assume !(1 == ~E_1~0); 105609#L702-3 assume !(1 == ~E_2~0); 105607#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 105605#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 105601#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 105599#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105596#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 105594#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 105574#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 105568#L947 assume !(0 == start_simulation_~tmp~3#1); 105569#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 106054#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 106050#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106044#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 106040#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 105869#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 105778#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 105767#L960 assume !(0 != start_simulation_~tmp___0~1#1); 102392#L928-2 [2024-10-31 22:04:33,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,223 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 8 times [2024-10-31 22:04:33,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769407610] [2024-10-31 22:04:33,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:33,234 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:33,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:33,250 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:33,250 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,251 INFO L85 PathProgramCache]: Analyzing trace with hash -1317535230, now seen corresponding path program 1 times [2024-10-31 22:04:33,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873388246] [2024-10-31 22:04:33,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:33,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:33,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:33,334 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [873388246] [2024-10-31 22:04:33,334 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [873388246] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:33,334 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:33,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:04:33,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1632444467] [2024-10-31 22:04:33,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:33,335 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:33,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:33,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:04:33,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:04:33,336 INFO L87 Difference]: Start difference. First operand 6674 states and 8807 transitions. cyclomatic complexity: 2137 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:33,554 INFO L93 Difference]: Finished difference Result 6830 states and 8918 transitions. [2024-10-31 22:04:33,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6830 states and 8918 transitions. [2024-10-31 22:04:33,581 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6712 [2024-10-31 22:04:33,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6830 states to 6830 states and 8918 transitions. [2024-10-31 22:04:33,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6830 [2024-10-31 22:04:33,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6830 [2024-10-31 22:04:33,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6830 states and 8918 transitions. [2024-10-31 22:04:33,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:33,616 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6830 states and 8918 transitions. [2024-10-31 22:04:33,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6830 states and 8918 transitions. [2024-10-31 22:04:33,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6830 to 6830. [2024-10-31 22:04:33,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6830 states, 6830 states have (on average 1.305710102489019) internal successors, (8918), 6829 states have internal predecessors, (8918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6830 states to 6830 states and 8918 transitions. [2024-10-31 22:04:33,725 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6830 states and 8918 transitions. [2024-10-31 22:04:33,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:04:33,725 INFO L425 stractBuchiCegarLoop]: Abstraction has 6830 states and 8918 transitions. [2024-10-31 22:04:33,726 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-31 22:04:33,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6830 states and 8918 transitions. [2024-10-31 22:04:33,753 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6712 [2024-10-31 22:04:33,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:33,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:33,755 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,755 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,756 INFO L745 eck$LassoCheckResult]: Stem: 115703#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 115704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 115843#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115844#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116005#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 115779#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115780#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115978#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115751#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115752#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115970#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115747#L599 assume !(0 == ~M_E~0); 115748#L599-2 assume !(0 == ~T1_E~0); 115404#L604-1 assume !(0 == ~T2_E~0); 115391#L609-1 assume !(0 == ~T3_E~0); 115392#L614-1 assume !(0 == ~T4_E~0); 115553#L619-1 assume !(0 == ~T5_E~0); 115678#L624-1 assume !(0 == ~E_M~0); 115784#L629-1 assume !(0 == ~E_1~0); 115478#L634-1 assume !(0 == ~E_2~0); 115479#L639-1 assume !(0 == ~E_3~0); 115912#L644-1 assume !(0 == ~E_4~0); 115929#L649-1 assume !(0 == ~E_5~0); 115445#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115446#L292 assume !(1 == ~m_pc~0); 115567#L292-2 is_master_triggered_~__retres1~0#1 := 0; 115720#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115836#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116016#L743 assume !(0 != activate_threads_~tmp~1#1); 115510#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115511#L311 assume !(1 == ~t1_pc~0); 115911#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115792#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115439#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115418#L751 assume !(0 != activate_threads_~tmp___0~0#1); 115419#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115914#L330 assume !(1 == ~t2_pc~0); 115681#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 115569#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115570#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 115848#L759 assume !(0 != activate_threads_~tmp___1~0#1); 116003#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115554#L349 assume !(1 == ~t3_pc~0); 115555#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 115876#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115877#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116040#L767 assume !(0 != activate_threads_~tmp___2~0#1); 115995#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 115996#L368 assume !(1 == ~t4_pc~0); 115641#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 115642#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115539#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 115540#L775 assume !(0 != activate_threads_~tmp___3~0#1); 115405#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115406#L387 assume !(1 == ~t5_pc~0); 115807#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 115808#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115683#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 115684#L783 assume !(0 != activate_threads_~tmp___4~0#1); 115530#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115629#L667 assume !(1 == ~M_E~0); 115713#L667-2 assume !(1 == ~T1_E~0); 115921#L672-1 assume !(1 == ~T2_E~0); 115665#L677-1 assume !(1 == ~T3_E~0); 115666#L682-1 assume !(1 == ~T4_E~0); 115889#L687-1 assume !(1 == ~T5_E~0); 115966#L692-1 assume !(1 == ~E_M~0); 115874#L697-1 assume !(1 == ~E_1~0); 115875#L702-1 assume !(1 == ~E_2~0); 115928#L707-1 assume !(1 == ~E_3~0); 115769#L712-1 assume !(1 == ~E_4~0); 115770#L717-1 assume !(1 == ~E_5~0); 115896#L722-1 assume { :end_inline_reset_delta_events } true; 115897#L928-2 [2024-10-31 22:04:33,756 INFO L747 eck$LassoCheckResult]: Loop: 115897#L928-2 assume !false; 117591#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117586#L574-1 assume !false; 117584#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 117581#L452 assume !(0 == ~m_st~0); 117582#L456 assume !(0 == ~t1_st~0); 118613#L460 assume !(0 == ~t2_st~0); 118611#L464 assume !(0 == ~t3_st~0); 118609#L468 assume !(0 == ~t4_st~0); 118606#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 118604#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118600#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 118597#L499 assume !(0 != eval_~tmp~0#1); 118595#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 118593#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 118590#L599-3 assume !(0 == ~M_E~0); 118588#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 118586#L604-3 assume !(0 == ~T2_E~0); 118584#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 118582#L614-3 assume !(0 == ~T4_E~0); 118580#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 118578#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 118576#L629-3 assume !(0 == ~E_1~0); 118572#L634-3 assume !(0 == ~E_2~0); 118570#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 118568#L644-3 assume !(0 == ~E_4~0); 118566#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 118563#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118561#L292-21 assume 1 == ~m_pc~0; 118556#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 118554#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118552#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 118548#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 118547#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118546#L311-21 assume !(1 == ~t1_pc~0); 118544#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 118541#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118539#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 118537#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 118536#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118534#L330-21 assume !(1 == ~t2_pc~0); 118533#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 118532#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118530#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118528#L759-21 assume !(0 != activate_threads_~tmp___1~0#1); 118527#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118526#L349-21 assume !(1 == ~t3_pc~0); 118523#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 118521#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118520#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118519#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 118516#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118515#L368-21 assume !(1 == ~t4_pc~0); 118514#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 118510#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118508#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 118506#L775-21 assume !(0 != activate_threads_~tmp___3~0#1); 118504#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118501#L387-21 assume !(1 == ~t5_pc~0); 118499#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 118531#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118529#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 118491#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 118489#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118487#L667-3 assume !(1 == ~M_E~0); 118376#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 118484#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 118481#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 118479#L682-3 assume !(1 == ~T4_E~0); 118477#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 118476#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 118473#L697-3 assume !(1 == ~E_1~0); 118471#L702-3 assume !(1 == ~E_2~0); 118467#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 118465#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 118463#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 118462#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 118460#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 117626#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 117623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 117618#L947 assume !(0 == start_simulation_~tmp~3#1); 117616#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 117611#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 117608#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 117604#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 117602#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117600#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117599#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 117596#L960 assume !(0 != start_simulation_~tmp___0~1#1); 115897#L928-2 [2024-10-31 22:04:33,757 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,757 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 9 times [2024-10-31 22:04:33,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122444995] [2024-10-31 22:04:33,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:33,769 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:33,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:33,786 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:33,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,787 INFO L85 PathProgramCache]: Analyzing trace with hash -1389921788, now seen corresponding path program 1 times [2024-10-31 22:04:33,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341461088] [2024-10-31 22:04:33,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:33,800 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:33,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:33,817 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:33,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,817 INFO L85 PathProgramCache]: Analyzing trace with hash 508394048, now seen corresponding path program 1 times [2024-10-31 22:04:33,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735817126] [2024-10-31 22:04:33,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:33,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:33,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:33,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735817126] [2024-10-31 22:04:33,916 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735817126] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:33,916 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:33,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:33,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440035853] [2024-10-31 22:04:33,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:35,491 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:35,493 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:35,493 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:35,493 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:35,493 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-31 22:04:35,493 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:35,494 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:35,494 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:35,494 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-1.c_Iteration22_Loop [2024-10-31 22:04:35,494 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:35,494 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:35,529 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,549 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,556 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,559 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,582 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,585 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,593 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,602 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,609 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,612 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,615 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,619 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,623 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,631 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,638 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,647 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,668 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,673 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,699 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,727 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,767 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,769 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,776 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,789 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,821 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,823 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,829 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,832 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,841 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,844 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:35,856 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,444 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:36,446 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-31 22:04:36,448 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:36,448 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:36,450 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:36,452 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-31 22:04:36,454 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:36,454 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:36,477 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:04:36,477 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:04:36,495 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-10-31 22:04:36,496 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:36,497 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:36,500 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:36,501 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-31 22:04:36,503 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:36,503 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:36,531 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:04:36,531 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:04:36,550 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-10-31 22:04:36,550 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:36,551 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:36,552 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:36,554 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-31 22:04:36,555 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:36,555 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:36,573 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:04:36,573 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:04:36,592 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-10-31 22:04:36,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:36,593 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:36,596 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:36,600 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-31 22:04:36,605 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:36,605 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:36,630 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:04:36,630 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:04:36,648 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:36,648 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:36,649 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:36,650 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:36,651 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-10-31 22:04:36,653 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:04:36,653 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:36,687 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-10-31 22:04:36,688 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:36,688 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:36,690 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:36,692 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-10-31 22:04:36,693 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-31 22:04:36,693 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:04:36,712 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-31 22:04:36,731 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-10-31 22:04:36,731 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:04:36,731 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:04:36,731 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:04:36,731 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:04:36,732 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-31 22:04:36,732 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:36,732 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:04:36,732 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:04:36,732 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-1.c_Iteration22_Loop [2024-10-31 22:04:36,732 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:04:36,732 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:04:36,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,752 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,759 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,761 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,767 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,770 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,773 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,775 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,781 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,787 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,791 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,821 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,828 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,844 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,849 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,852 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,861 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,897 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,911 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,915 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,918 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,927 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,930 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,943 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,946 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,954 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,962 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,965 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,967 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,970 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,978 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,981 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,992 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:36,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:37,001 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:04:37,560 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:04:37,567 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-31 22:04:37,569 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:37,570 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:37,572 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:37,574 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-10-31 22:04:37,575 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:37,590 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:37,590 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:04:37,591 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:37,591 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:37,591 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:37,593 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:04:37,593 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:04:37,595 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:04:37,613 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-10-31 22:04:37,614 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:37,614 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:37,616 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:37,618 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-10-31 22:04:37,619 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:37,633 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:37,634 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:04:37,634 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:37,634 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-31 22:04:37,634 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:37,637 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-31 22:04:37,637 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:04:37,640 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:04:37,657 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-10-31 22:04:37,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:37,658 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:37,660 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:37,661 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-10-31 22:04:37,662 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:37,676 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:37,677 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:04:37,677 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:37,677 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:37,677 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:37,678 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:04:37,678 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:04:37,683 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:04:37,700 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-10-31 22:04:37,701 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:37,701 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:37,703 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:37,706 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-10-31 22:04:37,708 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:37,722 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:37,722 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:04:37,722 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:37,723 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:37,723 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:37,723 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:04:37,724 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:04:37,726 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:04:37,744 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:37,745 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:37,745 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:37,747 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:37,748 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-10-31 22:04:37,749 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:04:37,763 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:04:37,763 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:04:37,763 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:04:37,763 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:04:37,763 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:04:37,765 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:04:37,765 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:04:37,768 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-31 22:04:37,771 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-31 22:04:37,772 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-31 22:04:37,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:37,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:37,780 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:37,782 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-10-31 22:04:37,783 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-31 22:04:37,783 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-31 22:04:37,783 INFO L474 LassoAnalysis]: Proved termination. [2024-10-31 22:04:37,784 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2024-10-31 22:04:37,803 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-10-31 22:04:37,805 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-31 22:04:37,832 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:37,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:37,891 INFO L255 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:04:37,893 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:38,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:38,087 INFO L255 TraceCheckSpWp]: Trace formula consists of 184 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-31 22:04:38,089 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:04:38,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:38,367 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-10-31 22:04:38,369 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 6830 states and 8918 transitions. cyclomatic complexity: 2092 Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:38,641 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 6830 states and 8918 transitions. cyclomatic complexity: 2092. Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 18720 states and 24649 transitions. Complement of second has 5 states. [2024-10-31 22:04:38,643 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:04:38,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:38,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 717 transitions. [2024-10-31 22:04:38,646 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 717 transitions. Stem has 73 letters. Loop has 89 letters. [2024-10-31 22:04:38,649 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:38,649 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 717 transitions. Stem has 162 letters. Loop has 89 letters. [2024-10-31 22:04:38,651 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:38,651 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 717 transitions. Stem has 73 letters. Loop has 178 letters. [2024-10-31 22:04:38,654 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:04:38,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18720 states and 24649 transitions. [2024-10-31 22:04:38,812 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_145f3f5d-c48f-4dbe-8fdd-4b514d9b7489/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-10-31 22:04:38,850 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12568 [2024-10-31 22:04:38,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18720 states to 18704 states and 24633 transitions. [2024-10-31 22:04:38,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12735 [2024-10-31 22:04:38,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12776 [2024-10-31 22:04:38,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18704 states and 24633 transitions. [2024-10-31 22:04:38,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:38,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18704 states and 24633 transitions. [2024-10-31 22:04:38,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18704 states and 24633 transitions. [2024-10-31 22:04:39,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18704 to 18647. [2024-10-31 22:04:39,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18647 states, 18647 states have (on average 1.3158148763876227) internal successors, (24536), 18646 states have internal predecessors, (24536), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:39,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18647 states to 18647 states and 24536 transitions. [2024-10-31 22:04:39,276 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18647 states and 24536 transitions. [2024-10-31 22:04:39,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:39,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:39,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:39,277 INFO L87 Difference]: Start difference. First operand 18647 states and 24536 transitions. Second operand has 3 states, 3 states have (on average 54.0) internal successors, (162), 3 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:39,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:39,455 INFO L93 Difference]: Finished difference Result 19727 states and 25760 transitions. [2024-10-31 22:04:39,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19727 states and 25760 transitions. [2024-10-31 22:04:39,657 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13288 [2024-10-31 22:04:39,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19727 states to 19727 states and 25760 transitions. [2024-10-31 22:04:39,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13439 [2024-10-31 22:04:39,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13439 [2024-10-31 22:04:39,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19727 states and 25760 transitions. [2024-10-31 22:04:39,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:39,813 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19727 states and 25760 transitions. [2024-10-31 22:04:39,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19727 states and 25760 transitions. [2024-10-31 22:04:40,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19727 to 18647. [2024-10-31 22:04:40,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18647 states, 18647 states have (on average 1.3106665951627607) internal successors, (24440), 18646 states have internal predecessors, (24440), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:40,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18647 states to 18647 states and 24440 transitions. [2024-10-31 22:04:40,273 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18647 states and 24440 transitions. [2024-10-31 22:04:40,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:40,274 INFO L425 stractBuchiCegarLoop]: Abstraction has 18647 states and 24440 transitions. [2024-10-31 22:04:40,274 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-31 22:04:40,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18647 states and 24440 transitions. [2024-10-31 22:04:40,339 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12568 [2024-10-31 22:04:40,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:40,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:40,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:40,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:40,342 INFO L745 eck$LassoCheckResult]: Stem: 180389#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 180390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 180648#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 180649#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180942#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 180530#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 180531#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 180889#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 180483#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 180484#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 180881#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 180477#L599 assume !(0 == ~M_E~0); 180478#L599-2 assume !(0 == ~T1_E~0); 179851#L604-1 assume !(0 == ~T2_E~0); 179829#L609-1 assume !(0 == ~T3_E~0); 179830#L614-1 assume !(0 == ~T4_E~0); 180130#L619-1 assume !(0 == ~T5_E~0); 180344#L624-1 assume !(0 == ~E_M~0); 180539#L629-1 assume !(0 == ~E_1~0); 179992#L634-1 assume !(0 == ~E_2~0); 179993#L639-1 assume !(0 == ~E_3~0); 180772#L644-1 assume !(0 == ~E_4~0); 180803#L649-1 assume !(0 == ~E_5~0); 179928#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 179929#L292 assume !(1 == ~m_pc~0); 180154#L292-2 is_master_triggered_~__retres1~0#1 := 0; 180415#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 181043#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 180968#L743 assume !(0 != activate_threads_~tmp~1#1); 180051#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 180052#L311 assume !(1 == ~t1_pc~0); 180770#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 180551#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 179917#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 179877#L751 assume !(0 != activate_threads_~tmp___0~0#1); 179878#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180777#L330 assume !(1 == ~t2_pc~0); 180348#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 180158#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 180657#L759 assume !(0 != activate_threads_~tmp___1~0#1); 180937#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180135#L349 assume !(1 == ~t3_pc~0); 180136#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 180710#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 179841#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 179842#L767 assume !(0 != activate_threads_~tmp___2~0#1); 180922#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180923#L368 assume !(1 == ~t4_pc~0); 180283#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 180284#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180105#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 180106#L775 assume !(0 != activate_threads_~tmp___3~0#1); 179852#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 179853#L387 assume !(1 == ~t5_pc~0); 180581#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 180582#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181044#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 181042#L783 assume !(0 != activate_threads_~tmp___4~0#1); 180088#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180260#L667 assume !(1 == ~M_E~0); 180403#L667-2 assume !(1 == ~T1_E~0); 180790#L672-1 assume !(1 == ~T2_E~0); 180320#L677-1 assume !(1 == ~T3_E~0); 180321#L682-1 assume !(1 == ~T4_E~0); 180733#L687-1 assume !(1 == ~T5_E~0); 180872#L692-1 assume !(1 == ~E_M~0); 180708#L697-1 assume !(1 == ~E_1~0); 180709#L702-1 assume !(1 == ~E_2~0); 180802#L707-1 assume !(1 == ~E_3~0); 180513#L712-1 assume !(1 == ~E_4~0); 180514#L717-1 assume !(1 == ~E_5~0); 180748#L722-1 assume { :end_inline_reset_delta_events } true; 180749#L928-2 assume !false; 181984#L929 [2024-10-31 22:04:40,347 INFO L747 eck$LassoCheckResult]: Loop: 181984#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 189456#L574-1 assume !false; 189455#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 189454#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 189453#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 189451#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 189450#L499 assume 0 != eval_~tmp~0#1; 189449#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 189446#L507 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 189443#L68 assume 0 == ~m_pc~0; 189442#L93-1 assume !false; 189441#L80 havoc master_#t~nondet4#1;~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189440#L292-3 assume 1 == ~m_pc~0; 189439#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 189438#L303-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189436#is_master_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 189432#L743-3 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 189430#L743-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189429#L311-3 assume !(1 == ~t1_pc~0); 189428#L311-5 is_transmit1_triggered_~__retres1~1#1 := 0; 189427#L322-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189426#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 189424#L751-3 assume !(0 != activate_threads_~tmp___0~0#1); 189423#L751-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189422#L330-3 assume !(1 == ~t2_pc~0); 189420#L330-5 is_transmit2_triggered_~__retres1~2#1 := 0; 189419#L341-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189418#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 189417#L759-3 assume !(0 != activate_threads_~tmp___1~0#1); 189416#L759-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189415#L349-3 assume 1 == ~t3_pc~0; 189414#L350-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 189412#L360-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189410#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189407#L767-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 189406#L767-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189404#L368-3 assume !(1 == ~t4_pc~0); 189403#L368-5 is_transmit4_triggered_~__retres1~4#1 := 0; 189401#L379-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189400#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 189399#L775-3 assume !(0 != activate_threads_~tmp___3~0#1); 189398#L775-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189397#L387-3 assume 1 == ~t5_pc~0; 189394#L388-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 189392#L398-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189390#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189379#L783-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 188469#L783-5 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 188107#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 188106#master_returnLabel#1 havoc master_#t~nondet4#1;assume { :end_inline_master } true; 188097#L507-2 havoc eval_~tmp_ndt_1~0#1; 188090#L504-1 assume !(0 == ~t1_st~0); 188080#L518-1 assume !(0 == ~t2_st~0); 188072#L532-1 assume !(0 == ~t3_st~0); 188066#L546-1 assume !(0 == ~t4_st~0); 188061#L560-1 assume !(0 == ~t5_st~0); 188058#L574-1 assume !false; 188057#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 188056#L452 assume !(0 == ~m_st~0); 188055#L456 assume !(0 == ~t1_st~0); 188054#L460 assume !(0 == ~t2_st~0); 188053#L464 assume !(0 == ~t3_st~0); 188052#L468 assume !(0 == ~t4_st~0); 188050#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 188049#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 188048#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 188046#L499 assume !(0 != eval_~tmp~0#1); 188045#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 188044#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 188043#L599-3 assume !(0 == ~M_E~0); 188042#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 188041#L604-3 assume !(0 == ~T2_E~0); 188040#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 188039#L614-3 assume !(0 == ~T4_E~0); 188038#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 188037#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 188036#L629-3 assume !(0 == ~E_1~0); 188035#L634-3 assume !(0 == ~E_2~0); 188034#L639-3 assume !(0 == ~E_3~0); 188033#L644-3 assume !(0 == ~E_4~0); 188032#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 188031#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 188030#L292-21 assume 1 == ~m_pc~0; 188028#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 188029#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189597#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 189595#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 189593#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189591#L311-21 assume !(1 == ~t1_pc~0); 189589#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 189587#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189584#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 189582#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 189580#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189576#L330-21 assume !(1 == ~t2_pc~0); 189574#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 189570#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189568#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 189566#L759-21 assume !(0 != activate_threads_~tmp___1~0#1); 189564#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189561#L349-21 assume 1 == ~t3_pc~0; 189559#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 189560#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189618#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189550#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 189548#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189546#L368-21 assume !(1 == ~t4_pc~0); 189544#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 189540#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189538#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 189536#L775-21 assume !(0 != activate_threads_~tmp___3~0#1); 189534#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189531#L387-21 assume 1 == ~t5_pc~0; 189528#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 189525#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189523#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189521#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 189518#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189516#L667-3 assume !(1 == ~M_E~0); 189512#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 189510#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 189508#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 189506#L682-3 assume !(1 == ~T4_E~0); 189504#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 189503#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 189502#L697-3 assume !(1 == ~E_1~0); 189500#L702-3 assume !(1 == ~E_2~0); 189498#L707-3 assume !(1 == ~E_3~0); 189497#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 189496#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189495#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 189492#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 189490#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 189488#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 189484#L947 assume !(0 == start_simulation_~tmp~3#1); 189482#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 189480#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 189479#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 189478#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 189474#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 189470#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 189466#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 189465#L960 assume !(0 != start_simulation_~tmp___0~1#1); 189463#L928-2 assume !false; 181984#L929 [2024-10-31 22:04:40,347 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:40,348 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 1 times [2024-10-31 22:04:40,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:40,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327433301] [2024-10-31 22:04:40,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:40,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:40,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:40,366 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:40,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:40,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:40,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:40,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1824082353, now seen corresponding path program 1 times [2024-10-31 22:04:40,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:40,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739806433] [2024-10-31 22:04:40,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:40,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:40,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:40,462 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:40,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:40,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739806433] [2024-10-31 22:04:40,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739806433] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:40,463 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:40,463 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:40,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159224482] [2024-10-31 22:04:40,463 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:40,464 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:40,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:40,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:40,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:40,464 INFO L87 Difference]: Start difference. First operand 18647 states and 24440 transitions. cyclomatic complexity: 5805 Second operand has 3 states, 3 states have (on average 48.0) internal successors, (144), 3 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:40,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:40,705 INFO L93 Difference]: Finished difference Result 22482 states and 29144 transitions. [2024-10-31 22:04:40,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22482 states and 29144 transitions. [2024-10-31 22:04:40,792 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15160 [2024-10-31 22:04:40,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22482 states to 22482 states and 29144 transitions. [2024-10-31 22:04:40,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15340 [2024-10-31 22:04:40,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15340 [2024-10-31 22:04:40,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22482 states and 29144 transitions. [2024-10-31 22:04:40,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:40,869 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22482 states and 29144 transitions. [2024-10-31 22:04:40,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22482 states and 29144 transitions. [2024-10-31 22:04:41,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22482 to 21306. [2024-10-31 22:04:41,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21306 states, 21306 states have (on average 1.3014174410964048) internal successors, (27728), 21305 states have internal predecessors, (27728), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:41,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21306 states to 21306 states and 27728 transitions. [2024-10-31 22:04:41,264 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21306 states and 27728 transitions. [2024-10-31 22:04:41,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:41,332 INFO L425 stractBuchiCegarLoop]: Abstraction has 21306 states and 27728 transitions. [2024-10-31 22:04:41,332 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-31 22:04:41,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21306 states and 27728 transitions. [2024-10-31 22:04:41,439 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14376 [2024-10-31 22:04:41,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:41,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:41,440 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:41,440 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:41,441 INFO L745 eck$LassoCheckResult]: Stem: 221526#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 221527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 221798#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221799#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 222135#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 221676#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 221677#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 222066#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 221625#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 221626#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 222050#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 221619#L599 assume !(0 == ~M_E~0); 221620#L599-2 assume !(0 == ~T1_E~0); 220982#L604-1 assume !(0 == ~T2_E~0); 220964#L609-1 assume !(0 == ~T3_E~0); 220965#L614-1 assume !(0 == ~T4_E~0); 221264#L619-1 assume !(0 == ~T5_E~0); 221484#L624-1 assume !(0 == ~E_M~0); 221685#L629-1 assume !(0 == ~E_1~0); 221127#L634-1 assume !(0 == ~E_2~0); 221128#L639-1 assume !(0 == ~E_3~0); 221919#L644-1 assume !(0 == ~E_4~0); 221960#L649-1 assume !(0 == ~E_5~0); 221063#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221064#L292 assume !(1 == ~m_pc~0); 221288#L292-2 is_master_triggered_~__retres1~0#1 := 0; 221558#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221478#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 221479#L743 assume !(0 != activate_threads_~tmp~1#1); 221186#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 221187#L311 assume !(1 == ~t1_pc~0); 221918#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 221698#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221052#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 221012#L751 assume !(0 != activate_threads_~tmp___0~0#1); 221013#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221920#L330 assume !(1 == ~t2_pc~0); 221488#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 221289#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221290#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 221806#L759 assume !(0 != activate_threads_~tmp___1~0#1); 222131#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221265#L349 assume !(1 == ~t3_pc~0); 221266#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221854#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220966#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 220967#L767 assume !(0 != activate_threads_~tmp___2~0#1); 222114#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 222115#L368 assume !(1 == ~t4_pc~0); 221421#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 221422#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221239#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 221240#L775 assume !(0 != activate_threads_~tmp___3~0#1); 220987#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220988#L387 assume !(1 == ~t5_pc~0); 221726#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 221727#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 222248#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 222247#L783 assume !(0 != activate_threads_~tmp___4~0#1); 221216#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221395#L667 assume !(1 == ~M_E~0); 221543#L667-2 assume !(1 == ~T1_E~0); 221936#L672-1 assume !(1 == ~T2_E~0); 221462#L677-1 assume !(1 == ~T3_E~0); 221463#L682-1 assume !(1 == ~T4_E~0); 221876#L687-1 assume !(1 == ~T5_E~0); 222043#L692-1 assume !(1 == ~E_M~0); 221852#L697-1 assume !(1 == ~E_1~0); 221853#L702-1 assume !(1 == ~E_2~0); 221959#L707-1 assume !(1 == ~E_3~0); 221661#L712-1 assume !(1 == ~E_4~0); 221662#L717-1 assume !(1 == ~E_5~0); 221891#L722-1 assume { :end_inline_reset_delta_events } true; 221892#L928-2 assume !false; 222602#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 222218#L574-1 [2024-10-31 22:04:41,441 INFO L747 eck$LassoCheckResult]: Loop: 222218#L574-1 assume !false; 241704#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 238495#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 238492#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 238488#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 238485#L499 assume 0 != eval_~tmp~0#1; 238482#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 238477#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 238475#L507-2 havoc eval_~tmp_ndt_1~0#1; 238473#L504-1 assume !(0 == ~t1_st~0); 238474#L518-1 assume !(0 == ~t2_st~0); 240736#L532-1 assume !(0 == ~t3_st~0); 240733#L546-1 assume !(0 == ~t4_st~0); 222217#L560-1 assume !(0 == ~t5_st~0); 222218#L574-1 [2024-10-31 22:04:41,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:41,442 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2024-10-31 22:04:41,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:41,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836179970] [2024-10-31 22:04:41,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:41,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:41,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:41,461 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:41,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:41,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:41,487 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:41,488 INFO L85 PathProgramCache]: Analyzing trace with hash -2088174432, now seen corresponding path program 1 times [2024-10-31 22:04:41,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:41,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522690051] [2024-10-31 22:04:41,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:41,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:41,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:41,494 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:41,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:41,499 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:41,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:41,500 INFO L85 PathProgramCache]: Analyzing trace with hash 672119718, now seen corresponding path program 1 times [2024-10-31 22:04:41,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:41,500 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177570504] [2024-10-31 22:04:41,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:41,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:41,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:41,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:41,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:41,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177570504] [2024-10-31 22:04:41,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177570504] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:41,562 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:41,562 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:41,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067923670] [2024-10-31 22:04:41,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:41,640 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:41,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:41,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:41,641 INFO L87 Difference]: Start difference. First operand 21306 states and 27728 transitions. cyclomatic complexity: 6446 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:41,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:41,930 INFO L93 Difference]: Finished difference Result 36732 states and 47292 transitions. [2024-10-31 22:04:41,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36732 states and 47292 transitions. [2024-10-31 22:04:42,083 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 24124 [2024-10-31 22:04:42,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36732 states to 36732 states and 47292 transitions. [2024-10-31 22:04:42,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25206 [2024-10-31 22:04:42,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25206 [2024-10-31 22:04:42,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36732 states and 47292 transitions. [2024-10-31 22:04:42,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:42,218 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36732 states and 47292 transitions. [2024-10-31 22:04:42,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36732 states and 47292 transitions. [2024-10-31 22:04:42,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36732 to 36732. [2024-10-31 22:04:42,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36732 states, 36732 states have (on average 1.2874877491016008) internal successors, (47292), 36731 states have internal predecessors, (47292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:42,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36732 states to 36732 states and 47292 transitions. [2024-10-31 22:04:42,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36732 states and 47292 transitions. [2024-10-31 22:04:42,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:42,917 INFO L425 stractBuchiCegarLoop]: Abstraction has 36732 states and 47292 transitions. [2024-10-31 22:04:42,917 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-10-31 22:04:42,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36732 states and 47292 transitions. [2024-10-31 22:04:43,032 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 24124 [2024-10-31 22:04:43,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:43,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:43,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:43,034 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:43,034 INFO L745 eck$LassoCheckResult]: Stem: 279561#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 279562#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 279824#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 279825#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 280156#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 279704#L414-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 279705#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 281576#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 281575#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 281574#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 281573#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 281572#L599 assume !(0 == ~M_E~0); 281571#L599-2 assume !(0 == ~T1_E~0); 281570#L604-1 assume !(0 == ~T2_E~0); 281569#L609-1 assume !(0 == ~T3_E~0); 281568#L614-1 assume !(0 == ~T4_E~0); 281567#L619-1 assume !(0 == ~T5_E~0); 281566#L624-1 assume !(0 == ~E_M~0); 281565#L629-1 assume !(0 == ~E_1~0); 281564#L634-1 assume !(0 == ~E_2~0); 281563#L639-1 assume !(0 == ~E_3~0); 281562#L644-1 assume !(0 == ~E_4~0); 281561#L649-1 assume !(0 == ~E_5~0); 281560#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281559#L292 assume !(1 == ~m_pc~0); 281558#L292-2 is_master_triggered_~__retres1~0#1 := 0; 281557#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 281556#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 281555#L743 assume !(0 != activate_threads_~tmp~1#1); 281554#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 281553#L311 assume !(1 == ~t1_pc~0); 281552#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 281551#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 281550#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 281549#L751 assume !(0 != activate_threads_~tmp___0~0#1); 281548#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 281547#L330 assume !(1 == ~t2_pc~0); 281545#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 281544#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281543#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 280153#L759 assume !(0 != activate_threads_~tmp___1~0#1); 280154#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 279313#L349 assume !(1 == ~t3_pc~0); 279314#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 280208#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 279022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 279023#L767 assume !(0 != activate_threads_~tmp___2~0#1); 280135#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 280136#L368 assume !(1 == ~t4_pc~0); 279457#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 279458#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279283#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 279284#L775 assume !(0 != activate_threads_~tmp___3~0#1); 280127#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 281523#L387 assume !(1 == ~t5_pc~0); 281521#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 281599#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 280257#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 280258#L783 assume !(0 != activate_threads_~tmp___4~0#1); 281503#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 281502#L667 assume !(1 == ~M_E~0); 281501#L667-2 assume !(1 == ~T1_E~0); 281500#L672-1 assume !(1 == ~T2_E~0); 281499#L677-1 assume !(1 == ~T3_E~0); 281498#L682-1 assume !(1 == ~T4_E~0); 281497#L687-1 assume !(1 == ~T5_E~0); 281496#L692-1 assume !(1 == ~E_M~0); 281495#L697-1 assume !(1 == ~E_1~0); 281494#L702-1 assume !(1 == ~E_2~0); 279991#L707-1 assume !(1 == ~E_3~0); 279688#L712-1 assume !(1 == ~E_4~0); 279689#L717-1 assume !(1 == ~E_5~0); 279967#L722-1 assume { :end_inline_reset_delta_events } true; 281479#L928-2 assume !false; 281480#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 295220#L574-1 [2024-10-31 22:04:43,035 INFO L747 eck$LassoCheckResult]: Loop: 295220#L574-1 assume !false; 295218#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 295215#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 295213#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 295212#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 295211#L499 assume 0 != eval_~tmp~0#1; 295207#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 295204#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 295202#L507-2 havoc eval_~tmp_ndt_1~0#1; 295200#L504-1 assume !(0 == ~t1_st~0); 295196#L518-1 assume !(0 == ~t2_st~0); 295193#L532-1 assume !(0 == ~t3_st~0); 295188#L546-1 assume !(0 == ~t4_st~0); 295189#L560-1 assume !(0 == ~t5_st~0); 295220#L574-1 [2024-10-31 22:04:43,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:43,036 INFO L85 PathProgramCache]: Analyzing trace with hash 1586209477, now seen corresponding path program 1 times [2024-10-31 22:04:43,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:43,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423482133] [2024-10-31 22:04:43,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:43,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:43,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:43,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:43,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:43,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423482133] [2024-10-31 22:04:43,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423482133] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:43,228 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:43,228 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:43,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171375726] [2024-10-31 22:04:43,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:43,229 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:43,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:43,230 INFO L85 PathProgramCache]: Analyzing trace with hash -2088174432, now seen corresponding path program 2 times [2024-10-31 22:04:43,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:43,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860404402] [2024-10-31 22:04:43,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:43,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:43,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:43,238 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:43,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:43,242 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:43,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:43,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:43,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:43,329 INFO L87 Difference]: Start difference. First operand 36732 states and 47292 transitions. cyclomatic complexity: 10602 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:43,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:43,425 INFO L93 Difference]: Finished difference Result 23261 states and 29866 transitions. [2024-10-31 22:04:43,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23261 states and 29866 transitions. [2024-10-31 22:04:43,544 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15790 [2024-10-31 22:04:43,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23261 states to 23261 states and 29866 transitions. [2024-10-31 22:04:43,634 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15974 [2024-10-31 22:04:43,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15974 [2024-10-31 22:04:43,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23261 states and 29866 transitions. [2024-10-31 22:04:43,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:43,656 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23261 states and 29866 transitions. [2024-10-31 22:04:43,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23261 states and 29866 transitions. [2024-10-31 22:04:44,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23261 to 23261. [2024-10-31 22:04:44,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23261 states, 23261 states have (on average 1.283951678775633) internal successors, (29866), 23260 states have internal predecessors, (29866), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:44,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23261 states to 23261 states and 29866 transitions. [2024-10-31 22:04:44,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23261 states and 29866 transitions. [2024-10-31 22:04:44,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:44,075 INFO L425 stractBuchiCegarLoop]: Abstraction has 23261 states and 29866 transitions. [2024-10-31 22:04:44,075 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-10-31 22:04:44,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23261 states and 29866 transitions. [2024-10-31 22:04:44,299 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15790 [2024-10-31 22:04:44,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:44,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:44,303 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:44,303 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:44,304 INFO L745 eck$LassoCheckResult]: Stem: 339549#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 339550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 339801#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 339802#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 340115#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 339688#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 339689#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 340059#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 339644#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 339645#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 340050#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 339638#L599 assume !(0 == ~M_E~0); 339639#L599-2 assume !(0 == ~T1_E~0); 339031#L604-1 assume !(0 == ~T2_E~0); 339009#L609-1 assume !(0 == ~T3_E~0); 339010#L614-1 assume !(0 == ~T4_E~0); 339304#L619-1 assume !(0 == ~T5_E~0); 339508#L624-1 assume !(0 == ~E_M~0); 339697#L629-1 assume !(0 == ~E_1~0); 339168#L634-1 assume !(0 == ~E_2~0); 339169#L639-1 assume !(0 == ~E_3~0); 339924#L644-1 assume !(0 == ~E_4~0); 339962#L649-1 assume !(0 == ~E_5~0); 339107#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 339108#L292 assume !(1 == ~m_pc~0); 339328#L292-2 is_master_triggered_~__retres1~0#1 := 0; 339575#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 339506#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 339507#L743 assume !(0 != activate_threads_~tmp~1#1); 339227#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 339228#L311 assume !(1 == ~t1_pc~0); 339923#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 339709#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 339096#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 339056#L751 assume !(0 != activate_threads_~tmp___0~0#1); 339057#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 339929#L330 assume !(1 == ~t2_pc~0); 339512#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 339331#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 339332#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 339810#L759 assume !(0 != activate_threads_~tmp___1~0#1); 340113#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 339309#L349 assume !(1 == ~t3_pc~0); 339310#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 340166#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 339021#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 339022#L767 assume !(0 != activate_threads_~tmp___2~0#1); 340095#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 340096#L368 assume !(1 == ~t4_pc~0); 339450#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 339451#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 339280#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 339281#L775 assume !(0 != activate_threads_~tmp___3~0#1); 339032#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 339033#L387 assume !(1 == ~t5_pc~0); 339732#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 339733#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 340203#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 340202#L783 assume !(0 != activate_threads_~tmp___4~0#1); 339262#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 339430#L667 assume !(1 == ~M_E~0); 339563#L667-2 assume !(1 == ~T1_E~0); 339948#L672-1 assume !(1 == ~T2_E~0); 339485#L677-1 assume !(1 == ~T3_E~0); 339486#L682-1 assume !(1 == ~T4_E~0); 339885#L687-1 assume !(1 == ~T5_E~0); 340038#L692-1 assume !(1 == ~E_M~0); 339859#L697-1 assume !(1 == ~E_1~0); 339860#L702-1 assume !(1 == ~E_2~0); 339961#L707-1 assume !(1 == ~E_3~0); 339674#L712-1 assume !(1 == ~E_4~0); 339675#L717-1 assume !(1 == ~E_5~0); 339899#L722-1 assume { :end_inline_reset_delta_events } true; 339900#L928-2 assume !false; 344229#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 351099#L574-1 [2024-10-31 22:04:44,304 INFO L747 eck$LassoCheckResult]: Loop: 351099#L574-1 assume !false; 351096#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 351094#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 351092#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 351089#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 351088#L499 assume 0 != eval_~tmp~0#1; 351087#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 351085#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 351083#L507-2 havoc eval_~tmp_ndt_1~0#1; 351081#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 351079#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 351080#L521-2 havoc eval_~tmp_ndt_2~0#1; 351111#L518-1 assume !(0 == ~t2_st~0); 351108#L532-1 assume !(0 == ~t3_st~0); 351103#L546-1 assume !(0 == ~t4_st~0); 351101#L560-1 assume !(0 == ~t5_st~0); 351099#L574-1 [2024-10-31 22:04:44,304 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:44,304 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2024-10-31 22:04:44,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:44,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869809327] [2024-10-31 22:04:44,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:44,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:44,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:44,325 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:44,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:44,346 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:44,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:44,348 INFO L85 PathProgramCache]: Analyzing trace with hash -1426982192, now seen corresponding path program 1 times [2024-10-31 22:04:44,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:44,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214708362] [2024-10-31 22:04:44,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:44,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:44,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:44,352 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:44,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:44,356 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:44,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:44,357 INFO L85 PathProgramCache]: Analyzing trace with hash 1220874326, now seen corresponding path program 1 times [2024-10-31 22:04:44,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:44,357 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [939980407] [2024-10-31 22:04:44,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:44,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:44,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:44,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:44,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:44,401 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [939980407] [2024-10-31 22:04:44,401 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [939980407] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:44,401 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:44,401 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:44,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1217393763] [2024-10-31 22:04:44,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:44,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:44,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:44,476 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:44,476 INFO L87 Difference]: Start difference. First operand 23261 states and 29866 transitions. cyclomatic complexity: 6629 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:44,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:44,611 INFO L93 Difference]: Finished difference Result 41587 states and 52969 transitions. [2024-10-31 22:04:44,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41587 states and 52969 transitions. [2024-10-31 22:04:44,922 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27902 [2024-10-31 22:04:45,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41587 states to 41587 states and 52969 transitions. [2024-10-31 22:04:45,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28186 [2024-10-31 22:04:45,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28186 [2024-10-31 22:04:45,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41587 states and 52969 transitions. [2024-10-31 22:04:45,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:45,080 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41587 states and 52969 transitions. [2024-10-31 22:04:45,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41587 states and 52969 transitions. [2024-10-31 22:04:45,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41587 to 41587. [2024-10-31 22:04:45,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41587 states, 41587 states have (on average 1.2736912977613197) internal successors, (52969), 41586 states have internal predecessors, (52969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:45,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41587 states to 41587 states and 52969 transitions. [2024-10-31 22:04:45,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41587 states and 52969 transitions. [2024-10-31 22:04:45,821 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:45,822 INFO L425 stractBuchiCegarLoop]: Abstraction has 41587 states and 52969 transitions. [2024-10-31 22:04:45,822 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-10-31 22:04:45,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41587 states and 52969 transitions. [2024-10-31 22:04:45,984 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27902 [2024-10-31 22:04:45,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:45,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:45,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:45,986 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:45,987 INFO L745 eck$LassoCheckResult]: Stem: 404408#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 404409#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 404666#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 404667#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 404993#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 404551#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 404552#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 404924#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 404505#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 404506#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 404912#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 404495#L599 assume !(0 == ~M_E~0); 404496#L599-2 assume !(0 == ~T1_E~0); 403887#L604-1 assume !(0 == ~T2_E~0); 403865#L609-1 assume !(0 == ~T3_E~0); 403866#L614-1 assume !(0 == ~T4_E~0); 404160#L619-1 assume !(0 == ~T5_E~0); 404367#L624-1 assume !(0 == ~E_M~0); 404559#L629-1 assume !(0 == ~E_1~0); 404025#L634-1 assume !(0 == ~E_2~0); 404026#L639-1 assume !(0 == ~E_3~0); 404786#L644-1 assume !(0 == ~E_4~0); 404822#L649-1 assume !(0 == ~E_5~0); 403963#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 403964#L292 assume !(1 == ~m_pc~0); 404184#L292-2 is_master_triggered_~__retres1~0#1 := 0; 404436#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 404365#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 404366#L743 assume !(0 != activate_threads_~tmp~1#1); 404084#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 404085#L311 assume !(1 == ~t1_pc~0); 404785#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 404572#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 403952#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 403912#L751 assume !(0 != activate_threads_~tmp___0~0#1); 403913#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 404791#L330 assume !(1 == ~t2_pc~0); 404371#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 404187#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 404188#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 404674#L759 assume !(0 != activate_threads_~tmp___1~0#1); 404989#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 404165#L349 assume !(1 == ~t3_pc~0); 404166#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 405049#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 403877#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 403878#L767 assume !(0 != activate_threads_~tmp___2~0#1); 404971#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 404972#L368 assume !(1 == ~t4_pc~0); 404309#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 404310#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 404135#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 404136#L775 assume !(0 != activate_threads_~tmp___3~0#1); 403888#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 403889#L387 assume !(1 == ~t5_pc~0); 404599#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 404600#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 405095#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 405094#L783 assume !(0 != activate_threads_~tmp___4~0#1); 404117#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 404288#L667 assume !(1 == ~M_E~0); 404422#L667-2 assume !(1 == ~T1_E~0); 404807#L672-1 assume !(1 == ~T2_E~0); 404344#L677-1 assume !(1 == ~T3_E~0); 404345#L682-1 assume !(1 == ~T4_E~0); 404747#L687-1 assume !(1 == ~T5_E~0); 404900#L692-1 assume !(1 == ~E_M~0); 404723#L697-1 assume !(1 == ~E_1~0); 404724#L702-1 assume !(1 == ~E_2~0); 404820#L707-1 assume !(1 == ~E_3~0); 404536#L712-1 assume !(1 == ~E_4~0); 404537#L717-1 assume !(1 == ~E_5~0); 404760#L722-1 assume { :end_inline_reset_delta_events } true; 404761#L928-2 assume !false; 413321#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 419748#L574-1 [2024-10-31 22:04:45,987 INFO L747 eck$LassoCheckResult]: Loop: 419748#L574-1 assume !false; 430983#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 430982#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 430981#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 430980#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 430979#L499 assume 0 != eval_~tmp~0#1; 430978#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 430976#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 430975#L507-2 havoc eval_~tmp_ndt_1~0#1; 430974#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 430972#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 430971#L521-2 havoc eval_~tmp_ndt_2~0#1; 430970#L518-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 430963#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 430969#L535-2 havoc eval_~tmp_ndt_3~0#1; 430992#L532-1 assume !(0 == ~t3_st~0); 430987#L546-1 assume !(0 == ~t4_st~0); 430985#L560-1 assume !(0 == ~t5_st~0); 419748#L574-1 [2024-10-31 22:04:45,988 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:45,990 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2024-10-31 22:04:45,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:45,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66894329] [2024-10-31 22:04:45,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:45,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:46,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:46,007 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:46,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:46,035 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:46,036 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:46,036 INFO L85 PathProgramCache]: Analyzing trace with hash 2075640608, now seen corresponding path program 1 times [2024-10-31 22:04:46,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:46,037 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687129569] [2024-10-31 22:04:46,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:46,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:46,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:46,043 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:04:46,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:04:46,051 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:04:46,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:46,054 INFO L85 PathProgramCache]: Analyzing trace with hash -249852122, now seen corresponding path program 1 times [2024-10-31 22:04:46,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:46,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352962587] [2024-10-31 22:04:46,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:46,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:46,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:46,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:46,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:46,121 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [352962587] [2024-10-31 22:04:46,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [352962587] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:46,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:46,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:46,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444190446] [2024-10-31 22:04:46,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:46,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:46,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:46,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:46,225 INFO L87 Difference]: Start difference. First operand 41587 states and 52969 transitions. cyclomatic complexity: 11406 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:46,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:46,794 INFO L93 Difference]: Finished difference Result 76365 states and 96990 transitions. [2024-10-31 22:04:46,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76365 states and 96990 transitions. [2024-10-31 22:04:47,172 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51324 [2024-10-31 22:04:47,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76365 states to 76365 states and 96990 transitions. [2024-10-31 22:04:47,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51808 [2024-10-31 22:04:47,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51808 [2024-10-31 22:04:47,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76365 states and 96990 transitions. [2024-10-31 22:04:47,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:04:47,394 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76365 states and 96990 transitions. [2024-10-31 22:04:47,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76365 states and 96990 transitions.