./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:11:20,614 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:11:20,721 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:11:20,727 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:11:20,728 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:11:20,767 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:11:20,768 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:11:20,768 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:11:20,771 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:11:20,773 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:11:20,774 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:11:20,775 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:11:20,775 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:11:20,780 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:11:20,780 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:11:20,780 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:11:20,781 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:11:20,781 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:11:20,781 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:11:20,781 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:11:20,782 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:11:20,782 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:11:20,783 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:11:20,783 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:11:20,785 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:11:20,785 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:11:20,786 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:11:20,786 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:11:20,786 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:11:20,787 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:11:20,787 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:11:20,787 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:11:20,787 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:11:20,788 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:11:20,788 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:11:20,789 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:11:20,790 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:11:20,790 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:11:20,791 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:11:20,791 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 [2024-10-31 22:11:21,019 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:11:21,051 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:11:21,053 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:11:21,056 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:11:21,056 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:11:21,057 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c Unable to find full path for "g++" [2024-10-31 22:11:23,210 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:11:23,493 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:11:23,494 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2024-10-31 22:11:23,506 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/data/412fbbd9e/dcad4251ecbd45069e80e55ed1f78c25/FLAG0816d589b [2024-10-31 22:11:23,827 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/data/412fbbd9e/dcad4251ecbd45069e80e55ed1f78c25 [2024-10-31 22:11:23,830 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:11:23,832 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:11:23,833 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:11:23,834 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:11:23,839 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:11:23,840 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:11:23" (1/1) ... [2024-10-31 22:11:23,841 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1b86750c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:23, skipping insertion in model container [2024-10-31 22:11:23,842 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:11:23" (1/1) ... [2024-10-31 22:11:23,892 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:11:24,178 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:11:24,197 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:11:24,264 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:11:24,301 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:11:24,301 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24 WrapperNode [2024-10-31 22:11:24,302 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:11:24,304 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:11:24,304 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:11:24,304 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:11:24,313 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,330 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,437 INFO L138 Inliner]: procedures = 40, calls = 51, calls flagged for inlining = 46, calls inlined = 116, statements flattened = 1679 [2024-10-31 22:11:24,438 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:11:24,439 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:11:24,439 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:11:24,439 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:11:24,453 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,453 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,468 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,497 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:11:24,498 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,498 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,529 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,546 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,550 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,555 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,570 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:11:24,571 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:11:24,571 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:11:24,571 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:11:24,572 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (1/1) ... [2024-10-31 22:11:24,586 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:11:24,613 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:11:24,647 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:11:24,651 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05013b8b-9e36-49d0-be57-ca88ec88d8a1/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:11:24,684 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:11:24,685 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:11:24,685 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:11:24,685 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:11:24,826 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:11:24,828 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:11:26,535 INFO L? ?]: Removed 322 outVars from TransFormulas that were not future-live. [2024-10-31 22:11:26,536 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:11:26,568 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:11:26,568 INFO L316 CfgBuilder]: Removed 9 assume(true) statements. [2024-10-31 22:11:26,569 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:11:26 BoogieIcfgContainer [2024-10-31 22:11:26,569 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:11:26,570 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:11:26,570 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:11:26,578 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:11:26,579 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:11:26,579 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:11:23" (1/3) ... [2024-10-31 22:11:26,580 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e37d59f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:11:26, skipping insertion in model container [2024-10-31 22:11:26,580 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:11:26,580 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:11:24" (2/3) ... [2024-10-31 22:11:26,581 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e37d59f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:11:26, skipping insertion in model container [2024-10-31 22:11:26,581 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:11:26,581 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:11:26" (3/3) ... [2024-10-31 22:11:26,583 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-1.c [2024-10-31 22:11:26,670 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:11:26,671 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:11:26,671 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:11:26,671 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:11:26,671 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:11:26,671 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:11:26,671 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:11:26,672 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:11:26,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:26,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2024-10-31 22:11:26,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:26,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:26,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:26,751 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:26,751 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:11:26,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:26,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2024-10-31 22:11:26,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:26,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:26,774 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:26,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:26,782 INFO L745 eck$LassoCheckResult]: Stem: 199#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 569#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 333#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 564#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 523#L487true assume !(1 == ~m_i~0);~m_st~0 := 2; 129#L487-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 268#L492-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 40#L497-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 149#L502-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 29#L507-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 115#L512-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 540#L517-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222#L696true assume !(0 == ~M_E~0); 534#L696-2true assume !(0 == ~T1_E~0); 537#L701-1true assume !(0 == ~T2_E~0); 567#L706-1true assume !(0 == ~T3_E~0); 305#L711-1true assume !(0 == ~T4_E~0); 151#L716-1true assume !(0 == ~T5_E~0); 587#L721-1true assume !(0 == ~T6_E~0); 273#L726-1true assume 0 == ~E_M~0;~E_M~0 := 1; 476#L731-1true assume !(0 == ~E_1~0); 247#L736-1true assume !(0 == ~E_2~0); 317#L741-1true assume !(0 == ~E_3~0); 626#L746-1true assume !(0 == ~E_4~0); 169#L751-1true assume !(0 == ~E_5~0); 232#L756-1true assume !(0 == ~E_6~0); 148#L761-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51#L346true assume !(1 == ~m_pc~0); 179#L346-2true is_master_triggered_~__retres1~0#1 := 0; 420#L357true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 553#L861true assume !(0 != activate_threads_~tmp~1#1); 475#L861-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69#L365true assume 1 == ~t1_pc~0; 138#L366true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 518#L376true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64#L869true assume !(0 != activate_threads_~tmp___0~0#1); 371#L869-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 502#L384true assume !(1 == ~t2_pc~0); 367#L384-2true is_transmit2_triggered_~__retres1~2#1 := 0; 628#L395true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24#L877true assume !(0 != activate_threads_~tmp___1~0#1); 236#L877-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233#L403true assume 1 == ~t3_pc~0; 152#L404true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 681#L414true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 416#L885true assume !(0 != activate_threads_~tmp___2~0#1); 226#L885-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 524#L422true assume 1 == ~t4_pc~0; 22#L423true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 438#L433true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 451#L893true assume !(0 != activate_threads_~tmp___3~0#1); 291#L893-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30#L441true assume !(1 == ~t5_pc~0); 469#L441-2true is_transmit5_triggered_~__retres1~5#1 := 0; 616#L452true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 698#L901true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 297#L901-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 424#L460true assume 1 == ~t6_pc~0; 4#L461true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33#L471true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 319#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 421#L909true assume !(0 != activate_threads_~tmp___5~0#1); 550#L909-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280#L774true assume !(1 == ~M_E~0); 592#L774-2true assume !(1 == ~T1_E~0); 442#L779-1true assume !(1 == ~T2_E~0); 210#L784-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 588#L789-1true assume !(1 == ~T4_E~0); 60#L794-1true assume !(1 == ~T5_E~0); 667#L799-1true assume !(1 == ~T6_E~0); 602#L804-1true assume !(1 == ~E_M~0); 659#L809-1true assume !(1 == ~E_1~0); 270#L814-1true assume !(1 == ~E_2~0); 12#L819-1true assume !(1 == ~E_3~0); 325#L824-1true assume 1 == ~E_4~0;~E_4~0 := 2; 649#L829-1true assume !(1 == ~E_5~0); 429#L834-1true assume !(1 == ~E_6~0); 139#L839-1true assume { :end_inline_reset_delta_events } true; 131#L1065-2true [2024-10-31 22:11:26,785 INFO L747 eck$LassoCheckResult]: Loop: 131#L1065-2true assume !false; 341#L1066true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 397#L671-1true assume false; 105#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 489#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163#L696-3true assume 0 == ~M_E~0;~M_E~0 := 1; 582#L696-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 198#L701-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 673#L706-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 548#L711-3true assume !(0 == ~T4_E~0); 535#L716-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 321#L721-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 184#L726-3true assume 0 == ~E_M~0;~E_M~0 := 1; 309#L731-3true assume 0 == ~E_1~0;~E_1~0 := 1; 511#L736-3true assume 0 == ~E_2~0;~E_2~0 := 1; 310#L741-3true assume 0 == ~E_3~0;~E_3~0 := 1; 145#L746-3true assume 0 == ~E_4~0;~E_4~0 := 1; 228#L751-3true assume !(0 == ~E_5~0); 430#L756-3true assume 0 == ~E_6~0;~E_6~0 := 1; 73#L761-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91#L346-24true assume 1 == ~m_pc~0; 413#L347-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 311#L357-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 500#L861-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 439#L861-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111#L365-24true assume 1 == ~t1_pc~0; 322#L366-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 655#L376-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 392#L869-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 586#L869-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83#L384-24true assume !(1 == ~t2_pc~0); 94#L384-26true is_transmit2_triggered_~__retres1~2#1 := 0; 640#L395-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 675#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 301#L877-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99#L877-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171#L403-24true assume 1 == ~t3_pc~0; 627#L404-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 200#L414-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 370#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 266#L885-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 577#L885-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130#L422-24true assume 1 == ~t4_pc~0; 574#L423-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 104#L433-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 481#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 539#L893-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 448#L893-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140#L441-24true assume !(1 == ~t5_pc~0); 292#L441-26true is_transmit5_triggered_~__retres1~5#1 := 0; 286#L452-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 243#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65#L901-24true assume !(0 != activate_threads_~tmp___4~0#1); 378#L901-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 374#L460-24true assume 1 == ~t6_pc~0; 590#L461-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 687#L471-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 468#L909-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 368#L909-26true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 636#L774-3true assume !(1 == ~M_E~0); 298#L774-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 183#L779-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 23#L784-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 686#L789-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 13#L794-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 70#L799-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 284#L804-3true assume 1 == ~E_M~0;~E_M~0 := 2; 521#L809-3true assume !(1 == ~E_1~0); 68#L814-3true assume 1 == ~E_2~0;~E_2~0 := 2; 221#L819-3true assume 1 == ~E_3~0;~E_3~0 := 2; 156#L824-3true assume 1 == ~E_4~0;~E_4~0 := 2; 144#L829-3true assume 1 == ~E_5~0;~E_5~0 := 2; 346#L834-3true assume 1 == ~E_6~0;~E_6~0 := 2; 59#L839-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 452#L530-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 109#L567-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 290#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 28#L1084true assume !(0 == start_simulation_~tmp~3#1); 492#L1084-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 167#L530-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80#L567-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 42#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 170#L1039true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76#L1046true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 175#L1097true assume !(0 != start_simulation_~tmp___0~1#1); 131#L1065-2true [2024-10-31 22:11:26,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:26,792 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2024-10-31 22:11:26,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:26,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17162646] [2024-10-31 22:11:26,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:26,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:26,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:27,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:27,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:27,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17162646] [2024-10-31 22:11:27,114 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17162646] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:27,114 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:27,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:27,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1706259934] [2024-10-31 22:11:27,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:27,123 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:27,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:27,125 INFO L85 PathProgramCache]: Analyzing trace with hash -1343600868, now seen corresponding path program 1 times [2024-10-31 22:11:27,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:27,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968422514] [2024-10-31 22:11:27,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:27,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:27,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:27,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:27,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:27,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1968422514] [2024-10-31 22:11:27,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1968422514] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:27,178 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:27,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:11:27,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571592181] [2024-10-31 22:11:27,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:27,180 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:27,181 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:27,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:27,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:27,223 INFO L87 Difference]: Start difference. First operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:27,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:27,328 INFO L93 Difference]: Finished difference Result 699 states and 1041 transitions. [2024-10-31 22:11:27,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 699 states and 1041 transitions. [2024-10-31 22:11:27,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:27,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 699 states to 693 states and 1035 transitions. [2024-10-31 22:11:27,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-10-31 22:11:27,366 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-10-31 22:11:27,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1035 transitions. [2024-10-31 22:11:27,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:27,372 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1035 transitions. [2024-10-31 22:11:27,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1035 transitions. [2024-10-31 22:11:27,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-10-31 22:11:27,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4935064935064934) internal successors, (1035), 692 states have internal predecessors, (1035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:27,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1035 transitions. [2024-10-31 22:11:27,439 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1035 transitions. [2024-10-31 22:11:27,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:27,445 INFO L425 stractBuchiCegarLoop]: Abstraction has 693 states and 1035 transitions. [2024-10-31 22:11:27,445 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:11:27,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1035 transitions. [2024-10-31 22:11:27,452 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:27,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:27,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:27,459 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:27,460 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:27,460 INFO L745 eck$LassoCheckResult]: Stem: 1771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1931#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1932#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2069#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1668#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1669#L492-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1500#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1501#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1473#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1474#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1642#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1802#L696 assume !(0 == ~M_E~0); 1803#L696-2 assume !(0 == ~T1_E~0); 2072#L701-1 assume !(0 == ~T2_E~0); 2075#L706-1 assume !(0 == ~T3_E~0); 1910#L711-1 assume !(0 == ~T4_E~0); 1703#L716-1 assume !(0 == ~T5_E~0); 1704#L721-1 assume !(0 == ~T6_E~0); 1868#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1869#L731-1 assume !(0 == ~E_1~0); 1838#L736-1 assume !(0 == ~E_2~0); 1839#L741-1 assume !(0 == ~E_3~0); 1919#L746-1 assume !(0 == ~E_4~0); 1728#L751-1 assume !(0 == ~E_5~0); 1729#L756-1 assume !(0 == ~E_6~0); 1700#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1521#L346 assume !(1 == ~m_pc~0); 1522#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1742#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1734#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1735#L861 assume !(0 != activate_threads_~tmp~1#1); 2051#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1554#L365 assume 1 == ~t1_pc~0; 1555#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1689#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1507#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1508#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1543#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1966#L384 assume !(1 == ~t2_pc~0); 1962#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1963#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1937#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1463#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1464#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1818#L403 assume 1 == ~t3_pc~0; 1705#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1706#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1432#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1813#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1814#L422 assume 1 == ~t4_pc~0; 1458#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1459#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1606#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1607#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1889#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1475#L441 assume !(1 == ~t5_pc~0); 1476#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2048#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1745#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1746#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1899#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1900#L460 assume 1 == ~t6_pc~0; 1419#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1420#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1483#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1921#L909 assume !(0 != activate_threads_~tmp___5~0#1); 2010#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1877#L774 assume !(1 == ~M_E~0); 1878#L774-2 assume !(1 == ~T1_E~0); 2027#L779-1 assume !(1 == ~T2_E~0); 1788#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1789#L789-1 assume !(1 == ~T4_E~0); 1538#L794-1 assume !(1 == ~T5_E~0); 1539#L799-1 assume !(1 == ~T6_E~0); 2092#L804-1 assume !(1 == ~E_M~0); 2093#L809-1 assume !(1 == ~E_1~0); 1866#L814-1 assume !(1 == ~E_2~0); 1437#L819-1 assume !(1 == ~E_3~0); 1438#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1927#L829-1 assume !(1 == ~E_5~0); 2017#L834-1 assume !(1 == ~E_6~0); 1690#L839-1 assume { :end_inline_reset_delta_events } true; 1673#L1065-2 [2024-10-31 22:11:27,461 INFO L747 eck$LassoCheckResult]: Loop: 1673#L1065-2 assume !false; 1674#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1645#L671-1 assume !false; 1995#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1997#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1510#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1524#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1954#L582 assume !(0 != eval_~tmp~0#1); 1622#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1719#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1720#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1767#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1768#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2079#L711-3 assume !(0 == ~T4_E~0); 2073#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1923#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1749#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1750#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1915#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1916#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1697#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1698#L751-3 assume !(0 == ~E_5~0); 1815#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1561#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1562#L346-24 assume 1 == ~m_pc~0; 1600#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1693#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1640#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1641#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2025#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632#L365-24 assume 1 == ~t1_pc~0; 1633#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1922#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2070#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1986#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1987#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1579#L384-24 assume !(1 == ~t2_pc~0); 1580#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1601#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2100#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1906#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1611#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1612#L403-24 assume 1 == ~t3_pc~0; 1730#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1769#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1770#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1863#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1864#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1670#L422-24 assume 1 == ~t4_pc~0; 1671#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1617#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1618#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2054#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2033#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1686#L441-24 assume !(1 == ~t5_pc~0); 1687#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1882#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1834#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1544#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 1545#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1967#L460-24 assume 1 == ~t6_pc~0; 1968#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2028#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1726#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1727#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1960#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1961#L774-3 assume !(1 == ~M_E~0); 1898#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1748#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1457#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1435#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1436#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1553#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1881#L809-3 assume !(1 == ~E_1~0); 1551#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1552#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1711#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1695#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1696#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1536#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1537#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1534#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1628#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1470#L1084 assume !(0 == start_simulation_~tmp~3#1); 1471#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1724#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1440#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1498#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1499#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1566#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1567#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1736#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1673#L1065-2 [2024-10-31 22:11:27,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:27,462 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2024-10-31 22:11:27,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:27,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303777910] [2024-10-31 22:11:27,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:27,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:27,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:27,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:27,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:27,620 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303777910] [2024-10-31 22:11:27,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [303777910] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:27,620 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:27,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:27,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666537353] [2024-10-31 22:11:27,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:27,622 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:27,622 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:27,622 INFO L85 PathProgramCache]: Analyzing trace with hash -1334440743, now seen corresponding path program 1 times [2024-10-31 22:11:27,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:27,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228732253] [2024-10-31 22:11:27,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:27,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:27,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:27,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:27,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:27,759 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228732253] [2024-10-31 22:11:27,759 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [228732253] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:27,759 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:27,759 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:27,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461387930] [2024-10-31 22:11:27,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:27,760 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:27,760 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:27,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:27,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:27,766 INFO L87 Difference]: Start difference. First operand 693 states and 1035 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:27,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:27,790 INFO L93 Difference]: Finished difference Result 693 states and 1034 transitions. [2024-10-31 22:11:27,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1034 transitions. [2024-10-31 22:11:27,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:27,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1034 transitions. [2024-10-31 22:11:27,802 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-10-31 22:11:27,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-10-31 22:11:27,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1034 transitions. [2024-10-31 22:11:27,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:27,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1034 transitions. [2024-10-31 22:11:27,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1034 transitions. [2024-10-31 22:11:27,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-10-31 22:11:27,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.492063492063492) internal successors, (1034), 692 states have internal predecessors, (1034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:27,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1034 transitions. [2024-10-31 22:11:27,842 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1034 transitions. [2024-10-31 22:11:27,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:27,845 INFO L425 stractBuchiCegarLoop]: Abstraction has 693 states and 1034 transitions. [2024-10-31 22:11:27,847 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:11:27,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1034 transitions. [2024-10-31 22:11:27,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:27,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:27,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:27,853 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:27,854 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:27,856 INFO L745 eck$LassoCheckResult]: Stem: 3162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3325#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3462#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 3061#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3062#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2889#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2890#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2866#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2867#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3035#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3195#L696 assume !(0 == ~M_E~0); 3196#L696-2 assume !(0 == ~T1_E~0); 3465#L701-1 assume !(0 == ~T2_E~0); 3467#L706-1 assume !(0 == ~T3_E~0); 3303#L711-1 assume !(0 == ~T4_E~0); 3096#L716-1 assume !(0 == ~T5_E~0); 3097#L721-1 assume !(0 == ~T6_E~0); 3261#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3262#L731-1 assume !(0 == ~E_1~0); 3231#L736-1 assume !(0 == ~E_2~0); 3232#L741-1 assume !(0 == ~E_3~0); 3312#L746-1 assume !(0 == ~E_4~0); 3121#L751-1 assume !(0 == ~E_5~0); 3122#L756-1 assume !(0 == ~E_6~0); 3093#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2912#L346 assume !(1 == ~m_pc~0); 2913#L346-2 is_master_triggered_~__retres1~0#1 := 0; 3135#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3127#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3128#L861 assume !(0 != activate_threads_~tmp~1#1); 3444#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2946#L365 assume 1 == ~t1_pc~0; 2947#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3079#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2895#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2896#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2936#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3359#L384 assume !(1 == ~t2_pc~0); 3353#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3354#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3326#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2854#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2855#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3210#L403 assume 1 == ~t3_pc~0; 3098#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3099#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2824#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2825#L885 assume !(0 != activate_threads_~tmp___2~0#1); 3203#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3204#L422 assume 1 == ~t4_pc~0; 2849#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2850#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2999#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3000#L893 assume !(0 != activate_threads_~tmp___3~0#1); 3282#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2868#L441 assume !(1 == ~t5_pc~0); 2869#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3440#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3138#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3139#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3291#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3292#L460 assume 1 == ~t6_pc~0; 2809#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2810#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2876#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3314#L909 assume !(0 != activate_threads_~tmp___5~0#1); 3403#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3270#L774 assume !(1 == ~M_E~0); 3271#L774-2 assume !(1 == ~T1_E~0); 3420#L779-1 assume !(1 == ~T2_E~0); 3181#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3182#L789-1 assume !(1 == ~T4_E~0); 2931#L794-1 assume !(1 == ~T5_E~0); 2932#L799-1 assume !(1 == ~T6_E~0); 3485#L804-1 assume !(1 == ~E_M~0); 3486#L809-1 assume !(1 == ~E_1~0); 3258#L814-1 assume !(1 == ~E_2~0); 2828#L819-1 assume !(1 == ~E_3~0); 2829#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3320#L829-1 assume !(1 == ~E_5~0); 3410#L834-1 assume !(1 == ~E_6~0); 3080#L839-1 assume { :end_inline_reset_delta_events } true; 3066#L1065-2 [2024-10-31 22:11:27,857 INFO L747 eck$LassoCheckResult]: Loop: 3066#L1065-2 assume !false; 3067#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3038#L671-1 assume !false; 3385#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3390#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2903#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2917#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3346#L582 assume !(0 != eval_~tmp~0#1); 3013#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3014#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3112#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3113#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3160#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3161#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3472#L711-3 assume !(0 == ~T4_E~0); 3466#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3315#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3142#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3143#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3308#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3309#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3090#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3091#L751-3 assume !(0 == ~E_5~0); 3208#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2954#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2955#L346-24 assume !(1 == ~m_pc~0); 2989#L346-26 is_master_triggered_~__retres1~0#1 := 0; 3086#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3033#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3034#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3418#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3025#L365-24 assume 1 == ~t1_pc~0; 3026#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3316#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3463#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3381#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3382#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2974#L384-24 assume 1 == ~t2_pc~0; 2976#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2996#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3493#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3299#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3005#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3006#L403-24 assume 1 == ~t3_pc~0; 3123#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3164#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3165#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3256#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3257#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3063#L422-24 assume 1 == ~t4_pc~0; 3064#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3011#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3012#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3447#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3426#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3081#L441-24 assume !(1 == ~t5_pc~0); 3082#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 3276#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3227#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2937#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 2938#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3360#L460-24 assume 1 == ~t6_pc~0; 3361#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3421#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3119#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3120#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3355#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3356#L774-3 assume !(1 == ~M_E~0); 3293#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3141#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2852#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2853#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2830#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2831#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2949#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3274#L809-3 assume !(1 == ~E_1~0); 2944#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2945#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3104#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3088#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3089#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2929#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2930#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2927#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3021#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2863#L1084 assume !(0 == start_simulation_~tmp~3#1); 2864#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3117#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2833#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2894#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2960#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2961#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3129#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 3066#L1065-2 [2024-10-31 22:11:27,858 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:27,860 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2024-10-31 22:11:27,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:27,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441067182] [2024-10-31 22:11:27,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:27,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:27,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:27,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:27,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:27,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441067182] [2024-10-31 22:11:27,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1441067182] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:27,932 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:27,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:27,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285678342] [2024-10-31 22:11:27,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:27,934 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:27,936 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:27,936 INFO L85 PathProgramCache]: Analyzing trace with hash -437079207, now seen corresponding path program 1 times [2024-10-31 22:11:27,936 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:27,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445347406] [2024-10-31 22:11:27,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:27,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:27,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:28,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:28,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:28,068 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445347406] [2024-10-31 22:11:28,068 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445347406] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:28,068 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:28,068 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:28,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876281580] [2024-10-31 22:11:28,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:28,069 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:28,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:28,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:28,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:28,071 INFO L87 Difference]: Start difference. First operand 693 states and 1034 transitions. cyclomatic complexity: 342 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:28,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:28,092 INFO L93 Difference]: Finished difference Result 693 states and 1033 transitions. [2024-10-31 22:11:28,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1033 transitions. [2024-10-31 22:11:28,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:28,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1033 transitions. [2024-10-31 22:11:28,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-10-31 22:11:28,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-10-31 22:11:28,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1033 transitions. [2024-10-31 22:11:28,104 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:28,104 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1033 transitions. [2024-10-31 22:11:28,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1033 transitions. [2024-10-31 22:11:28,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-10-31 22:11:28,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4906204906204905) internal successors, (1033), 692 states have internal predecessors, (1033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:28,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1033 transitions. [2024-10-31 22:11:28,118 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1033 transitions. [2024-10-31 22:11:28,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:28,121 INFO L425 stractBuchiCegarLoop]: Abstraction has 693 states and 1033 transitions. [2024-10-31 22:11:28,121 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:11:28,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1033 transitions. [2024-10-31 22:11:28,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:28,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:28,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:28,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:28,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:28,132 INFO L745 eck$LassoCheckResult]: Stem: 4555#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4717#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4718#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4855#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 4454#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4455#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4284#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4285#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4259#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4260#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4428#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4588#L696 assume !(0 == ~M_E~0); 4589#L696-2 assume !(0 == ~T1_E~0); 4858#L701-1 assume !(0 == ~T2_E~0); 4860#L706-1 assume !(0 == ~T3_E~0); 4696#L711-1 assume !(0 == ~T4_E~0); 4489#L716-1 assume !(0 == ~T5_E~0); 4490#L721-1 assume !(0 == ~T6_E~0); 4654#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4655#L731-1 assume !(0 == ~E_1~0); 4624#L736-1 assume !(0 == ~E_2~0); 4625#L741-1 assume !(0 == ~E_3~0); 4705#L746-1 assume !(0 == ~E_4~0); 4514#L751-1 assume !(0 == ~E_5~0); 4515#L756-1 assume !(0 == ~E_6~0); 4486#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4305#L346 assume !(1 == ~m_pc~0); 4306#L346-2 is_master_triggered_~__retres1~0#1 := 0; 4528#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4520#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4521#L861 assume !(0 != activate_threads_~tmp~1#1); 4837#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4340#L365 assume 1 == ~t1_pc~0; 4341#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4472#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4288#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4289#L869 assume !(0 != activate_threads_~tmp___0~0#1); 4329#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4752#L384 assume !(1 == ~t2_pc~0); 4746#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4747#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4247#L877 assume !(0 != activate_threads_~tmp___1~0#1); 4248#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4603#L403 assume 1 == ~t3_pc~0; 4491#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4492#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4217#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4218#L885 assume !(0 != activate_threads_~tmp___2~0#1); 4596#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4597#L422 assume 1 == ~t4_pc~0; 4244#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4245#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4392#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4393#L893 assume !(0 != activate_threads_~tmp___3~0#1); 4675#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4261#L441 assume !(1 == ~t5_pc~0); 4262#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4833#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4531#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4532#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4684#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4685#L460 assume 1 == ~t6_pc~0; 4202#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4203#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4269#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4707#L909 assume !(0 != activate_threads_~tmp___5~0#1); 4796#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4663#L774 assume !(1 == ~M_E~0); 4664#L774-2 assume !(1 == ~T1_E~0); 4813#L779-1 assume !(1 == ~T2_E~0); 4574#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4575#L789-1 assume !(1 == ~T4_E~0); 4324#L794-1 assume !(1 == ~T5_E~0); 4325#L799-1 assume !(1 == ~T6_E~0); 4878#L804-1 assume !(1 == ~E_M~0); 4879#L809-1 assume !(1 == ~E_1~0); 4651#L814-1 assume !(1 == ~E_2~0); 4223#L819-1 assume !(1 == ~E_3~0); 4224#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4713#L829-1 assume !(1 == ~E_5~0); 4803#L834-1 assume !(1 == ~E_6~0); 4473#L839-1 assume { :end_inline_reset_delta_events } true; 4459#L1065-2 [2024-10-31 22:11:28,133 INFO L747 eck$LassoCheckResult]: Loop: 4459#L1065-2 assume !false; 4460#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4431#L671-1 assume !false; 4778#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4783#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4296#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4310#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4739#L582 assume !(0 != eval_~tmp~0#1); 4406#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4407#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4505#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4506#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4553#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4554#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4865#L711-3 assume !(0 == ~T4_E~0); 4859#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4708#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4535#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4536#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4701#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4702#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4483#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4484#L751-3 assume !(0 == ~E_5~0); 4601#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4347#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4348#L346-24 assume !(1 == ~m_pc~0); 4382#L346-26 is_master_triggered_~__retres1~0#1 := 0; 4479#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4426#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4427#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4811#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4420#L365-24 assume 1 == ~t1_pc~0; 4421#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4709#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4856#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4774#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4775#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4369#L384-24 assume !(1 == ~t2_pc~0); 4370#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4389#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4886#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4692#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4398#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4399#L403-24 assume 1 == ~t3_pc~0; 4516#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4557#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4558#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4649#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4650#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4456#L422-24 assume 1 == ~t4_pc~0; 4457#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4404#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4405#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4840#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4819#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4474#L441-24 assume !(1 == ~t5_pc~0); 4475#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 4669#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4620#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4330#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 4331#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4753#L460-24 assume 1 == ~t6_pc~0; 4754#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4814#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4512#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4513#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4748#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4749#L774-3 assume !(1 == ~M_E~0); 4686#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4534#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4242#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4243#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4221#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4222#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4339#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4667#L809-3 assume !(1 == ~E_1~0); 4332#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4333#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4495#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4480#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4481#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4322#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4323#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4320#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4414#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4256#L1084 assume !(0 == start_simulation_~tmp~3#1); 4257#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4510#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4226#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4282#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4283#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4349#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4350#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4522#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 4459#L1065-2 [2024-10-31 22:11:28,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:28,133 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2024-10-31 22:11:28,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:28,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865859851] [2024-10-31 22:11:28,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:28,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:28,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:28,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:28,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:28,231 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865859851] [2024-10-31 22:11:28,231 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865859851] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:28,232 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:28,232 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:28,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615005880] [2024-10-31 22:11:28,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:28,233 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:28,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:28,234 INFO L85 PathProgramCache]: Analyzing trace with hash -196811878, now seen corresponding path program 1 times [2024-10-31 22:11:28,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:28,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933603046] [2024-10-31 22:11:28,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:28,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:28,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:28,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:28,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:28,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [933603046] [2024-10-31 22:11:28,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [933603046] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:28,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:28,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:28,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1409191410] [2024-10-31 22:11:28,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:28,329 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:28,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:28,329 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:28,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:28,330 INFO L87 Difference]: Start difference. First operand 693 states and 1033 transitions. cyclomatic complexity: 341 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:28,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:28,353 INFO L93 Difference]: Finished difference Result 693 states and 1032 transitions. [2024-10-31 22:11:28,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1032 transitions. [2024-10-31 22:11:28,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:28,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1032 transitions. [2024-10-31 22:11:28,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-10-31 22:11:28,365 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-10-31 22:11:28,365 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1032 transitions. [2024-10-31 22:11:28,367 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:28,367 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1032 transitions. [2024-10-31 22:11:28,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1032 transitions. [2024-10-31 22:11:28,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-10-31 22:11:28,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4891774891774892) internal successors, (1032), 692 states have internal predecessors, (1032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:28,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1032 transitions. [2024-10-31 22:11:28,389 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1032 transitions. [2024-10-31 22:11:28,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:28,391 INFO L425 stractBuchiCegarLoop]: Abstraction has 693 states and 1032 transitions. [2024-10-31 22:11:28,391 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:11:28,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1032 transitions. [2024-10-31 22:11:28,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:28,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:28,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:28,401 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:28,402 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:28,402 INFO L745 eck$LassoCheckResult]: Stem: 5950#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5951#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6110#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6111#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6248#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 5847#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5848#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5679#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5680#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5652#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5653#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5821#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5981#L696 assume !(0 == ~M_E~0); 5982#L696-2 assume !(0 == ~T1_E~0); 6251#L701-1 assume !(0 == ~T2_E~0); 6254#L706-1 assume !(0 == ~T3_E~0); 6089#L711-1 assume !(0 == ~T4_E~0); 5882#L716-1 assume !(0 == ~T5_E~0); 5883#L721-1 assume !(0 == ~T6_E~0); 6047#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6048#L731-1 assume !(0 == ~E_1~0); 6017#L736-1 assume !(0 == ~E_2~0); 6018#L741-1 assume !(0 == ~E_3~0); 6098#L746-1 assume !(0 == ~E_4~0); 5907#L751-1 assume !(0 == ~E_5~0); 5908#L756-1 assume !(0 == ~E_6~0); 5879#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5700#L346 assume !(1 == ~m_pc~0); 5701#L346-2 is_master_triggered_~__retres1~0#1 := 0; 5921#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5913#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5914#L861 assume !(0 != activate_threads_~tmp~1#1); 6230#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5733#L365 assume 1 == ~t1_pc~0; 5734#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5868#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5686#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5687#L869 assume !(0 != activate_threads_~tmp___0~0#1); 5722#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6145#L384 assume !(1 == ~t2_pc~0); 6141#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6142#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6116#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5642#L877 assume !(0 != activate_threads_~tmp___1~0#1); 5643#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5997#L403 assume 1 == ~t3_pc~0; 5884#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5885#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5610#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5611#L885 assume !(0 != activate_threads_~tmp___2~0#1); 5992#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5993#L422 assume 1 == ~t4_pc~0; 5637#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5638#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5785#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5786#L893 assume !(0 != activate_threads_~tmp___3~0#1); 6068#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5654#L441 assume !(1 == ~t5_pc~0); 5655#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6227#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5925#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5926#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6078#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6079#L460 assume 1 == ~t6_pc~0; 5598#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5599#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5662#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6100#L909 assume !(0 != activate_threads_~tmp___5~0#1); 6189#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6056#L774 assume !(1 == ~M_E~0); 6057#L774-2 assume !(1 == ~T1_E~0); 6206#L779-1 assume !(1 == ~T2_E~0); 5967#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5968#L789-1 assume !(1 == ~T4_E~0); 5717#L794-1 assume !(1 == ~T5_E~0); 5718#L799-1 assume !(1 == ~T6_E~0); 6271#L804-1 assume !(1 == ~E_M~0); 6272#L809-1 assume !(1 == ~E_1~0); 6045#L814-1 assume !(1 == ~E_2~0); 5616#L819-1 assume !(1 == ~E_3~0); 5617#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6106#L829-1 assume !(1 == ~E_5~0); 6196#L834-1 assume !(1 == ~E_6~0); 5869#L839-1 assume { :end_inline_reset_delta_events } true; 5856#L1065-2 [2024-10-31 22:11:28,403 INFO L747 eck$LassoCheckResult]: Loop: 5856#L1065-2 assume !false; 5857#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5824#L671-1 assume !false; 6175#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6176#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5689#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5703#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6133#L582 assume !(0 != eval_~tmp~0#1); 5801#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5802#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5898#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5899#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5946#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5947#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6258#L711-3 assume !(0 == ~T4_E~0); 6252#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6102#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5928#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5929#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6094#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6095#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5876#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5877#L751-3 assume !(0 == ~E_5~0); 5994#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5740#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5741#L346-24 assume 1 == ~m_pc~0; 5776#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5870#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5819#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5820#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6204#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5811#L365-24 assume 1 == ~t1_pc~0; 5812#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6101#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6249#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6167#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6168#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5760#L384-24 assume !(1 == ~t2_pc~0); 5761#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 5782#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6279#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6085#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5791#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5792#L403-24 assume 1 == ~t3_pc~0; 5909#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5948#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5949#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6042#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6043#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5849#L422-24 assume 1 == ~t4_pc~0; 5850#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5796#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5797#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6233#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6212#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5865#L441-24 assume !(1 == ~t5_pc~0); 5866#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 6061#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6013#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5723#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 5724#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6146#L460-24 assume 1 == ~t6_pc~0; 6147#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6207#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5905#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5906#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6139#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6140#L774-3 assume !(1 == ~M_E~0); 6077#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5927#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5635#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5636#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5614#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5615#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5732#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6060#L809-3 assume !(1 == ~E_1~0); 5730#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5731#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5890#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5874#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5875#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5715#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5716#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5713#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5649#L1084 assume !(0 == start_simulation_~tmp~3#1); 5650#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5903#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5619#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5678#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5746#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5747#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5915#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 5856#L1065-2 [2024-10-31 22:11:28,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:28,404 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2024-10-31 22:11:28,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:28,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587806566] [2024-10-31 22:11:28,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:28,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:28,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:28,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:28,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:28,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587806566] [2024-10-31 22:11:28,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587806566] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:28,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:28,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:28,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100435831] [2024-10-31 22:11:28,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:28,469 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:28,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:28,470 INFO L85 PathProgramCache]: Analyzing trace with hash -1334440743, now seen corresponding path program 2 times [2024-10-31 22:11:28,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:28,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498886357] [2024-10-31 22:11:28,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:28,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:28,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:28,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:28,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:28,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498886357] [2024-10-31 22:11:28,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498886357] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:28,548 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:28,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:28,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839244776] [2024-10-31 22:11:28,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:28,549 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:28,549 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:28,550 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:28,550 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:28,550 INFO L87 Difference]: Start difference. First operand 693 states and 1032 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:28,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:28,569 INFO L93 Difference]: Finished difference Result 693 states and 1031 transitions. [2024-10-31 22:11:28,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1031 transitions. [2024-10-31 22:11:28,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:28,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1031 transitions. [2024-10-31 22:11:28,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-10-31 22:11:28,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-10-31 22:11:28,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1031 transitions. [2024-10-31 22:11:28,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:28,579 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1031 transitions. [2024-10-31 22:11:28,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1031 transitions. [2024-10-31 22:11:28,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-10-31 22:11:28,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4877344877344878) internal successors, (1031), 692 states have internal predecessors, (1031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:28,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1031 transitions. [2024-10-31 22:11:28,592 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1031 transitions. [2024-10-31 22:11:28,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:28,593 INFO L425 stractBuchiCegarLoop]: Abstraction has 693 states and 1031 transitions. [2024-10-31 22:11:28,593 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:11:28,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1031 transitions. [2024-10-31 22:11:28,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:28,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:28,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:28,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:28,599 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:28,600 INFO L745 eck$LassoCheckResult]: Stem: 7341#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7503#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7504#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7641#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 7240#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7241#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7068#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7069#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7045#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7046#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7214#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7374#L696 assume !(0 == ~M_E~0); 7375#L696-2 assume !(0 == ~T1_E~0); 7644#L701-1 assume !(0 == ~T2_E~0); 7646#L706-1 assume !(0 == ~T3_E~0); 7482#L711-1 assume !(0 == ~T4_E~0); 7275#L716-1 assume !(0 == ~T5_E~0); 7276#L721-1 assume !(0 == ~T6_E~0); 7440#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7441#L731-1 assume !(0 == ~E_1~0); 7410#L736-1 assume !(0 == ~E_2~0); 7411#L741-1 assume !(0 == ~E_3~0); 7491#L746-1 assume !(0 == ~E_4~0); 7300#L751-1 assume !(0 == ~E_5~0); 7301#L756-1 assume !(0 == ~E_6~0); 7272#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7091#L346 assume !(1 == ~m_pc~0); 7092#L346-2 is_master_triggered_~__retres1~0#1 := 0; 7314#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7306#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7307#L861 assume !(0 != activate_threads_~tmp~1#1); 7623#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7125#L365 assume 1 == ~t1_pc~0; 7126#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7258#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7074#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7075#L869 assume !(0 != activate_threads_~tmp___0~0#1); 7115#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7538#L384 assume !(1 == ~t2_pc~0); 7532#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7533#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7505#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7033#L877 assume !(0 != activate_threads_~tmp___1~0#1); 7034#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7389#L403 assume 1 == ~t3_pc~0; 7277#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7278#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7003#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7004#L885 assume !(0 != activate_threads_~tmp___2~0#1); 7382#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7383#L422 assume 1 == ~t4_pc~0; 7028#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7029#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7178#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7179#L893 assume !(0 != activate_threads_~tmp___3~0#1); 7461#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7047#L441 assume !(1 == ~t5_pc~0); 7048#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7619#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7317#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7318#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7470#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7471#L460 assume 1 == ~t6_pc~0; 6988#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6989#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7055#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7493#L909 assume !(0 != activate_threads_~tmp___5~0#1); 7582#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7449#L774 assume !(1 == ~M_E~0); 7450#L774-2 assume !(1 == ~T1_E~0); 7599#L779-1 assume !(1 == ~T2_E~0); 7360#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7361#L789-1 assume !(1 == ~T4_E~0); 7110#L794-1 assume !(1 == ~T5_E~0); 7111#L799-1 assume !(1 == ~T6_E~0); 7664#L804-1 assume !(1 == ~E_M~0); 7665#L809-1 assume !(1 == ~E_1~0); 7437#L814-1 assume !(1 == ~E_2~0); 7007#L819-1 assume !(1 == ~E_3~0); 7008#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7499#L829-1 assume !(1 == ~E_5~0); 7589#L834-1 assume !(1 == ~E_6~0); 7259#L839-1 assume { :end_inline_reset_delta_events } true; 7245#L1065-2 [2024-10-31 22:11:28,600 INFO L747 eck$LassoCheckResult]: Loop: 7245#L1065-2 assume !false; 7246#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7217#L671-1 assume !false; 7564#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7569#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7082#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7096#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7525#L582 assume !(0 != eval_~tmp~0#1); 7192#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7193#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7291#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7292#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7339#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7340#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7651#L711-3 assume !(0 == ~T4_E~0); 7645#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7494#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7321#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7322#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7487#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7488#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7269#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7270#L751-3 assume !(0 == ~E_5~0); 7387#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7133#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7134#L346-24 assume !(1 == ~m_pc~0); 7168#L346-26 is_master_triggered_~__retres1~0#1 := 0; 7265#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7212#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7213#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7597#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7204#L365-24 assume 1 == ~t1_pc~0; 7205#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7495#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7642#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7560#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7561#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7153#L384-24 assume !(1 == ~t2_pc~0); 7154#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 7175#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7672#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7478#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7184#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7185#L403-24 assume 1 == ~t3_pc~0; 7302#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7343#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7344#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7435#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7436#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7242#L422-24 assume 1 == ~t4_pc~0; 7243#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7190#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7191#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7626#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7605#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7260#L441-24 assume !(1 == ~t5_pc~0); 7261#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 7455#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7406#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7116#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 7117#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7539#L460-24 assume 1 == ~t6_pc~0; 7540#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7600#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7298#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7299#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7534#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7535#L774-3 assume !(1 == ~M_E~0); 7472#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7320#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7031#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7032#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7009#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7010#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7128#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7453#L809-3 assume !(1 == ~E_1~0); 7123#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7124#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7283#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7267#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7268#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7108#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7109#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7106#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7042#L1084 assume !(0 == start_simulation_~tmp~3#1); 7043#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7296#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7012#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7072#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7073#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7139#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7140#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7308#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 7245#L1065-2 [2024-10-31 22:11:28,601 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:28,601 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2024-10-31 22:11:28,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:28,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289974169] [2024-10-31 22:11:28,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:28,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:28,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:28,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:28,646 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:28,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289974169] [2024-10-31 22:11:28,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289974169] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:28,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:28,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:28,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7555282] [2024-10-31 22:11:28,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:28,653 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:28,653 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:28,653 INFO L85 PathProgramCache]: Analyzing trace with hash -196811878, now seen corresponding path program 2 times [2024-10-31 22:11:28,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:28,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770337290] [2024-10-31 22:11:28,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:28,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:28,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:28,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:28,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:28,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770337290] [2024-10-31 22:11:28,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770337290] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:28,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:28,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:28,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1009901226] [2024-10-31 22:11:28,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:28,722 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:28,722 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:28,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:28,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:28,722 INFO L87 Difference]: Start difference. First operand 693 states and 1031 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:28,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:28,742 INFO L93 Difference]: Finished difference Result 693 states and 1030 transitions. [2024-10-31 22:11:28,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1030 transitions. [2024-10-31 22:11:28,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:28,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1030 transitions. [2024-10-31 22:11:28,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-10-31 22:11:28,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-10-31 22:11:28,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1030 transitions. [2024-10-31 22:11:28,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:28,753 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1030 transitions. [2024-10-31 22:11:28,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1030 transitions. [2024-10-31 22:11:28,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-10-31 22:11:28,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4862914862914862) internal successors, (1030), 692 states have internal predecessors, (1030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:28,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1030 transitions. [2024-10-31 22:11:28,767 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1030 transitions. [2024-10-31 22:11:28,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:28,769 INFO L425 stractBuchiCegarLoop]: Abstraction has 693 states and 1030 transitions. [2024-10-31 22:11:28,770 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:11:28,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1030 transitions. [2024-10-31 22:11:28,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-10-31 22:11:28,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:28,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:28,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:28,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:28,777 INFO L745 eck$LassoCheckResult]: Stem: 8734#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8896#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8897#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9034#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 8633#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8634#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8465#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8466#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8438#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8439#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8607#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8767#L696 assume !(0 == ~M_E~0); 8768#L696-2 assume !(0 == ~T1_E~0); 9037#L701-1 assume !(0 == ~T2_E~0); 9039#L706-1 assume !(0 == ~T3_E~0); 8875#L711-1 assume !(0 == ~T4_E~0); 8668#L716-1 assume !(0 == ~T5_E~0); 8669#L721-1 assume !(0 == ~T6_E~0); 8833#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8834#L731-1 assume !(0 == ~E_1~0); 8803#L736-1 assume !(0 == ~E_2~0); 8804#L741-1 assume !(0 == ~E_3~0); 8884#L746-1 assume !(0 == ~E_4~0); 8693#L751-1 assume !(0 == ~E_5~0); 8694#L756-1 assume !(0 == ~E_6~0); 8665#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8484#L346 assume !(1 == ~m_pc~0); 8485#L346-2 is_master_triggered_~__retres1~0#1 := 0; 8707#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8699#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8700#L861 assume !(0 != activate_threads_~tmp~1#1); 9016#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8519#L365 assume 1 == ~t1_pc~0; 8520#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8654#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8469#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8470#L869 assume !(0 != activate_threads_~tmp___0~0#1); 8508#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8931#L384 assume !(1 == ~t2_pc~0); 8927#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8928#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8898#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8426#L877 assume !(0 != activate_threads_~tmp___1~0#1); 8427#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8782#L403 assume 1 == ~t3_pc~0; 8670#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8671#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8396#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8397#L885 assume !(0 != activate_threads_~tmp___2~0#1); 8775#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8776#L422 assume 1 == ~t4_pc~0; 8423#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8424#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8571#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8572#L893 assume !(0 != activate_threads_~tmp___3~0#1); 8854#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8440#L441 assume !(1 == ~t5_pc~0); 8441#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9012#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8710#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8711#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8864#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8865#L460 assume 1 == ~t6_pc~0; 8381#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8382#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8448#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8886#L909 assume !(0 != activate_threads_~tmp___5~0#1); 8975#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8842#L774 assume !(1 == ~M_E~0); 8843#L774-2 assume !(1 == ~T1_E~0); 8992#L779-1 assume !(1 == ~T2_E~0); 8753#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8754#L789-1 assume !(1 == ~T4_E~0); 8503#L794-1 assume !(1 == ~T5_E~0); 8504#L799-1 assume !(1 == ~T6_E~0); 9057#L804-1 assume !(1 == ~E_M~0); 9058#L809-1 assume !(1 == ~E_1~0); 8830#L814-1 assume !(1 == ~E_2~0); 8402#L819-1 assume !(1 == ~E_3~0); 8403#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8892#L829-1 assume !(1 == ~E_5~0); 8982#L834-1 assume !(1 == ~E_6~0); 8655#L839-1 assume { :end_inline_reset_delta_events } true; 8638#L1065-2 [2024-10-31 22:11:28,778 INFO L747 eck$LassoCheckResult]: Loop: 8638#L1065-2 assume !false; 8639#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8610#L671-1 assume !false; 8957#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8962#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8475#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8489#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8918#L582 assume !(0 != eval_~tmp~0#1); 8585#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8586#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8684#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8685#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8732#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8733#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9044#L711-3 assume !(0 == ~T4_E~0); 9038#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8887#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8714#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8715#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8880#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8881#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8662#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8663#L751-3 assume !(0 == ~E_5~0); 8780#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8526#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8527#L346-24 assume !(1 == ~m_pc~0); 8561#L346-26 is_master_triggered_~__retres1~0#1 := 0; 8658#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8605#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8606#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8990#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8599#L365-24 assume 1 == ~t1_pc~0; 8600#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8888#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9035#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8953#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8954#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8548#L384-24 assume !(1 == ~t2_pc~0); 8549#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8568#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9065#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8872#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8577#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8578#L403-24 assume 1 == ~t3_pc~0; 8695#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8736#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8737#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8828#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8829#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8635#L422-24 assume 1 == ~t4_pc~0; 8636#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8582#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8583#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9019#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8998#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8651#L441-24 assume !(1 == ~t5_pc~0); 8652#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 8847#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8799#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8509#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 8510#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8932#L460-24 assume 1 == ~t6_pc~0; 8933#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8993#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8691#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8692#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8925#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8926#L774-3 assume !(1 == ~M_E~0); 8863#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8713#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8421#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8422#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8400#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8401#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8518#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8846#L809-3 assume !(1 == ~E_1~0); 8513#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8514#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8674#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8659#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8660#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8501#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8502#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8499#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8593#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8435#L1084 assume !(0 == start_simulation_~tmp~3#1); 8436#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8689#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8405#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8463#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8464#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8528#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8529#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8701#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 8638#L1065-2 [2024-10-31 22:11:28,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:28,780 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2024-10-31 22:11:28,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:28,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956293663] [2024-10-31 22:11:28,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:28,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:28,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:28,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:28,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:28,894 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956293663] [2024-10-31 22:11:28,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956293663] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:28,895 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:28,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:28,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547799328] [2024-10-31 22:11:28,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:28,895 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:28,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:28,896 INFO L85 PathProgramCache]: Analyzing trace with hash -196811878, now seen corresponding path program 3 times [2024-10-31 22:11:28,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:28,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787768963] [2024-10-31 22:11:28,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:28,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:28,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:28,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:28,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:28,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787768963] [2024-10-31 22:11:28,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [787768963] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:28,952 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:28,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:28,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577104922] [2024-10-31 22:11:28,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:28,953 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:28,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:28,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:11:28,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:11:28,954 INFO L87 Difference]: Start difference. First operand 693 states and 1030 transitions. cyclomatic complexity: 338 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:29,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:29,150 INFO L93 Difference]: Finished difference Result 1194 states and 1770 transitions. [2024-10-31 22:11:29,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1194 states and 1770 transitions. [2024-10-31 22:11:29,158 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1088 [2024-10-31 22:11:29,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1194 states to 1194 states and 1770 transitions. [2024-10-31 22:11:29,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1194 [2024-10-31 22:11:29,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1194 [2024-10-31 22:11:29,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1194 states and 1770 transitions. [2024-10-31 22:11:29,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:29,168 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1194 states and 1770 transitions. [2024-10-31 22:11:29,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1194 states and 1770 transitions. [2024-10-31 22:11:29,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1194 to 1193. [2024-10-31 22:11:29,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1193 states, 1193 states have (on average 1.4828164291701593) internal successors, (1769), 1192 states have internal predecessors, (1769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:29,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1193 states to 1193 states and 1769 transitions. [2024-10-31 22:11:29,195 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1193 states and 1769 transitions. [2024-10-31 22:11:29,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:11:29,196 INFO L425 stractBuchiCegarLoop]: Abstraction has 1193 states and 1769 transitions. [2024-10-31 22:11:29,197 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:11:29,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1193 states and 1769 transitions. [2024-10-31 22:11:29,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1088 [2024-10-31 22:11:29,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:29,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:29,205 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:29,205 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:29,205 INFO L745 eck$LassoCheckResult]: Stem: 10636#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10808#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10809#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10976#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 10532#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10533#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10358#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10359#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10335#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10336#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10506#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10671#L696 assume !(0 == ~M_E~0); 10672#L696-2 assume !(0 == ~T1_E~0); 10984#L701-1 assume !(0 == ~T2_E~0); 10986#L706-1 assume !(0 == ~T3_E~0); 10784#L711-1 assume !(0 == ~T4_E~0); 10567#L716-1 assume !(0 == ~T5_E~0); 10568#L721-1 assume !(0 == ~T6_E~0); 10740#L726-1 assume !(0 == ~E_M~0); 10741#L731-1 assume !(0 == ~E_1~0); 10709#L736-1 assume !(0 == ~E_2~0); 10710#L741-1 assume !(0 == ~E_3~0); 10795#L746-1 assume !(0 == ~E_4~0); 10595#L751-1 assume !(0 == ~E_5~0); 10596#L756-1 assume !(0 == ~E_6~0); 10564#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10382#L346 assume !(1 == ~m_pc~0); 10383#L346-2 is_master_triggered_~__retres1~0#1 := 0; 10609#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10601#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10602#L861 assume !(0 != activate_threads_~tmp~1#1); 10953#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10417#L365 assume 1 == ~t1_pc~0; 10418#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10550#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10365#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10366#L869 assume !(0 != activate_threads_~tmp___0~0#1); 10407#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10851#L384 assume !(1 == ~t2_pc~0); 10845#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10846#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10323#L877 assume !(0 != activate_threads_~tmp___1~0#1); 10324#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10687#L403 assume 1 == ~t3_pc~0; 10569#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10570#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10293#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10294#L885 assume !(0 != activate_threads_~tmp___2~0#1); 10679#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10680#L422 assume 1 == ~t4_pc~0; 10318#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10319#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10470#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10471#L893 assume !(0 != activate_threads_~tmp___3~0#1); 10763#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10337#L441 assume !(1 == ~t5_pc~0); 10338#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10949#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10612#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10613#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10772#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10773#L460 assume 1 == ~t6_pc~0; 10278#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10279#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10797#L909 assume !(0 != activate_threads_~tmp___5~0#1); 10910#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10749#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 10750#L774-2 assume !(1 == ~T1_E~0); 11009#L779-1 assume !(1 == ~T2_E~0); 11072#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11071#L789-1 assume !(1 == ~T4_E~0); 11070#L794-1 assume !(1 == ~T5_E~0); 11069#L799-1 assume !(1 == ~T6_E~0); 11068#L804-1 assume !(1 == ~E_M~0); 11013#L809-1 assume !(1 == ~E_1~0); 10737#L814-1 assume !(1 == ~E_2~0); 10297#L819-1 assume !(1 == ~E_3~0); 10298#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10803#L829-1 assume !(1 == ~E_5~0); 10917#L834-1 assume !(1 == ~E_6~0); 10918#L839-1 assume { :end_inline_reset_delta_events } true; 11055#L1065-2 [2024-10-31 22:11:29,206 INFO L747 eck$LassoCheckResult]: Loop: 11055#L1065-2 assume !false; 10820#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10509#L671-1 assume !false; 11000#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11001#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10387#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10388#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11039#L582 assume !(0 != eval_~tmp~0#1); 11041#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10962#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10963#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11045#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11412#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11411#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11410#L711-3 assume !(0 == ~T4_E~0); 11409#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11408#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11407#L726-3 assume !(0 == ~E_M~0); 11406#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11405#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11404#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11403#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11402#L751-3 assume !(0 == ~E_5~0); 11401#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11400#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11399#L346-24 assume !(1 == ~m_pc~0); 11397#L346-26 is_master_triggered_~__retres1~0#1 := 0; 11396#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11395#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11394#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11393#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11392#L365-24 assume 1 == ~t1_pc~0; 11390#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11389#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11388#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11387#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11386#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11385#L384-24 assume !(1 == ~t2_pc~0); 11383#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11382#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11381#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11380#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11379#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11378#L403-24 assume 1 == ~t3_pc~0; 11376#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11375#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11374#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11373#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11372#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11371#L422-24 assume !(1 == ~t4_pc~0); 11369#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 11368#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11367#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11366#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11365#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11364#L441-24 assume 1 == ~t5_pc~0; 11362#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11361#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11360#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11359#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 11358#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11357#L460-24 assume 1 == ~t6_pc~0; 11355#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11354#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11353#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11352#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11351#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11350#L774-3 assume !(1 == ~M_E~0); 11026#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11349#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11348#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11347#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11346#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11345#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11344#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10754#L809-3 assume !(1 == ~E_1~0); 11343#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11342#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11341#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11340#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11339#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11338#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11334#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11330#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11329#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11328#L1084 assume !(0 == start_simulation_~tmp~3#1); 10941#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11327#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11320#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11319#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 11318#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11317#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11316#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 11057#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 11055#L1065-2 [2024-10-31 22:11:29,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:29,207 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2024-10-31 22:11:29,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:29,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390293578] [2024-10-31 22:11:29,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:29,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:29,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:29,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:29,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:29,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390293578] [2024-10-31 22:11:29,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390293578] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:29,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:29,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:11:29,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [66660762] [2024-10-31 22:11:29,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:29,270 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:29,270 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:29,270 INFO L85 PathProgramCache]: Analyzing trace with hash -86295588, now seen corresponding path program 1 times [2024-10-31 22:11:29,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:29,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763248771] [2024-10-31 22:11:29,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:29,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:29,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:29,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:29,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:29,337 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763248771] [2024-10-31 22:11:29,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763248771] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:29,339 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:29,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:29,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647501393] [2024-10-31 22:11:29,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:29,340 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:29,340 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:29,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:29,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:29,341 INFO L87 Difference]: Start difference. First operand 1193 states and 1769 transitions. cyclomatic complexity: 578 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:29,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:29,443 INFO L93 Difference]: Finished difference Result 2162 states and 3179 transitions. [2024-10-31 22:11:29,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2162 states and 3179 transitions. [2024-10-31 22:11:29,458 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2054 [2024-10-31 22:11:29,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2162 states to 2162 states and 3179 transitions. [2024-10-31 22:11:29,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2162 [2024-10-31 22:11:29,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2162 [2024-10-31 22:11:29,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2162 states and 3179 transitions. [2024-10-31 22:11:29,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:29,474 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2162 states and 3179 transitions. [2024-10-31 22:11:29,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2162 states and 3179 transitions. [2024-10-31 22:11:29,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2162 to 2158. [2024-10-31 22:11:29,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2158 states, 2158 states have (on average 1.4712696941612604) internal successors, (3175), 2157 states have internal predecessors, (3175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:29,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2158 states to 2158 states and 3175 transitions. [2024-10-31 22:11:29,520 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2158 states and 3175 transitions. [2024-10-31 22:11:29,520 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:29,522 INFO L425 stractBuchiCegarLoop]: Abstraction has 2158 states and 3175 transitions. [2024-10-31 22:11:29,522 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:11:29,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2158 states and 3175 transitions. [2024-10-31 22:11:29,534 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2050 [2024-10-31 22:11:29,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:29,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:29,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:29,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:29,536 INFO L745 eck$LassoCheckResult]: Stem: 13994#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 13995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14170#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14171#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14324#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 13889#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13890#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13724#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13725#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13697#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13698#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13863#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14026#L696 assume !(0 == ~M_E~0); 14027#L696-2 assume !(0 == ~T1_E~0); 14332#L701-1 assume !(0 == ~T2_E~0); 14334#L706-1 assume !(0 == ~T3_E~0); 14146#L711-1 assume !(0 == ~T4_E~0); 13924#L716-1 assume !(0 == ~T5_E~0); 13925#L721-1 assume !(0 == ~T6_E~0); 14098#L726-1 assume !(0 == ~E_M~0); 14099#L731-1 assume !(0 == ~E_1~0); 14064#L736-1 assume !(0 == ~E_2~0); 14065#L741-1 assume !(0 == ~E_3~0); 14155#L746-1 assume !(0 == ~E_4~0); 13950#L751-1 assume !(0 == ~E_5~0); 13951#L756-1 assume !(0 == ~E_6~0); 13921#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13745#L346 assume !(1 == ~m_pc~0); 13746#L346-2 is_master_triggered_~__retres1~0#1 := 0; 13965#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13957#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13958#L861 assume !(0 != activate_threads_~tmp~1#1); 14304#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13779#L365 assume !(1 == ~t1_pc~0); 13780#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14315#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13731#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13732#L869 assume !(0 != activate_threads_~tmp___0~0#1); 13768#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14208#L384 assume !(1 == ~t2_pc~0); 14204#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14205#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14176#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13687#L877 assume !(0 != activate_threads_~tmp___1~0#1); 13688#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14044#L403 assume 1 == ~t3_pc~0; 13926#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13927#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13654#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13655#L885 assume !(0 != activate_threads_~tmp___2~0#1); 14039#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14040#L422 assume 1 == ~t4_pc~0; 13682#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13683#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13830#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13831#L893 assume !(0 != activate_threads_~tmp___3~0#1); 14125#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13699#L441 assume !(1 == ~t5_pc~0); 13700#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14301#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13969#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13970#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14135#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14136#L460 assume 1 == ~t6_pc~0; 13643#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13644#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13709#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14158#L909 assume !(0 != activate_threads_~tmp___5~0#1); 14258#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14110#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 14111#L774-2 assume !(1 == ~T1_E~0); 15042#L779-1 assume !(1 == ~T2_E~0); 15039#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14363#L789-1 assume !(1 == ~T4_E~0); 13762#L794-1 assume !(1 == ~T5_E~0); 13763#L799-1 assume !(1 == ~T6_E~0); 14395#L804-1 assume !(1 == ~E_M~0); 14368#L809-1 assume !(1 == ~E_1~0); 14392#L814-1 assume !(1 == ~E_2~0); 14675#L819-1 assume !(1 == ~E_3~0); 14166#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14167#L829-1 assume !(1 == ~E_5~0); 14265#L834-1 assume !(1 == ~E_6~0); 14266#L839-1 assume { :end_inline_reset_delta_events } true; 14587#L1065-2 [2024-10-31 22:11:29,537 INFO L747 eck$LassoCheckResult]: Loop: 14587#L1065-2 assume !false; 14582#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14580#L671-1 assume !false; 14579#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14576#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14570#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14569#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14567#L582 assume !(0 != eval_~tmp~0#1); 14566#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14564#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14561#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14558#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14559#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14552#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14553#L711-3 assume !(0 == ~T4_E~0); 14545#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14546#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14539#L726-3 assume !(0 == ~E_M~0); 14540#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14533#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14534#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14511#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14512#L751-3 assume !(0 == ~E_5~0); 14497#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14498#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14479#L346-24 assume !(1 == ~m_pc~0); 14480#L346-26 is_master_triggered_~__retres1~0#1 := 0; 15051#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15047#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15044#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15041#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15038#L365-24 assume !(1 == ~t1_pc~0); 15036#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15032#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15028#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15025#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15022#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15019#L384-24 assume !(1 == ~t2_pc~0); 15014#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 15011#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15007#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15004#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15000#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14996#L403-24 assume !(1 == ~t3_pc~0); 14992#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 14986#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14981#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14977#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14974#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14970#L422-24 assume !(1 == ~t4_pc~0); 14964#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 14959#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14954#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14950#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14946#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14943#L441-24 assume 1 == ~t5_pc~0; 14937#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14932#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14927#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14923#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 14920#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14917#L460-24 assume 1 == ~t6_pc~0; 14912#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14909#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14904#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14901#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14898#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14894#L774-3 assume !(1 == ~M_E~0); 14889#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14877#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14873#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14870#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14867#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14864#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14861#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14856#L809-3 assume !(1 == ~E_1~0); 14853#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14849#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14846#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14843#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14839#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14836#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14825#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14818#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14813#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 14808#L1084 assume !(0 == start_simulation_~tmp~3#1); 14804#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14682#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14674#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14673#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14672#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14610#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14600#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 14592#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 14587#L1065-2 [2024-10-31 22:11:29,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:29,537 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2024-10-31 22:11:29,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:29,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56258779] [2024-10-31 22:11:29,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:29,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:29,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:29,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:29,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:29,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56258779] [2024-10-31 22:11:29,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56258779] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:29,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:29,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:11:29,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209922295] [2024-10-31 22:11:29,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:29,634 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:29,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:29,634 INFO L85 PathProgramCache]: Analyzing trace with hash -1610208162, now seen corresponding path program 1 times [2024-10-31 22:11:29,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:29,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15490261] [2024-10-31 22:11:29,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:29,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:29,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:29,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:29,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:29,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15490261] [2024-10-31 22:11:29,680 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15490261] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:29,680 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:29,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:29,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737170731] [2024-10-31 22:11:29,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:29,681 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:29,681 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:29,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:29,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:29,682 INFO L87 Difference]: Start difference. First operand 2158 states and 3175 transitions. cyclomatic complexity: 1021 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:29,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:29,791 INFO L93 Difference]: Finished difference Result 3975 states and 5808 transitions. [2024-10-31 22:11:29,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3975 states and 5808 transitions. [2024-10-31 22:11:29,817 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3860 [2024-10-31 22:11:29,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3975 states to 3975 states and 5808 transitions. [2024-10-31 22:11:29,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3975 [2024-10-31 22:11:29,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3975 [2024-10-31 22:11:29,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3975 states and 5808 transitions. [2024-10-31 22:11:29,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:29,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3975 states and 5808 transitions. [2024-10-31 22:11:29,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3975 states and 5808 transitions. [2024-10-31 22:11:29,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3975 to 3967. [2024-10-31 22:11:29,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3967 states, 3967 states have (on average 1.4620620115956642) internal successors, (5800), 3966 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:29,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3967 states to 3967 states and 5800 transitions. [2024-10-31 22:11:29,937 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3967 states and 5800 transitions. [2024-10-31 22:11:29,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:29,938 INFO L425 stractBuchiCegarLoop]: Abstraction has 3967 states and 5800 transitions. [2024-10-31 22:11:29,938 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:11:29,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3967 states and 5800 transitions. [2024-10-31 22:11:29,957 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3852 [2024-10-31 22:11:29,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:29,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:29,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:29,959 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:29,960 INFO L745 eck$LassoCheckResult]: Stem: 20133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 20134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 20322#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20323#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20498#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 20028#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20029#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19863#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19864#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19836#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19837#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20006#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20172#L696 assume !(0 == ~M_E~0); 20173#L696-2 assume !(0 == ~T1_E~0); 20503#L701-1 assume !(0 == ~T2_E~0); 20505#L706-1 assume !(0 == ~T3_E~0); 20297#L711-1 assume !(0 == ~T4_E~0); 20065#L716-1 assume !(0 == ~T5_E~0); 20066#L721-1 assume !(0 == ~T6_E~0); 20245#L726-1 assume !(0 == ~E_M~0); 20246#L731-1 assume !(0 == ~E_1~0); 20208#L736-1 assume !(0 == ~E_2~0); 20209#L741-1 assume !(0 == ~E_3~0); 20307#L746-1 assume !(0 == ~E_4~0); 20087#L751-1 assume !(0 == ~E_5~0); 20088#L756-1 assume !(0 == ~E_6~0); 20062#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19883#L346 assume !(1 == ~m_pc~0); 19884#L346-2 is_master_triggered_~__retres1~0#1 := 0; 20106#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20095#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20096#L861 assume !(0 != activate_threads_~tmp~1#1); 20471#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19917#L365 assume !(1 == ~t1_pc~0); 19918#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20486#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19869#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19870#L869 assume !(0 != activate_threads_~tmp___0~0#1); 19906#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20362#L384 assume !(1 == ~t2_pc~0); 20358#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20359#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20328#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19826#L877 assume !(0 != activate_threads_~tmp___1~0#1); 19827#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20187#L403 assume !(1 == ~t3_pc~0); 20188#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20403#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19794#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19795#L885 assume !(0 != activate_threads_~tmp___2~0#1); 20182#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20183#L422 assume 1 == ~t4_pc~0; 19821#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19822#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19968#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19969#L893 assume !(0 != activate_threads_~tmp___3~0#1); 20274#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19838#L441 assume !(1 == ~t5_pc~0); 19839#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20467#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20108#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20109#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20286#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20287#L460 assume 1 == ~t6_pc~0; 19783#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19784#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19848#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20309#L909 assume !(0 != activate_threads_~tmp___5~0#1); 20419#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20257#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 20258#L774-2 assume !(1 == ~T1_E~0); 21809#L779-1 assume !(1 == ~T2_E~0); 21808#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21807#L789-1 assume !(1 == ~T4_E~0); 21806#L794-1 assume !(1 == ~T5_E~0); 21805#L799-1 assume !(1 == ~T6_E~0); 21804#L804-1 assume !(1 == ~E_M~0); 20544#L809-1 assume !(1 == ~E_1~0); 21803#L814-1 assume !(1 == ~E_2~0); 21802#L819-1 assume !(1 == ~E_3~0); 21801#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21800#L829-1 assume !(1 == ~E_5~0); 20427#L834-1 assume !(1 == ~E_6~0); 20428#L839-1 assume { :end_inline_reset_delta_events } true; 21021#L1065-2 [2024-10-31 22:11:29,960 INFO L747 eck$LassoCheckResult]: Loop: 21021#L1065-2 assume !false; 21022#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20856#L671-1 assume !false; 20857#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20783#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20778#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 21773#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21771#L582 assume !(0 != eval_~tmp~0#1); 21769#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21683#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21684#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22134#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22133#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22132#L711-3 assume !(0 == ~T4_E~0); 22131#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22130#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22129#L726-3 assume !(0 == ~E_M~0); 22128#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22127#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22126#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22125#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22124#L751-3 assume !(0 == ~E_5~0); 22123#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22122#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22121#L346-24 assume !(1 == ~m_pc~0); 22119#L346-26 is_master_triggered_~__retres1~0#1 := 0; 22118#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22117#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22116#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22115#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22114#L365-24 assume !(1 == ~t1_pc~0); 22113#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 22112#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22111#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22110#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22109#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22108#L384-24 assume !(1 == ~t2_pc~0); 22106#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 22105#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22104#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22103#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22102#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22101#L403-24 assume !(1 == ~t3_pc~0); 22100#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 22099#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22098#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22097#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22096#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22095#L422-24 assume !(1 == ~t4_pc~0); 22093#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 22092#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22091#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22090#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22089#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22088#L441-24 assume 1 == ~t5_pc~0; 22086#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22085#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22084#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22083#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 22080#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22078#L460-24 assume 1 == ~t6_pc~0; 22073#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22071#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22069#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22067#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22065#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22063#L774-3 assume !(1 == ~M_E~0); 21268#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21264#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21265#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22054#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22052#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22050#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22047#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21254#L809-3 assume !(1 == ~E_1~0); 22046#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22045#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22044#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22043#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22042#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22041#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 21200#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 21197#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 21192#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 21193#L1084 assume !(0 == start_simulation_~tmp~3#1); 21047#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 21048#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 21035#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 21033#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 21030#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21031#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21795#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 21794#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 21021#L1065-2 [2024-10-31 22:11:29,961 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:29,961 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2024-10-31 22:11:29,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:29,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583315602] [2024-10-31 22:11:29,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:29,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:29,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:30,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:30,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:30,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583315602] [2024-10-31 22:11:30,016 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583315602] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:30,016 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:30,016 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:11:30,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105241741] [2024-10-31 22:11:30,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:30,017 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:30,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:30,017 INFO L85 PathProgramCache]: Analyzing trace with hash -1610208162, now seen corresponding path program 2 times [2024-10-31 22:11:30,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:30,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583277527] [2024-10-31 22:11:30,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:30,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:30,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:30,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:30,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:30,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583277527] [2024-10-31 22:11:30,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583277527] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:30,064 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:30,064 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:30,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319957698] [2024-10-31 22:11:30,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:30,064 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:30,065 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:30,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:30,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:30,065 INFO L87 Difference]: Start difference. First operand 3967 states and 5800 transitions. cyclomatic complexity: 1841 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:30,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:30,187 INFO L93 Difference]: Finished difference Result 7374 states and 10725 transitions. [2024-10-31 22:11:30,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7374 states and 10725 transitions. [2024-10-31 22:11:30,288 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7232 [2024-10-31 22:11:30,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7374 states to 7374 states and 10725 transitions. [2024-10-31 22:11:30,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7374 [2024-10-31 22:11:30,331 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7374 [2024-10-31 22:11:30,332 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7374 states and 10725 transitions. [2024-10-31 22:11:30,342 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:30,342 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7374 states and 10725 transitions. [2024-10-31 22:11:30,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7374 states and 10725 transitions. [2024-10-31 22:11:30,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7374 to 7358. [2024-10-31 22:11:30,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7358 states, 7358 states have (on average 1.4554226692035879) internal successors, (10709), 7357 states have internal predecessors, (10709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:30,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7358 states to 7358 states and 10709 transitions. [2024-10-31 22:11:30,485 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7358 states and 10709 transitions. [2024-10-31 22:11:30,485 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:30,487 INFO L425 stractBuchiCegarLoop]: Abstraction has 7358 states and 10709 transitions. [2024-10-31 22:11:30,487 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:11:30,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7358 states and 10709 transitions. [2024-10-31 22:11:30,517 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7216 [2024-10-31 22:11:30,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:30,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:30,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:30,519 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:30,519 INFO L745 eck$LassoCheckResult]: Stem: 31472#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 31473#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 31670#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31671#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31841#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 31369#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31370#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31200#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31201#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31177#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31178#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31344#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31511#L696 assume !(0 == ~M_E~0); 31512#L696-2 assume !(0 == ~T1_E~0); 31850#L701-1 assume !(0 == ~T2_E~0); 31853#L706-1 assume !(0 == ~T3_E~0); 31638#L711-1 assume !(0 == ~T4_E~0); 31401#L716-1 assume !(0 == ~T5_E~0); 31402#L721-1 assume !(0 == ~T6_E~0); 31589#L726-1 assume !(0 == ~E_M~0); 31590#L731-1 assume !(0 == ~E_1~0); 31551#L736-1 assume !(0 == ~E_2~0); 31552#L741-1 assume !(0 == ~E_3~0); 31649#L746-1 assume !(0 == ~E_4~0); 31427#L751-1 assume !(0 == ~E_5~0); 31428#L756-1 assume !(0 == ~E_6~0); 31398#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31222#L346 assume !(1 == ~m_pc~0); 31223#L346-2 is_master_triggered_~__retres1~0#1 := 0; 31441#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31433#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31434#L861 assume !(0 != activate_threads_~tmp~1#1); 31812#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31256#L365 assume !(1 == ~t1_pc~0); 31257#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31825#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31207#L869 assume !(0 != activate_threads_~tmp___0~0#1); 31246#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31707#L384 assume !(1 == ~t2_pc~0); 31702#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31703#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31672#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31166#L877 assume !(0 != activate_threads_~tmp___1~0#1); 31167#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31528#L403 assume !(1 == ~t3_pc~0); 31529#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31747#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31141#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31142#L885 assume !(0 != activate_threads_~tmp___2~0#1); 31521#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31522#L422 assume !(1 == ~t4_pc~0); 31668#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31669#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31309#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31310#L893 assume !(0 != activate_threads_~tmp___3~0#1); 31615#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31179#L441 assume !(1 == ~t5_pc~0); 31180#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 31807#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31444#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31445#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31626#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31627#L460 assume 1 == ~t6_pc~0; 31128#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31129#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31187#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31651#L909 assume !(0 != activate_threads_~tmp___5~0#1); 31763#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31599#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 31600#L774-2 assume !(1 == ~T1_E~0); 31780#L779-1 assume !(1 == ~T2_E~0); 31491#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31492#L789-1 assume !(1 == ~T4_E~0); 31241#L794-1 assume !(1 == ~T5_E~0); 31242#L799-1 assume !(1 == ~T6_E~0); 31897#L804-1 assume !(1 == ~E_M~0); 31898#L809-1 assume !(1 == ~E_1~0); 31584#L814-1 assume !(1 == ~E_2~0); 31145#L819-1 assume !(1 == ~E_3~0); 31146#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 31661#L829-1 assume !(1 == ~E_5~0); 31770#L834-1 assume !(1 == ~E_6~0); 31385#L839-1 assume { :end_inline_reset_delta_events } true; 31373#L1065-2 [2024-10-31 22:11:30,519 INFO L747 eck$LassoCheckResult]: Loop: 31373#L1065-2 assume !false; 31374#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31347#L671-1 assume !false; 31742#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31748#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31213#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31227#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31694#L582 assume !(0 != eval_~tmp~0#1); 31938#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38121#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38119#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38117#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38115#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38113#L711-3 assume !(0 == ~T4_E~0); 38111#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38109#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38107#L726-3 assume !(0 == ~E_M~0); 38105#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38103#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38102#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31395#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31396#L751-3 assume !(0 == ~E_5~0); 31526#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31264#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31265#L346-24 assume !(1 == ~m_pc~0); 31298#L346-26 is_master_triggered_~__retres1~0#1 := 0; 31391#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38086#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38084#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38081#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38080#L365-24 assume !(1 == ~t1_pc~0); 38079#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 38078#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38077#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38076#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38075#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38074#L384-24 assume !(1 == ~t2_pc~0); 38072#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 38071#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38070#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38069#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38068#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38067#L403-24 assume !(1 == ~t3_pc~0); 38066#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 38065#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38064#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38063#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38062#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38061#L422-24 assume !(1 == ~t4_pc~0); 38060#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 38059#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31816#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31817#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31789#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31790#L441-24 assume 1 == ~t5_pc~0; 38057#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31608#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31609#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31247#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 31248#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31715#L460-24 assume 1 == ~t6_pc~0; 38054#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38052#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31425#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31426#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38048#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38046#L774-3 assume !(1 == ~M_E~0); 31628#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31447#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31448#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38040#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31147#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31148#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31604#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31605#L809-3 assume !(1 == ~E_1~0); 31254#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31255#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38036#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31393#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31394#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31682#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31792#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31237#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31333#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 31174#L1084 assume !(0 == start_simulation_~tmp~3#1); 31175#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31423#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31150#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31204#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 31205#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31269#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31270#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 31435#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 31373#L1065-2 [2024-10-31 22:11:30,520 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:30,520 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2024-10-31 22:11:30,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:30,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529749768] [2024-10-31 22:11:30,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:30,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:30,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:30,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:30,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:30,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529749768] [2024-10-31 22:11:30,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [529749768] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:30,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:30,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:11:30,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387695084] [2024-10-31 22:11:30,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:30,595 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:30,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:30,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1610208162, now seen corresponding path program 3 times [2024-10-31 22:11:30,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:30,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869979287] [2024-10-31 22:11:30,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:30,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:30,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:30,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:30,643 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:30,643 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869979287] [2024-10-31 22:11:30,643 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869979287] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:30,643 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:30,643 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:30,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1457353092] [2024-10-31 22:11:30,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:30,644 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:30,644 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:30,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:11:30,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:11:30,645 INFO L87 Difference]: Start difference. First operand 7358 states and 10709 transitions. cyclomatic complexity: 3367 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:31,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:31,034 INFO L93 Difference]: Finished difference Result 7673 states and 11024 transitions. [2024-10-31 22:11:31,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7673 states and 11024 transitions. [2024-10-31 22:11:31,081 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7528 [2024-10-31 22:11:31,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7673 states to 7673 states and 11024 transitions. [2024-10-31 22:11:31,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7673 [2024-10-31 22:11:31,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7673 [2024-10-31 22:11:31,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7673 states and 11024 transitions. [2024-10-31 22:11:31,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:31,152 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7673 states and 11024 transitions. [2024-10-31 22:11:31,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7673 states and 11024 transitions. [2024-10-31 22:11:31,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7673 to 7673. [2024-10-31 22:11:31,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7673 states, 7673 states have (on average 1.4367261827186237) internal successors, (11024), 7672 states have internal predecessors, (11024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:31,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7673 states to 7673 states and 11024 transitions. [2024-10-31 22:11:31,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7673 states and 11024 transitions. [2024-10-31 22:11:31,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:11:31,355 INFO L425 stractBuchiCegarLoop]: Abstraction has 7673 states and 11024 transitions. [2024-10-31 22:11:31,356 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:11:31,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7673 states and 11024 transitions. [2024-10-31 22:11:31,388 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7528 [2024-10-31 22:11:31,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:31,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:31,389 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:31,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:31,390 INFO L745 eck$LassoCheckResult]: Stem: 46505#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 46506#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 46689#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46690#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46852#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 46409#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46410#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46242#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46243#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46219#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46220#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46384#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46539#L696 assume !(0 == ~M_E~0); 46540#L696-2 assume !(0 == ~T1_E~0); 46861#L701-1 assume !(0 == ~T2_E~0); 46864#L706-1 assume !(0 == ~T3_E~0); 46662#L711-1 assume !(0 == ~T4_E~0); 46443#L716-1 assume !(0 == ~T5_E~0); 46444#L721-1 assume !(0 == ~T6_E~0); 46616#L726-1 assume !(0 == ~E_M~0); 46617#L731-1 assume !(0 == ~E_1~0); 46578#L736-1 assume !(0 == ~E_2~0); 46579#L741-1 assume !(0 == ~E_3~0); 46673#L746-1 assume !(0 == ~E_4~0); 46465#L751-1 assume !(0 == ~E_5~0); 46466#L756-1 assume !(0 == ~E_6~0); 46440#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46264#L346 assume !(1 == ~m_pc~0); 46265#L346-2 is_master_triggered_~__retres1~0#1 := 0; 46478#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46470#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46471#L861 assume !(0 != activate_threads_~tmp~1#1); 46827#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46299#L365 assume !(1 == ~t1_pc~0); 46300#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46839#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46249#L869 assume !(0 != activate_threads_~tmp___0~0#1); 46289#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46728#L384 assume !(1 == ~t2_pc~0); 46721#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46722#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46692#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46207#L877 assume !(0 != activate_threads_~tmp___1~0#1); 46208#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46555#L403 assume !(1 == ~t3_pc~0); 46556#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46761#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46181#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46182#L885 assume !(0 != activate_threads_~tmp___2~0#1); 46548#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46549#L422 assume !(1 == ~t4_pc~0); 46687#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46688#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46351#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46352#L893 assume !(0 != activate_threads_~tmp___3~0#1); 46640#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46221#L441 assume !(1 == ~t5_pc~0); 46222#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46822#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46944#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46943#L901 assume !(0 != activate_threads_~tmp___4~0#1); 46650#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46651#L460 assume 1 == ~t6_pc~0; 46168#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46169#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46229#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46675#L909 assume !(0 != activate_threads_~tmp___5~0#1); 46776#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46626#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 46627#L774-2 assume !(1 == ~T1_E~0); 46798#L779-1 assume !(1 == ~T2_E~0); 46525#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46526#L789-1 assume !(1 == ~T4_E~0); 46283#L794-1 assume !(1 == ~T5_E~0); 46284#L799-1 assume !(1 == ~T6_E~0); 52290#L804-1 assume !(1 == ~E_M~0); 46906#L809-1 assume !(1 == ~E_1~0); 46927#L814-1 assume !(1 == ~E_2~0); 46185#L819-1 assume !(1 == ~E_3~0); 46186#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 46683#L829-1 assume !(1 == ~E_5~0); 46784#L834-1 assume !(1 == ~E_6~0); 46785#L839-1 assume { :end_inline_reset_delta_events } true; 52168#L1065-2 [2024-10-31 22:11:31,390 INFO L747 eck$LassoCheckResult]: Loop: 52168#L1065-2 assume !false; 52159#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52153#L671-1 assume !false; 52150#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 52114#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 52104#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 52100#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 52092#L582 assume !(0 != eval_~tmp~0#1); 52093#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52872#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52870#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52868#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52866#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52864#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52862#L711-3 assume !(0 == ~T4_E~0); 52860#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52858#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52855#L726-3 assume !(0 == ~E_M~0); 52853#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52851#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52849#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52847#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52843#L751-3 assume !(0 == ~E_5~0); 52841#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52839#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52837#L346-24 assume !(1 == ~m_pc~0); 52833#L346-26 is_master_triggered_~__retres1~0#1 := 0; 52831#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52829#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 52826#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52824#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52822#L365-24 assume !(1 == ~t1_pc~0); 52820#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 52818#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52817#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 52815#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52814#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52716#L384-24 assume !(1 == ~t2_pc~0); 52710#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 52702#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52695#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52688#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52679#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52653#L403-24 assume !(1 == ~t3_pc~0); 52645#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 52622#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52603#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52575#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52572#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52568#L422-24 assume !(1 == ~t4_pc~0); 52553#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 52548#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52544#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52540#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52536#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52534#L441-24 assume !(1 == ~t5_pc~0); 52531#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 52528#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52524#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52521#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 52517#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52514#L460-24 assume 1 == ~t6_pc~0; 52508#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52502#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52496#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52489#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52485#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52467#L774-3 assume !(1 == ~M_E~0); 52465#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52463#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52461#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52459#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52457#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52455#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52453#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52449#L809-3 assume !(1 == ~E_1~0); 52447#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52445#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52443#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52441#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52430#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52428#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 52343#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 52338#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 52329#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 52317#L1084 assume !(0 == start_simulation_~tmp~3#1); 52314#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 52312#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 52285#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 52281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 52191#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52190#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52188#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 52176#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 52168#L1065-2 [2024-10-31 22:11:31,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:31,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2024-10-31 22:11:31,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:31,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175376282] [2024-10-31 22:11:31,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:31,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:31,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:31,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:31,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:31,451 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175376282] [2024-10-31 22:11:31,451 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175376282] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:31,451 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:31,451 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:11:31,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46548119] [2024-10-31 22:11:31,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:31,452 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:31,452 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:31,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1727830751, now seen corresponding path program 1 times [2024-10-31 22:11:31,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:31,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675422840] [2024-10-31 22:11:31,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:31,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:31,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:31,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:31,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:31,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1675422840] [2024-10-31 22:11:31,506 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1675422840] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:31,506 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:31,506 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:31,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787097108] [2024-10-31 22:11:31,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:31,506 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:31,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:31,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:31,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:31,507 INFO L87 Difference]: Start difference. First operand 7673 states and 11024 transitions. cyclomatic complexity: 3367 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:31,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:31,719 INFO L93 Difference]: Finished difference Result 14708 states and 21001 transitions. [2024-10-31 22:11:31,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14708 states and 21001 transitions. [2024-10-31 22:11:31,787 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14492 [2024-10-31 22:11:31,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14708 states to 14708 states and 21001 transitions. [2024-10-31 22:11:31,831 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14708 [2024-10-31 22:11:31,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14708 [2024-10-31 22:11:31,842 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14708 states and 21001 transitions. [2024-10-31 22:11:31,859 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:31,860 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14708 states and 21001 transitions. [2024-10-31 22:11:31,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14708 states and 21001 transitions. [2024-10-31 22:11:32,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14708 to 14676. [2024-10-31 22:11:32,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14676 states, 14676 states have (on average 1.4287953120741346) internal successors, (20969), 14675 states have internal predecessors, (20969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:32,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14676 states to 14676 states and 20969 transitions. [2024-10-31 22:11:32,294 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14676 states and 20969 transitions. [2024-10-31 22:11:32,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:32,298 INFO L425 stractBuchiCegarLoop]: Abstraction has 14676 states and 20969 transitions. [2024-10-31 22:11:32,298 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:11:32,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14676 states and 20969 transitions. [2024-10-31 22:11:32,352 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14460 [2024-10-31 22:11:32,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:32,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:32,354 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:32,354 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:32,354 INFO L745 eck$LassoCheckResult]: Stem: 68904#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 68905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 69097#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69098#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69278#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 68801#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68802#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68632#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68633#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68606#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68607#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68775#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68944#L696 assume !(0 == ~M_E~0); 68945#L696-2 assume !(0 == ~T1_E~0); 69283#L701-1 assume !(0 == ~T2_E~0); 69285#L706-1 assume !(0 == ~T3_E~0); 69068#L711-1 assume !(0 == ~T4_E~0); 68837#L716-1 assume !(0 == ~T5_E~0); 68838#L721-1 assume !(0 == ~T6_E~0); 69014#L726-1 assume !(0 == ~E_M~0); 69015#L731-1 assume !(0 == ~E_1~0); 68982#L736-1 assume !(0 == ~E_2~0); 68983#L741-1 assume !(0 == ~E_3~0); 69078#L746-1 assume !(0 == ~E_4~0); 68860#L751-1 assume !(0 == ~E_5~0); 68861#L756-1 assume !(0 == ~E_6~0); 68834#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68651#L346 assume !(1 == ~m_pc~0); 68652#L346-2 is_master_triggered_~__retres1~0#1 := 0; 68874#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68866#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68867#L861 assume !(0 != activate_threads_~tmp~1#1); 69253#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68688#L365 assume !(1 == ~t1_pc~0); 68689#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69268#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68636#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68637#L869 assume !(0 != activate_threads_~tmp___0~0#1); 68676#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69141#L384 assume !(1 == ~t2_pc~0); 69136#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69137#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69099#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68594#L877 assume !(0 != activate_threads_~tmp___1~0#1); 68595#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68960#L403 assume !(1 == ~t3_pc~0); 68961#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69182#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68568#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68569#L885 assume !(0 != activate_threads_~tmp___2~0#1); 68956#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68957#L422 assume !(1 == ~t4_pc~0); 69095#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 69096#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68740#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68741#L893 assume !(0 != activate_threads_~tmp___3~0#1); 69043#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68608#L441 assume !(1 == ~t5_pc~0); 68609#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69248#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68877#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 68878#L901 assume !(0 != activate_threads_~tmp___4~0#1); 69055#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69056#L460 assume !(1 == ~t6_pc~0); 69202#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 68615#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68616#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69080#L909 assume !(0 != activate_threads_~tmp___5~0#1); 69199#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69026#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 69027#L774-2 assume !(1 == ~T1_E~0); 69219#L779-1 assume !(1 == ~T2_E~0); 69220#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73846#L789-1 assume !(1 == ~T4_E~0); 73844#L794-1 assume !(1 == ~T5_E~0); 73842#L799-1 assume !(1 == ~T6_E~0); 73840#L804-1 assume !(1 == ~E_M~0); 69332#L809-1 assume !(1 == ~E_1~0); 73837#L814-1 assume !(1 == ~E_2~0); 73835#L819-1 assume !(1 == ~E_3~0); 69088#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69089#L829-1 assume !(1 == ~E_5~0); 69207#L834-1 assume !(1 == ~E_6~0); 69208#L839-1 assume { :end_inline_reset_delta_events } true; 73743#L1065-2 [2024-10-31 22:11:32,355 INFO L747 eck$LassoCheckResult]: Loop: 73743#L1065-2 assume !false; 73729#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73720#L671-1 assume !false; 73715#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 73635#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 73625#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 73620#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 73612#L582 assume !(0 != eval_~tmp~0#1); 73613#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 74303#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74302#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 74299#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 74297#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 74295#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74293#L711-3 assume !(0 == ~T4_E~0); 74291#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 74289#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 74287#L726-3 assume !(0 == ~E_M~0); 74285#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 74283#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 74281#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 74279#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 74277#L751-3 assume !(0 == ~E_5~0); 74274#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74272#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74270#L346-24 assume !(1 == ~m_pc~0); 74267#L346-26 is_master_triggered_~__retres1~0#1 := 0; 74265#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74263#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 74261#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 74259#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74257#L365-24 assume !(1 == ~t1_pc~0); 74255#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 74253#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74251#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 74249#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74247#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74245#L384-24 assume !(1 == ~t2_pc~0); 74241#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 74238#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74236#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 74234#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 74232#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74230#L403-24 assume !(1 == ~t3_pc~0); 74228#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 74226#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74224#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 74222#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74220#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74218#L422-24 assume !(1 == ~t4_pc~0); 74216#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 74213#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74211#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74209#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74207#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74205#L441-24 assume !(1 == ~t5_pc~0); 74183#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 74202#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74180#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 74159#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 74153#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74145#L460-24 assume !(1 == ~t6_pc~0); 74137#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 74131#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74125#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 74119#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 74113#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74107#L774-3 assume !(1 == ~M_E~0); 74096#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 74092#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 74085#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74078#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74072#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 74061#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 74055#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 74051#L809-3 assume !(1 == ~E_1~0); 74049#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 74047#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 74045#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 74040#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 74036#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 74032#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 73915#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 73902#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 73893#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 73884#L1084 assume !(0 == start_simulation_~tmp~3#1); 73878#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 73760#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 73753#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 73751#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 73749#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 73748#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73747#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 73746#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 73743#L1065-2 [2024-10-31 22:11:32,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:32,355 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2024-10-31 22:11:32,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:32,356 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152010135] [2024-10-31 22:11:32,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:32,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:32,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:32,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:32,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:32,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152010135] [2024-10-31 22:11:32,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152010135] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:32,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:32,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:11:32,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795153506] [2024-10-31 22:11:32,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:32,425 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:32,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:32,426 INFO L85 PathProgramCache]: Analyzing trace with hash 151272992, now seen corresponding path program 1 times [2024-10-31 22:11:32,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:32,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635703058] [2024-10-31 22:11:32,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:32,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:32,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:32,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:32,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:32,476 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635703058] [2024-10-31 22:11:32,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635703058] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:32,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:32,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:32,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339956372] [2024-10-31 22:11:32,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:32,477 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:32,477 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:32,477 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:32,477 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:32,478 INFO L87 Difference]: Start difference. First operand 14676 states and 20969 transitions. cyclomatic complexity: 6325 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:32,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:32,690 INFO L93 Difference]: Finished difference Result 21861 states and 31258 transitions. [2024-10-31 22:11:32,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21861 states and 31258 transitions. [2024-10-31 22:11:32,785 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21596 [2024-10-31 22:11:32,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21861 states to 21861 states and 31258 transitions. [2024-10-31 22:11:32,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21861 [2024-10-31 22:11:32,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21861 [2024-10-31 22:11:32,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21861 states and 31258 transitions. [2024-10-31 22:11:33,058 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:33,059 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21861 states and 31258 transitions. [2024-10-31 22:11:33,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21861 states and 31258 transitions. [2024-10-31 22:11:33,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21861 to 15306. [2024-10-31 22:11:33,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15306 states, 15306 states have (on average 1.4321834574676597) internal successors, (21921), 15305 states have internal predecessors, (21921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:33,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15306 states to 15306 states and 21921 transitions. [2024-10-31 22:11:33,654 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15306 states and 21921 transitions. [2024-10-31 22:11:33,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:33,656 INFO L425 stractBuchiCegarLoop]: Abstraction has 15306 states and 21921 transitions. [2024-10-31 22:11:33,656 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:11:33,656 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15306 states and 21921 transitions. [2024-10-31 22:11:33,726 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15104 [2024-10-31 22:11:33,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:33,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:33,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:33,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:33,729 INFO L745 eck$LassoCheckResult]: Stem: 105447#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 105448#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 105630#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105631#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105794#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 105343#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105344#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105176#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105177#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105149#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105150#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 105320#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105480#L696 assume !(0 == ~M_E~0); 105481#L696-2 assume !(0 == ~T1_E~0); 105801#L701-1 assume !(0 == ~T2_E~0); 105803#L706-1 assume !(0 == ~T3_E~0); 105605#L711-1 assume !(0 == ~T4_E~0); 105378#L716-1 assume !(0 == ~T5_E~0); 105379#L721-1 assume !(0 == ~T6_E~0); 105551#L726-1 assume !(0 == ~E_M~0); 105552#L731-1 assume !(0 == ~E_1~0); 105518#L736-1 assume !(0 == ~E_2~0); 105519#L741-1 assume !(0 == ~E_3~0); 105615#L746-1 assume !(0 == ~E_4~0); 105401#L751-1 assume !(0 == ~E_5~0); 105402#L756-1 assume !(0 == ~E_6~0); 105375#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105196#L346 assume !(1 == ~m_pc~0); 105197#L346-2 is_master_triggered_~__retres1~0#1 := 0; 105417#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105407#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105408#L861 assume !(0 != activate_threads_~tmp~1#1); 105770#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105230#L365 assume !(1 == ~t1_pc~0); 105231#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105783#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105182#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105183#L869 assume !(0 != activate_threads_~tmp___0~0#1); 105219#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105669#L384 assume !(1 == ~t2_pc~0); 105666#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105667#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105637#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105139#L877 assume !(0 != activate_threads_~tmp___1~0#1); 105140#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105496#L403 assume !(1 == ~t3_pc~0); 105497#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105703#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105111#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 105112#L885 assume !(0 != activate_threads_~tmp___2~0#1); 105490#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105491#L422 assume !(1 == ~t4_pc~0); 105628#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105629#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105281#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 105282#L893 assume !(0 != activate_threads_~tmp___3~0#1); 105582#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105151#L441 assume !(1 == ~t5_pc~0); 105152#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 105766#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105420#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 105421#L901 assume !(0 != activate_threads_~tmp___4~0#1); 105594#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105595#L460 assume !(1 == ~t6_pc~0); 105724#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 105160#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105161#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 105617#L909 assume !(0 != activate_threads_~tmp___5~0#1); 105719#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105566#L774 assume !(1 == ~M_E~0); 105567#L774-2 assume !(1 == ~T1_E~0); 105740#L779-1 assume !(1 == ~T2_E~0); 105464#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 105465#L789-1 assume !(1 == ~T4_E~0); 105213#L794-1 assume !(1 == ~T5_E~0); 105214#L799-1 assume !(1 == ~T6_E~0); 105837#L804-1 assume !(1 == ~E_M~0); 105838#L809-1 assume !(1 == ~E_1~0); 105547#L814-1 assume !(1 == ~E_2~0); 105117#L819-1 assume !(1 == ~E_3~0); 105118#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 105623#L829-1 assume !(1 == ~E_5~0); 105727#L834-1 assume !(1 == ~E_6~0); 105364#L839-1 assume { :end_inline_reset_delta_events } true; 105365#L1065-2 [2024-10-31 22:11:33,729 INFO L747 eck$LassoCheckResult]: Loop: 105365#L1065-2 assume !false; 114859#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 114850#L671-1 assume !false; 114848#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 114843#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 114836#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 114834#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 114832#L582 assume !(0 != eval_~tmp~0#1); 105296#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105297#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 105392#L696-3 assume !(0 == ~M_E~0); 105393#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 105443#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 105444#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 105809#L711-3 assume !(0 == ~T4_E~0); 105800#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 105618#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 105423#L726-3 assume !(0 == ~E_M~0); 105424#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 105609#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 105610#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 105372#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 105373#L751-3 assume !(0 == ~E_5~0); 120285#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 120235#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 120234#L346-24 assume 1 == ~m_pc~0; 120233#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 120231#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 120230#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 120229#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 120228#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 120227#L365-24 assume !(1 == ~t1_pc~0); 120226#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 120225#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120224#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 120223#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 120222#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 120221#L384-24 assume !(1 == ~t2_pc~0); 120219#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 120218#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116870#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 116866#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116862#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116834#L403-24 assume !(1 == ~t3_pc~0); 116830#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 116827#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116817#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 116814#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 116812#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116811#L422-24 assume !(1 == ~t4_pc~0); 116810#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 116808#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116806#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 116805#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 116804#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116802#L441-24 assume !(1 == ~t5_pc~0); 116801#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 116809#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116807#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 116792#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 116790#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116788#L460-24 assume !(1 == ~t6_pc~0); 116786#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 116784#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116782#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116780#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 116778#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116776#L774-3 assume !(1 == ~M_E~0); 110168#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116772#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116770#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116768#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116766#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116764#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 116762#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116761#L809-3 assume !(1 == ~E_1~0); 116760#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116734#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116728#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116724#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116720#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 116716#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 116692#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 116684#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 116098#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 110300#L1084 assume !(0 == start_simulation_~tmp~3#1); 110301#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 118986#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 118974#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 118972#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 118970#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 118968#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 118965#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 118963#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 105365#L1065-2 [2024-10-31 22:11:33,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:33,730 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2024-10-31 22:11:33,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:33,731 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688787407] [2024-10-31 22:11:33,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:33,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:33,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:33,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:33,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:33,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688787407] [2024-10-31 22:11:33,920 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688787407] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:33,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:33,921 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:33,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871818147] [2024-10-31 22:11:33,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:33,922 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:33,922 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:33,924 INFO L85 PathProgramCache]: Analyzing trace with hash 1429480477, now seen corresponding path program 1 times [2024-10-31 22:11:33,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:33,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463726406] [2024-10-31 22:11:33,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:33,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:33,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:33,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:33,973 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:33,973 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463726406] [2024-10-31 22:11:33,973 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1463726406] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:33,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:33,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:33,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444982368] [2024-10-31 22:11:33,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:33,975 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:33,975 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:33,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:11:33,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:11:33,976 INFO L87 Difference]: Start difference. First operand 15306 states and 21921 transitions. cyclomatic complexity: 6631 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:34,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:34,167 INFO L93 Difference]: Finished difference Result 24428 states and 34861 transitions. [2024-10-31 22:11:34,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24428 states and 34861 transitions. [2024-10-31 22:11:34,273 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24096 [2024-10-31 22:11:34,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24428 states to 24428 states and 34861 transitions. [2024-10-31 22:11:34,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24428 [2024-10-31 22:11:34,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24428 [2024-10-31 22:11:34,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24428 states and 34861 transitions. [2024-10-31 22:11:34,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:34,525 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24428 states and 34861 transitions. [2024-10-31 22:11:34,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24428 states and 34861 transitions. [2024-10-31 22:11:34,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24428 to 17449. [2024-10-31 22:11:34,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17449 states, 17449 states have (on average 1.4309129463006476) internal successors, (24968), 17448 states have internal predecessors, (24968), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:34,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17449 states to 17449 states and 24968 transitions. [2024-10-31 22:11:34,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17449 states and 24968 transitions. [2024-10-31 22:11:34,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:11:34,914 INFO L425 stractBuchiCegarLoop]: Abstraction has 17449 states and 24968 transitions. [2024-10-31 22:11:34,914 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:11:34,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17449 states and 24968 transitions. [2024-10-31 22:11:34,963 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17184 [2024-10-31 22:11:34,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:34,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:34,965 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:34,965 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:34,965 INFO L745 eck$LassoCheckResult]: Stem: 145187#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 145188#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 145368#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 145369#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 145539#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 145083#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145084#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144921#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144922#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144894#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144895#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 145061#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 145220#L696 assume !(0 == ~M_E~0); 145221#L696-2 assume !(0 == ~T1_E~0); 145554#L701-1 assume !(0 == ~T2_E~0); 145556#L706-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 145578#L711-1 assume !(0 == ~T4_E~0); 145684#L716-1 assume !(0 == ~T5_E~0); 145595#L721-1 assume !(0 == ~T6_E~0); 145596#L726-1 assume !(0 == ~E_M~0); 145683#L731-1 assume !(0 == ~E_1~0); 145682#L736-1 assume !(0 == ~E_2~0); 145350#L741-1 assume !(0 == ~E_3~0); 145351#L746-1 assume !(0 == ~E_4~0); 145142#L751-1 assume !(0 == ~E_5~0); 145143#L756-1 assume !(0 == ~E_6~0); 145235#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 145680#L346 assume !(1 == ~m_pc~0); 145678#L346-2 is_master_triggered_~__retres1~0#1 := 0; 145677#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 145676#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 145570#L861 assume !(0 != activate_threads_~tmp~1#1); 145510#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145511#L365 assume !(1 == ~t1_pc~0); 145674#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 145673#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144927#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144928#L869 assume !(0 != activate_threads_~tmp___0~0#1); 144963#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145407#L384 assume !(1 == ~t2_pc~0); 145404#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 145405#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145375#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144884#L877 assume !(0 != activate_threads_~tmp___1~0#1); 144885#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 145236#L403 assume !(1 == ~t3_pc~0); 145237#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 145443#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144855#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 144856#L885 assume !(0 != activate_threads_~tmp___2~0#1); 145230#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145231#L422 assume !(1 == ~t4_pc~0); 145366#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 145367#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 145024#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 145025#L893 assume !(0 != activate_threads_~tmp___3~0#1); 145491#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 145656#L441 assume !(1 == ~t5_pc~0); 145560#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 145655#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 145653#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 145650#L901 assume !(0 != activate_threads_~tmp___4~0#1); 145327#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 145328#L460 assume !(1 == ~t6_pc~0); 145464#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 145647#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 145646#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 145645#L909 assume !(0 != activate_threads_~tmp___5~0#1); 145565#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145566#L774 assume !(1 == ~M_E~0); 145644#L774-2 assume !(1 == ~T1_E~0); 145643#L779-1 assume !(1 == ~T2_E~0); 145642#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 145205#L789-1 assume !(1 == ~T4_E~0); 144958#L794-1 assume !(1 == ~T5_E~0); 144959#L799-1 assume !(1 == ~T6_E~0); 145604#L804-1 assume !(1 == ~E_M~0); 145605#L809-1 assume !(1 == ~E_1~0); 145288#L814-1 assume !(1 == ~E_2~0); 144861#L819-1 assume !(1 == ~E_3~0); 144862#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 145363#L829-1 assume !(1 == ~E_5~0); 145468#L834-1 assume !(1 == ~E_6~0); 145103#L839-1 assume { :end_inline_reset_delta_events } true; 145104#L1065-2 [2024-10-31 22:11:34,966 INFO L747 eck$LassoCheckResult]: Loop: 145104#L1065-2 assume !false; 155476#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 155473#L671-1 assume !false; 155471#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 155466#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 155459#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 155457#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 155455#L582 assume !(0 != eval_~tmp~0#1); 155452#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 155451#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 155448#L696-3 assume !(0 == ~M_E~0); 155444#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 155440#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 155435#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 155434#L711-3 assume !(0 == ~T4_E~0); 155433#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 155432#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 155431#L726-3 assume !(0 == ~E_M~0); 155430#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 155429#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 155428#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 155427#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 155426#L751-3 assume !(0 == ~E_5~0); 155425#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 155424#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155423#L346-24 assume 1 == ~m_pc~0; 155422#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 155420#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155419#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 155418#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155417#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155416#L365-24 assume !(1 == ~t1_pc~0); 155415#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 155414#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155413#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 155412#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 155411#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155410#L384-24 assume !(1 == ~t2_pc~0); 155408#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 155407#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155406#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 155405#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 155404#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155403#L403-24 assume !(1 == ~t3_pc~0); 155402#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 155401#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155400#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 155399#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 155398#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 155397#L422-24 assume !(1 == ~t4_pc~0); 155396#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 155395#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155394#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 155393#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 155392#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 155391#L441-24 assume !(1 == ~t5_pc~0); 155390#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 156210#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 156209#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 155385#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 155384#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 155383#L460-24 assume !(1 == ~t6_pc~0); 155382#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 155381#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 155380#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 155379#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 155378#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155377#L774-3 assume !(1 == ~M_E~0); 153914#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 155376#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 155374#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 155372#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 155370#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 155368#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 155366#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 155364#L809-3 assume !(1 == ~E_1~0); 155362#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 155361#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 155357#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 155355#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 155353#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 155352#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 154138#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 154133#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 153703#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 151904#L1084 assume !(0 == start_simulation_~tmp~3#1); 151905#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 155727#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 155719#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 155717#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 155715#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 155713#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 155711#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 155709#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 145104#L1065-2 [2024-10-31 22:11:34,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:34,966 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2024-10-31 22:11:34,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:34,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136247921] [2024-10-31 22:11:34,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:34,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:34,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:35,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:35,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:35,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136247921] [2024-10-31 22:11:35,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136247921] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:35,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:35,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:35,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638091443] [2024-10-31 22:11:35,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:35,029 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:35,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:35,029 INFO L85 PathProgramCache]: Analyzing trace with hash 1429480477, now seen corresponding path program 2 times [2024-10-31 22:11:35,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:35,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239401401] [2024-10-31 22:11:35,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:35,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:35,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:35,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:35,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:35,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239401401] [2024-10-31 22:11:35,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239401401] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:35,074 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:35,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:35,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473554932] [2024-10-31 22:11:35,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:35,075 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:35,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:35,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:11:35,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:11:35,076 INFO L87 Difference]: Start difference. First operand 17449 states and 24968 transitions. cyclomatic complexity: 7535 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:35,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:35,251 INFO L93 Difference]: Finished difference Result 22274 states and 31679 transitions. [2024-10-31 22:11:35,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22274 states and 31679 transitions. [2024-10-31 22:11:35,447 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22016 [2024-10-31 22:11:35,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22274 states to 22274 states and 31679 transitions. [2024-10-31 22:11:35,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22274 [2024-10-31 22:11:35,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22274 [2024-10-31 22:11:35,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22274 states and 31679 transitions. [2024-10-31 22:11:35,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:35,569 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22274 states and 31679 transitions. [2024-10-31 22:11:35,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22274 states and 31679 transitions. [2024-10-31 22:11:35,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22274 to 15306. [2024-10-31 22:11:35,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15306 states, 15306 states have (on average 1.42578073957925) internal successors, (21823), 15305 states have internal predecessors, (21823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:35,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15306 states to 15306 states and 21823 transitions. [2024-10-31 22:11:35,977 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15306 states and 21823 transitions. [2024-10-31 22:11:35,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:11:35,978 INFO L425 stractBuchiCegarLoop]: Abstraction has 15306 states and 21823 transitions. [2024-10-31 22:11:35,978 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 22:11:35,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15306 states and 21823 transitions. [2024-10-31 22:11:36,024 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15104 [2024-10-31 22:11:36,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:36,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:36,027 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:36,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:36,027 INFO L745 eck$LassoCheckResult]: Stem: 184925#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 184926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 185107#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 185108#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 185285#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 184817#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 184818#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 184650#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 184651#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 184624#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 184625#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 184794#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 184961#L696 assume !(0 == ~M_E~0); 184962#L696-2 assume !(0 == ~T1_E~0); 185294#L701-1 assume !(0 == ~T2_E~0); 185296#L706-1 assume !(0 == ~T3_E~0); 185079#L711-1 assume !(0 == ~T4_E~0); 184853#L716-1 assume !(0 == ~T5_E~0); 184854#L721-1 assume !(0 == ~T6_E~0); 185031#L726-1 assume !(0 == ~E_M~0); 185032#L731-1 assume !(0 == ~E_1~0); 184997#L736-1 assume !(0 == ~E_2~0); 184998#L741-1 assume !(0 == ~E_3~0); 185088#L746-1 assume !(0 == ~E_4~0); 184879#L751-1 assume !(0 == ~E_5~0); 184880#L756-1 assume !(0 == ~E_6~0); 184850#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 184670#L346 assume !(1 == ~m_pc~0); 184671#L346-2 is_master_triggered_~__retres1~0#1 := 0; 184894#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 184884#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 184885#L861 assume !(0 != activate_threads_~tmp~1#1); 185254#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 184704#L365 assume !(1 == ~t1_pc~0); 184705#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 185270#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 184656#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 184657#L869 assume !(0 != activate_threads_~tmp___0~0#1); 184693#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 185146#L384 assume !(1 == ~t2_pc~0); 185143#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 185144#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 185113#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 184615#L877 assume !(0 != activate_threads_~tmp___1~0#1); 184616#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 184976#L403 assume !(1 == ~t3_pc~0); 184977#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 185186#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 184587#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 184588#L885 assume !(0 != activate_threads_~tmp___2~0#1); 184971#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 184972#L422 assume !(1 == ~t4_pc~0); 185105#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 185106#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 184756#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 184757#L893 assume !(0 != activate_threads_~tmp___3~0#1); 185056#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 184626#L441 assume !(1 == ~t5_pc~0); 184627#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 185250#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 184896#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 184897#L901 assume !(0 != activate_threads_~tmp___4~0#1); 185068#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 185069#L460 assume !(1 == ~t6_pc~0); 185209#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 184635#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 184636#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 185091#L909 assume !(0 != activate_threads_~tmp___5~0#1); 185204#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185042#L774 assume !(1 == ~M_E~0); 185043#L774-2 assume !(1 == ~T1_E~0); 185225#L779-1 assume !(1 == ~T2_E~0); 184942#L784-1 assume !(1 == ~T3_E~0); 184943#L789-1 assume !(1 == ~T4_E~0); 184688#L794-1 assume !(1 == ~T5_E~0); 184689#L799-1 assume !(1 == ~T6_E~0); 185335#L804-1 assume !(1 == ~E_M~0); 185336#L809-1 assume !(1 == ~E_1~0); 185027#L814-1 assume !(1 == ~E_2~0); 184593#L819-1 assume !(1 == ~E_3~0); 184594#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 185098#L829-1 assume !(1 == ~E_5~0); 185214#L834-1 assume !(1 == ~E_6~0); 184838#L839-1 assume { :end_inline_reset_delta_events } true; 184839#L1065-2 [2024-10-31 22:11:36,028 INFO L747 eck$LassoCheckResult]: Loop: 184839#L1065-2 assume !false; 195401#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 195398#L671-1 assume !false; 195396#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 195391#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 195385#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 195382#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 195380#L582 assume !(0 != eval_~tmp~0#1); 195381#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 199692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199690#L696-3 assume !(0 == ~M_E~0); 199688#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 199686#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 199684#L706-3 assume !(0 == ~T3_E~0); 199682#L711-3 assume !(0 == ~T4_E~0); 199680#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 199678#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 199676#L726-3 assume !(0 == ~E_M~0); 199674#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 199672#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 199670#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 199668#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 199666#L751-3 assume !(0 == ~E_5~0); 199664#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 199662#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199659#L346-24 assume 1 == ~m_pc~0; 199657#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 199654#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199652#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 199650#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 199648#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 199645#L365-24 assume !(1 == ~t1_pc~0); 199643#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 199641#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199639#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 199637#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 199635#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199632#L384-24 assume 1 == ~t2_pc~0; 199630#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 199627#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199625#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 199623#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 199621#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 199619#L403-24 assume !(1 == ~t3_pc~0); 199617#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 199615#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 199613#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 199611#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 199609#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 199606#L422-24 assume !(1 == ~t4_pc~0); 199604#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 199602#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 199600#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 199598#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 199596#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199593#L441-24 assume !(1 == ~t5_pc~0); 199591#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 199698#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 199696#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 199582#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 199580#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 199578#L460-24 assume !(1 == ~t6_pc~0); 199576#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 199574#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199572#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 199570#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 199568#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199567#L774-3 assume !(1 == ~M_E~0); 188520#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 199566#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 199565#L784-3 assume !(1 == ~T3_E~0); 199564#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 199563#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 199562#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 199561#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 199560#L809-3 assume !(1 == ~E_1~0); 199382#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 199380#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 199156#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 199157#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 199372#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 199142#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 198997#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 198808#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 198807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 188671#L1084 assume !(0 == start_simulation_~tmp~3#1); 188672#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 195531#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 195524#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 195523#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 195521#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 195520#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 195519#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 195518#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 184839#L1065-2 [2024-10-31 22:11:36,028 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:36,029 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2024-10-31 22:11:36,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:36,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087831287] [2024-10-31 22:11:36,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:36,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:36,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:36,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:36,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:36,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2087831287] [2024-10-31 22:11:36,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2087831287] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:36,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:36,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:36,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321275206] [2024-10-31 22:11:36,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:36,104 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:36,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:36,105 INFO L85 PathProgramCache]: Analyzing trace with hash -2638436, now seen corresponding path program 1 times [2024-10-31 22:11:36,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:36,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335366164] [2024-10-31 22:11:36,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:36,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:36,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:36,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:36,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:36,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335366164] [2024-10-31 22:11:36,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335366164] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:36,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:36,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:36,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552880851] [2024-10-31 22:11:36,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:36,163 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:36,163 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:36,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:11:36,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:11:36,164 INFO L87 Difference]: Start difference. First operand 15306 states and 21823 transitions. cyclomatic complexity: 6533 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:36,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:36,479 INFO L93 Difference]: Finished difference Result 24188 states and 34235 transitions. [2024-10-31 22:11:36,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24188 states and 34235 transitions. [2024-10-31 22:11:36,697 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23856 [2024-10-31 22:11:36,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24188 states to 24188 states and 34235 transitions. [2024-10-31 22:11:36,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24188 [2024-10-31 22:11:36,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24188 [2024-10-31 22:11:36,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24188 states and 34235 transitions. [2024-10-31 22:11:36,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:36,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24188 states and 34235 transitions. [2024-10-31 22:11:36,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24188 states and 34235 transitions. [2024-10-31 22:11:37,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24188 to 17449. [2024-10-31 22:11:37,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17449 states, 17449 states have (on average 1.41933635165339) internal successors, (24766), 17448 states have internal predecessors, (24766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:37,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17449 states to 17449 states and 24766 transitions. [2024-10-31 22:11:37,233 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17449 states and 24766 transitions. [2024-10-31 22:11:37,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:11:37,233 INFO L425 stractBuchiCegarLoop]: Abstraction has 17449 states and 24766 transitions. [2024-10-31 22:11:37,234 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-31 22:11:37,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17449 states and 24766 transitions. [2024-10-31 22:11:37,285 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17184 [2024-10-31 22:11:37,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:37,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:37,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:37,288 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:37,288 INFO L745 eck$LassoCheckResult]: Stem: 224427#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 224428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 224601#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 224602#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 224770#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 224324#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 224325#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224153#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224154#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 224130#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 224131#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 224299#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 224460#L696 assume !(0 == ~M_E~0); 224461#L696-2 assume !(0 == ~T1_E~0); 224776#L701-1 assume !(0 == ~T2_E~0); 224778#L706-1 assume !(0 == ~T3_E~0); 224576#L711-1 assume !(0 == ~T4_E~0); 224361#L716-1 assume !(0 == ~T5_E~0); 224362#L721-1 assume !(0 == ~T6_E~0); 224531#L726-1 assume !(0 == ~E_M~0); 224532#L731-1 assume !(0 == ~E_1~0); 224500#L736-1 assume !(0 == ~E_2~0); 224501#L741-1 assume !(0 == ~E_3~0); 224585#L746-1 assume 0 == ~E_4~0;~E_4~0 := 1; 224828#L751-1 assume !(0 == ~E_5~0); 224885#L756-1 assume !(0 == ~E_6~0); 224357#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 224358#L346 assume !(1 == ~m_pc~0); 224399#L346-2 is_master_triggered_~__retres1~0#1 := 0; 224400#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 224690#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 224790#L861 assume !(0 != activate_threads_~tmp~1#1); 224742#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 224743#L365 assume !(1 == ~t1_pc~0); 224882#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 224881#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 224159#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 224160#L869 assume !(0 != activate_threads_~tmp___0~0#1); 224200#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 224879#L384 assume !(1 == ~t2_pc~0); 224632#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 224633#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 224603#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 224604#L877 assume !(0 != activate_threads_~tmp___1~0#1); 224878#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224877#L403 assume !(1 == ~t3_pc~0); 224876#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 224851#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224092#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 224093#L885 assume !(0 != activate_threads_~tmp___2~0#1); 224469#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 224470#L422 assume !(1 == ~t4_pc~0); 224771#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 224871#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 224870#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 224869#L893 assume !(0 != activate_threads_~tmp___3~0#1); 224554#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224132#L441 assume !(1 == ~t5_pc~0); 224133#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 224823#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 224403#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 224404#L901 assume !(0 != activate_threads_~tmp___4~0#1); 224854#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 224861#L460 assume !(1 == ~t6_pc~0); 224773#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 224139#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 224140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 224859#L909 assume !(0 != activate_threads_~tmp___5~0#1); 224787#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 224788#L774 assume !(1 == ~M_E~0); 224813#L774-2 assume !(1 == ~T1_E~0); 224709#L779-1 assume !(1 == ~T2_E~0); 224446#L784-1 assume !(1 == ~T3_E~0); 224447#L789-1 assume !(1 == ~T4_E~0); 224856#L794-1 assume !(1 == ~T5_E~0); 224846#L799-1 assume !(1 == ~T6_E~0); 224847#L804-1 assume !(1 == ~E_M~0); 224842#L809-1 assume !(1 == ~E_1~0); 224843#L814-1 assume !(1 == ~E_2~0); 224096#L819-1 assume !(1 == ~E_3~0); 224097#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 224595#L829-1 assume !(1 == ~E_5~0); 224699#L834-1 assume !(1 == ~E_6~0); 224342#L839-1 assume { :end_inline_reset_delta_events } true; 224343#L1065-2 [2024-10-31 22:11:37,288 INFO L747 eck$LassoCheckResult]: Loop: 224343#L1065-2 assume !false; 232693#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 231749#L671-1 assume !false; 232688#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 232672#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 232661#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 232658#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 230624#L582 assume !(0 != eval_~tmp~0#1); 230625#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 232888#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 232885#L696-3 assume !(0 == ~M_E~0); 232882#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 232879#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 232877#L706-3 assume !(0 == ~T3_E~0); 232874#L711-3 assume !(0 == ~T4_E~0); 232871#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 232868#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 232865#L726-3 assume !(0 == ~E_M~0); 232863#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 232860#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 232857#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 232853#L746-3 assume !(0 == ~E_4~0); 232854#L751-3 assume !(0 == ~E_5~0); 233117#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 233114#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233110#L346-24 assume 1 == ~m_pc~0; 233106#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 233102#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233099#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 233096#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 233093#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233090#L365-24 assume !(1 == ~t1_pc~0); 233086#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 233083#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233080#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 233077#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 233074#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 233069#L384-24 assume 1 == ~t2_pc~0; 233066#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 233059#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 233027#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 233024#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 233022#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233020#L403-24 assume !(1 == ~t3_pc~0); 233018#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 233016#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 233014#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 233012#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 233010#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 233008#L422-24 assume !(1 == ~t4_pc~0); 233006#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 233004#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 233002#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 232999#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 232997#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 232995#L441-24 assume 1 == ~t5_pc~0; 232993#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 232994#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 233054#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 232984#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 232981#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 232979#L460-24 assume !(1 == ~t6_pc~0); 232977#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 232975#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232973#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 232971#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 232969#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232967#L774-3 assume !(1 == ~M_E~0); 228244#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 232962#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 232960#L784-3 assume !(1 == ~T3_E~0); 232958#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 232956#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 232952#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 232950#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 232948#L809-3 assume !(1 == ~E_1~0); 232946#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 232892#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 232790#L824-3 assume !(1 == ~E_4~0); 232786#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 232783#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 232780#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 232706#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 232700#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 232697#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 225090#L1084 assume !(0 == start_simulation_~tmp~3#1); 225091#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 232909#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 232900#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 232898#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 232896#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 232893#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 232702#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 232699#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 224343#L1065-2 [2024-10-31 22:11:37,289 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:37,289 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2024-10-31 22:11:37,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:37,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139312237] [2024-10-31 22:11:37,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:37,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:37,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:37,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:37,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:37,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139312237] [2024-10-31 22:11:37,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139312237] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:37,357 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:37,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:37,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180607749] [2024-10-31 22:11:37,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:37,358 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:37,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:37,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1977820965, now seen corresponding path program 1 times [2024-10-31 22:11:37,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:37,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71358133] [2024-10-31 22:11:37,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:37,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:37,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:37,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:37,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:37,409 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [71358133] [2024-10-31 22:11:37,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [71358133] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:37,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:37,410 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:37,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642267553] [2024-10-31 22:11:37,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:37,410 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:37,411 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:37,411 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:11:37,411 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:11:37,411 INFO L87 Difference]: Start difference. First operand 17449 states and 24766 transitions. cyclomatic complexity: 7333 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:37,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:37,619 INFO L93 Difference]: Finished difference Result 21862 states and 30841 transitions. [2024-10-31 22:11:37,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21862 states and 30841 transitions. [2024-10-31 22:11:37,928 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21596 [2024-10-31 22:11:38,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21862 states to 21862 states and 30841 transitions. [2024-10-31 22:11:38,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21862 [2024-10-31 22:11:38,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21862 [2024-10-31 22:11:38,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21862 states and 30841 transitions. [2024-10-31 22:11:38,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:38,039 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21862 states and 30841 transitions. [2024-10-31 22:11:38,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21862 states and 30841 transitions. [2024-10-31 22:11:38,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21862 to 15306. [2024-10-31 22:11:38,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15306 states, 15306 states have (on average 1.4125833006664053) internal successors, (21621), 15305 states have internal predecessors, (21621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:38,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15306 states to 15306 states and 21621 transitions. [2024-10-31 22:11:38,331 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15306 states and 21621 transitions. [2024-10-31 22:11:38,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:11:38,332 INFO L425 stractBuchiCegarLoop]: Abstraction has 15306 states and 21621 transitions. [2024-10-31 22:11:38,332 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-31 22:11:38,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15306 states and 21621 transitions. [2024-10-31 22:11:38,394 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15104 [2024-10-31 22:11:38,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:38,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:38,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:38,396 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:38,397 INFO L745 eck$LassoCheckResult]: Stem: 263746#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 263747#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 263922#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 263923#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264088#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 263647#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 263648#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 263475#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 263476#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 263450#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 263451#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 263621#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 263779#L696 assume !(0 == ~M_E~0); 263780#L696-2 assume !(0 == ~T1_E~0); 264095#L701-1 assume !(0 == ~T2_E~0); 264099#L706-1 assume !(0 == ~T3_E~0); 263894#L711-1 assume !(0 == ~T4_E~0); 263682#L716-1 assume !(0 == ~T5_E~0); 263683#L721-1 assume !(0 == ~T6_E~0); 263848#L726-1 assume !(0 == ~E_M~0); 263849#L731-1 assume !(0 == ~E_1~0); 263816#L736-1 assume !(0 == ~E_2~0); 263817#L741-1 assume !(0 == ~E_3~0); 263904#L746-1 assume !(0 == ~E_4~0); 263704#L751-1 assume !(0 == ~E_5~0); 263705#L756-1 assume !(0 == ~E_6~0); 263679#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 263495#L346 assume !(1 == ~m_pc~0); 263496#L346-2 is_master_triggered_~__retres1~0#1 := 0; 263717#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 263709#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 263710#L861 assume !(0 != activate_threads_~tmp~1#1); 264064#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 263532#L365 assume !(1 == ~t1_pc~0); 263533#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 264077#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 263481#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 263482#L869 assume !(0 != activate_threads_~tmp___0~0#1); 263520#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 263960#L384 assume !(1 == ~t2_pc~0); 263957#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 263958#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 263925#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263438#L877 assume !(0 != activate_threads_~tmp___1~0#1); 263439#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 263795#L403 assume !(1 == ~t3_pc~0); 263796#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 263996#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263412#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 263413#L885 assume !(0 != activate_threads_~tmp___2~0#1); 263791#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 263792#L422 assume !(1 == ~t4_pc~0); 263920#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 263921#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263584#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 263585#L893 assume !(0 != activate_threads_~tmp___3~0#1); 263873#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 263452#L441 assume !(1 == ~t5_pc~0); 263453#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 264060#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 263720#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 263721#L901 assume !(0 != activate_threads_~tmp___4~0#1); 263883#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 263884#L460 assume !(1 == ~t6_pc~0); 264014#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 263459#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 263460#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 263906#L909 assume !(0 != activate_threads_~tmp___5~0#1); 264011#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 263858#L774 assume !(1 == ~M_E~0); 263859#L774-2 assume !(1 == ~T1_E~0); 264032#L779-1 assume !(1 == ~T2_E~0); 263765#L784-1 assume !(1 == ~T3_E~0); 263766#L789-1 assume !(1 == ~T4_E~0); 263514#L794-1 assume !(1 == ~T5_E~0); 263515#L799-1 assume !(1 == ~T6_E~0); 264143#L804-1 assume !(1 == ~E_M~0); 264144#L809-1 assume !(1 == ~E_1~0); 263843#L814-1 assume !(1 == ~E_2~0); 263418#L819-1 assume !(1 == ~E_3~0); 263419#L824-1 assume !(1 == ~E_4~0); 263914#L829-1 assume !(1 == ~E_5~0); 264020#L834-1 assume !(1 == ~E_6~0); 263667#L839-1 assume { :end_inline_reset_delta_events } true; 263668#L1065-2 [2024-10-31 22:11:38,397 INFO L747 eck$LassoCheckResult]: Loop: 263668#L1065-2 assume !false; 272489#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 272484#L671-1 assume !false; 272481#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 272477#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 272468#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 272465#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 272461#L582 assume !(0 != eval_~tmp~0#1); 272458#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 272455#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 272452#L696-3 assume !(0 == ~M_E~0); 272449#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 272445#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 272442#L706-3 assume !(0 == ~T3_E~0); 272438#L711-3 assume !(0 == ~T4_E~0); 272434#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 272431#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 272427#L726-3 assume !(0 == ~E_M~0); 272424#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 272421#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 272220#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 272219#L746-3 assume !(0 == ~E_4~0); 272218#L751-3 assume !(0 == ~E_5~0); 272217#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 272216#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272215#L346-24 assume !(1 == ~m_pc~0); 272212#L346-26 is_master_triggered_~__retres1~0#1 := 0; 272211#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272210#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 272209#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 272208#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 272207#L365-24 assume !(1 == ~t1_pc~0); 272206#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 272205#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272203#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 272201#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 272199#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272197#L384-24 assume !(1 == ~t2_pc~0); 272194#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 272192#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272190#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 272188#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 272186#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 272184#L403-24 assume !(1 == ~t3_pc~0); 272182#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 272180#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272178#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 272176#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 272174#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272172#L422-24 assume !(1 == ~t4_pc~0); 272170#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 272167#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 272165#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 272163#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 272161#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272159#L441-24 assume 1 == ~t5_pc~0; 272157#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 272158#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272214#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 271820#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 271815#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 271812#L460-24 assume !(1 == ~t6_pc~0); 271808#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 271805#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 271801#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 271797#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 271738#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 271723#L774-3 assume !(1 == ~M_E~0); 271719#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 271715#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 271711#L784-3 assume !(1 == ~T3_E~0); 271707#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 271704#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 271701#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 271698#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 271696#L809-3 assume !(1 == ~E_1~0); 271694#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 271693#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 271692#L824-3 assume !(1 == ~E_4~0); 271691#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 271690#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 271689#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 271684#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 271680#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 271679#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 271654#L1084 assume !(0 == start_simulation_~tmp~3#1); 271655#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 272552#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 272544#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 272543#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 272525#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 272517#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 272509#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 272501#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 263668#L1065-2 [2024-10-31 22:11:38,543 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:38,543 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2024-10-31 22:11:38,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:38,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180151307] [2024-10-31 22:11:38,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:38,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:38,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:38,559 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:11:38,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:38,622 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:11:38,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:38,624 INFO L85 PathProgramCache]: Analyzing trace with hash -599924771, now seen corresponding path program 1 times [2024-10-31 22:11:38,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:38,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459723462] [2024-10-31 22:11:38,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:38,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:38,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:38,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:38,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:38,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459723462] [2024-10-31 22:11:38,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1459723462] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:38,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:38,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:38,679 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797550775] [2024-10-31 22:11:38,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:38,679 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:38,680 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:38,680 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:38,680 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:38,680 INFO L87 Difference]: Start difference. First operand 15306 states and 21621 transitions. cyclomatic complexity: 6331 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:38,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:38,870 INFO L93 Difference]: Finished difference Result 22965 states and 32247 transitions. [2024-10-31 22:11:38,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22965 states and 32247 transitions. [2024-10-31 22:11:38,963 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22660 [2024-10-31 22:11:39,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22965 states to 22965 states and 32247 transitions. [2024-10-31 22:11:39,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22965 [2024-10-31 22:11:39,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22965 [2024-10-31 22:11:39,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22965 states and 32247 transitions. [2024-10-31 22:11:39,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:39,067 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22965 states and 32247 transitions. [2024-10-31 22:11:39,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22965 states and 32247 transitions. [2024-10-31 22:11:39,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22965 to 22805. [2024-10-31 22:11:39,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22805 states, 22805 states have (on average 1.4028064021048017) internal successors, (31991), 22804 states have internal predecessors, (31991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:39,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22805 states to 22805 states and 31991 transitions. [2024-10-31 22:11:39,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22805 states and 31991 transitions. [2024-10-31 22:11:39,561 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:39,562 INFO L425 stractBuchiCegarLoop]: Abstraction has 22805 states and 31991 transitions. [2024-10-31 22:11:39,562 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-31 22:11:39,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22805 states and 31991 transitions. [2024-10-31 22:11:39,629 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22500 [2024-10-31 22:11:39,630 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:39,630 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:39,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:39,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:39,632 INFO L745 eck$LassoCheckResult]: Stem: 302018#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 302019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 302201#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 302202#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 302385#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 301914#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 301915#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 301749#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 301750#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 301725#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 301726#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 301893#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 302052#L696 assume !(0 == ~M_E~0); 302053#L696-2 assume !(0 == ~T1_E~0); 302396#L701-1 assume !(0 == ~T2_E~0); 302398#L706-1 assume !(0 == ~T3_E~0); 302173#L711-1 assume !(0 == ~T4_E~0); 301948#L716-1 assume !(0 == ~T5_E~0); 301949#L721-1 assume !(0 == ~T6_E~0); 302126#L726-1 assume !(0 == ~E_M~0); 302127#L731-1 assume 0 == ~E_1~0;~E_1~0 := 1; 302090#L736-1 assume !(0 == ~E_2~0); 302091#L741-1 assume !(0 == ~E_3~0); 302461#L746-1 assume !(0 == ~E_4~0); 302462#L751-1 assume !(0 == ~E_5~0); 302530#L756-1 assume !(0 == ~E_6~0); 301944#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 301945#L346 assume !(1 == ~m_pc~0); 301989#L346-2 is_master_triggered_~__retres1~0#1 := 0; 301990#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 302310#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 302412#L861 assume !(0 != activate_threads_~tmp~1#1); 302357#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 302358#L365 assume !(1 == ~t1_pc~0); 302527#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 302526#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 301757#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 301758#L869 assume !(0 != activate_threads_~tmp___0~0#1); 301793#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 302524#L384 assume !(1 == ~t2_pc~0); 302243#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 302244#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 302206#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 302207#L877 assume !(0 != activate_threads_~tmp___1~0#1); 302523#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 302522#L403 assume !(1 == ~t3_pc~0); 302521#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 302484#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 302485#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 302520#L885 assume !(0 != activate_threads_~tmp___2~0#1); 302519#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 302388#L422 assume !(1 == ~t4_pc~0); 302389#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 302518#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 302517#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 302516#L893 assume !(0 != activate_threads_~tmp___3~0#1); 302150#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 301727#L441 assume !(1 == ~t5_pc~0); 301728#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 302354#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 301992#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 301993#L901 assume !(0 != activate_threads_~tmp___4~0#1); 302492#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 302505#L460 assume !(1 == ~t6_pc~0); 302504#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 302503#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 302186#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 302187#L909 assume !(0 != activate_threads_~tmp___5~0#1); 302311#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 302136#L774 assume !(1 == ~M_E~0); 302137#L774-2 assume !(1 == ~T1_E~0); 302329#L779-1 assume !(1 == ~T2_E~0); 302036#L784-1 assume !(1 == ~T3_E~0); 302037#L789-1 assume !(1 == ~T4_E~0); 301788#L794-1 assume !(1 == ~T5_E~0); 301789#L799-1 assume !(1 == ~T6_E~0); 302446#L804-1 assume !(1 == ~E_M~0); 302447#L809-1 assume 1 == ~E_1~0;~E_1~0 := 2; 302122#L814-1 assume !(1 == ~E_2~0); 301695#L819-1 assume !(1 == ~E_3~0); 301696#L824-1 assume !(1 == ~E_4~0); 302194#L829-1 assume !(1 == ~E_5~0); 302319#L834-1 assume !(1 == ~E_6~0); 301933#L839-1 assume { :end_inline_reset_delta_events } true; 301934#L1065-2 [2024-10-31 22:11:39,632 INFO L747 eck$LassoCheckResult]: Loop: 301934#L1065-2 assume !false; 308134#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 308129#L671-1 assume !false; 308124#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 308117#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 308108#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 308104#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 308099#L582 assume !(0 != eval_~tmp~0#1); 308094#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 308090#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 308086#L696-3 assume !(0 == ~M_E~0); 308081#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 308076#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 308072#L706-3 assume !(0 == ~T3_E~0); 308068#L711-3 assume !(0 == ~T4_E~0); 308064#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 308060#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 308055#L726-3 assume !(0 == ~E_M~0); 308050#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 308051#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 308082#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 308077#L746-3 assume !(0 == ~E_4~0); 308073#L751-3 assume !(0 == ~E_5~0); 308069#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 308065#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 308061#L346-24 assume !(1 == ~m_pc~0); 308056#L346-26 is_master_triggered_~__retres1~0#1 := 0; 308052#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 308041#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 308037#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 308032#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 308027#L365-24 assume !(1 == ~t1_pc~0); 308022#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 308000#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 307996#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 307992#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 307988#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 307983#L384-24 assume !(1 == ~t2_pc~0); 307978#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 307976#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 307971#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 307960#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 307957#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307954#L403-24 assume !(1 == ~t3_pc~0); 307950#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 307947#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 307944#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 307941#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 307938#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 307934#L422-24 assume !(1 == ~t4_pc~0); 307929#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 307926#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 307923#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 307919#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 307915#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 307912#L441-24 assume !(1 == ~t5_pc~0); 307908#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 307922#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 307918#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 307892#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 307887#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 307883#L460-24 assume !(1 == ~t6_pc~0); 307879#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 307875#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 307871#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 307868#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 307865#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307862#L774-3 assume !(1 == ~M_E~0); 307628#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 307858#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 307855#L784-3 assume !(1 == ~T3_E~0); 307852#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 307848#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 307844#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 307840#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 307835#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 307829#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 307825#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 307821#L824-3 assume !(1 == ~E_4~0); 307818#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 307815#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 307811#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 307799#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 307792#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 307788#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 307783#L1084 assume !(0 == start_simulation_~tmp~3#1); 307784#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 308192#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 308184#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 308182#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 308178#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 308176#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 308174#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 308160#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 301934#L1065-2 [2024-10-31 22:11:39,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:39,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1678656137, now seen corresponding path program 1 times [2024-10-31 22:11:39,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:39,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782093265] [2024-10-31 22:11:39,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:39,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:39,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:39,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:39,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:39,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782093265] [2024-10-31 22:11:39,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782093265] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:39,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:39,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:39,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070774273] [2024-10-31 22:11:39,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:39,705 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:11:39,706 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:39,706 INFO L85 PathProgramCache]: Analyzing trace with hash 132090588, now seen corresponding path program 1 times [2024-10-31 22:11:39,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:39,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626749725] [2024-10-31 22:11:39,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:39,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:39,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:39,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:39,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:39,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [626749725] [2024-10-31 22:11:39,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [626749725] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:39,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:39,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:11:39,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450814813] [2024-10-31 22:11:39,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:39,913 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:39,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:39,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:11:39,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:11:39,914 INFO L87 Difference]: Start difference. First operand 22805 states and 31991 transitions. cyclomatic complexity: 9202 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:40,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:40,195 INFO L93 Difference]: Finished difference Result 30824 states and 43184 transitions. [2024-10-31 22:11:40,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30824 states and 43184 transitions. [2024-10-31 22:11:40,318 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 29728 [2024-10-31 22:11:40,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30824 states to 30824 states and 43184 transitions. [2024-10-31 22:11:40,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30824 [2024-10-31 22:11:40,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30824 [2024-10-31 22:11:40,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30824 states and 43184 transitions. [2024-10-31 22:11:40,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:40,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30824 states and 43184 transitions. [2024-10-31 22:11:40,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30824 states and 43184 transitions. [2024-10-31 22:11:41,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30824 to 21710. [2024-10-31 22:11:41,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21710 states, 21710 states have (on average 1.4013818516812528) internal successors, (30424), 21709 states have internal predecessors, (30424), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:41,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21710 states to 21710 states and 30424 transitions. [2024-10-31 22:11:41,118 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21710 states and 30424 transitions. [2024-10-31 22:11:41,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:11:41,119 INFO L425 stractBuchiCegarLoop]: Abstraction has 21710 states and 30424 transitions. [2024-10-31 22:11:41,120 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-31 22:11:41,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21710 states and 30424 transitions. [2024-10-31 22:11:41,203 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21468 [2024-10-31 22:11:41,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:41,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:41,205 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:41,205 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:41,205 INFO L745 eck$LassoCheckResult]: Stem: 355660#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 355661#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 355836#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 355837#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 356002#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 355558#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 355559#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 355395#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 355396#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 355369#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 355370#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 355536#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 355694#L696 assume !(0 == ~M_E~0); 355695#L696-2 assume !(0 == ~T1_E~0); 356008#L701-1 assume !(0 == ~T2_E~0); 356010#L706-1 assume !(0 == ~T3_E~0); 355811#L711-1 assume !(0 == ~T4_E~0); 355594#L716-1 assume !(0 == ~T5_E~0); 355595#L721-1 assume !(0 == ~T6_E~0); 355765#L726-1 assume !(0 == ~E_M~0); 355766#L731-1 assume !(0 == ~E_1~0); 355730#L736-1 assume !(0 == ~E_2~0); 355731#L741-1 assume !(0 == ~E_3~0); 355820#L746-1 assume !(0 == ~E_4~0); 355617#L751-1 assume !(0 == ~E_5~0); 355618#L756-1 assume !(0 == ~E_6~0); 355591#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 355415#L346 assume !(1 == ~m_pc~0); 355416#L346-2 is_master_triggered_~__retres1~0#1 := 0; 355633#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 355623#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 355624#L861 assume !(0 != activate_threads_~tmp~1#1); 355979#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 355449#L365 assume !(1 == ~t1_pc~0); 355450#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 355992#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 355401#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 355402#L869 assume !(0 != activate_threads_~tmp___0~0#1); 355438#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 355876#L384 assume !(1 == ~t2_pc~0); 355871#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 355872#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 355842#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 355359#L877 assume !(0 != activate_threads_~tmp___1~0#1); 355360#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 355709#L403 assume !(1 == ~t3_pc~0); 355710#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 355912#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 355331#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 355332#L885 assume !(0 != activate_threads_~tmp___2~0#1); 355704#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 355705#L422 assume !(1 == ~t4_pc~0); 355834#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 355835#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 355500#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 355501#L893 assume !(0 != activate_threads_~tmp___3~0#1); 355789#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 355371#L441 assume !(1 == ~t5_pc~0); 355372#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 355975#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 355635#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 355636#L901 assume !(0 != activate_threads_~tmp___4~0#1); 355799#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 355800#L460 assume !(1 == ~t6_pc~0); 355935#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 355380#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 355381#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 355822#L909 assume !(0 != activate_threads_~tmp___5~0#1); 355930#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 355776#L774 assume !(1 == ~M_E~0); 355777#L774-2 assume !(1 == ~T1_E~0); 355948#L779-1 assume !(1 == ~T2_E~0); 355678#L784-1 assume !(1 == ~T3_E~0); 355679#L789-1 assume !(1 == ~T4_E~0); 355432#L794-1 assume !(1 == ~T5_E~0); 355433#L799-1 assume !(1 == ~T6_E~0); 356046#L804-1 assume !(1 == ~E_M~0); 356047#L809-1 assume !(1 == ~E_1~0); 355761#L814-1 assume !(1 == ~E_2~0); 355337#L819-1 assume !(1 == ~E_3~0); 355338#L824-1 assume !(1 == ~E_4~0); 355829#L829-1 assume !(1 == ~E_5~0); 355938#L834-1 assume !(1 == ~E_6~0); 355579#L839-1 assume { :end_inline_reset_delta_events } true; 355580#L1065-2 [2024-10-31 22:11:41,206 INFO L747 eck$LassoCheckResult]: Loop: 355580#L1065-2 assume !false; 362433#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 362431#L671-1 assume !false; 362430#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 361866#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 361859#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 361857#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 361854#L582 assume !(0 != eval_~tmp~0#1); 361852#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 361850#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 361848#L696-3 assume !(0 == ~M_E~0); 361846#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 361842#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 361840#L706-3 assume !(0 == ~T3_E~0); 361838#L711-3 assume !(0 == ~T4_E~0); 361836#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 361835#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 361832#L726-3 assume !(0 == ~E_M~0); 361830#L731-3 assume !(0 == ~E_1~0); 361828#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 361826#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 361824#L746-3 assume !(0 == ~E_4~0); 361822#L751-3 assume !(0 == ~E_5~0); 361820#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 361818#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 361816#L346-24 assume 1 == ~m_pc~0; 361815#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 361812#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 361810#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 361808#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 361806#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 361804#L365-24 assume !(1 == ~t1_pc~0); 361802#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 361799#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 361797#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 361795#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 361793#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 361791#L384-24 assume 1 == ~t2_pc~0; 361787#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 361784#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 361780#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 361778#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 361776#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 361774#L403-24 assume !(1 == ~t3_pc~0); 361772#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 361770#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 361768#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 361765#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 361763#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 361761#L422-24 assume !(1 == ~t4_pc~0); 361759#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 361757#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 361755#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 361754#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 361751#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 361749#L441-24 assume !(1 == ~t5_pc~0); 361747#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 362092#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 362090#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 361739#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 361737#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 361735#L460-24 assume !(1 == ~t6_pc~0); 361733#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 361731#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 361729#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 361727#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 361724#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 361722#L774-3 assume !(1 == ~M_E~0); 360811#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 361718#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 361716#L784-3 assume !(1 == ~T3_E~0); 361714#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 361713#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 361676#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 361663#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 361661#L809-3 assume !(1 == ~E_1~0); 361658#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 361657#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 361649#L824-3 assume !(1 == ~E_4~0); 361646#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 361644#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 361642#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 361589#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 361585#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 361564#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 359121#L1084 assume !(0 == start_simulation_~tmp~3#1); 359122#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 362466#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 362457#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 362453#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 362449#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 362445#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 362444#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 362442#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 355580#L1065-2 [2024-10-31 22:11:41,207 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:41,207 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2024-10-31 22:11:41,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:41,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226956569] [2024-10-31 22:11:41,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:41,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:41,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:41,225 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:11:41,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:41,266 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:11:41,266 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:41,267 INFO L85 PathProgramCache]: Analyzing trace with hash -717118950, now seen corresponding path program 1 times [2024-10-31 22:11:41,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:41,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753234616] [2024-10-31 22:11:41,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:41,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:41,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:41,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:41,355 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:41,355 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753234616] [2024-10-31 22:11:41,355 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753234616] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:41,355 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:41,355 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:11:41,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497880931] [2024-10-31 22:11:41,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:41,356 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:41,356 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:41,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:11:41,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:11:41,358 INFO L87 Difference]: Start difference. First operand 21710 states and 30424 transitions. cyclomatic complexity: 8730 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:41,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:41,597 INFO L93 Difference]: Finished difference Result 21982 states and 30696 transitions. [2024-10-31 22:11:41,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21982 states and 30696 transitions. [2024-10-31 22:11:41,712 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21740 [2024-10-31 22:11:41,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21982 states to 21982 states and 30696 transitions. [2024-10-31 22:11:41,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21982 [2024-10-31 22:11:41,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21982 [2024-10-31 22:11:41,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21982 states and 30696 transitions. [2024-10-31 22:11:41,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:41,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21982 states and 30696 transitions. [2024-10-31 22:11:41,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21982 states and 30696 transitions. [2024-10-31 22:11:42,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21982 to 21854. [2024-10-31 22:11:42,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21854 states, 21854 states have (on average 1.3987370733046582) internal successors, (30568), 21853 states have internal predecessors, (30568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:42,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21854 states to 21854 states and 30568 transitions. [2024-10-31 22:11:42,452 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21854 states and 30568 transitions. [2024-10-31 22:11:42,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:11:42,453 INFO L425 stractBuchiCegarLoop]: Abstraction has 21854 states and 30568 transitions. [2024-10-31 22:11:42,453 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-31 22:11:42,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21854 states and 30568 transitions. [2024-10-31 22:11:42,516 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21612 [2024-10-31 22:11:42,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:42,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:42,518 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:42,518 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:42,518 INFO L745 eck$LassoCheckResult]: Stem: 399360#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 399361#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 399536#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 399537#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 399707#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 399259#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 399260#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 399092#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 399093#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 399067#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 399068#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 399238#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 399395#L696 assume !(0 == ~M_E~0); 399396#L696-2 assume !(0 == ~T1_E~0); 399716#L701-1 assume !(0 == ~T2_E~0); 399718#L706-1 assume !(0 == ~T3_E~0); 399512#L711-1 assume !(0 == ~T4_E~0); 399293#L716-1 assume !(0 == ~T5_E~0); 399294#L721-1 assume !(0 == ~T6_E~0); 399465#L726-1 assume !(0 == ~E_M~0); 399466#L731-1 assume !(0 == ~E_1~0); 399432#L736-1 assume !(0 == ~E_2~0); 399433#L741-1 assume !(0 == ~E_3~0); 399522#L746-1 assume !(0 == ~E_4~0); 399317#L751-1 assume !(0 == ~E_5~0); 399318#L756-1 assume !(0 == ~E_6~0); 399290#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 399114#L346 assume !(1 == ~m_pc~0); 399115#L346-2 is_master_triggered_~__retres1~0#1 := 0; 399332#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 399322#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 399323#L861 assume !(0 != activate_threads_~tmp~1#1); 399679#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399148#L365 assume !(1 == ~t1_pc~0); 399149#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 399695#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 399100#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 399101#L869 assume !(0 != activate_threads_~tmp___0~0#1); 399137#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 399580#L384 assume !(1 == ~t2_pc~0); 399577#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 399578#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 399542#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 399058#L877 assume !(0 != activate_threads_~tmp___1~0#1); 399059#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 399411#L403 assume !(1 == ~t3_pc~0); 399412#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 399615#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 399030#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 399031#L885 assume !(0 != activate_threads_~tmp___2~0#1); 399405#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 399406#L422 assume !(1 == ~t4_pc~0); 399534#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 399535#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 399201#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 399202#L893 assume !(0 != activate_threads_~tmp___3~0#1); 399489#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 399069#L441 assume !(1 == ~t5_pc~0); 399070#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 399675#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 399334#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 399335#L901 assume !(0 != activate_threads_~tmp___4~0#1); 399500#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 399501#L460 assume !(1 == ~t6_pc~0); 399634#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 399076#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 399077#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 399524#L909 assume !(0 != activate_threads_~tmp___5~0#1); 399629#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 399475#L774 assume !(1 == ~M_E~0); 399476#L774-2 assume !(1 == ~T1_E~0); 399648#L779-1 assume !(1 == ~T2_E~0); 399377#L784-1 assume !(1 == ~T3_E~0); 399378#L789-1 assume !(1 == ~T4_E~0); 399132#L794-1 assume !(1 == ~T5_E~0); 399133#L799-1 assume !(1 == ~T6_E~0); 399757#L804-1 assume !(1 == ~E_M~0); 399758#L809-1 assume !(1 == ~E_1~0); 399461#L814-1 assume !(1 == ~E_2~0); 399036#L819-1 assume !(1 == ~E_3~0); 399037#L824-1 assume !(1 == ~E_4~0); 399531#L829-1 assume !(1 == ~E_5~0); 399637#L834-1 assume !(1 == ~E_6~0); 399279#L839-1 assume { :end_inline_reset_delta_events } true; 399280#L1065-2 [2024-10-31 22:11:42,519 INFO L747 eck$LassoCheckResult]: Loop: 399280#L1065-2 assume !false; 408971#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 408969#L671-1 assume !false; 408968#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 408678#L530 assume !(0 == ~m_st~0); 408679#L534 assume !(0 == ~t1_st~0); 408674#L538 assume !(0 == ~t2_st~0); 408675#L542 assume !(0 == ~t3_st~0); 408677#L546 assume !(0 == ~t4_st~0); 408672#L550 assume !(0 == ~t5_st~0); 408673#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 408676#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 418846#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 418844#L582 assume !(0 != eval_~tmp~0#1); 418842#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 418840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 418838#L696-3 assume !(0 == ~M_E~0); 418835#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 418833#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 418831#L706-3 assume !(0 == ~T3_E~0); 418829#L711-3 assume !(0 == ~T4_E~0); 418827#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 418825#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 418823#L726-3 assume !(0 == ~E_M~0); 418821#L731-3 assume !(0 == ~E_1~0); 418819#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 418817#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 418815#L746-3 assume !(0 == ~E_4~0); 418813#L751-3 assume !(0 == ~E_5~0); 418811#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 418809#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 418807#L346-24 assume !(1 == ~m_pc~0); 418804#L346-26 is_master_triggered_~__retres1~0#1 := 0; 418802#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 418800#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 418797#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 418795#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 418793#L365-24 assume !(1 == ~t1_pc~0); 418790#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 418788#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 418786#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 418783#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 418781#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 418779#L384-24 assume !(1 == ~t2_pc~0); 418776#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 418774#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 418770#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 418768#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 418766#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 418764#L403-24 assume !(1 == ~t3_pc~0); 418762#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 418760#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 418758#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 418756#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 418753#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 418751#L422-24 assume !(1 == ~t4_pc~0); 418749#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 418747#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 418745#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 418743#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 418741#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 418740#L441-24 assume 1 == ~t5_pc~0; 418738#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 418737#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 418736#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 418728#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 418725#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 418723#L460-24 assume !(1 == ~t6_pc~0); 418720#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 418718#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 418710#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 418708#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 418706#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 418704#L774-3 assume !(1 == ~M_E~0); 417147#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 418701#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 418699#L784-3 assume !(1 == ~T3_E~0); 418697#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 418695#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 418694#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 418692#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 418691#L809-3 assume !(1 == ~E_1~0); 418690#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 418681#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 418679#L824-3 assume !(1 == ~E_4~0); 418677#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 418676#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 418675#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 418671#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 418667#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 413921#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 413918#L1084 assume !(0 == start_simulation_~tmp~3#1); 413916#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 413915#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 413901#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 410486#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 410484#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 410482#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 410412#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 408980#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 399280#L1065-2 [2024-10-31 22:11:42,519 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:42,519 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2024-10-31 22:11:42,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:42,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384384970] [2024-10-31 22:11:42,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:42,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:42,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:42,535 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:11:42,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:42,576 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:11:42,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:42,576 INFO L85 PathProgramCache]: Analyzing trace with hash -650385366, now seen corresponding path program 1 times [2024-10-31 22:11:42,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:42,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808212751] [2024-10-31 22:11:42,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:42,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:42,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:42,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:42,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:42,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808212751] [2024-10-31 22:11:42,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808212751] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:42,654 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:42,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:11:42,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764579759] [2024-10-31 22:11:42,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:42,655 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:42,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:42,656 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:11:42,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:11:42,656 INFO L87 Difference]: Start difference. First operand 21854 states and 30568 transitions. cyclomatic complexity: 8730 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:43,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:43,011 INFO L93 Difference]: Finished difference Result 21854 states and 30263 transitions. [2024-10-31 22:11:43,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21854 states and 30263 transitions. [2024-10-31 22:11:43,099 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21612 [2024-10-31 22:11:43,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21854 states to 21854 states and 30263 transitions. [2024-10-31 22:11:43,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21854 [2024-10-31 22:11:43,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21854 [2024-10-31 22:11:43,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21854 states and 30263 transitions. [2024-10-31 22:11:43,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:43,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21854 states and 30263 transitions. [2024-10-31 22:11:43,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21854 states and 30263 transitions. [2024-10-31 22:11:43,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21854 to 21854. [2024-10-31 22:11:43,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21854 states, 21854 states have (on average 1.384780818156859) internal successors, (30263), 21853 states have internal predecessors, (30263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:43,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21854 states to 21854 states and 30263 transitions. [2024-10-31 22:11:43,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21854 states and 30263 transitions. [2024-10-31 22:11:43,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:11:43,438 INFO L425 stractBuchiCegarLoop]: Abstraction has 21854 states and 30263 transitions. [2024-10-31 22:11:43,438 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-31 22:11:43,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21854 states and 30263 transitions. [2024-10-31 22:11:43,505 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21612 [2024-10-31 22:11:43,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:43,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:43,508 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:43,508 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:43,509 INFO L745 eck$LassoCheckResult]: Stem: 443076#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 443077#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 443261#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 443262#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 443452#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 442972#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 442973#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 442809#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 442810#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 442783#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 442784#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 442951#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 443113#L696 assume !(0 == ~M_E~0); 443114#L696-2 assume !(0 == ~T1_E~0); 443461#L701-1 assume !(0 == ~T2_E~0); 443463#L706-1 assume !(0 == ~T3_E~0); 443235#L711-1 assume !(0 == ~T4_E~0); 443006#L716-1 assume !(0 == ~T5_E~0); 443007#L721-1 assume !(0 == ~T6_E~0); 443185#L726-1 assume !(0 == ~E_M~0); 443186#L731-1 assume !(0 == ~E_1~0); 443151#L736-1 assume !(0 == ~E_2~0); 443152#L741-1 assume !(0 == ~E_3~0); 443245#L746-1 assume !(0 == ~E_4~0); 443030#L751-1 assume !(0 == ~E_5~0); 443031#L756-1 assume !(0 == ~E_6~0); 443003#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 442829#L346 assume !(1 == ~m_pc~0); 442830#L346-2 is_master_triggered_~__retres1~0#1 := 0; 443048#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 443037#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 443038#L861 assume !(0 != activate_threads_~tmp~1#1); 443427#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 442864#L365 assume !(1 == ~t1_pc~0); 442865#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 443441#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 442815#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 442816#L869 assume !(0 != activate_threads_~tmp___0~0#1); 442853#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 443308#L384 assume !(1 == ~t2_pc~0); 443303#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 443304#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 443266#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 442774#L877 assume !(0 != activate_threads_~tmp___1~0#1); 442775#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 443131#L403 assume !(1 == ~t3_pc~0); 443132#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 443353#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 442746#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 442747#L885 assume !(0 != activate_threads_~tmp___2~0#1); 443123#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 443124#L422 assume !(1 == ~t4_pc~0); 443259#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 443260#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 442915#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 442916#L893 assume !(0 != activate_threads_~tmp___3~0#1); 443210#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 442785#L441 assume !(1 == ~t5_pc~0); 442786#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 443424#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 443516#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 443552#L901 assume !(0 != activate_threads_~tmp___4~0#1); 443222#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 443223#L460 assume !(1 == ~t6_pc~0); 443378#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 442794#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 442795#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 443247#L909 assume !(0 != activate_threads_~tmp___5~0#1); 443373#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 443196#L774 assume !(1 == ~M_E~0); 443197#L774-2 assume !(1 == ~T1_E~0); 443394#L779-1 assume !(1 == ~T2_E~0); 443094#L784-1 assume !(1 == ~T3_E~0); 443095#L789-1 assume !(1 == ~T4_E~0); 442847#L794-1 assume !(1 == ~T5_E~0); 442848#L799-1 assume !(1 == ~T6_E~0); 443508#L804-1 assume !(1 == ~E_M~0); 443509#L809-1 assume !(1 == ~E_1~0); 443181#L814-1 assume !(1 == ~E_2~0); 442752#L819-1 assume !(1 == ~E_3~0); 442753#L824-1 assume !(1 == ~E_4~0); 443254#L829-1 assume !(1 == ~E_5~0); 443382#L834-1 assume !(1 == ~E_6~0); 442992#L839-1 assume { :end_inline_reset_delta_events } true; 442993#L1065-2 [2024-10-31 22:11:43,509 INFO L747 eck$LassoCheckResult]: Loop: 442993#L1065-2 assume !false; 463577#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 461197#L671-1 assume !false; 463576#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 443354#L530 assume !(0 == ~m_st~0); 443355#L534 assume !(0 == ~t1_st~0); 442995#L538 assume !(0 == ~t2_st~0); 442996#L542 assume !(0 == ~t3_st~0); 442817#L546 assume !(0 == ~t4_st~0); 442819#L550 assume !(0 == ~t5_st~0); 443274#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 442832#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 442833#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 464496#L582 assume !(0 != eval_~tmp~0#1); 464493#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 464491#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 464489#L696-3 assume !(0 == ~M_E~0); 464487#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 464485#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 464483#L706-3 assume !(0 == ~T3_E~0); 464481#L711-3 assume !(0 == ~T4_E~0); 464478#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 464475#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 464472#L726-3 assume !(0 == ~E_M~0); 464469#L731-3 assume !(0 == ~E_1~0); 464466#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 464463#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 464462#L746-3 assume !(0 == ~E_4~0); 464461#L751-3 assume !(0 == ~E_5~0); 464460#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 464459#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 464458#L346-24 assume 1 == ~m_pc~0; 464457#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 464455#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 464454#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 464453#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 464451#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 464446#L365-24 assume !(1 == ~t1_pc~0); 464444#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 464442#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 464441#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 464438#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 464434#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 464432#L384-24 assume 1 == ~t2_pc~0; 464431#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 464428#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 464426#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 464424#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 442920#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 442921#L403-24 assume !(1 == ~t3_pc~0); 443033#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 464422#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 443306#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 443307#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 464283#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 463779#L422-24 assume !(1 == ~t4_pc~0); 463778#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 463777#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 463755#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 463754#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 463753#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 463752#L441-24 assume !(1 == ~t5_pc~0); 463751#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 463749#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 463747#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 463744#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 463743#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 463742#L460-24 assume !(1 == ~t6_pc~0); 463741#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 463740#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 463739#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 463738#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 463737#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 463631#L774-3 assume !(1 == ~M_E~0); 463629#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 463627#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 463625#L784-3 assume !(1 == ~T3_E~0); 463623#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 463621#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 463619#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 463617#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 463615#L809-3 assume !(1 == ~E_1~0); 463613#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 463611#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 463610#L824-3 assume !(1 == ~E_4~0); 463609#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 463608#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 463607#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 463603#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 463599#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 463597#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 463595#L1084 assume !(0 == start_simulation_~tmp~3#1); 463592#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 463590#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 463583#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 463582#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 463581#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 463580#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 463579#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 463578#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 442993#L1065-2 [2024-10-31 22:11:43,509 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:43,510 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2024-10-31 22:11:43,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:43,510 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532182243] [2024-10-31 22:11:43,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:43,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:43,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:43,523 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:11:43,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:43,551 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:11:43,552 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:43,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1309757353, now seen corresponding path program 1 times [2024-10-31 22:11:43,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:43,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131576049] [2024-10-31 22:11:43,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:43,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:43,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:43,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:43,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:43,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131576049] [2024-10-31 22:11:43,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2131576049] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:43,946 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:43,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:11:43,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738846317] [2024-10-31 22:11:43,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:43,947 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:43,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:43,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:11:43,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:11:43,948 INFO L87 Difference]: Start difference. First operand 21854 states and 30263 transitions. cyclomatic complexity: 8425 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:44,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:44,264 INFO L93 Difference]: Finished difference Result 22166 states and 30382 transitions. [2024-10-31 22:11:44,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22166 states and 30382 transitions. [2024-10-31 22:11:44,345 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21924 [2024-10-31 22:11:44,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22166 states to 22166 states and 30382 transitions. [2024-10-31 22:11:44,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22166 [2024-10-31 22:11:44,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22166 [2024-10-31 22:11:44,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22166 states and 30382 transitions. [2024-10-31 22:11:44,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:44,428 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22166 states and 30382 transitions. [2024-10-31 22:11:44,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22166 states and 30382 transitions. [2024-10-31 22:11:44,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22166 to 22166. [2024-10-31 22:11:44,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22166 states, 22166 states have (on average 1.3706577641432824) internal successors, (30382), 22165 states have internal predecessors, (30382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:44,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22166 states to 22166 states and 30382 transitions. [2024-10-31 22:11:44,692 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22166 states and 30382 transitions. [2024-10-31 22:11:44,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:11:44,693 INFO L425 stractBuchiCegarLoop]: Abstraction has 22166 states and 30382 transitions. [2024-10-31 22:11:44,693 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-31 22:11:44,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22166 states and 30382 transitions. [2024-10-31 22:11:44,756 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21924 [2024-10-31 22:11:44,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:44,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:44,758 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:44,758 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:44,759 INFO L745 eck$LassoCheckResult]: Stem: 487110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 487111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 487290#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 487291#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 487467#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 487007#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 487008#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 486836#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 486837#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 486813#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 486814#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 486983#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 487144#L696 assume !(0 == ~M_E~0); 487145#L696-2 assume !(0 == ~T1_E~0); 487472#L701-1 assume !(0 == ~T2_E~0); 487474#L706-1 assume !(0 == ~T3_E~0); 487262#L711-1 assume !(0 == ~T4_E~0); 487043#L716-1 assume !(0 == ~T5_E~0); 487044#L721-1 assume !(0 == ~T6_E~0); 487217#L726-1 assume !(0 == ~E_M~0); 487218#L731-1 assume !(0 == ~E_1~0); 487183#L736-1 assume !(0 == ~E_2~0); 487184#L741-1 assume !(0 == ~E_3~0); 487273#L746-1 assume !(0 == ~E_4~0); 487065#L751-1 assume !(0 == ~E_5~0); 487066#L756-1 assume !(0 == ~E_6~0); 487040#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 486857#L346 assume !(1 == ~m_pc~0); 486858#L346-2 is_master_triggered_~__retres1~0#1 := 0; 487081#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 487073#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 487074#L861 assume !(0 != activate_threads_~tmp~1#1); 487441#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 486892#L365 assume !(1 == ~t1_pc~0); 486893#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 487458#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 486841#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 486842#L869 assume !(0 != activate_threads_~tmp___0~0#1); 486882#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 487334#L384 assume !(1 == ~t2_pc~0); 487328#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 487329#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 487294#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 486801#L877 assume !(0 != activate_threads_~tmp___1~0#1); 486802#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 487161#L403 assume !(1 == ~t3_pc~0); 487162#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 487372#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 486776#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 486777#L885 assume !(0 != activate_threads_~tmp___2~0#1); 487154#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 487155#L422 assume !(1 == ~t4_pc~0); 487288#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 487289#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 486947#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 486948#L893 assume !(0 != activate_threads_~tmp___3~0#1); 487240#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 486815#L441 assume !(1 == ~t5_pc~0); 486816#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 487436#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 487528#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 487558#L901 assume !(0 != activate_threads_~tmp___4~0#1); 487250#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 487251#L460 assume !(1 == ~t6_pc~0); 487395#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 486822#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 486823#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 487276#L909 assume !(0 != activate_threads_~tmp___5~0#1); 487392#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 487227#L774 assume !(1 == ~M_E~0); 487228#L774-2 assume !(1 == ~T1_E~0); 487412#L779-1 assume !(1 == ~T2_E~0); 487130#L784-1 assume !(1 == ~T3_E~0); 487131#L789-1 assume !(1 == ~T4_E~0); 486877#L794-1 assume !(1 == ~T5_E~0); 486878#L799-1 assume !(1 == ~T6_E~0); 487515#L804-1 assume !(1 == ~E_M~0); 487516#L809-1 assume !(1 == ~E_1~0); 487212#L814-1 assume !(1 == ~E_2~0); 486780#L819-1 assume !(1 == ~E_3~0); 486781#L824-1 assume !(1 == ~E_4~0); 487282#L829-1 assume !(1 == ~E_5~0); 487401#L834-1 assume !(1 == ~E_6~0); 487025#L839-1 assume { :end_inline_reset_delta_events } true; 487026#L1065-2 [2024-10-31 22:11:44,759 INFO L747 eck$LassoCheckResult]: Loop: 487026#L1065-2 assume !false; 497028#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 495047#L671-1 assume !false; 497025#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 497010#L530 assume !(0 == ~m_st~0); 497011#L534 assume !(0 == ~t1_st~0); 497006#L538 assume !(0 == ~t2_st~0); 497007#L542 assume !(0 == ~t3_st~0); 497009#L546 assume !(0 == ~t4_st~0); 497004#L550 assume !(0 == ~t5_st~0); 497005#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 497008#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 496581#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 496582#L582 assume !(0 != eval_~tmp~0#1); 497285#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 497283#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 497281#L696-3 assume !(0 == ~M_E~0); 497279#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 497277#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 497275#L706-3 assume !(0 == ~T3_E~0); 497273#L711-3 assume !(0 == ~T4_E~0); 497271#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 497269#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 497267#L726-3 assume !(0 == ~E_M~0); 497265#L731-3 assume !(0 == ~E_1~0); 497263#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 497261#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 497259#L746-3 assume !(0 == ~E_4~0); 497257#L751-3 assume !(0 == ~E_5~0); 497255#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 497253#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 497251#L346-24 assume 1 == ~m_pc~0; 497248#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 497245#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 497241#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 497238#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 497235#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 497231#L365-24 assume !(1 == ~t1_pc~0); 497228#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 497225#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 497222#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 497219#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 497216#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 497213#L384-24 assume 1 == ~t2_pc~0; 497209#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 497205#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 497202#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 497199#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 497196#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 497192#L403-24 assume !(1 == ~t3_pc~0); 497189#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 497186#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 497183#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 497180#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 497177#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 497173#L422-24 assume !(1 == ~t4_pc~0); 497170#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 497167#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 497165#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 497162#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 497159#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 497156#L441-24 assume 1 == ~t5_pc~0; 497152#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 497147#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 497142#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 497137#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 497133#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 497129#L460-24 assume !(1 == ~t6_pc~0); 497125#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 497121#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 497117#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 497114#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 497111#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 497107#L774-3 assume !(1 == ~M_E~0); 497105#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 497103#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 497101#L784-3 assume !(1 == ~T3_E~0); 497099#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 497096#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 497094#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 497092#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 497090#L809-3 assume !(1 == ~E_1~0); 497088#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 497086#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 497083#L824-3 assume !(1 == ~E_4~0); 497080#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 497077#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 497074#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 497068#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 497061#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 497058#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 497054#L1084 assume !(0 == start_simulation_~tmp~3#1); 497051#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 497049#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 497041#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 497039#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 497037#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 497035#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 497033#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 497031#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 487026#L1065-2 [2024-10-31 22:11:44,760 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:44,760 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2024-10-31 22:11:44,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:44,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28286717] [2024-10-31 22:11:44,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:44,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:44,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:44,773 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:11:44,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:44,805 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:11:44,805 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:44,805 INFO L85 PathProgramCache]: Analyzing trace with hash -623576280, now seen corresponding path program 1 times [2024-10-31 22:11:44,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:44,806 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1243972281] [2024-10-31 22:11:44,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:44,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:44,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:44,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:44,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:44,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1243972281] [2024-10-31 22:11:44,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1243972281] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:44,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:44,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:11:44,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406775932] [2024-10-31 22:11:44,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:44,904 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:44,904 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:44,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:11:44,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:11:44,905 INFO L87 Difference]: Start difference. First operand 22166 states and 30382 transitions. cyclomatic complexity: 8232 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:45,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:45,364 INFO L93 Difference]: Finished difference Result 22658 states and 30733 transitions. [2024-10-31 22:11:45,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22658 states and 30733 transitions. [2024-10-31 22:11:45,444 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22416 [2024-10-31 22:11:45,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22658 states to 22658 states and 30733 transitions. [2024-10-31 22:11:45,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22658 [2024-10-31 22:11:45,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22658 [2024-10-31 22:11:45,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22658 states and 30733 transitions. [2024-10-31 22:11:45,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:45,528 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22658 states and 30733 transitions. [2024-10-31 22:11:45,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22658 states and 30733 transitions. [2024-10-31 22:11:45,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22658 to 22658. [2024-10-31 22:11:45,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22658 states, 22658 states have (on average 1.3563862653367464) internal successors, (30733), 22657 states have internal predecessors, (30733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:45,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22658 states to 22658 states and 30733 transitions. [2024-10-31 22:11:45,781 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22658 states and 30733 transitions. [2024-10-31 22:11:45,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:11:45,782 INFO L425 stractBuchiCegarLoop]: Abstraction has 22658 states and 30733 transitions. [2024-10-31 22:11:45,782 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-10-31 22:11:45,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22658 states and 30733 transitions. [2024-10-31 22:11:45,844 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22416 [2024-10-31 22:11:45,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:45,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:45,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:45,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:45,847 INFO L745 eck$LassoCheckResult]: Stem: 531936#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 531937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 532118#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 532119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 532297#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 531833#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 531834#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 531668#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 531669#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 531643#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 531644#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 531812#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 531973#L696 assume !(0 == ~M_E~0); 531974#L696-2 assume !(0 == ~T1_E~0); 532305#L701-1 assume !(0 == ~T2_E~0); 532307#L706-1 assume !(0 == ~T3_E~0); 532091#L711-1 assume !(0 == ~T4_E~0); 531867#L716-1 assume !(0 == ~T5_E~0); 531868#L721-1 assume !(0 == ~T6_E~0); 532043#L726-1 assume !(0 == ~E_M~0); 532044#L731-1 assume !(0 == ~E_1~0); 532009#L736-1 assume !(0 == ~E_2~0); 532010#L741-1 assume !(0 == ~E_3~0); 532102#L746-1 assume !(0 == ~E_4~0); 531891#L751-1 assume !(0 == ~E_5~0); 531892#L756-1 assume !(0 == ~E_6~0); 531864#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 531690#L346 assume !(1 == ~m_pc~0); 531691#L346-2 is_master_triggered_~__retres1~0#1 := 0; 531907#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 531897#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 531898#L861 assume !(0 != activate_threads_~tmp~1#1); 532266#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 531724#L365 assume !(1 == ~t1_pc~0); 531725#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 532285#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 531676#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 531677#L869 assume !(0 != activate_threads_~tmp___0~0#1); 531713#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 532161#L384 assume !(1 == ~t2_pc~0); 532157#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 532158#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 532123#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 531634#L877 assume !(0 != activate_threads_~tmp___1~0#1); 531635#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 531988#L403 assume !(1 == ~t3_pc~0); 531989#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 532203#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 531606#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 531607#L885 assume !(0 != activate_threads_~tmp___2~0#1); 531983#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 531984#L422 assume !(1 == ~t4_pc~0); 532116#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 532117#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 531774#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 531775#L893 assume !(0 != activate_threads_~tmp___3~0#1); 532067#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 531645#L441 assume !(1 == ~t5_pc~0); 531646#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 532262#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 532367#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 532402#L901 assume !(0 != activate_threads_~tmp___4~0#1); 532079#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 532080#L460 assume !(1 == ~t6_pc~0); 532221#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 531654#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 531655#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 532104#L909 assume !(0 != activate_threads_~tmp___5~0#1); 532216#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 532053#L774 assume !(1 == ~M_E~0); 532054#L774-2 assume !(1 == ~T1_E~0); 532234#L779-1 assume !(1 == ~T2_E~0); 531954#L784-1 assume !(1 == ~T3_E~0); 531955#L789-1 assume !(1 == ~T4_E~0); 531707#L794-1 assume !(1 == ~T5_E~0); 531708#L799-1 assume !(1 == ~T6_E~0); 532356#L804-1 assume !(1 == ~E_M~0); 532357#L809-1 assume !(1 == ~E_1~0); 532039#L814-1 assume !(1 == ~E_2~0); 531612#L819-1 assume !(1 == ~E_3~0); 531613#L824-1 assume !(1 == ~E_4~0); 532111#L829-1 assume !(1 == ~E_5~0); 532224#L834-1 assume !(1 == ~E_6~0); 531853#L839-1 assume { :end_inline_reset_delta_events } true; 531854#L1065-2 [2024-10-31 22:11:45,847 INFO L747 eck$LassoCheckResult]: Loop: 531854#L1065-2 assume !false; 550604#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 550601#L671-1 assume !false; 550599#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 550593#L530 assume !(0 == ~m_st~0); 550594#L534 assume !(0 == ~t1_st~0); 550589#L538 assume !(0 == ~t2_st~0); 550590#L542 assume !(0 == ~t3_st~0); 550592#L546 assume !(0 == ~t4_st~0); 550587#L550 assume !(0 == ~t5_st~0); 550588#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 550591#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 554248#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 554247#L582 assume !(0 != eval_~tmp~0#1); 531790#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 531791#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 554209#L696-3 assume !(0 == ~M_E~0); 554210#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 554240#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 554239#L706-3 assume !(0 == ~T3_E~0); 554238#L711-3 assume !(0 == ~T4_E~0); 554237#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 554236#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 554235#L726-3 assume !(0 == ~E_M~0); 554234#L731-3 assume !(0 == ~E_1~0); 554233#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 554232#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 554231#L746-3 assume !(0 == ~E_4~0); 554230#L751-3 assume !(0 == ~E_5~0); 554229#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 554228#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 554227#L346-24 assume !(1 == ~m_pc~0); 554225#L346-26 is_master_triggered_~__retres1~0#1 := 0; 554224#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 554223#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 554222#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 532232#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 531801#L365-24 assume !(1 == ~t1_pc~0); 531802#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 554189#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 554187#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 554185#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 554183#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 554181#L384-24 assume !(1 == ~t2_pc~0); 554178#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 554176#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 554174#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 532088#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 531780#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 531781#L403-24 assume !(1 == ~t3_pc~0); 531894#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 554080#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 554079#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 554077#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 554075#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 554073#L422-24 assume !(1 == ~t4_pc~0); 554070#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 531786#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 531787#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 532270#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 532242#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 531850#L441-24 assume !(1 == ~t5_pc~0); 531851#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 532068#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 553527#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 553526#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 531715#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 532163#L460-24 assume !(1 == ~t6_pc~0); 532164#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 532235#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 531889#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 531890#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 532155#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 532156#L774-3 assume !(1 == ~M_E~0); 532078#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 531911#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 531630#L784-3 assume !(1 == ~T3_E~0); 531631#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 532393#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 553358#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 553357#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 553355#L809-3 assume !(1 == ~E_1~0); 553354#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 553350#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 531872#L824-3 assume !(1 == ~E_4~0); 531859#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 531860#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 531705#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 531706#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 531703#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 553129#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 550655#L1084 assume !(0 == start_simulation_~tmp~3#1); 550652#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 550650#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 550642#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 550639#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 550637#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 550635#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 550633#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 550631#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 531854#L1065-2 [2024-10-31 22:11:45,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:45,848 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2024-10-31 22:11:45,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:45,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439301761] [2024-10-31 22:11:45,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:45,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:45,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:45,861 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:11:45,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:45,880 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:11:45,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:45,881 INFO L85 PathProgramCache]: Analyzing trace with hash -1399702353, now seen corresponding path program 1 times [2024-10-31 22:11:45,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:45,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089552998] [2024-10-31 22:11:45,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:45,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:45,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:45,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:45,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:45,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1089552998] [2024-10-31 22:11:45,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1089552998] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:45,969 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:45,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:11:45,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553240308] [2024-10-31 22:11:45,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:45,970 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:45,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:45,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:11:45,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:11:45,970 INFO L87 Difference]: Start difference. First operand 22658 states and 30733 transitions. cyclomatic complexity: 8091 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:46,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:46,280 INFO L93 Difference]: Finished difference Result 23549 states and 31624 transitions. [2024-10-31 22:11:46,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23549 states and 31624 transitions. [2024-10-31 22:11:46,367 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23304 [2024-10-31 22:11:46,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23549 states to 23549 states and 31624 transitions. [2024-10-31 22:11:46,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23549 [2024-10-31 22:11:46,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23549 [2024-10-31 22:11:46,692 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23549 states and 31624 transitions. [2024-10-31 22:11:46,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:46,713 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23549 states and 31624 transitions. [2024-10-31 22:11:46,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23549 states and 31624 transitions. [2024-10-31 22:11:46,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23549 to 23549. [2024-10-31 22:11:47,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23549 states, 23549 states have (on average 1.3429020340566478) internal successors, (31624), 23548 states have internal predecessors, (31624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:47,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23549 states to 23549 states and 31624 transitions. [2024-10-31 22:11:47,072 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23549 states and 31624 transitions. [2024-10-31 22:11:47,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:11:47,073 INFO L425 stractBuchiCegarLoop]: Abstraction has 23549 states and 31624 transitions. [2024-10-31 22:11:47,073 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-10-31 22:11:47,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23549 states and 31624 transitions. [2024-10-31 22:11:47,160 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23304 [2024-10-31 22:11:47,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:11:47,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:11:47,162 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:47,162 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:11:47,162 INFO L745 eck$LassoCheckResult]: Stem: 578148#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 578149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 578330#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 578331#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 578492#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 578047#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 578048#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 577885#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 577886#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 577858#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 577859#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 578026#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 578180#L696 assume !(0 == ~M_E~0); 578181#L696-2 assume !(0 == ~T1_E~0); 578501#L701-1 assume !(0 == ~T2_E~0); 578503#L706-1 assume !(0 == ~T3_E~0); 578300#L711-1 assume !(0 == ~T4_E~0); 578082#L716-1 assume !(0 == ~T5_E~0); 578083#L721-1 assume !(0 == ~T6_E~0); 578251#L726-1 assume !(0 == ~E_M~0); 578252#L731-1 assume !(0 == ~E_1~0); 578216#L736-1 assume !(0 == ~E_2~0); 578217#L741-1 assume !(0 == ~E_3~0); 578311#L746-1 assume !(0 == ~E_4~0); 578104#L751-1 assume !(0 == ~E_5~0); 578105#L756-1 assume !(0 == ~E_6~0); 578079#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 577905#L346 assume !(1 == ~m_pc~0); 577906#L346-2 is_master_triggered_~__retres1~0#1 := 0; 578119#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 578588#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 578517#L861 assume !(0 != activate_threads_~tmp~1#1); 578468#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 577939#L365 assume !(1 == ~t1_pc~0); 577940#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 578480#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 577891#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 577892#L869 assume !(0 != activate_threads_~tmp___0~0#1); 577928#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 578370#L384 assume !(1 == ~t2_pc~0); 578367#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 578368#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 578336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 577848#L877 assume !(0 != activate_threads_~tmp___1~0#1); 577849#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 578196#L403 assume !(1 == ~t3_pc~0); 578197#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 578404#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 577821#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 577822#L885 assume !(0 != activate_threads_~tmp___2~0#1); 578190#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 578191#L422 assume !(1 == ~t4_pc~0); 578328#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 578329#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 577990#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 577991#L893 assume !(0 != activate_threads_~tmp___3~0#1); 578276#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 577860#L441 assume !(1 == ~t5_pc~0); 577861#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 578463#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 578587#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 578586#L901 assume !(0 != activate_threads_~tmp___4~0#1); 578287#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 578288#L460 assume !(1 == ~t6_pc~0); 578424#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 577869#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 577870#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 578313#L909 assume !(0 != activate_threads_~tmp___5~0#1); 578419#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 578261#L774 assume !(1 == ~M_E~0); 578262#L774-2 assume !(1 == ~T1_E~0); 578438#L779-1 assume !(1 == ~T2_E~0); 578165#L784-1 assume !(1 == ~T3_E~0); 578166#L789-1 assume !(1 == ~T4_E~0); 577922#L794-1 assume !(1 == ~T5_E~0); 577923#L799-1 assume !(1 == ~T6_E~0); 578543#L804-1 assume !(1 == ~E_M~0); 578544#L809-1 assume !(1 == ~E_1~0); 578247#L814-1 assume !(1 == ~E_2~0); 577827#L819-1 assume !(1 == ~E_3~0); 577828#L824-1 assume !(1 == ~E_4~0); 578320#L829-1 assume !(1 == ~E_5~0); 578428#L834-1 assume !(1 == ~E_6~0); 578067#L839-1 assume { :end_inline_reset_delta_events } true; 578068#L1065-2 [2024-10-31 22:11:47,163 INFO L747 eck$LassoCheckResult]: Loop: 578068#L1065-2 assume !false; 596931#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 596928#L671-1 assume !false; 596925#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 596920#L530 assume !(0 == ~m_st~0); 596921#L534 assume !(0 == ~t1_st~0); 596916#L538 assume !(0 == ~t2_st~0); 596917#L542 assume !(0 == ~t3_st~0); 596919#L546 assume !(0 == ~t4_st~0); 596914#L550 assume !(0 == ~t5_st~0); 596915#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 596918#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 597401#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 597397#L582 assume !(0 != eval_~tmp~0#1); 597395#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 597393#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 597391#L696-3 assume !(0 == ~M_E~0); 597389#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 597387#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 597385#L706-3 assume !(0 == ~T3_E~0); 597383#L711-3 assume !(0 == ~T4_E~0); 597380#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 597378#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 597376#L726-3 assume !(0 == ~E_M~0); 597374#L731-3 assume !(0 == ~E_1~0); 597372#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 597370#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 597368#L746-3 assume !(0 == ~E_4~0); 597367#L751-3 assume !(0 == ~E_5~0); 597366#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 597365#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 597364#L346-24 assume !(1 == ~m_pc~0); 597361#L346-26 is_master_triggered_~__retres1~0#1 := 0; 597353#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 597351#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 597349#L861-24 assume !(0 != activate_threads_~tmp~1#1); 597344#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 597342#L365-24 assume !(1 == ~t1_pc~0); 597334#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 597332#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 597330#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 597328#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 597326#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 597324#L384-24 assume !(1 == ~t2_pc~0); 597321#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 597319#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 597317#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 597316#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 597314#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 597313#L403-24 assume !(1 == ~t3_pc~0); 597312#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 597311#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 597310#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 597309#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 597308#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 597307#L422-24 assume !(1 == ~t4_pc~0); 597306#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 597305#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 597303#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 597302#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 597301#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 597299#L441-24 assume !(1 == ~t5_pc~0); 597297#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 597300#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 597298#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 597291#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 597290#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 597289#L460-24 assume !(1 == ~t6_pc~0); 597288#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 597287#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 597286#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 597285#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 597284#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 597095#L774-3 assume !(1 == ~M_E~0); 597093#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 597091#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 597089#L784-3 assume !(1 == ~T3_E~0); 597087#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 597085#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 597083#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 597081#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 597079#L809-3 assume !(1 == ~E_1~0); 597077#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 597075#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 597073#L824-3 assume !(1 == ~E_4~0); 597071#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 597070#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 597069#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 597065#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 597061#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 597060#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 597055#L1084 assume !(0 == start_simulation_~tmp~3#1); 597052#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 597050#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 597042#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 597039#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 597037#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 597035#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 597033#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 597031#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 578068#L1065-2 [2024-10-31 22:11:47,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:47,164 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 7 times [2024-10-31 22:11:47,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:47,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1370390740] [2024-10-31 22:11:47,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:47,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:47,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:47,181 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:11:47,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:11:47,202 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:11:47,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:11:47,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1209085105, now seen corresponding path program 1 times [2024-10-31 22:11:47,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:11:47,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027579998] [2024-10-31 22:11:47,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:11:47,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:11:47,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:11:47,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:11:47,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:11:47,267 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027579998] [2024-10-31 22:11:47,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027579998] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:11:47,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:11:47,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:11:47,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2094228542] [2024-10-31 22:11:47,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:11:47,269 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:11:47,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:11:47,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:11:47,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:11:47,270 INFO L87 Difference]: Start difference. First operand 23549 states and 31624 transitions. cyclomatic complexity: 8091 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:47,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:11:47,574 INFO L93 Difference]: Finished difference Result 44237 states and 58540 transitions. [2024-10-31 22:11:47,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44237 states and 58540 transitions. [2024-10-31 22:11:47,846 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43840 [2024-10-31 22:11:47,999 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44237 states to 44237 states and 58540 transitions. [2024-10-31 22:11:47,999 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44237 [2024-10-31 22:11:48,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44237 [2024-10-31 22:11:48,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44237 states and 58540 transitions. [2024-10-31 22:11:48,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:11:48,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44237 states and 58540 transitions. [2024-10-31 22:11:48,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44237 states and 58540 transitions. [2024-10-31 22:11:48,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44237 to 42701. [2024-10-31 22:11:48,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42701 states, 42701 states have (on average 1.326713660101637) internal successors, (56652), 42700 states have internal predecessors, (56652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:11:49,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42701 states to 42701 states and 56652 transitions. [2024-10-31 22:11:49,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42701 states and 56652 transitions. [2024-10-31 22:11:49,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:11:49,069 INFO L425 stractBuchiCegarLoop]: Abstraction has 42701 states and 56652 transitions. [2024-10-31 22:11:49,070 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-10-31 22:11:49,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42701 states and 56652 transitions.