./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:17:56,131 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:17:56,252 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:17:56,262 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:17:56,262 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:17:56,304 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:17:56,307 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:17:56,308 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:17:56,309 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:17:56,311 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:17:56,312 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:17:56,312 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:17:56,313 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:17:56,313 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:17:56,314 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:17:56,316 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:17:56,317 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:17:56,317 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:17:56,318 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:17:56,318 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:17:56,318 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:17:56,323 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:17:56,323 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:17:56,324 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:17:56,324 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:17:56,324 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:17:56,325 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:17:56,325 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:17:56,326 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:17:56,326 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:17:56,326 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:17:56,327 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:17:56,327 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:17:56,328 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:17:56,328 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:17:56,329 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:17:56,329 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:17:56,329 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:17:56,330 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:17:56,330 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 [2024-10-31 22:17:56,678 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:17:56,709 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:17:56,715 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:17:56,717 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:17:56,717 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:17:56,719 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c Unable to find full path for "g++" [2024-10-31 22:17:59,217 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:17:59,540 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:17:59,541 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2024-10-31 22:17:59,559 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/data/c1b94b1f7/56f966f88f7247f1a0335a917f995f1f/FLAGe2b9214bb [2024-10-31 22:17:59,579 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/data/c1b94b1f7/56f966f88f7247f1a0335a917f995f1f [2024-10-31 22:17:59,583 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:17:59,585 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:17:59,587 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:17:59,587 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:17:59,595 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:17:59,596 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:17:59" (1/1) ... [2024-10-31 22:17:59,597 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@596e03c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:17:59, skipping insertion in model container [2024-10-31 22:17:59,598 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:17:59" (1/1) ... [2024-10-31 22:17:59,666 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:18:00,071 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:00,092 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:18:00,192 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:00,230 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:18:00,231 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00 WrapperNode [2024-10-31 22:18:00,231 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:18:00,234 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:00,234 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:18:00,235 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:18:00,245 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,261 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,359 INFO L138 Inliner]: procedures = 42, calls = 53, calls flagged for inlining = 48, calls inlined = 135, statements flattened = 2006 [2024-10-31 22:18:00,360 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:00,361 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:18:00,361 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:18:00,361 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:18:00,377 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,377 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,386 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,410 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:18:00,411 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,411 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,479 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,513 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,521 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,533 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,545 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:18:00,546 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:18:00,546 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:18:00,547 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:18:00,547 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (1/1) ... [2024-10-31 22:18:00,554 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:00,568 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:00,582 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:18:00,584 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c6debe44-fc25-46c2-bbdd-f29460c505d3/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:18:00,613 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:18:00,614 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:18:00,614 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:18:00,614 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:18:00,725 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:18:00,727 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:18:02,874 INFO L? ?]: Removed 392 outVars from TransFormulas that were not future-live. [2024-10-31 22:18:02,875 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:18:02,930 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:18:02,930 INFO L316 CfgBuilder]: Removed 10 assume(true) statements. [2024-10-31 22:18:02,931 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:02 BoogieIcfgContainer [2024-10-31 22:18:02,931 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:18:02,932 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:18:02,933 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:18:02,940 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:18:02,941 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:02,943 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:17:59" (1/3) ... [2024-10-31 22:18:02,945 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1bfc536b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:02, skipping insertion in model container [2024-10-31 22:18:02,946 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:02,946 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:00" (2/3) ... [2024-10-31 22:18:02,948 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1bfc536b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:02, skipping insertion in model container [2024-10-31 22:18:02,949 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:02,949 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:02" (3/3) ... [2024-10-31 22:18:02,950 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-1.c [2024-10-31 22:18:03,066 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:18:03,067 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:18:03,067 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:18:03,067 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:18:03,067 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:18:03,067 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:18:03,067 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:18:03,068 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:18:03,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 845 states, 844 states have (on average 1.5130331753554502) internal successors, (1277), 844 states have internal predecessors, (1277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:03,140 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 738 [2024-10-31 22:18:03,140 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:03,140 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:03,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:03,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:03,153 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:18:03,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 845 states, 844 states have (on average 1.5130331753554502) internal successors, (1277), 844 states have internal predecessors, (1277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:03,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 738 [2024-10-31 22:18:03,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:03,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:03,181 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:03,181 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:03,193 INFO L745 eck$LassoCheckResult]: Stem: 111#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 764#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 625#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 760#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 581#L536true assume !(1 == ~m_i~0);~m_st~0 := 2; 793#L536-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 264#L541-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 151#L546-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 650#L551-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 139#L556-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 599#L561-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 578#L566-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 376#L571-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 670#L769true assume !(0 == ~M_E~0); 393#L769-2true assume !(0 == ~T1_E~0); 417#L774-1true assume !(0 == ~T2_E~0); 688#L779-1true assume !(0 == ~T3_E~0); 559#L784-1true assume !(0 == ~T4_E~0); 374#L789-1true assume !(0 == ~T5_E~0); 473#L794-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 826#L799-1true assume !(0 == ~T7_E~0); 378#L804-1true assume !(0 == ~E_M~0); 410#L809-1true assume !(0 == ~E_1~0); 592#L814-1true assume !(0 == ~E_2~0); 9#L819-1true assume !(0 == ~E_3~0); 189#L824-1true assume !(0 == ~E_4~0); 816#L829-1true assume !(0 == ~E_5~0); 683#L834-1true assume 0 == ~E_6~0;~E_6~0 := 1; 72#L839-1true assume !(0 == ~E_7~0); 479#L844-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 330#L376true assume !(1 == ~m_pc~0); 328#L376-2true is_master_triggered_~__retres1~0#1 := 0; 775#L387true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43#L955true assume !(0 != activate_threads_~tmp~1#1); 256#L955-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394#L395true assume 1 == ~t1_pc~0; 61#L396true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 560#L406true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 606#L963true assume !(0 != activate_threads_~tmp___0~0#1); 336#L963-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 836#L414true assume !(1 == ~t2_pc~0); 590#L414-2true is_transmit2_triggered_~__retres1~2#1 := 0; 824#L425true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 588#L971true assume !(0 != activate_threads_~tmp___1~0#1); 699#L971-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 261#L433true assume 1 == ~t3_pc~0; 220#L434true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 709#L444true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 522#L979true assume !(0 != activate_threads_~tmp___2~0#1); 55#L979-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 794#L452true assume !(1 == ~t4_pc~0); 137#L452-2true is_transmit4_triggered_~__retres1~4#1 := 0; 363#L463true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 706#L987true assume !(0 != activate_threads_~tmp___3~0#1); 156#L987-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 458#L471true assume 1 == ~t5_pc~0; 755#L472true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 145#L482true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 542#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 822#L995true assume !(0 != activate_threads_~tmp___4~0#1); 673#L995-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 741#L490true assume 1 == ~t6_pc~0; 632#L491true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 368#L501true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 371#L1003true assume !(0 != activate_threads_~tmp___5~0#1); 270#L1003-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 244#L509true assume !(1 == ~t7_pc~0); 593#L509-2true is_transmit7_triggered_~__retres1~7#1 := 0; 123#L520true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 778#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 159#L1011true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 708#L1011-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 603#L857true assume !(1 == ~M_E~0); 46#L857-2true assume !(1 == ~T1_E~0); 198#L862-1true assume !(1 == ~T2_E~0); 203#L867-1true assume !(1 == ~T3_E~0); 262#L872-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 436#L877-1true assume !(1 == ~T5_E~0); 631#L882-1true assume !(1 == ~T6_E~0); 748#L887-1true assume !(1 == ~T7_E~0); 497#L892-1true assume !(1 == ~E_M~0); 714#L897-1true assume !(1 == ~E_1~0); 213#L902-1true assume !(1 == ~E_2~0); 514#L907-1true assume !(1 == ~E_3~0); 448#L912-1true assume 1 == ~E_4~0;~E_4~0 := 2; 442#L917-1true assume !(1 == ~E_5~0); 692#L922-1true assume !(1 == ~E_6~0); 801#L927-1true assume !(1 == ~E_7~0); 433#L932-1true assume { :end_inline_reset_delta_events } true; 727#L1178-2true [2024-10-31 22:18:03,196 INFO L747 eck$LassoCheckResult]: Loop: 727#L1178-2true assume !false; 420#L1179true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 536#L744-1true assume false; 500#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 306#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 668#L769-3true assume 0 == ~M_E~0;~M_E~0 := 1; 259#L769-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 399#L774-3true assume !(0 == ~T2_E~0); 99#L779-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 14#L784-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 837#L789-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 10#L794-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 32#L799-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 162#L804-3true assume 0 == ~E_M~0;~E_M~0 := 1; 332#L809-3true assume 0 == ~E_1~0;~E_1~0 := 1; 30#L814-3true assume !(0 == ~E_2~0); 570#L819-3true assume 0 == ~E_3~0;~E_3~0 := 1; 525#L824-3true assume 0 == ~E_4~0;~E_4~0 := 1; 518#L829-3true assume 0 == ~E_5~0;~E_5~0 := 1; 199#L834-3true assume 0 == ~E_6~0;~E_6~0 := 1; 472#L839-3true assume 0 == ~E_7~0;~E_7~0 := 1; 600#L844-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 740#L376-27true assume !(1 == ~m_pc~0); 827#L376-29true is_master_triggered_~__retres1~0#1 := 0; 397#L387-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 464#is_master_triggered_returnLabel#10true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 701#L955-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 832#L955-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 817#L395-27true assume !(1 == ~t1_pc~0); 275#L395-29true is_transmit1_triggered_~__retres1~1#1 := 0; 200#L406-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 392#L963-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 266#L963-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 664#L414-27true assume !(1 == ~t2_pc~0); 757#L414-29true is_transmit2_triggered_~__retres1~2#1 := 0; 441#L425-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 439#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319#L971-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36#L971-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85#L433-27true assume !(1 == ~t3_pc~0); 323#L433-29true is_transmit3_triggered_~__retres1~3#1 := 0; 272#L444-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 302#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 125#L979-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 765#L979-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 751#L452-27true assume !(1 == ~t4_pc~0); 408#L452-29true is_transmit4_triggered_~__retres1~4#1 := 0; 563#L463-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 243#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 659#L987-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 671#L987-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33#L471-27true assume 1 == ~t5_pc~0; 501#L472-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 833#L482-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 555#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 461#L995-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 395#L995-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 329#L490-27true assume !(1 == ~t6_pc~0); 622#L490-29true is_transmit6_triggered_~__retres1~6#1 := 0; 131#L501-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 684#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 447#L1003-27true assume !(0 != activate_threads_~tmp___5~0#1); 722#L1003-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18#L509-27true assume !(1 == ~t7_pc~0); 242#L509-29true is_transmit7_triggered_~__retres1~7#1 := 0; 552#L520-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 166#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 349#L1011-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 811#L1011-29true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 359#L857-3true assume 1 == ~M_E~0;~M_E~0 := 2; 389#L857-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 798#L862-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 742#L867-3true assume !(1 == ~T3_E~0); 273#L872-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 354#L877-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 776#L882-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 386#L887-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 109#L892-3true assume 1 == ~E_M~0;~E_M~0 := 2; 548#L897-3true assume 1 == ~E_1~0;~E_1~0 := 2; 835#L902-3true assume 1 == ~E_2~0;~E_2~0 := 2; 212#L907-3true assume !(1 == ~E_3~0); 310#L912-3true assume 1 == ~E_4~0;~E_4~0 := 2; 585#L917-3true assume 1 == ~E_5~0;~E_5~0 := 2; 276#L922-3true assume 1 == ~E_6~0;~E_6~0 := 2; 138#L927-3true assume 1 == ~E_7~0;~E_7~0 := 2; 221#L932-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 60#L584-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 476#L626-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 170#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 251#L1197true assume !(0 == start_simulation_~tmp~3#1); 529#L1197-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 88#L584-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 258#L626-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 753#L1152true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 545#L1159true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 321#stop_simulation_returnLabel#1true start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 24#L1210true assume !(0 != start_simulation_~tmp___0~1#1); 727#L1178-2true [2024-10-31 22:18:03,202 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:03,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2024-10-31 22:18:03,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:03,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920191295] [2024-10-31 22:18:03,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:03,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:03,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:03,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:03,652 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:03,652 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920191295] [2024-10-31 22:18:03,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920191295] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:03,654 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:03,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:03,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1730603863] [2024-10-31 22:18:03,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:03,667 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:03,668 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:03,668 INFO L85 PathProgramCache]: Analyzing trace with hash 698466512, now seen corresponding path program 1 times [2024-10-31 22:18:03,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:03,669 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306249821] [2024-10-31 22:18:03,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:03,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:03,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:03,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:03,745 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:03,745 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1306249821] [2024-10-31 22:18:03,745 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1306249821] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:03,746 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:03,746 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:03,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883892542] [2024-10-31 22:18:03,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:03,750 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:03,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:03,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:03,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:03,798 INFO L87 Difference]: Start difference. First operand has 845 states, 844 states have (on average 1.5130331753554502) internal successors, (1277), 844 states have internal predecessors, (1277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:03,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:03,925 INFO L93 Difference]: Finished difference Result 843 states and 1253 transitions. [2024-10-31 22:18:03,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1253 transitions. [2024-10-31 22:18:03,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:03,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 838 states and 1248 transitions. [2024-10-31 22:18:03,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-10-31 22:18:03,956 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-10-31 22:18:03,956 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1248 transitions. [2024-10-31 22:18:03,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:03,962 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1248 transitions. [2024-10-31 22:18:03,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1248 transitions. [2024-10-31 22:18:04,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-10-31 22:18:04,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4892601431980907) internal successors, (1248), 837 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:04,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1248 transitions. [2024-10-31 22:18:04,050 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1248 transitions. [2024-10-31 22:18:04,052 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:04,058 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1248 transitions. [2024-10-31 22:18:04,058 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:18:04,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1248 transitions. [2024-10-31 22:18:04,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:04,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:04,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:04,070 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:04,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:04,071 INFO L745 eck$LassoCheckResult]: Stem: 1924#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1925#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2481#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2482#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2461#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2462#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2169#L541-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1993#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1994#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1975#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1976#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2460#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2285#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2286#L769 assume !(0 == ~M_E~0); 2305#L769-2 assume !(0 == ~T1_E~0); 2306#L774-1 assume !(0 == ~T2_E~0); 2333#L779-1 assume !(0 == ~T3_E~0); 2450#L784-1 assume !(0 == ~T4_E~0); 2283#L789-1 assume !(0 == ~T5_E~0); 2284#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2389#L799-1 assume !(0 == ~T7_E~0); 2288#L804-1 assume !(0 == ~E_M~0); 2289#L809-1 assume !(0 == ~E_1~0); 2328#L814-1 assume !(0 == ~E_2~0); 1712#L819-1 assume !(0 == ~E_3~0); 1713#L824-1 assume !(0 == ~E_4~0); 2066#L829-1 assume !(0 == ~E_5~0); 2509#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1849#L839-1 assume !(0 == ~E_7~0); 1850#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2241#L376 assume !(1 == ~m_pc~0); 2230#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2229#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2435#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1790#L955 assume !(0 != activate_threads_~tmp~1#1); 1791#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2162#L395 assume 1 == ~t1_pc~0; 1826#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1827#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1742#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1743#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2245#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2246#L414 assume !(1 == ~t2_pc~0); 1852#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1853#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2072#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2073#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2465#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2166#L433 assume 1 == ~t3_pc~0; 2108#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1964#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1710#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1711#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1815#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1816#L452 assume !(1 == ~t4_pc~0); 1971#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1972#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1809#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1810#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2004#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2005#L471 assume 1 == ~t5_pc~0; 2376#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1986#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1987#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2438#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2500#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2501#L490 assume 1 == ~t6_pc~0; 2486#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2244#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2059#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2060#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2176#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2144#L509 assume !(1 == ~t7_pc~0); 2145#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1946#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1947#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2011#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2012#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2471#L857 assume !(1 == ~M_E~0); 1797#L857-2 assume !(1 == ~T1_E~0); 1798#L862-1 assume !(1 == ~T2_E~0); 2076#L867-1 assume !(1 == ~T3_E~0); 2081#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2167#L877-1 assume !(1 == ~T5_E~0); 2352#L882-1 assume !(1 == ~T6_E~0); 2485#L887-1 assume !(1 == ~T7_E~0); 2405#L892-1 assume !(1 == ~E_M~0); 2406#L897-1 assume !(1 == ~E_1~0); 2096#L902-1 assume !(1 == ~E_2~0); 2097#L907-1 assume !(1 == ~E_3~0); 2366#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2358#L917-1 assume !(1 == ~E_5~0); 2359#L922-1 assume !(1 == ~E_6~0); 2511#L927-1 assume !(1 == ~E_7~0); 2347#L932-1 assume { :end_inline_reset_delta_events } true; 1747#L1178-2 [2024-10-31 22:18:04,074 INFO L747 eck$LassoCheckResult]: Loop: 1747#L1178-2 assume !false; 2334#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2335#L744-1 assume !false; 2208#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2209#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1782#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1991#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2093#L641 assume !(0 != eval_~tmp~0#1); 2407#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2216#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2217#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2164#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2165#L774-3 assume !(0 == ~T2_E~0); 1903#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1723#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1724#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1714#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1715#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1764#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2018#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1760#L814-3 assume !(0 == ~E_2~0); 1761#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2426#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2421#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2077#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2078#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2388#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2469#L376-27 assume 1 == ~m_pc~0; 2362#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2311#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2312#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2383#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2513#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2534#L395-27 assume 1 == ~t1_pc~0; 2530#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2079#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2080#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2276#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2171#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2172#L414-27 assume 1 == ~t2_pc~0; 2497#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2357#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2356#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2232#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1772#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1773#L433-27 assume !(1 == ~t3_pc~0); 1875#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2178#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2179#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1949#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1950#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2525#L452-27 assume !(1 == ~t4_pc~0); 2325#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2326#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2142#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2143#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2494#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1765#L471-27 assume 1 == ~t5_pc~0; 1766#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2090#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2447#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2380#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2307#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2240#L490-27 assume 1 == ~t6_pc~0; 2139#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1960#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1961#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2364#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 2365#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1732#L509-27 assume 1 == ~t7_pc~0; 1733#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2141#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2022#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2023#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2260#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2272#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2273#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2303#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2524#L867-3 assume !(1 == ~T3_E~0); 2180#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2181#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2267#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2297#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1920#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1921#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2444#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2094#L907-3 assume !(1 == ~E_3~0); 2095#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2220#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2185#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1973#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1974#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1824#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1721#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2031#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2032#L1197 assume !(0 == start_simulation_~tmp~3#1); 2153#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1883#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1847#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1740#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1741#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2441#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2234#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1746#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1747#L1178-2 [2024-10-31 22:18:04,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:04,075 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2024-10-31 22:18:04,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:04,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290986926] [2024-10-31 22:18:04,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:04,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:04,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:04,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:04,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:04,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290986926] [2024-10-31 22:18:04,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290986926] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:04,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:04,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:04,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264011382] [2024-10-31 22:18:04,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:04,151 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:04,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:04,152 INFO L85 PathProgramCache]: Analyzing trace with hash -542624296, now seen corresponding path program 1 times [2024-10-31 22:18:04,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:04,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587379134] [2024-10-31 22:18:04,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:04,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:04,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:04,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:04,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:04,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587379134] [2024-10-31 22:18:04,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1587379134] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:04,250 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:04,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:04,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896796861] [2024-10-31 22:18:04,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:04,251 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:04,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:04,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:04,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:04,252 INFO L87 Difference]: Start difference. First operand 838 states and 1248 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:04,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:04,277 INFO L93 Difference]: Finished difference Result 838 states and 1247 transitions. [2024-10-31 22:18:04,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1247 transitions. [2024-10-31 22:18:04,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:04,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1247 transitions. [2024-10-31 22:18:04,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-10-31 22:18:04,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-10-31 22:18:04,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1247 transitions. [2024-10-31 22:18:04,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:04,292 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1247 transitions. [2024-10-31 22:18:04,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1247 transitions. [2024-10-31 22:18:04,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-10-31 22:18:04,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4880668257756564) internal successors, (1247), 837 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:04,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1247 transitions. [2024-10-31 22:18:04,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1247 transitions. [2024-10-31 22:18:04,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:04,311 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1247 transitions. [2024-10-31 22:18:04,311 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:18:04,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1247 transitions. [2024-10-31 22:18:04,316 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:04,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:04,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:04,318 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:04,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:04,319 INFO L745 eck$LassoCheckResult]: Stem: 3607#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3608#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4164#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4165#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4144#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 4145#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3852#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3676#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3677#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3658#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3659#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4143#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3968#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3969#L769 assume !(0 == ~M_E~0); 3988#L769-2 assume !(0 == ~T1_E~0); 3989#L774-1 assume !(0 == ~T2_E~0); 4016#L779-1 assume !(0 == ~T3_E~0); 4133#L784-1 assume !(0 == ~T4_E~0); 3966#L789-1 assume !(0 == ~T5_E~0); 3967#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4072#L799-1 assume !(0 == ~T7_E~0); 3971#L804-1 assume !(0 == ~E_M~0); 3972#L809-1 assume !(0 == ~E_1~0); 4011#L814-1 assume !(0 == ~E_2~0); 3395#L819-1 assume !(0 == ~E_3~0); 3396#L824-1 assume !(0 == ~E_4~0); 3749#L829-1 assume !(0 == ~E_5~0); 4192#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3532#L839-1 assume !(0 == ~E_7~0); 3533#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3924#L376 assume !(1 == ~m_pc~0); 3913#L376-2 is_master_triggered_~__retres1~0#1 := 0; 3912#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4118#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3473#L955 assume !(0 != activate_threads_~tmp~1#1); 3474#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3845#L395 assume 1 == ~t1_pc~0; 3509#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3510#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3425#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3426#L963 assume !(0 != activate_threads_~tmp___0~0#1); 3928#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3929#L414 assume !(1 == ~t2_pc~0); 3535#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3536#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3755#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3756#L971 assume !(0 != activate_threads_~tmp___1~0#1); 4148#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3849#L433 assume 1 == ~t3_pc~0; 3791#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3647#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3393#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3394#L979 assume !(0 != activate_threads_~tmp___2~0#1); 3498#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3499#L452 assume !(1 == ~t4_pc~0); 3654#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3655#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3492#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3493#L987 assume !(0 != activate_threads_~tmp___3~0#1); 3687#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3688#L471 assume 1 == ~t5_pc~0; 4059#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3669#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4121#L995 assume !(0 != activate_threads_~tmp___4~0#1); 4183#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4184#L490 assume 1 == ~t6_pc~0; 4169#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3927#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3742#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3743#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 3859#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3827#L509 assume !(1 == ~t7_pc~0); 3828#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3629#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3630#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3694#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3695#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4154#L857 assume !(1 == ~M_E~0); 3480#L857-2 assume !(1 == ~T1_E~0); 3481#L862-1 assume !(1 == ~T2_E~0); 3759#L867-1 assume !(1 == ~T3_E~0); 3764#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3850#L877-1 assume !(1 == ~T5_E~0); 4035#L882-1 assume !(1 == ~T6_E~0); 4168#L887-1 assume !(1 == ~T7_E~0); 4088#L892-1 assume !(1 == ~E_M~0); 4089#L897-1 assume !(1 == ~E_1~0); 3779#L902-1 assume !(1 == ~E_2~0); 3780#L907-1 assume !(1 == ~E_3~0); 4049#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4041#L917-1 assume !(1 == ~E_5~0); 4042#L922-1 assume !(1 == ~E_6~0); 4194#L927-1 assume !(1 == ~E_7~0); 4030#L932-1 assume { :end_inline_reset_delta_events } true; 3430#L1178-2 [2024-10-31 22:18:04,320 INFO L747 eck$LassoCheckResult]: Loop: 3430#L1178-2 assume !false; 4017#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4018#L744-1 assume !false; 3891#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3892#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3465#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3674#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3776#L641 assume !(0 != eval_~tmp~0#1); 4090#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3899#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3900#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3847#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3848#L774-3 assume !(0 == ~T2_E~0); 3586#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3406#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3407#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3397#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3398#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3447#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3701#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3443#L814-3 assume !(0 == ~E_2~0); 3444#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4109#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4104#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3760#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3761#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4071#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4152#L376-27 assume 1 == ~m_pc~0; 4045#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3994#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3995#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4066#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4196#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4217#L395-27 assume 1 == ~t1_pc~0; 4213#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3762#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3763#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3959#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3854#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3855#L414-27 assume 1 == ~t2_pc~0; 4180#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4040#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4039#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3915#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3455#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3456#L433-27 assume !(1 == ~t3_pc~0); 3558#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 3861#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3862#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3632#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3633#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4208#L452-27 assume 1 == ~t4_pc~0; 4209#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4009#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3825#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3826#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4177#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3448#L471-27 assume 1 == ~t5_pc~0; 3449#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3773#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4130#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4063#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3990#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3923#L490-27 assume 1 == ~t6_pc~0; 3822#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3643#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3644#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4047#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 4048#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3415#L509-27 assume 1 == ~t7_pc~0; 3416#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3824#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3705#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3706#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3943#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3955#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3956#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3986#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4207#L867-3 assume !(1 == ~T3_E~0); 3863#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3864#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3950#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3980#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3603#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3604#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4127#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3777#L907-3 assume !(1 == ~E_3~0); 3778#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3903#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3868#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3656#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3657#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3507#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3404#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3714#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3715#L1197 assume !(0 == start_simulation_~tmp~3#1); 3836#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3566#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3530#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3423#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 3424#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4124#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3917#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3429#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 3430#L1178-2 [2024-10-31 22:18:04,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:04,321 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2024-10-31 22:18:04,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:04,322 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893669640] [2024-10-31 22:18:04,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:04,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:04,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:04,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:04,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:04,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893669640] [2024-10-31 22:18:04,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893669640] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:04,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:04,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:04,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022759868] [2024-10-31 22:18:04,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:04,374 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:04,375 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:04,375 INFO L85 PathProgramCache]: Analyzing trace with hash -268845801, now seen corresponding path program 1 times [2024-10-31 22:18:04,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:04,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368635238] [2024-10-31 22:18:04,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:04,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:04,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:04,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:04,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:04,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368635238] [2024-10-31 22:18:04,506 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368635238] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:04,506 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:04,506 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:04,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589409375] [2024-10-31 22:18:04,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:04,507 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:04,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:04,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:04,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:04,508 INFO L87 Difference]: Start difference. First operand 838 states and 1247 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:04,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:04,563 INFO L93 Difference]: Finished difference Result 838 states and 1246 transitions. [2024-10-31 22:18:04,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1246 transitions. [2024-10-31 22:18:04,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:04,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1246 transitions. [2024-10-31 22:18:04,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-10-31 22:18:04,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-10-31 22:18:04,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1246 transitions. [2024-10-31 22:18:04,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:04,576 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1246 transitions. [2024-10-31 22:18:04,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1246 transitions. [2024-10-31 22:18:04,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-10-31 22:18:04,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4868735083532219) internal successors, (1246), 837 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:04,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1246 transitions. [2024-10-31 22:18:04,591 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1246 transitions. [2024-10-31 22:18:04,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:04,593 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1246 transitions. [2024-10-31 22:18:04,593 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:18:04,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1246 transitions. [2024-10-31 22:18:04,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:04,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:04,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:04,605 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:04,605 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:04,606 INFO L745 eck$LassoCheckResult]: Stem: 5290#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5847#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5848#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5827#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 5828#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5535#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5359#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5360#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5341#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5342#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5826#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5651#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5652#L769 assume !(0 == ~M_E~0); 5671#L769-2 assume !(0 == ~T1_E~0); 5672#L774-1 assume !(0 == ~T2_E~0); 5699#L779-1 assume !(0 == ~T3_E~0); 5816#L784-1 assume !(0 == ~T4_E~0); 5649#L789-1 assume !(0 == ~T5_E~0); 5650#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5755#L799-1 assume !(0 == ~T7_E~0); 5654#L804-1 assume !(0 == ~E_M~0); 5655#L809-1 assume !(0 == ~E_1~0); 5694#L814-1 assume !(0 == ~E_2~0); 5078#L819-1 assume !(0 == ~E_3~0); 5079#L824-1 assume !(0 == ~E_4~0); 5432#L829-1 assume !(0 == ~E_5~0); 5875#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5215#L839-1 assume !(0 == ~E_7~0); 5216#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5607#L376 assume !(1 == ~m_pc~0); 5596#L376-2 is_master_triggered_~__retres1~0#1 := 0; 5595#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5801#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5156#L955 assume !(0 != activate_threads_~tmp~1#1); 5157#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5528#L395 assume 1 == ~t1_pc~0; 5192#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5193#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5108#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5109#L963 assume !(0 != activate_threads_~tmp___0~0#1); 5611#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5612#L414 assume !(1 == ~t2_pc~0); 5218#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5219#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5438#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5439#L971 assume !(0 != activate_threads_~tmp___1~0#1); 5831#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5532#L433 assume 1 == ~t3_pc~0; 5474#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5330#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5076#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5077#L979 assume !(0 != activate_threads_~tmp___2~0#1); 5181#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5182#L452 assume !(1 == ~t4_pc~0); 5337#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5338#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5175#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5176#L987 assume !(0 != activate_threads_~tmp___3~0#1); 5370#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5371#L471 assume 1 == ~t5_pc~0; 5742#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5352#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5353#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5804#L995 assume !(0 != activate_threads_~tmp___4~0#1); 5866#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5867#L490 assume 1 == ~t6_pc~0; 5852#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5610#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5425#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5426#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 5542#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5510#L509 assume !(1 == ~t7_pc~0); 5511#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5312#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5313#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5377#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5378#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5837#L857 assume !(1 == ~M_E~0); 5163#L857-2 assume !(1 == ~T1_E~0); 5164#L862-1 assume !(1 == ~T2_E~0); 5442#L867-1 assume !(1 == ~T3_E~0); 5447#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5533#L877-1 assume !(1 == ~T5_E~0); 5718#L882-1 assume !(1 == ~T6_E~0); 5851#L887-1 assume !(1 == ~T7_E~0); 5771#L892-1 assume !(1 == ~E_M~0); 5772#L897-1 assume !(1 == ~E_1~0); 5462#L902-1 assume !(1 == ~E_2~0); 5463#L907-1 assume !(1 == ~E_3~0); 5732#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5724#L917-1 assume !(1 == ~E_5~0); 5725#L922-1 assume !(1 == ~E_6~0); 5877#L927-1 assume !(1 == ~E_7~0); 5713#L932-1 assume { :end_inline_reset_delta_events } true; 5113#L1178-2 [2024-10-31 22:18:04,606 INFO L747 eck$LassoCheckResult]: Loop: 5113#L1178-2 assume !false; 5700#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5701#L744-1 assume !false; 5574#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5575#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5148#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5357#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5459#L641 assume !(0 != eval_~tmp~0#1); 5773#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5582#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5583#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5530#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5531#L774-3 assume !(0 == ~T2_E~0); 5269#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5089#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5090#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5080#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5081#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5130#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5384#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5126#L814-3 assume !(0 == ~E_2~0); 5127#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5792#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5787#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5443#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5444#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5754#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5835#L376-27 assume 1 == ~m_pc~0; 5728#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5677#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5678#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5749#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5879#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5900#L395-27 assume 1 == ~t1_pc~0; 5896#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5445#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5446#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5642#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5537#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5538#L414-27 assume 1 == ~t2_pc~0; 5863#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5723#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5722#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5598#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5138#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5139#L433-27 assume !(1 == ~t3_pc~0); 5241#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 5544#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5545#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5315#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5316#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5891#L452-27 assume 1 == ~t4_pc~0; 5892#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5692#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5508#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5509#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5860#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5131#L471-27 assume 1 == ~t5_pc~0; 5132#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5456#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5813#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5746#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5673#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5606#L490-27 assume 1 == ~t6_pc~0; 5505#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5326#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5327#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5730#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 5731#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5098#L509-27 assume 1 == ~t7_pc~0; 5099#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5507#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5388#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5389#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5626#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5638#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5639#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5669#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5890#L867-3 assume !(1 == ~T3_E~0); 5546#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5547#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5633#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5663#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5286#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5287#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5810#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5460#L907-3 assume !(1 == ~E_3~0); 5461#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5586#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5551#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5339#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5340#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5190#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5087#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5398#L1197 assume !(0 == start_simulation_~tmp~3#1); 5519#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5249#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5213#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5106#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 5107#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5807#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5600#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5112#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 5113#L1178-2 [2024-10-31 22:18:04,607 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:04,607 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2024-10-31 22:18:04,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:04,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389797187] [2024-10-31 22:18:04,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:04,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:04,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:04,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:04,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:04,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389797187] [2024-10-31 22:18:04,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1389797187] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:04,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:04,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:04,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703258378] [2024-10-31 22:18:04,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:04,691 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:04,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:04,691 INFO L85 PathProgramCache]: Analyzing trace with hash -268845801, now seen corresponding path program 2 times [2024-10-31 22:18:04,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:04,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955364310] [2024-10-31 22:18:04,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:04,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:04,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:04,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:04,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:04,779 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955364310] [2024-10-31 22:18:04,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1955364310] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:04,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:04,780 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:04,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73755666] [2024-10-31 22:18:04,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:04,780 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:04,780 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:04,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:04,781 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:04,781 INFO L87 Difference]: Start difference. First operand 838 states and 1246 transitions. cyclomatic complexity: 409 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:04,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:04,807 INFO L93 Difference]: Finished difference Result 838 states and 1245 transitions. [2024-10-31 22:18:04,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1245 transitions. [2024-10-31 22:18:04,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:04,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1245 transitions. [2024-10-31 22:18:04,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-10-31 22:18:04,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-10-31 22:18:04,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1245 transitions. [2024-10-31 22:18:04,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:04,821 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1245 transitions. [2024-10-31 22:18:04,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1245 transitions. [2024-10-31 22:18:04,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-10-31 22:18:04,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4856801909307875) internal successors, (1245), 837 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:04,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1245 transitions. [2024-10-31 22:18:04,840 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1245 transitions. [2024-10-31 22:18:04,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:04,841 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1245 transitions. [2024-10-31 22:18:04,842 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:18:04,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1245 transitions. [2024-10-31 22:18:04,847 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:04,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:04,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:04,854 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:04,854 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:04,855 INFO L745 eck$LassoCheckResult]: Stem: 6975#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 6976#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7530#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7531#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7510#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 7511#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7218#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7042#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7043#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7024#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7025#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7509#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7334#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7335#L769 assume !(0 == ~M_E~0); 7354#L769-2 assume !(0 == ~T1_E~0); 7355#L774-1 assume !(0 == ~T2_E~0); 7382#L779-1 assume !(0 == ~T3_E~0); 7499#L784-1 assume !(0 == ~T4_E~0); 7332#L789-1 assume !(0 == ~T5_E~0); 7333#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7438#L799-1 assume !(0 == ~T7_E~0); 7337#L804-1 assume !(0 == ~E_M~0); 7338#L809-1 assume !(0 == ~E_1~0); 7377#L814-1 assume !(0 == ~E_2~0); 6763#L819-1 assume !(0 == ~E_3~0); 6764#L824-1 assume !(0 == ~E_4~0); 7115#L829-1 assume !(0 == ~E_5~0); 7558#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6898#L839-1 assume !(0 == ~E_7~0); 6899#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7290#L376 assume !(1 == ~m_pc~0); 7283#L376-2 is_master_triggered_~__retres1~0#1 := 0; 7282#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7484#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6841#L955 assume !(0 != activate_threads_~tmp~1#1); 6842#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7211#L395 assume 1 == ~t1_pc~0; 6875#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6876#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6791#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6792#L963 assume !(0 != activate_threads_~tmp___0~0#1); 7295#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7296#L414 assume !(1 == ~t2_pc~0); 6901#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6902#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7121#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7122#L971 assume !(0 != activate_threads_~tmp___1~0#1); 7514#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7215#L433 assume 1 == ~t3_pc~0; 7157#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7015#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6759#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6760#L979 assume !(0 != activate_threads_~tmp___2~0#1); 6864#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6865#L452 assume !(1 == ~t4_pc~0); 7020#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7021#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6858#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6859#L987 assume !(0 != activate_threads_~tmp___3~0#1); 7053#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7054#L471 assume 1 == ~t5_pc~0; 7425#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7035#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7036#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7487#L995 assume !(0 != activate_threads_~tmp___4~0#1); 7549#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7550#L490 assume 1 == ~t6_pc~0; 7536#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7293#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7108#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7109#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 7227#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7193#L509 assume !(1 == ~t7_pc~0); 7194#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7000#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7001#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7060#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7061#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7520#L857 assume !(1 == ~M_E~0); 6846#L857-2 assume !(1 == ~T1_E~0); 6847#L862-1 assume !(1 == ~T2_E~0); 7125#L867-1 assume !(1 == ~T3_E~0); 7130#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7216#L877-1 assume !(1 == ~T5_E~0); 7401#L882-1 assume !(1 == ~T6_E~0); 7534#L887-1 assume !(1 == ~T7_E~0); 7454#L892-1 assume !(1 == ~E_M~0); 7455#L897-1 assume !(1 == ~E_1~0); 7147#L902-1 assume !(1 == ~E_2~0); 7148#L907-1 assume !(1 == ~E_3~0); 7417#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7407#L917-1 assume !(1 == ~E_5~0); 7408#L922-1 assume !(1 == ~E_6~0); 7560#L927-1 assume !(1 == ~E_7~0); 7396#L932-1 assume { :end_inline_reset_delta_events } true; 6796#L1178-2 [2024-10-31 22:18:04,855 INFO L747 eck$LassoCheckResult]: Loop: 6796#L1178-2 assume !false; 7383#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7384#L744-1 assume !false; 7257#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7258#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6831#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7040#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7144#L641 assume !(0 != eval_~tmp~0#1); 7456#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7265#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7266#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7213#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7214#L774-3 assume !(0 == ~T2_E~0); 6954#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6772#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6773#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6765#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6766#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6813#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7068#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6809#L814-3 assume !(0 == ~E_2~0); 6810#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7475#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7470#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7126#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7127#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7437#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7518#L376-27 assume 1 == ~m_pc~0; 7411#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7360#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7361#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7432#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7562#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7583#L395-27 assume !(1 == ~t1_pc~0); 7233#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7128#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7129#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7325#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7220#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7221#L414-27 assume 1 == ~t2_pc~0; 7546#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7406#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7405#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7278#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6821#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6822#L433-27 assume !(1 == ~t3_pc~0); 6924#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 7225#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7226#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6996#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6997#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7574#L452-27 assume 1 == ~t4_pc~0; 7575#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7375#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7191#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7192#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7543#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6814#L471-27 assume !(1 == ~t5_pc~0); 6816#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 7136#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7496#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7429#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7356#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7289#L490-27 assume 1 == ~t6_pc~0; 7188#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7009#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7010#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7413#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 7414#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6781#L509-27 assume 1 == ~t7_pc~0; 6782#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7190#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7071#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7072#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7309#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7321#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7322#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7352#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7573#L867-3 assume !(1 == ~T3_E~0); 7229#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7230#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7316#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7346#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6967#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6968#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7493#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7142#L907-3 assume !(1 == ~E_3~0); 7143#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7269#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7234#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7022#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7023#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6873#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6770#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7081#L1197 assume !(0 == start_simulation_~tmp~3#1); 7201#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6932#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6896#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6789#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 6790#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7490#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7280#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 6795#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 6796#L1178-2 [2024-10-31 22:18:04,855 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:04,856 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2024-10-31 22:18:04,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:04,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717773539] [2024-10-31 22:18:04,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:04,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:04,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:04,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:04,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:04,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717773539] [2024-10-31 22:18:04,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [717773539] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:04,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:04,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:04,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1971607714] [2024-10-31 22:18:04,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:04,926 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:04,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:04,927 INFO L85 PathProgramCache]: Analyzing trace with hash 177358105, now seen corresponding path program 1 times [2024-10-31 22:18:04,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:04,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109630664] [2024-10-31 22:18:04,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:04,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:04,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:05,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:05,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:05,001 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109630664] [2024-10-31 22:18:05,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109630664] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:05,001 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:05,002 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:05,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315052498] [2024-10-31 22:18:05,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:05,002 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:05,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:05,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:05,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:05,005 INFO L87 Difference]: Start difference. First operand 838 states and 1245 transitions. cyclomatic complexity: 408 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:05,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:05,046 INFO L93 Difference]: Finished difference Result 838 states and 1244 transitions. [2024-10-31 22:18:05,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1244 transitions. [2024-10-31 22:18:05,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:05,057 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1244 transitions. [2024-10-31 22:18:05,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-10-31 22:18:05,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-10-31 22:18:05,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1244 transitions. [2024-10-31 22:18:05,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:05,060 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1244 transitions. [2024-10-31 22:18:05,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1244 transitions. [2024-10-31 22:18:05,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-10-31 22:18:05,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4844868735083532) internal successors, (1244), 837 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:05,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1244 transitions. [2024-10-31 22:18:05,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1244 transitions. [2024-10-31 22:18:05,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:05,080 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1244 transitions. [2024-10-31 22:18:05,080 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:18:05,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1244 transitions. [2024-10-31 22:18:05,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:05,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:05,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:05,087 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:05,087 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:05,088 INFO L745 eck$LassoCheckResult]: Stem: 8656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9213#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9214#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9193#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 9194#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8901#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8725#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8726#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8707#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8708#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9192#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9017#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9018#L769 assume !(0 == ~M_E~0); 9037#L769-2 assume !(0 == ~T1_E~0); 9038#L774-1 assume !(0 == ~T2_E~0); 9065#L779-1 assume !(0 == ~T3_E~0); 9182#L784-1 assume !(0 == ~T4_E~0); 9015#L789-1 assume !(0 == ~T5_E~0); 9016#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9121#L799-1 assume !(0 == ~T7_E~0); 9020#L804-1 assume !(0 == ~E_M~0); 9021#L809-1 assume !(0 == ~E_1~0); 9060#L814-1 assume !(0 == ~E_2~0); 8446#L819-1 assume !(0 == ~E_3~0); 8447#L824-1 assume !(0 == ~E_4~0); 8798#L829-1 assume !(0 == ~E_5~0); 9241#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8581#L839-1 assume !(0 == ~E_7~0); 8582#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8973#L376 assume !(1 == ~m_pc~0); 8963#L376-2 is_master_triggered_~__retres1~0#1 := 0; 8962#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9167#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8524#L955 assume !(0 != activate_threads_~tmp~1#1); 8525#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8894#L395 assume 1 == ~t1_pc~0; 8558#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8559#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8474#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8475#L963 assume !(0 != activate_threads_~tmp___0~0#1); 8978#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8979#L414 assume !(1 == ~t2_pc~0); 8584#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8585#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8804#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8805#L971 assume !(0 != activate_threads_~tmp___1~0#1); 9197#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8898#L433 assume 1 == ~t3_pc~0; 8840#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8698#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8442#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8443#L979 assume !(0 != activate_threads_~tmp___2~0#1); 8547#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8548#L452 assume !(1 == ~t4_pc~0); 8703#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8704#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8541#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8542#L987 assume !(0 != activate_threads_~tmp___3~0#1); 8736#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8737#L471 assume 1 == ~t5_pc~0; 9108#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8718#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8719#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9170#L995 assume !(0 != activate_threads_~tmp___4~0#1); 9232#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9233#L490 assume 1 == ~t6_pc~0; 9219#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8976#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8791#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8792#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 8908#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8876#L509 assume !(1 == ~t7_pc~0); 8877#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8680#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8681#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8743#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8744#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9203#L857 assume !(1 == ~M_E~0); 8529#L857-2 assume !(1 == ~T1_E~0); 8530#L862-1 assume !(1 == ~T2_E~0); 8808#L867-1 assume !(1 == ~T3_E~0); 8813#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8899#L877-1 assume !(1 == ~T5_E~0); 9084#L882-1 assume !(1 == ~T6_E~0); 9217#L887-1 assume !(1 == ~T7_E~0); 9137#L892-1 assume !(1 == ~E_M~0); 9138#L897-1 assume !(1 == ~E_1~0); 8830#L902-1 assume !(1 == ~E_2~0); 8831#L907-1 assume !(1 == ~E_3~0); 9100#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9090#L917-1 assume !(1 == ~E_5~0); 9091#L922-1 assume !(1 == ~E_6~0); 9243#L927-1 assume !(1 == ~E_7~0); 9079#L932-1 assume { :end_inline_reset_delta_events } true; 8479#L1178-2 [2024-10-31 22:18:05,088 INFO L747 eck$LassoCheckResult]: Loop: 8479#L1178-2 assume !false; 9066#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9067#L744-1 assume !false; 8940#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8941#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8514#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8723#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8827#L641 assume !(0 != eval_~tmp~0#1); 9139#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8948#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8949#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8896#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8897#L774-3 assume !(0 == ~T2_E~0); 8635#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8455#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8456#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8448#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8449#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8496#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8751#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8494#L814-3 assume !(0 == ~E_2~0); 8495#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9158#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9153#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8809#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8810#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9120#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9201#L376-27 assume 1 == ~m_pc~0; 9094#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9043#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9044#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9115#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9245#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9266#L395-27 assume !(1 == ~t1_pc~0); 8917#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 8811#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8812#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9008#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8903#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8904#L414-27 assume 1 == ~t2_pc~0; 9229#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9089#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9088#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8965#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8504#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8505#L433-27 assume 1 == ~t3_pc~0; 8608#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8910#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8911#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8683#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8684#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9257#L452-27 assume !(1 == ~t4_pc~0); 9057#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 9058#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8874#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8875#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9226#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8497#L471-27 assume 1 == ~t5_pc~0; 8498#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8817#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9179#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9112#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9039#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8972#L490-27 assume 1 == ~t6_pc~0; 8871#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8692#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8693#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9096#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 9097#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8464#L509-27 assume 1 == ~t7_pc~0; 8465#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8873#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8754#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8755#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8991#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9004#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9005#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9033#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9256#L867-3 assume !(1 == ~T3_E~0); 8912#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8913#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8999#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9029#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8650#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8651#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9176#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8825#L907-3 assume !(1 == ~E_3~0); 8826#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8952#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8916#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8705#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8706#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8556#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8451#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8763#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8764#L1197 assume !(0 == start_simulation_~tmp~3#1); 8883#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8612#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8579#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8472#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 8473#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9173#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8960#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8478#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 8479#L1178-2 [2024-10-31 22:18:05,089 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:05,089 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2024-10-31 22:18:05,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:05,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256070278] [2024-10-31 22:18:05,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:05,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:05,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:05,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:05,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:05,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256070278] [2024-10-31 22:18:05,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1256070278] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:05,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:05,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:05,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832892] [2024-10-31 22:18:05,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:05,149 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:05,149 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:05,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1466614696, now seen corresponding path program 1 times [2024-10-31 22:18:05,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:05,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708426790] [2024-10-31 22:18:05,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:05,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:05,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:05,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:05,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:05,220 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [708426790] [2024-10-31 22:18:05,220 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [708426790] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:05,220 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:05,220 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:05,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515200497] [2024-10-31 22:18:05,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:05,221 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:05,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:05,222 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:05,222 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:05,222 INFO L87 Difference]: Start difference. First operand 838 states and 1244 transitions. cyclomatic complexity: 407 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:05,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:05,244 INFO L93 Difference]: Finished difference Result 838 states and 1243 transitions. [2024-10-31 22:18:05,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1243 transitions. [2024-10-31 22:18:05,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:05,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1243 transitions. [2024-10-31 22:18:05,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-10-31 22:18:05,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-10-31 22:18:05,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1243 transitions. [2024-10-31 22:18:05,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:05,256 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1243 transitions. [2024-10-31 22:18:05,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1243 transitions. [2024-10-31 22:18:05,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-10-31 22:18:05,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4832935560859188) internal successors, (1243), 837 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:05,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1243 transitions. [2024-10-31 22:18:05,272 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1243 transitions. [2024-10-31 22:18:05,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:05,273 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1243 transitions. [2024-10-31 22:18:05,273 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:18:05,273 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1243 transitions. [2024-10-31 22:18:05,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:05,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:05,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:05,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:05,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:05,280 INFO L745 eck$LassoCheckResult]: Stem: 10339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10896#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10897#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10876#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 10877#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10584#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10408#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10409#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10390#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10391#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10875#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10700#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10701#L769 assume !(0 == ~M_E~0); 10720#L769-2 assume !(0 == ~T1_E~0); 10721#L774-1 assume !(0 == ~T2_E~0); 10748#L779-1 assume !(0 == ~T3_E~0); 10865#L784-1 assume !(0 == ~T4_E~0); 10698#L789-1 assume !(0 == ~T5_E~0); 10699#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10804#L799-1 assume !(0 == ~T7_E~0); 10703#L804-1 assume !(0 == ~E_M~0); 10704#L809-1 assume !(0 == ~E_1~0); 10743#L814-1 assume !(0 == ~E_2~0); 10127#L819-1 assume !(0 == ~E_3~0); 10128#L824-1 assume !(0 == ~E_4~0); 10481#L829-1 assume !(0 == ~E_5~0); 10924#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10264#L839-1 assume !(0 == ~E_7~0); 10265#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10656#L376 assume !(1 == ~m_pc~0); 10645#L376-2 is_master_triggered_~__retres1~0#1 := 0; 10644#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10850#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10205#L955 assume !(0 != activate_threads_~tmp~1#1); 10206#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10577#L395 assume 1 == ~t1_pc~0; 10241#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10242#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10158#L963 assume !(0 != activate_threads_~tmp___0~0#1); 10660#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10661#L414 assume !(1 == ~t2_pc~0); 10267#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10268#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10487#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10488#L971 assume !(0 != activate_threads_~tmp___1~0#1); 10880#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10581#L433 assume 1 == ~t3_pc~0; 10523#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10379#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10126#L979 assume !(0 != activate_threads_~tmp___2~0#1); 10230#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10231#L452 assume !(1 == ~t4_pc~0); 10386#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10387#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10224#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10225#L987 assume !(0 != activate_threads_~tmp___3~0#1); 10419#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10420#L471 assume 1 == ~t5_pc~0; 10791#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10401#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10402#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10853#L995 assume !(0 != activate_threads_~tmp___4~0#1); 10915#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10916#L490 assume 1 == ~t6_pc~0; 10901#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10659#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10474#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10475#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 10591#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10559#L509 assume !(1 == ~t7_pc~0); 10560#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10361#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10362#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10426#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10427#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10886#L857 assume !(1 == ~M_E~0); 10212#L857-2 assume !(1 == ~T1_E~0); 10213#L862-1 assume !(1 == ~T2_E~0); 10491#L867-1 assume !(1 == ~T3_E~0); 10496#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10582#L877-1 assume !(1 == ~T5_E~0); 10767#L882-1 assume !(1 == ~T6_E~0); 10900#L887-1 assume !(1 == ~T7_E~0); 10820#L892-1 assume !(1 == ~E_M~0); 10821#L897-1 assume !(1 == ~E_1~0); 10511#L902-1 assume !(1 == ~E_2~0); 10512#L907-1 assume !(1 == ~E_3~0); 10781#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10773#L917-1 assume !(1 == ~E_5~0); 10774#L922-1 assume !(1 == ~E_6~0); 10926#L927-1 assume !(1 == ~E_7~0); 10762#L932-1 assume { :end_inline_reset_delta_events } true; 10162#L1178-2 [2024-10-31 22:18:05,280 INFO L747 eck$LassoCheckResult]: Loop: 10162#L1178-2 assume !false; 10749#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10750#L744-1 assume !false; 10623#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10624#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10197#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10406#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10508#L641 assume !(0 != eval_~tmp~0#1); 10822#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10631#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10632#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10579#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10580#L774-3 assume !(0 == ~T2_E~0); 10318#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10138#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10139#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10129#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10130#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10179#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10433#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10175#L814-3 assume !(0 == ~E_2~0); 10176#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10841#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10836#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10492#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10493#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10803#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10884#L376-27 assume 1 == ~m_pc~0; 10777#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10726#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10727#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10798#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10928#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10949#L395-27 assume 1 == ~t1_pc~0; 10945#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10494#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10495#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10691#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10586#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10587#L414-27 assume 1 == ~t2_pc~0; 10912#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10772#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10771#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10647#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10187#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10188#L433-27 assume !(1 == ~t3_pc~0); 10290#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10593#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10594#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10364#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10365#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10940#L452-27 assume !(1 == ~t4_pc~0); 10740#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 10741#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10557#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10558#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10909#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10180#L471-27 assume 1 == ~t5_pc~0; 10181#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10505#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10862#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10795#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10722#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10655#L490-27 assume 1 == ~t6_pc~0; 10554#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10375#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10376#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10779#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 10780#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10147#L509-27 assume 1 == ~t7_pc~0; 10148#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10556#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10437#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10438#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10675#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10687#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10688#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10718#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10939#L867-3 assume !(1 == ~T3_E~0); 10595#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10596#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10682#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10712#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10335#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10336#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10859#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10509#L907-3 assume !(1 == ~E_3~0); 10510#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10635#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10600#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10388#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10389#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10239#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10136#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10446#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10447#L1197 assume !(0 == start_simulation_~tmp~3#1); 10568#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10298#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10262#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 10156#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10856#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10649#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10161#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 10162#L1178-2 [2024-10-31 22:18:05,281 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:05,281 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2024-10-31 22:18:05,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:05,281 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115357584] [2024-10-31 22:18:05,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:05,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:05,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:05,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:05,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:05,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115357584] [2024-10-31 22:18:05,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115357584] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:05,322 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:05,322 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:05,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039935984] [2024-10-31 22:18:05,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:05,323 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:05,323 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:05,323 INFO L85 PathProgramCache]: Analyzing trace with hash -542624296, now seen corresponding path program 2 times [2024-10-31 22:18:05,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:05,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486113206] [2024-10-31 22:18:05,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:05,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:05,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:05,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:05,380 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:05,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486113206] [2024-10-31 22:18:05,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486113206] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:05,381 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:05,381 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:05,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451051832] [2024-10-31 22:18:05,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:05,382 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:05,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:05,382 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:05,382 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:05,382 INFO L87 Difference]: Start difference. First operand 838 states and 1243 transitions. cyclomatic complexity: 406 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:05,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:05,437 INFO L93 Difference]: Finished difference Result 838 states and 1242 transitions. [2024-10-31 22:18:05,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 838 states and 1242 transitions. [2024-10-31 22:18:05,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:05,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 838 states to 838 states and 1242 transitions. [2024-10-31 22:18:05,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 838 [2024-10-31 22:18:05,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 838 [2024-10-31 22:18:05,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 838 states and 1242 transitions. [2024-10-31 22:18:05,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:05,453 INFO L218 hiAutomatonCegarLoop]: Abstraction has 838 states and 1242 transitions. [2024-10-31 22:18:05,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 838 states and 1242 transitions. [2024-10-31 22:18:05,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 838 to 838. [2024-10-31 22:18:05,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 838 states, 838 states have (on average 1.4821002386634845) internal successors, (1242), 837 states have internal predecessors, (1242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:05,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 1242 transitions. [2024-10-31 22:18:05,473 INFO L240 hiAutomatonCegarLoop]: Abstraction has 838 states and 1242 transitions. [2024-10-31 22:18:05,474 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:05,474 INFO L425 stractBuchiCegarLoop]: Abstraction has 838 states and 1242 transitions. [2024-10-31 22:18:05,474 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:18:05,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 838 states and 1242 transitions. [2024-10-31 22:18:05,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 735 [2024-10-31 22:18:05,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:05,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:05,483 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:05,483 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:05,484 INFO L745 eck$LassoCheckResult]: Stem: 12022#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12559#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 12560#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12267#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12091#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12092#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12073#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12074#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12558#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12383#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12384#L769 assume !(0 == ~M_E~0); 12403#L769-2 assume !(0 == ~T1_E~0); 12404#L774-1 assume !(0 == ~T2_E~0); 12431#L779-1 assume !(0 == ~T3_E~0); 12548#L784-1 assume !(0 == ~T4_E~0); 12381#L789-1 assume !(0 == ~T5_E~0); 12382#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12487#L799-1 assume !(0 == ~T7_E~0); 12386#L804-1 assume !(0 == ~E_M~0); 12387#L809-1 assume !(0 == ~E_1~0); 12426#L814-1 assume !(0 == ~E_2~0); 11810#L819-1 assume !(0 == ~E_3~0); 11811#L824-1 assume !(0 == ~E_4~0); 12164#L829-1 assume !(0 == ~E_5~0); 12607#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11947#L839-1 assume !(0 == ~E_7~0); 11948#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12339#L376 assume !(1 == ~m_pc~0); 12328#L376-2 is_master_triggered_~__retres1~0#1 := 0; 12327#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12533#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11888#L955 assume !(0 != activate_threads_~tmp~1#1); 11889#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12260#L395 assume 1 == ~t1_pc~0; 11924#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11925#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11841#L963 assume !(0 != activate_threads_~tmp___0~0#1); 12343#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12344#L414 assume !(1 == ~t2_pc~0); 11950#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11951#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12170#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12171#L971 assume !(0 != activate_threads_~tmp___1~0#1); 12563#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12264#L433 assume 1 == ~t3_pc~0; 12206#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12062#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11808#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11809#L979 assume !(0 != activate_threads_~tmp___2~0#1); 11913#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11914#L452 assume !(1 == ~t4_pc~0); 12069#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12070#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11907#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11908#L987 assume !(0 != activate_threads_~tmp___3~0#1); 12102#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12103#L471 assume 1 == ~t5_pc~0; 12474#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12084#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12085#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12536#L995 assume !(0 != activate_threads_~tmp___4~0#1); 12598#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12599#L490 assume 1 == ~t6_pc~0; 12584#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12342#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12157#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12158#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 12274#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12242#L509 assume !(1 == ~t7_pc~0); 12243#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12044#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12045#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12109#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12110#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12569#L857 assume !(1 == ~M_E~0); 11895#L857-2 assume !(1 == ~T1_E~0); 11896#L862-1 assume !(1 == ~T2_E~0); 12174#L867-1 assume !(1 == ~T3_E~0); 12179#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12265#L877-1 assume !(1 == ~T5_E~0); 12450#L882-1 assume !(1 == ~T6_E~0); 12583#L887-1 assume !(1 == ~T7_E~0); 12503#L892-1 assume !(1 == ~E_M~0); 12504#L897-1 assume !(1 == ~E_1~0); 12194#L902-1 assume !(1 == ~E_2~0); 12195#L907-1 assume !(1 == ~E_3~0); 12464#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12456#L917-1 assume !(1 == ~E_5~0); 12457#L922-1 assume !(1 == ~E_6~0); 12609#L927-1 assume !(1 == ~E_7~0); 12445#L932-1 assume { :end_inline_reset_delta_events } true; 11845#L1178-2 [2024-10-31 22:18:05,484 INFO L747 eck$LassoCheckResult]: Loop: 11845#L1178-2 assume !false; 12432#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12433#L744-1 assume !false; 12306#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12307#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11880#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12089#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12191#L641 assume !(0 != eval_~tmp~0#1); 12505#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12314#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12315#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12262#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12263#L774-3 assume !(0 == ~T2_E~0); 12001#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11821#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11822#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11812#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11813#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11862#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12116#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11858#L814-3 assume !(0 == ~E_2~0); 11859#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12524#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12519#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12175#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12176#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12486#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12567#L376-27 assume 1 == ~m_pc~0; 12460#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12409#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12410#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12481#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12611#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12632#L395-27 assume 1 == ~t1_pc~0; 12628#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12177#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12178#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12374#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12269#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12270#L414-27 assume 1 == ~t2_pc~0; 12595#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12455#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12454#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12330#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11870#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11871#L433-27 assume !(1 == ~t3_pc~0); 11973#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 12276#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12277#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12047#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12048#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12623#L452-27 assume 1 == ~t4_pc~0; 12624#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12424#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12240#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12241#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12592#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11863#L471-27 assume 1 == ~t5_pc~0; 11864#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12188#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12545#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12478#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12405#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12338#L490-27 assume 1 == ~t6_pc~0; 12237#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12058#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12059#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12462#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 12463#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11830#L509-27 assume 1 == ~t7_pc~0; 11831#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12239#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12120#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12121#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12358#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12370#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12371#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12401#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12622#L867-3 assume !(1 == ~T3_E~0); 12278#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12279#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12365#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12395#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12018#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12019#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12542#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12192#L907-3 assume !(1 == ~E_3~0); 12193#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12318#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12283#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12071#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12072#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11922#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11819#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12129#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12130#L1197 assume !(0 == start_simulation_~tmp~3#1); 12251#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11981#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11945#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11838#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 11839#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12539#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12332#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11844#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 11845#L1178-2 [2024-10-31 22:18:05,485 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:05,485 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2024-10-31 22:18:05,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:05,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058627426] [2024-10-31 22:18:05,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:05,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:05,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:05,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:05,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:05,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058627426] [2024-10-31 22:18:05,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058627426] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:05,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:05,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:05,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055210049] [2024-10-31 22:18:05,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:05,607 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:05,607 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:05,611 INFO L85 PathProgramCache]: Analyzing trace with hash -268845801, now seen corresponding path program 3 times [2024-10-31 22:18:05,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:05,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144784838] [2024-10-31 22:18:05,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:05,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:05,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:05,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:05,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:05,699 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144784838] [2024-10-31 22:18:05,699 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144784838] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:05,699 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:05,699 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:05,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485792334] [2024-10-31 22:18:05,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:05,700 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:05,700 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:05,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:05,700 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:05,701 INFO L87 Difference]: Start difference. First operand 838 states and 1242 transitions. cyclomatic complexity: 405 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:05,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:05,891 INFO L93 Difference]: Finished difference Result 1515 states and 2236 transitions. [2024-10-31 22:18:05,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1515 states and 2236 transitions. [2024-10-31 22:18:05,905 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2024-10-31 22:18:05,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1515 states to 1515 states and 2236 transitions. [2024-10-31 22:18:05,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1515 [2024-10-31 22:18:05,916 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1515 [2024-10-31 22:18:05,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1515 states and 2236 transitions. [2024-10-31 22:18:05,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:05,919 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1515 states and 2236 transitions. [2024-10-31 22:18:05,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1515 states and 2236 transitions. [2024-10-31 22:18:05,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1515 to 1515. [2024-10-31 22:18:05,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1515 states, 1515 states have (on average 1.475907590759076) internal successors, (2236), 1514 states have internal predecessors, (2236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:05,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1515 states to 1515 states and 2236 transitions. [2024-10-31 22:18:05,961 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1515 states and 2236 transitions. [2024-10-31 22:18:05,965 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:05,965 INFO L425 stractBuchiCegarLoop]: Abstraction has 1515 states and 2236 transitions. [2024-10-31 22:18:05,966 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:18:05,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1515 states and 2236 transitions. [2024-10-31 22:18:05,980 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2024-10-31 22:18:05,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:05,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:05,982 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:05,982 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:05,982 INFO L745 eck$LassoCheckResult]: Stem: 14385#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14948#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 14949#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14635#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14455#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14456#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14436#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14437#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14947#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14758#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14759#L769 assume !(0 == ~M_E~0); 14779#L769-2 assume !(0 == ~T1_E~0); 14780#L774-1 assume !(0 == ~T2_E~0); 14809#L779-1 assume !(0 == ~T3_E~0); 14936#L784-1 assume !(0 == ~T4_E~0); 14756#L789-1 assume !(0 == ~T5_E~0); 14757#L794-1 assume !(0 == ~T6_E~0); 14869#L799-1 assume !(0 == ~T7_E~0); 14761#L804-1 assume !(0 == ~E_M~0); 14762#L809-1 assume !(0 == ~E_1~0); 14803#L814-1 assume !(0 == ~E_2~0); 14173#L819-1 assume !(0 == ~E_3~0); 14174#L824-1 assume !(0 == ~E_4~0); 14530#L829-1 assume !(0 == ~E_5~0); 15008#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14310#L839-1 assume !(0 == ~E_7~0); 14311#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14709#L376 assume !(1 == ~m_pc~0); 14696#L376-2 is_master_triggered_~__retres1~0#1 := 0; 14695#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14916#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14251#L955 assume !(0 != activate_threads_~tmp~1#1); 14252#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14628#L395 assume 1 == ~t1_pc~0; 14287#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14288#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14204#L963 assume !(0 != activate_threads_~tmp___0~0#1); 14713#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14714#L414 assume !(1 == ~t2_pc~0); 14313#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14314#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14536#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14537#L971 assume !(0 != activate_threads_~tmp___1~0#1); 14953#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14632#L433 assume 1 == ~t3_pc~0; 14573#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14425#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14171#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14172#L979 assume !(0 != activate_threads_~tmp___2~0#1); 14276#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14277#L452 assume !(1 == ~t4_pc~0); 14432#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14433#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14270#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14271#L987 assume !(0 != activate_threads_~tmp___3~0#1); 14466#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14467#L471 assume 1 == ~t5_pc~0; 14856#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14447#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14448#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14920#L995 assume !(0 != activate_threads_~tmp___4~0#1); 14999#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15000#L490 assume 1 == ~t6_pc~0; 14979#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14712#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14523#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14524#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 14642#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14610#L509 assume !(1 == ~t7_pc~0); 14611#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14407#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14408#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14473#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14474#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14959#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 14258#L857-2 assume !(1 == ~T1_E~0); 14259#L862-1 assume !(1 == ~T2_E~0); 14540#L867-1 assume !(1 == ~T3_E~0); 14545#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14633#L877-1 assume !(1 == ~T5_E~0); 14831#L882-1 assume !(1 == ~T6_E~0); 14978#L887-1 assume !(1 == ~T7_E~0); 15159#L892-1 assume !(1 == ~E_M~0); 15157#L897-1 assume !(1 == ~E_1~0); 15155#L902-1 assume !(1 == ~E_2~0); 15153#L907-1 assume !(1 == ~E_3~0); 14845#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14846#L917-1 assume !(1 == ~E_5~0); 15076#L922-1 assume !(1 == ~E_6~0); 15072#L927-1 assume !(1 == ~E_7~0); 14826#L932-1 assume { :end_inline_reset_delta_events } true; 14208#L1178-2 [2024-10-31 22:18:05,983 INFO L747 eck$LassoCheckResult]: Loop: 14208#L1178-2 assume !false; 14810#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14811#L744-1 assume !false; 14674#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14675#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14243#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14453#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14558#L641 assume !(0 != eval_~tmp~0#1); 14887#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14682#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14683#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14630#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14631#L774-3 assume !(0 == ~T2_E~0); 14364#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14184#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14185#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14175#L794-3 assume !(0 == ~T6_E~0); 14176#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14225#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14480#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14221#L814-3 assume !(0 == ~E_2~0); 14222#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14907#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14902#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14541#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14542#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14868#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14957#L376-27 assume 1 == ~m_pc~0; 14841#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14785#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14786#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14863#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15012#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15040#L395-27 assume 1 == ~t1_pc~0; 15032#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14543#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14544#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14749#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14637#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14638#L414-27 assume 1 == ~t2_pc~0; 14992#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14836#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14835#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14698#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14233#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14234#L433-27 assume !(1 == ~t3_pc~0); 14336#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 14644#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14645#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14410#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14411#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15026#L452-27 assume !(1 == ~t4_pc~0); 14800#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 14801#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14608#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14609#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14989#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14997#L471-27 assume !(1 == ~t5_pc~0); 15146#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15145#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15144#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15143#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15142#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15141#L490-27 assume 1 == ~t6_pc~0; 15139#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15138#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15134#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15132#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 15130#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15129#L509-27 assume 1 == ~t7_pc~0; 14739#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14607#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14484#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14485#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14729#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15037#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14745#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14777#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15024#L867-3 assume !(1 == ~T3_E~0); 14646#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14647#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14738#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14771#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14381#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14382#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14927#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14559#L907-3 assume !(1 == ~E_3~0); 14560#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14686#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14951#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15099#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15098#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15097#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15088#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15086#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 15085#L1197 assume !(0 == start_simulation_~tmp~3#1); 15031#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15084#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15068#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15067#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 15066#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15065#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14700#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 14207#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 14208#L1178-2 [2024-10-31 22:18:05,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:05,984 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2024-10-31 22:18:05,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:05,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798232097] [2024-10-31 22:18:05,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:05,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:06,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:06,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:06,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:06,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798232097] [2024-10-31 22:18:06,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1798232097] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:06,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:06,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:06,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406651973] [2024-10-31 22:18:06,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:06,148 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:06,149 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:06,149 INFO L85 PathProgramCache]: Analyzing trace with hash 864207127, now seen corresponding path program 1 times [2024-10-31 22:18:06,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:06,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402163572] [2024-10-31 22:18:06,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:06,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:06,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:06,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:06,217 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:06,217 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402163572] [2024-10-31 22:18:06,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [402163572] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:06,218 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:06,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:06,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259376764] [2024-10-31 22:18:06,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:06,218 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:06,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:06,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:06,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:06,219 INFO L87 Difference]: Start difference. First operand 1515 states and 2236 transitions. cyclomatic complexity: 723 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:06,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:06,445 INFO L93 Difference]: Finished difference Result 2735 states and 4023 transitions. [2024-10-31 22:18:06,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2735 states and 4023 transitions. [2024-10-31 22:18:06,467 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2602 [2024-10-31 22:18:06,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2735 states to 2735 states and 4023 transitions. [2024-10-31 22:18:06,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2735 [2024-10-31 22:18:06,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2735 [2024-10-31 22:18:06,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2735 states and 4023 transitions. [2024-10-31 22:18:06,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:06,490 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2735 states and 4023 transitions. [2024-10-31 22:18:06,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2735 states and 4023 transitions. [2024-10-31 22:18:06,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2735 to 2733. [2024-10-31 22:18:06,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2733 states, 2733 states have (on average 1.4712769849981706) internal successors, (4021), 2732 states have internal predecessors, (4021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:06,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2733 states to 2733 states and 4021 transitions. [2024-10-31 22:18:06,545 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2733 states and 4021 transitions. [2024-10-31 22:18:06,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:06,547 INFO L425 stractBuchiCegarLoop]: Abstraction has 2733 states and 4021 transitions. [2024-10-31 22:18:06,547 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:18:06,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2733 states and 4021 transitions. [2024-10-31 22:18:06,565 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2602 [2024-10-31 22:18:06,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:06,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:06,567 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:06,567 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:06,567 INFO L745 eck$LassoCheckResult]: Stem: 18647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19216#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19217#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19194#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 19195#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18893#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18714#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18715#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18696#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18697#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19193#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19012#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19013#L769 assume !(0 == ~M_E~0); 19032#L769-2 assume !(0 == ~T1_E~0); 19033#L774-1 assume !(0 == ~T2_E~0); 19060#L779-1 assume !(0 == ~T3_E~0); 19181#L784-1 assume !(0 == ~T4_E~0); 19010#L789-1 assume !(0 == ~T5_E~0); 19011#L794-1 assume !(0 == ~T6_E~0); 19117#L799-1 assume !(0 == ~T7_E~0); 19015#L804-1 assume !(0 == ~E_M~0); 19016#L809-1 assume !(0 == ~E_1~0); 19055#L814-1 assume !(0 == ~E_2~0); 18435#L819-1 assume !(0 == ~E_3~0); 18436#L824-1 assume !(0 == ~E_4~0); 18789#L829-1 assume !(0 == ~E_5~0); 19245#L834-1 assume !(0 == ~E_6~0); 18570#L839-1 assume !(0 == ~E_7~0); 18571#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18966#L376 assume !(1 == ~m_pc~0); 18959#L376-2 is_master_triggered_~__retres1~0#1 := 0; 18958#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19165#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18513#L955 assume !(0 != activate_threads_~tmp~1#1); 18514#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18886#L395 assume 1 == ~t1_pc~0; 18547#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18548#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18463#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18464#L963 assume !(0 != activate_threads_~tmp___0~0#1); 18971#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18972#L414 assume !(1 == ~t2_pc~0); 18573#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18574#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18796#L971 assume !(0 != activate_threads_~tmp___1~0#1); 19198#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18890#L433 assume 1 == ~t3_pc~0; 18832#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18687#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18431#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18432#L979 assume !(0 != activate_threads_~tmp___2~0#1); 18536#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18537#L452 assume !(1 == ~t4_pc~0); 18692#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18693#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18530#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18531#L987 assume !(0 != activate_threads_~tmp___3~0#1); 18725#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18726#L471 assume 1 == ~t5_pc~0; 19103#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18707#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18708#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19168#L995 assume !(0 != activate_threads_~tmp___4~0#1); 19236#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19237#L490 assume 1 == ~t6_pc~0; 19222#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18969#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18782#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18783#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 18902#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18868#L509 assume !(1 == ~t7_pc~0); 18869#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18672#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18673#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18732#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18733#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19204#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 19205#L857-2 assume !(1 == ~T1_E~0); 19402#L862-1 assume !(1 == ~T2_E~0); 18804#L867-1 assume !(1 == ~T3_E~0); 18805#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18891#L877-1 assume !(1 == ~T5_E~0); 19079#L882-1 assume !(1 == ~T6_E~0); 19220#L887-1 assume !(1 == ~T7_E~0); 19133#L892-1 assume !(1 == ~E_M~0); 19134#L897-1 assume !(1 == ~E_1~0); 19352#L902-1 assume !(1 == ~E_2~0); 19350#L907-1 assume !(1 == ~E_3~0); 19095#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19085#L917-1 assume !(1 == ~E_5~0); 19086#L922-1 assume !(1 == ~E_6~0); 19322#L927-1 assume !(1 == ~E_7~0); 19314#L932-1 assume { :end_inline_reset_delta_events } true; 19308#L1178-2 [2024-10-31 22:18:06,568 INFO L747 eck$LassoCheckResult]: Loop: 19308#L1178-2 assume !false; 19304#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19303#L744-1 assume !false; 19302#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19301#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19293#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19292#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19290#L641 assume !(0 != eval_~tmp~0#1); 19289#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19288#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19286#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19287#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20481#L774-3 assume !(0 == ~T2_E~0); 20156#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20147#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20145#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20143#L794-3 assume !(0 == ~T6_E~0); 20141#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20139#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20137#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20135#L814-3 assume !(0 == ~E_2~0); 20116#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20113#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20110#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20106#L834-3 assume !(0 == ~E_6~0); 20103#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20100#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20097#L376-27 assume 1 == ~m_pc~0; 20073#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20069#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20065#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20049#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20044#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20038#L395-27 assume !(1 == ~t1_pc~0); 20030#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 20025#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20021#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20016#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20012#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20006#L414-27 assume 1 == ~t2_pc~0; 19998#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19993#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19988#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19981#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19976#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19971#L433-27 assume !(1 == ~t3_pc~0); 19963#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 19958#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19953#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19946#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19941#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19937#L452-27 assume 1 == ~t4_pc~0; 19930#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19851#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19849#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19847#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19844#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19842#L471-27 assume 1 == ~t5_pc~0; 19840#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19837#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19767#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19765#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19763#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19761#L490-27 assume 1 == ~t6_pc~0; 19758#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19756#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19753#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19752#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 19722#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19721#L509-27 assume 1 == ~t7_pc~0; 19719#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19716#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19714#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19712#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19710#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19708#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18998#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19705#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19703#L867-3 assume !(1 == ~T3_E~0); 19701#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19685#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19641#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19638#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19636#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19635#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19634#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19633#L907-3 assume !(1 == ~E_3~0); 19631#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19628#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19604#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19599#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19594#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19586#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19575#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19572#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 19571#L1197 assume !(0 == start_simulation_~tmp~3#1); 19278#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19370#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19360#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 19336#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19332#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19323#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19315#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 19308#L1178-2 [2024-10-31 22:18:06,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:06,569 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2024-10-31 22:18:06,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:06,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [875980368] [2024-10-31 22:18:06,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:06,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:06,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:06,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:06,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:06,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [875980368] [2024-10-31 22:18:06,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [875980368] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:06,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:06,653 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:06,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576260642] [2024-10-31 22:18:06,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:06,654 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:06,657 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:06,658 INFO L85 PathProgramCache]: Analyzing trace with hash -66395884, now seen corresponding path program 1 times [2024-10-31 22:18:06,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:06,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312058451] [2024-10-31 22:18:06,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:06,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:06,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:06,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:06,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:06,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312058451] [2024-10-31 22:18:06,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312058451] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:06,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:06,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:06,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172060125] [2024-10-31 22:18:06,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:06,718 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:06,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:06,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:06,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:06,720 INFO L87 Difference]: Start difference. First operand 2733 states and 4021 transitions. cyclomatic complexity: 1292 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:06,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:06,923 INFO L93 Difference]: Finished difference Result 5067 states and 7400 transitions. [2024-10-31 22:18:06,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5067 states and 7400 transitions. [2024-10-31 22:18:06,991 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4929 [2024-10-31 22:18:07,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5067 states to 5067 states and 7400 transitions. [2024-10-31 22:18:07,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5067 [2024-10-31 22:18:07,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5067 [2024-10-31 22:18:07,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5067 states and 7400 transitions. [2024-10-31 22:18:07,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:07,031 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5067 states and 7400 transitions. [2024-10-31 22:18:07,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5067 states and 7400 transitions. [2024-10-31 22:18:07,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5067 to 5059. [2024-10-31 22:18:07,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5059 states, 5059 states have (on average 1.4611583316861039) internal successors, (7392), 5058 states have internal predecessors, (7392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:07,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5059 states to 5059 states and 7392 transitions. [2024-10-31 22:18:07,154 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5059 states and 7392 transitions. [2024-10-31 22:18:07,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:07,155 INFO L425 stractBuchiCegarLoop]: Abstraction has 5059 states and 7392 transitions. [2024-10-31 22:18:07,155 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:18:07,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5059 states and 7392 transitions. [2024-10-31 22:18:07,177 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4921 [2024-10-31 22:18:07,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:07,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:07,179 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:07,179 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:07,179 INFO L745 eck$LassoCheckResult]: Stem: 26452#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26453#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 27094#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27095#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27063#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 27064#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26708#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26527#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26528#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26507#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26508#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27060#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26841#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26842#L769 assume !(0 == ~M_E~0); 26862#L769-2 assume !(0 == ~T1_E~0); 26863#L774-1 assume !(0 == ~T2_E~0); 26898#L779-1 assume !(0 == ~T3_E~0); 27047#L784-1 assume !(0 == ~T4_E~0); 26839#L789-1 assume !(0 == ~T5_E~0); 26840#L794-1 assume !(0 == ~T6_E~0); 26965#L799-1 assume !(0 == ~T7_E~0); 26844#L804-1 assume !(0 == ~E_M~0); 26845#L809-1 assume !(0 == ~E_1~0); 26890#L814-1 assume !(0 == ~E_2~0); 26242#L819-1 assume !(0 == ~E_3~0); 26243#L824-1 assume !(0 == ~E_4~0); 26600#L829-1 assume !(0 == ~E_5~0); 27144#L834-1 assume !(0 == ~E_6~0); 26376#L839-1 assume !(0 == ~E_7~0); 26377#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26791#L376 assume !(1 == ~m_pc~0); 26779#L376-2 is_master_triggered_~__retres1~0#1 := 0; 26778#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27024#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26319#L955 assume !(0 != activate_threads_~tmp~1#1); 26320#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26701#L395 assume !(1 == ~t1_pc~0); 26864#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27026#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26270#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26271#L963 assume !(0 != activate_threads_~tmp___0~0#1); 26796#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26797#L414 assume !(1 == ~t2_pc~0); 26379#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26380#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26608#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26609#L971 assume !(0 != activate_threads_~tmp___1~0#1); 27070#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26705#L433 assume 1 == ~t3_pc~0; 26645#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26498#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26238#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26239#L979 assume !(0 != activate_threads_~tmp___2~0#1); 26343#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26344#L452 assume !(1 == ~t4_pc~0); 26503#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26504#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26337#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26338#L987 assume !(0 != activate_threads_~tmp___3~0#1); 26538#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26539#L471 assume 1 == ~t5_pc~0; 26947#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26519#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26520#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27029#L995 assume !(0 != activate_threads_~tmp___4~0#1); 27133#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27134#L490 assume 1 == ~t6_pc~0; 27103#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26794#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26595#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 26717#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26683#L509 assume !(1 == ~t7_pc~0); 26684#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26478#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26479#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26545#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26546#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27079#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 27080#L857-2 assume !(1 == ~T1_E~0); 29842#L862-1 assume !(1 == ~T2_E~0); 26617#L867-1 assume !(1 == ~T3_E~0); 26618#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26706#L877-1 assume !(1 == ~T5_E~0); 27100#L882-1 assume !(1 == ~T6_E~0); 27101#L887-1 assume !(1 == ~T7_E~0); 26985#L892-1 assume !(1 == ~E_M~0); 26986#L897-1 assume !(1 == ~E_1~0); 26635#L902-1 assume !(1 == ~E_2~0); 26636#L907-1 assume !(1 == ~E_3~0); 26939#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26926#L917-1 assume !(1 == ~E_5~0); 26927#L922-1 assume !(1 == ~E_6~0); 27146#L927-1 assume !(1 == ~E_7~0); 26912#L932-1 assume { :end_inline_reset_delta_events } true; 26913#L1178-2 [2024-10-31 22:18:07,180 INFO L747 eck$LassoCheckResult]: Loop: 26913#L1178-2 assume !false; 27447#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27087#L744-1 assume !false; 27440#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27431#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 26524#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 26525#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26632#L641 assume !(0 != eval_~tmp~0#1); 26988#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26760#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26761#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26703#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26704#L774-3 assume !(0 == ~T2_E~0); 26430#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26251#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26252#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26244#L794-3 assume !(0 == ~T6_E~0); 26245#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26291#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26553#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26289#L814-3 assume !(0 == ~E_2~0); 26290#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27013#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27006#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26613#L834-3 assume !(0 == ~E_6~0); 26614#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26964#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31175#L376-27 assume 1 == ~m_pc~0; 31173#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31172#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31171#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31170#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31169#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31168#L395-27 assume !(1 == ~t1_pc~0); 31167#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 31166#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31165#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31164#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31163#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31162#L414-27 assume 1 == ~t2_pc~0; 31159#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31156#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31155#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31154#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31153#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31152#L433-27 assume !(1 == ~t3_pc~0); 31150#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 31149#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31148#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31147#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31146#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31145#L452-27 assume 1 == ~t4_pc~0; 31143#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31142#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31141#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31140#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31139#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31138#L471-27 assume !(1 == ~t5_pc~0); 31136#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 31135#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31134#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31132#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31119#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31117#L490-27 assume 1 == ~t6_pc~0; 31114#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31111#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31108#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31105#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 31102#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31097#L509-27 assume 1 == ~t7_pc~0; 31091#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31087#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31084#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31081#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31078#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31075#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26825#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31070#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27173#L867-3 assume !(1 == ~T3_E~0); 26719#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26720#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26819#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26854#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26446#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26447#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27037#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26630#L907-3 assume !(1 == ~E_3~0); 26631#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26765#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26723#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26505#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26506#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 26353#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 26247#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 26565#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 26566#L1197 assume !(0 == start_simulation_~tmp~3#1); 26690#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27545#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27536#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27535#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 27531#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27525#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27461#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 27455#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 26913#L1178-2 [2024-10-31 22:18:07,180 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:07,180 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2024-10-31 22:18:07,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:07,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594447529] [2024-10-31 22:18:07,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:07,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:07,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:07,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:07,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:07,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [594447529] [2024-10-31 22:18:07,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [594447529] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:07,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:07,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:07,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2120893448] [2024-10-31 22:18:07,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:07,255 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:07,256 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:07,256 INFO L85 PathProgramCache]: Analyzing trace with hash -1959838059, now seen corresponding path program 1 times [2024-10-31 22:18:07,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:07,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140226014] [2024-10-31 22:18:07,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:07,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:07,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:07,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:07,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:07,314 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140226014] [2024-10-31 22:18:07,315 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140226014] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:07,315 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:07,315 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:07,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489695633] [2024-10-31 22:18:07,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:07,315 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:07,317 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:07,318 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:07,318 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:07,318 INFO L87 Difference]: Start difference. First operand 5059 states and 7392 transitions. cyclomatic complexity: 2341 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:07,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:07,568 INFO L93 Difference]: Finished difference Result 9453 states and 13724 transitions. [2024-10-31 22:18:07,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9453 states and 13724 transitions. [2024-10-31 22:18:07,620 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9300 [2024-10-31 22:18:07,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9453 states to 9453 states and 13724 transitions. [2024-10-31 22:18:07,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9453 [2024-10-31 22:18:07,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9453 [2024-10-31 22:18:07,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9453 states and 13724 transitions. [2024-10-31 22:18:07,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:07,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9453 states and 13724 transitions. [2024-10-31 22:18:07,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9453 states and 13724 transitions. [2024-10-31 22:18:07,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9453 to 9437. [2024-10-31 22:18:07,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9437 states, 9437 states have (on average 1.4525802691533327) internal successors, (13708), 9436 states have internal predecessors, (13708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:07,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9437 states to 9437 states and 13708 transitions. [2024-10-31 22:18:07,999 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9437 states and 13708 transitions. [2024-10-31 22:18:08,000 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:08,000 INFO L425 stractBuchiCegarLoop]: Abstraction has 9437 states and 13708 transitions. [2024-10-31 22:18:08,001 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:18:08,001 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9437 states and 13708 transitions. [2024-10-31 22:18:08,047 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9284 [2024-10-31 22:18:08,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:08,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:08,049 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:08,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:08,050 INFO L745 eck$LassoCheckResult]: Stem: 40971#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 40972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 41577#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41578#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41551#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 41552#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41216#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41041#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41042#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41023#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41024#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41550#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41345#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41346#L769 assume !(0 == ~M_E~0); 41367#L769-2 assume !(0 == ~T1_E~0); 41368#L774-1 assume !(0 == ~T2_E~0); 41400#L779-1 assume !(0 == ~T3_E~0); 41535#L784-1 assume !(0 == ~T4_E~0); 41342#L789-1 assume !(0 == ~T5_E~0); 41343#L794-1 assume !(0 == ~T6_E~0); 41462#L799-1 assume !(0 == ~T7_E~0); 41348#L804-1 assume !(0 == ~E_M~0); 41349#L809-1 assume !(0 == ~E_1~0); 41392#L814-1 assume !(0 == ~E_2~0); 40763#L819-1 assume !(0 == ~E_3~0); 40764#L824-1 assume !(0 == ~E_4~0); 41115#L829-1 assume !(0 == ~E_5~0); 41621#L834-1 assume !(0 == ~E_6~0); 40894#L839-1 assume !(0 == ~E_7~0); 40895#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41293#L376 assume !(1 == ~m_pc~0); 41285#L376-2 is_master_triggered_~__retres1~0#1 := 0; 41284#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41514#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40838#L955 assume !(0 != activate_threads_~tmp~1#1); 40839#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41209#L395 assume !(1 == ~t1_pc~0); 41369#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41517#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40789#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40790#L963 assume !(0 != activate_threads_~tmp___0~0#1); 41298#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41299#L414 assume !(1 == ~t2_pc~0); 40897#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40898#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41121#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41122#L971 assume !(0 != activate_threads_~tmp___1~0#1); 41555#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41213#L433 assume !(1 == ~t3_pc~0); 41013#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41014#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40757#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40758#L979 assume !(0 != activate_threads_~tmp___2~0#1); 40862#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40863#L452 assume !(1 == ~t4_pc~0); 41019#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41020#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40856#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40857#L987 assume !(0 != activate_threads_~tmp___3~0#1); 41053#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41054#L471 assume 1 == ~t5_pc~0; 41448#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41036#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41518#L995 assume !(0 != activate_threads_~tmp___4~0#1); 41612#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41613#L490 assume 1 == ~t6_pc~0; 41585#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41296#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41109#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41110#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 41227#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41191#L509 assume !(1 == ~t7_pc~0); 41192#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 40999#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41000#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41060#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41061#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41563#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 40843#L857-2 assume !(1 == ~T1_E~0); 40844#L862-1 assume !(1 == ~T2_E~0); 41125#L867-1 assume !(1 == ~T3_E~0); 41130#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41214#L877-1 assume !(1 == ~T5_E~0); 41423#L882-1 assume !(1 == ~T6_E~0); 41583#L887-1 assume !(1 == ~T7_E~0); 42509#L892-1 assume !(1 == ~E_M~0); 42506#L897-1 assume !(1 == ~E_1~0); 42504#L902-1 assume !(1 == ~E_2~0); 42502#L907-1 assume !(1 == ~E_3~0); 42500#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 42498#L917-1 assume !(1 == ~E_5~0); 42496#L922-1 assume !(1 == ~E_6~0); 42492#L927-1 assume !(1 == ~E_7~0); 42460#L932-1 assume { :end_inline_reset_delta_events } true; 42458#L1178-2 [2024-10-31 22:18:08,051 INFO L747 eck$LassoCheckResult]: Loop: 42458#L1178-2 assume !false; 42341#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42339#L744-1 assume !false; 42337#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42335#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42326#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42323#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42320#L641 assume !(0 != eval_~tmp~0#1); 42321#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49902#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49901#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49900#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49899#L774-3 assume !(0 == ~T2_E~0); 49898#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49897#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49896#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49895#L794-3 assume !(0 == ~T6_E~0); 49894#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49892#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49890#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49888#L814-3 assume !(0 == ~E_2~0); 49886#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49884#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49882#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49880#L834-3 assume !(0 == ~E_6~0); 49878#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49876#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49874#L376-27 assume !(1 == ~m_pc~0); 49872#L376-29 is_master_triggered_~__retres1~0#1 := 0; 49869#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49867#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49865#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49863#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49861#L395-27 assume !(1 == ~t1_pc~0); 49859#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 49857#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49855#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49852#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49850#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49848#L414-27 assume 1 == ~t2_pc~0; 41688#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41658#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49819#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49818#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49688#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49687#L433-27 assume !(1 == ~t3_pc~0); 49529#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 45574#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45571#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45569#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45567#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45565#L452-27 assume 1 == ~t4_pc~0; 45562#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45560#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45557#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45555#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45553#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45551#L471-27 assume !(1 == ~t5_pc~0); 45547#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 45544#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45542#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45540#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45538#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45536#L490-27 assume 1 == ~t6_pc~0; 45533#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45530#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45528#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45526#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 45524#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45522#L509-27 assume 1 == ~t7_pc~0; 45520#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45518#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45516#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45514#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45512#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45510#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44834#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45505#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45503#L867-3 assume !(1 == ~T3_E~0); 45501#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45497#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44820#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44817#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44815#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44813#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44811#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44809#L907-3 assume !(1 == ~E_3~0); 44807#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44034#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44031#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44028#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44026#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43247#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43238#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43236#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 43234#L1197 assume !(0 == start_simulation_~tmp~3#1); 43231#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42480#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42471#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42469#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 42467#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42465#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42463#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 42461#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 42458#L1178-2 [2024-10-31 22:18:08,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:08,052 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2024-10-31 22:18:08,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:08,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612178157] [2024-10-31 22:18:08,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:08,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:08,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:08,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:08,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:08,143 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612178157] [2024-10-31 22:18:08,143 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612178157] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:08,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:08,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:08,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078666988] [2024-10-31 22:18:08,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:08,147 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:08,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:08,148 INFO L85 PathProgramCache]: Analyzing trace with hash 492815446, now seen corresponding path program 1 times [2024-10-31 22:18:08,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:08,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1924700764] [2024-10-31 22:18:08,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:08,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:08,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:08,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:08,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:08,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1924700764] [2024-10-31 22:18:08,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1924700764] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:08,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:08,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:08,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1738278689] [2024-10-31 22:18:08,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:08,227 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:08,228 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:08,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:08,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:08,229 INFO L87 Difference]: Start difference. First operand 9437 states and 13708 transitions. cyclomatic complexity: 4287 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:08,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:08,459 INFO L93 Difference]: Finished difference Result 18156 states and 26197 transitions. [2024-10-31 22:18:08,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18156 states and 26197 transitions. [2024-10-31 22:18:08,580 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17948 [2024-10-31 22:18:08,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18156 states to 18156 states and 26197 transitions. [2024-10-31 22:18:08,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18156 [2024-10-31 22:18:08,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18156 [2024-10-31 22:18:08,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18156 states and 26197 transitions. [2024-10-31 22:18:08,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:08,878 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18156 states and 26197 transitions. [2024-10-31 22:18:08,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18156 states and 26197 transitions. [2024-10-31 22:18:09,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18156 to 18124. [2024-10-31 22:18:09,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18124 states, 18124 states have (on average 1.4436658574266166) internal successors, (26165), 18123 states have internal predecessors, (26165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:09,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18124 states to 18124 states and 26165 transitions. [2024-10-31 22:18:09,416 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18124 states and 26165 transitions. [2024-10-31 22:18:09,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:09,422 INFO L425 stractBuchiCegarLoop]: Abstraction has 18124 states and 26165 transitions. [2024-10-31 22:18:09,422 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:18:09,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18124 states and 26165 transitions. [2024-10-31 22:18:09,484 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17916 [2024-10-31 22:18:09,485 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:09,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:09,486 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:09,486 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:09,487 INFO L745 eck$LassoCheckResult]: Stem: 68570#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 68571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 69238#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69239#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69198#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 69199#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68827#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68646#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68647#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68626#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68627#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69197#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68963#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68964#L769 assume !(0 == ~M_E~0); 68988#L769-2 assume !(0 == ~T1_E~0); 68989#L774-1 assume !(0 == ~T2_E~0); 69023#L779-1 assume !(0 == ~T3_E~0); 69179#L784-1 assume !(0 == ~T4_E~0); 68961#L789-1 assume !(0 == ~T5_E~0); 68962#L794-1 assume !(0 == ~T6_E~0); 69090#L799-1 assume !(0 == ~T7_E~0); 68966#L804-1 assume !(0 == ~E_M~0); 68967#L809-1 assume !(0 == ~E_1~0); 69015#L814-1 assume !(0 == ~E_2~0); 68359#L819-1 assume !(0 == ~E_3~0); 68360#L824-1 assume !(0 == ~E_4~0); 68719#L829-1 assume !(0 == ~E_5~0); 69290#L834-1 assume !(0 == ~E_6~0); 68494#L839-1 assume !(0 == ~E_7~0); 68495#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68912#L376 assume !(1 == ~m_pc~0); 68899#L376-2 is_master_triggered_~__retres1~0#1 := 0; 68898#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69154#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68438#L955 assume !(0 != activate_threads_~tmp~1#1); 68439#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68818#L395 assume !(1 == ~t1_pc~0); 68990#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69156#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68389#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68390#L963 assume !(0 != activate_threads_~tmp___0~0#1); 68917#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68918#L414 assume !(1 == ~t2_pc~0); 68497#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68498#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68726#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68727#L971 assume !(0 != activate_threads_~tmp___1~0#1); 69207#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68823#L433 assume !(1 == ~t3_pc~0); 68616#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68617#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68357#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68358#L979 assume !(0 != activate_threads_~tmp___2~0#1); 68461#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68462#L452 assume !(1 == ~t4_pc~0); 68622#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68623#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68455#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68456#L987 assume !(0 != activate_threads_~tmp___3~0#1); 68657#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68658#L471 assume !(1 == ~t5_pc~0); 69074#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68639#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69159#L995 assume !(0 != activate_threads_~tmp___4~0#1); 69279#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69280#L490 assume 1 == ~t6_pc~0; 69249#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68915#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68713#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68714#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 68834#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68798#L509 assume !(1 == ~t7_pc~0); 68799#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68595#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68596#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68664#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68665#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69220#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 68443#L857-2 assume !(1 == ~T1_E~0); 68444#L862-1 assume !(1 == ~T2_E~0); 68730#L867-1 assume !(1 == ~T3_E~0); 68735#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68824#L877-1 assume !(1 == ~T5_E~0); 69044#L882-1 assume !(1 == ~T6_E~0); 71093#L887-1 assume !(1 == ~T7_E~0); 71090#L892-1 assume !(1 == ~E_M~0); 71088#L897-1 assume !(1 == ~E_1~0); 71086#L902-1 assume !(1 == ~E_2~0); 71084#L907-1 assume !(1 == ~E_3~0); 69064#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69051#L917-1 assume !(1 == ~E_5~0); 69052#L922-1 assume !(1 == ~E_6~0); 70997#L927-1 assume !(1 == ~E_7~0); 70966#L932-1 assume { :end_inline_reset_delta_events } true; 70944#L1178-2 [2024-10-31 22:18:09,487 INFO L747 eck$LassoCheckResult]: Loop: 70944#L1178-2 assume !false; 70933#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70902#L744-1 assume !false; 70894#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 70837#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 70827#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 70825#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 70822#L641 assume !(0 != eval_~tmp~0#1); 70823#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 71878#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 71876#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 71874#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 71872#L774-3 assume !(0 == ~T2_E~0); 71870#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71868#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71865#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 71863#L794-3 assume !(0 == ~T6_E~0); 71861#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 71859#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 71857#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 71856#L814-3 assume !(0 == ~E_2~0); 71855#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 71854#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71853#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71852#L834-3 assume !(0 == ~E_6~0); 71851#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71850#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71849#L376-27 assume !(1 == ~m_pc~0); 71733#L376-29 is_master_triggered_~__retres1~0#1 := 0; 71730#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71727#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 71725#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 71723#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71721#L395-27 assume !(1 == ~t1_pc~0); 71719#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 71717#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71715#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 71713#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 71711#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71709#L414-27 assume !(1 == ~t2_pc~0); 71707#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 71704#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71702#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 71700#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 71698#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71696#L433-27 assume !(1 == ~t3_pc~0); 71694#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 71692#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71690#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 71688#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 71686#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71683#L452-27 assume !(1 == ~t4_pc~0); 71681#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 71678#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71676#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 71674#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 71672#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71670#L471-27 assume !(1 == ~t5_pc~0); 71668#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 71666#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71664#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 71662#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 71660#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 71657#L490-27 assume !(1 == ~t6_pc~0); 71655#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 71652#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 71650#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71648#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 71646#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 71643#L509-27 assume !(1 == ~t7_pc~0); 71641#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 71638#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71636#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71634#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 71632#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71629#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 71392#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71624#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71622#L867-3 assume !(1 == ~T3_E~0); 71620#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 71618#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 71616#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 71612#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 71610#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 71608#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 71606#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 71604#L907-3 assume !(1 == ~E_3~0); 71601#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 71599#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 71184#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 71180#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 71178#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 71176#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 71167#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 71165#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 71163#L1197 assume !(0 == start_simulation_~tmp~3#1); 71161#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 71046#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 71037#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 71035#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 71033#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 71032#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 71000#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 70967#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 70944#L1178-2 [2024-10-31 22:18:09,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:09,488 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2024-10-31 22:18:09,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:09,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487023406] [2024-10-31 22:18:09,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:09,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:09,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:09,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:09,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:09,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487023406] [2024-10-31 22:18:09,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487023406] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:09,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:09,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:09,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103916215] [2024-10-31 22:18:09,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:09,560 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:09,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:09,560 INFO L85 PathProgramCache]: Analyzing trace with hash 1162954138, now seen corresponding path program 1 times [2024-10-31 22:18:09,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:09,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849651259] [2024-10-31 22:18:09,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:09,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:09,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:09,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:09,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:09,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849651259] [2024-10-31 22:18:09,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [849651259] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:09,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:09,679 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:09,679 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071258251] [2024-10-31 22:18:09,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:09,680 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:09,680 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:09,681 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:09,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:09,682 INFO L87 Difference]: Start difference. First operand 18124 states and 26165 transitions. cyclomatic complexity: 8073 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:10,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:10,075 INFO L93 Difference]: Finished difference Result 34071 states and 48958 transitions. [2024-10-31 22:18:10,076 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34071 states and 48958 transitions. [2024-10-31 22:18:10,471 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 33720 [2024-10-31 22:18:10,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34071 states to 34071 states and 48958 transitions. [2024-10-31 22:18:10,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34071 [2024-10-31 22:18:10,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34071 [2024-10-31 22:18:10,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34071 states and 48958 transitions. [2024-10-31 22:18:10,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:10,823 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34071 states and 48958 transitions. [2024-10-31 22:18:10,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34071 states and 48958 transitions. [2024-10-31 22:18:11,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34071 to 34007. [2024-10-31 22:18:11,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34007 states, 34007 states have (on average 1.437762813538389) internal successors, (48894), 34006 states have internal predecessors, (48894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:11,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34007 states to 34007 states and 48894 transitions. [2024-10-31 22:18:11,431 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34007 states and 48894 transitions. [2024-10-31 22:18:11,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:11,433 INFO L425 stractBuchiCegarLoop]: Abstraction has 34007 states and 48894 transitions. [2024-10-31 22:18:11,433 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:18:11,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34007 states and 48894 transitions. [2024-10-31 22:18:11,681 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 33656 [2024-10-31 22:18:11,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:11,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:11,684 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:11,684 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:11,684 INFO L745 eck$LassoCheckResult]: Stem: 120774#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 120775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 121393#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 121394#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 121365#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 121366#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121027#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 120845#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 120846#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 120827#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120828#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121363#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121154#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121155#L769 assume !(0 == ~M_E~0); 121177#L769-2 assume !(0 == ~T1_E~0); 121178#L774-1 assume !(0 == ~T2_E~0); 121207#L779-1 assume !(0 == ~T3_E~0); 121345#L784-1 assume !(0 == ~T4_E~0); 121152#L789-1 assume !(0 == ~T5_E~0); 121153#L794-1 assume !(0 == ~T6_E~0); 121269#L799-1 assume !(0 == ~T7_E~0); 121157#L804-1 assume !(0 == ~E_M~0); 121158#L809-1 assume !(0 == ~E_1~0); 121202#L814-1 assume !(0 == ~E_2~0); 120561#L819-1 assume !(0 == ~E_3~0); 120562#L824-1 assume !(0 == ~E_4~0); 120919#L829-1 assume !(0 == ~E_5~0); 121433#L834-1 assume !(0 == ~E_6~0); 120697#L839-1 assume !(0 == ~E_7~0); 120698#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121107#L376 assume !(1 == ~m_pc~0); 121091#L376-2 is_master_triggered_~__retres1~0#1 := 0; 121090#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121328#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 120639#L955 assume !(0 != activate_threads_~tmp~1#1); 120640#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121019#L395 assume !(1 == ~t1_pc~0); 121179#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 121329#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120591#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 120592#L963 assume !(0 != activate_threads_~tmp___0~0#1); 121113#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121114#L414 assume !(1 == ~t2_pc~0); 120700#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 120701#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 120925#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 120926#L971 assume !(0 != activate_threads_~tmp___1~0#1); 121372#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 121024#L433 assume !(1 == ~t3_pc~0); 120814#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 120815#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120559#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 120560#L979 assume !(0 != activate_threads_~tmp___2~0#1); 120665#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120666#L452 assume !(1 == ~t4_pc~0); 120823#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 120824#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120659#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 120660#L987 assume !(0 != activate_threads_~tmp___3~0#1); 120855#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 120856#L471 assume !(1 == ~t5_pc~0); 121254#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 120838#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 120839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121332#L995 assume !(0 != activate_threads_~tmp___4~0#1); 121420#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121421#L490 assume !(1 == ~t6_pc~0); 121111#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121112#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 120913#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 120914#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 121035#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 121000#L509 assume !(1 == ~t7_pc~0); 121001#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 120797#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120798#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 120862#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 120863#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121380#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 120646#L857-2 assume !(1 == ~T1_E~0); 120647#L862-1 assume !(1 == ~T2_E~0); 120929#L867-1 assume !(1 == ~T3_E~0); 120934#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 121025#L877-1 assume !(1 == ~T5_E~0); 121229#L882-1 assume !(1 == ~T6_E~0); 121397#L887-1 assume !(1 == ~T7_E~0); 129835#L892-1 assume !(1 == ~E_M~0); 129833#L897-1 assume !(1 == ~E_1~0); 129831#L902-1 assume !(1 == ~E_2~0); 129829#L907-1 assume !(1 == ~E_3~0); 129827#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 129825#L917-1 assume !(1 == ~E_5~0); 129823#L922-1 assume !(1 == ~E_6~0); 128799#L927-1 assume !(1 == ~E_7~0); 129787#L932-1 assume { :end_inline_reset_delta_events } true; 129785#L1178-2 [2024-10-31 22:18:11,685 INFO L747 eck$LassoCheckResult]: Loop: 129785#L1178-2 assume !false; 129683#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129681#L744-1 assume !false; 129679#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 129677#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 129669#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 129666#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 129664#L641 assume !(0 != eval_~tmp~0#1); 129665#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 137363#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 137362#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 137361#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 137360#L774-3 assume !(0 == ~T2_E~0); 137359#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 137358#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 137357#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 137356#L794-3 assume !(0 == ~T6_E~0); 137355#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 137354#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 137353#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 137352#L814-3 assume !(0 == ~E_2~0); 137351#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 137350#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 137349#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 137348#L834-3 assume !(0 == ~E_6~0); 137347#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 137346#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137344#L376-27 assume !(1 == ~m_pc~0); 137342#L376-29 is_master_triggered_~__retres1~0#1 := 0; 137339#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137337#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 137335#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 137333#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137330#L395-27 assume !(1 == ~t1_pc~0); 137328#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 137326#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 137323#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 137319#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 137316#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 137313#L414-27 assume !(1 == ~t2_pc~0); 137310#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 137306#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137303#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 137300#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 137297#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 137293#L433-27 assume !(1 == ~t3_pc~0); 137290#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 137287#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 137284#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 137280#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 137277#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137273#L452-27 assume !(1 == ~t4_pc~0); 137270#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 137266#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137263#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 137260#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 137257#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 137253#L471-27 assume !(1 == ~t5_pc~0); 137248#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 137244#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 137240#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 137235#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 137232#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 137229#L490-27 assume !(1 == ~t6_pc~0); 137226#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 137224#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 137222#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 137220#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 137217#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 137214#L509-27 assume !(1 == ~t7_pc~0); 137210#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 137206#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 137202#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 137198#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 137195#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137192#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 130435#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 137186#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 137181#L867-3 assume !(1 == ~T3_E~0); 137177#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 137173#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 137168#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 130422#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 137159#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 137155#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 137151#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 137146#L907-3 assume !(1 == ~E_3~0); 137142#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 137137#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 137133#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 134131#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 137126#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 136884#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 136720#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 136716#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 121009#L1197 assume !(0 == start_simulation_~tmp~3#1); 121010#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 129808#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 129799#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 129796#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 129794#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 129792#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129790#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 129788#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 129785#L1178-2 [2024-10-31 22:18:11,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:11,686 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2024-10-31 22:18:11,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:11,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852739255] [2024-10-31 22:18:11,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:11,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:11,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:11,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:11,785 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:11,785 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852739255] [2024-10-31 22:18:11,786 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [852739255] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:11,786 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:11,787 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:11,787 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996274071] [2024-10-31 22:18:11,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:11,788 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:11,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:11,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1162954138, now seen corresponding path program 2 times [2024-10-31 22:18:11,791 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:11,791 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414197525] [2024-10-31 22:18:11,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:11,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:11,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:11,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:11,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:11,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414197525] [2024-10-31 22:18:11,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414197525] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:11,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:11,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:11,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491660352] [2024-10-31 22:18:11,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:11,873 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:11,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:11,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:18:11,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:18:11,875 INFO L87 Difference]: Start difference. First operand 34007 states and 48894 transitions. cyclomatic complexity: 14951 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:12,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:12,448 INFO L93 Difference]: Finished difference Result 35354 states and 50241 transitions. [2024-10-31 22:18:12,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35354 states and 50241 transitions. [2024-10-31 22:18:12,724 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35000 [2024-10-31 22:18:12,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35354 states to 35354 states and 50241 transitions. [2024-10-31 22:18:12,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35354 [2024-10-31 22:18:12,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35354 [2024-10-31 22:18:12,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35354 states and 50241 transitions. [2024-10-31 22:18:12,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:12,998 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35354 states and 50241 transitions. [2024-10-31 22:18:13,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35354 states and 50241 transitions. [2024-10-31 22:18:13,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35354 to 35354. [2024-10-31 22:18:13,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35354 states, 35354 states have (on average 1.4210838943259603) internal successors, (50241), 35353 states have internal predecessors, (50241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:13,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35354 states to 35354 states and 50241 transitions. [2024-10-31 22:18:13,641 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35354 states and 50241 transitions. [2024-10-31 22:18:13,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:18:13,643 INFO L425 stractBuchiCegarLoop]: Abstraction has 35354 states and 50241 transitions. [2024-10-31 22:18:13,643 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:18:13,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35354 states and 50241 transitions. [2024-10-31 22:18:13,776 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35000 [2024-10-31 22:18:13,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:13,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:13,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:13,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:13,779 INFO L745 eck$LassoCheckResult]: Stem: 190138#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 190139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 190776#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 190777#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 190747#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 190748#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 190391#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 190208#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 190209#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 190189#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 190190#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 190745#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 190526#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 190527#L769 assume !(0 == ~M_E~0); 190553#L769-2 assume !(0 == ~T1_E~0); 190554#L774-1 assume !(0 == ~T2_E~0); 190584#L779-1 assume !(0 == ~T3_E~0); 190729#L784-1 assume !(0 == ~T4_E~0); 190524#L789-1 assume !(0 == ~T5_E~0); 190525#L794-1 assume !(0 == ~T6_E~0); 190641#L799-1 assume !(0 == ~T7_E~0); 190530#L804-1 assume !(0 == ~E_M~0); 190531#L809-1 assume !(0 == ~E_1~0); 190579#L814-1 assume !(0 == ~E_2~0); 189931#L819-1 assume !(0 == ~E_3~0); 189932#L824-1 assume !(0 == ~E_4~0); 190281#L829-1 assume !(0 == ~E_5~0); 190822#L834-1 assume !(0 == ~E_6~0); 190061#L839-1 assume !(0 == ~E_7~0); 190062#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190473#L376 assume !(1 == ~m_pc~0); 190458#L376-2 is_master_triggered_~__retres1~0#1 := 0; 190457#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 190712#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190007#L955 assume !(0 != activate_threads_~tmp~1#1); 190008#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190384#L395 assume !(1 == ~t1_pc~0); 190555#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 190713#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189961#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189962#L963 assume !(0 != activate_threads_~tmp___0~0#1); 190477#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190478#L414 assume !(1 == ~t2_pc~0); 190064#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 190065#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 190287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 190288#L971 assume !(0 != activate_threads_~tmp___1~0#1); 190753#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 190388#L433 assume !(1 == ~t3_pc~0); 190177#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 190178#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189929#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189930#L979 assume !(0 != activate_threads_~tmp___2~0#1); 190031#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 190032#L452 assume !(1 == ~t4_pc~0); 190185#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 190186#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 190025#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 190026#L987 assume !(0 != activate_threads_~tmp___3~0#1); 190218#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190219#L471 assume !(1 == ~t5_pc~0); 190626#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 190200#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 190201#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 190716#L995 assume !(0 != activate_threads_~tmp___4~0#1); 190809#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 190810#L490 assume !(1 == ~t6_pc~0); 190475#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 190476#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190275#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 190276#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 190398#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 190365#L509 assume !(1 == ~t7_pc~0); 190366#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 190160#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 190161#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 190225#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 190226#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 190763#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 190014#L857-2 assume !(1 == ~T1_E~0); 190015#L862-1 assume !(1 == ~T2_E~0); 190291#L867-1 assume !(1 == ~T3_E~0); 190296#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 190389#L877-1 assume !(1 == ~T5_E~0); 190602#L882-1 assume !(1 == ~T6_E~0); 190783#L887-1 assume !(1 == ~T7_E~0); 190664#L892-1 assume !(1 == ~E_M~0); 190665#L897-1 assume !(1 == ~E_1~0); 190312#L902-1 assume !(1 == ~E_2~0); 190313#L907-1 assume !(1 == ~E_3~0); 190617#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 190609#L917-1 assume !(1 == ~E_5~0); 190610#L922-1 assume !(1 == ~E_6~0); 190825#L927-1 assume !(1 == ~E_7~0); 198822#L932-1 assume { :end_inline_reset_delta_events } true; 198820#L1178-2 [2024-10-31 22:18:13,779 INFO L747 eck$LassoCheckResult]: Loop: 198820#L1178-2 assume !false; 198696#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 198693#L744-1 assume !false; 198691#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 198689#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 198681#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 198678#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 198676#L641 assume !(0 != eval_~tmp~0#1); 198677#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 199075#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199073#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 199071#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 199069#L774-3 assume !(0 == ~T2_E~0); 199066#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 199064#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 199062#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 199060#L794-3 assume !(0 == ~T6_E~0); 199058#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 199056#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 199054#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 199052#L814-3 assume !(0 == ~E_2~0); 199050#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 199048#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 199046#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 199044#L834-3 assume !(0 == ~E_6~0); 199041#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 199039#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199037#L376-27 assume !(1 == ~m_pc~0); 199035#L376-29 is_master_triggered_~__retres1~0#1 := 0; 199032#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199030#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 199028#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 199026#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 199024#L395-27 assume !(1 == ~t1_pc~0); 199022#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 199020#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199018#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 199015#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 199013#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199011#L414-27 assume !(1 == ~t2_pc~0); 199009#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 199006#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199004#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 199002#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 199000#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 198998#L433-27 assume !(1 == ~t3_pc~0); 198996#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 198994#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 198992#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 198990#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 198988#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 198986#L452-27 assume 1 == ~t4_pc~0; 198983#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 198981#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 198977#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198975#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 198973#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 198971#L471-27 assume !(1 == ~t5_pc~0); 198968#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 198966#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 198965#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 198964#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 198963#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 198961#L490-27 assume !(1 == ~t6_pc~0); 198959#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 198957#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198955#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 198953#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 198950#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 198948#L509-27 assume !(1 == ~t7_pc~0); 198946#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 200043#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 200037#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 198893#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 198890#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198888#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 196775#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 198882#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 198880#L867-3 assume !(1 == ~T3_E~0); 198878#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 198876#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 198874#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 198870#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 198868#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 198866#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 198864#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 198862#L907-3 assume !(1 == ~E_3~0); 198860#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 198858#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 198856#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 196743#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 198853#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 198851#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 198842#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 198840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 198839#L1197 assume !(0 == start_simulation_~tmp~3#1); 198837#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 198836#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 198828#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 198827#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 198826#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 198825#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 198824#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 198823#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 198820#L1178-2 [2024-10-31 22:18:13,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:13,780 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2024-10-31 22:18:13,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:13,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38496402] [2024-10-31 22:18:13,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:13,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:13,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:13,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:13,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:13,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38496402] [2024-10-31 22:18:13,881 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [38496402] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:13,881 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:13,881 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:13,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012052313] [2024-10-31 22:18:13,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:13,882 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:13,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:13,882 INFO L85 PathProgramCache]: Analyzing trace with hash 2138332507, now seen corresponding path program 1 times [2024-10-31 22:18:13,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:13,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117598701] [2024-10-31 22:18:13,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:13,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:13,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:14,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:14,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:14,123 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117598701] [2024-10-31 22:18:14,123 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117598701] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:14,123 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:14,123 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:14,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634716921] [2024-10-31 22:18:14,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:14,124 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:14,124 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:14,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:14,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:14,125 INFO L87 Difference]: Start difference. First operand 35354 states and 50241 transitions. cyclomatic complexity: 14951 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:14,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:14,384 INFO L93 Difference]: Finished difference Result 44340 states and 63028 transitions. [2024-10-31 22:18:14,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44340 states and 63028 transitions. [2024-10-31 22:18:14,769 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 43944 [2024-10-31 22:18:14,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44340 states to 44340 states and 63028 transitions. [2024-10-31 22:18:14,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44340 [2024-10-31 22:18:14,974 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44340 [2024-10-31 22:18:14,974 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44340 states and 63028 transitions. [2024-10-31 22:18:15,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:15,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44340 states and 63028 transitions. [2024-10-31 22:18:15,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44340 states and 63028 transitions. [2024-10-31 22:18:15,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44340 to 19046. [2024-10-31 22:18:15,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19046 states, 19046 states have (on average 1.4274388323007456) internal successors, (27187), 19045 states have internal predecessors, (27187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:15,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19046 states to 19046 states and 27187 transitions. [2024-10-31 22:18:15,577 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19046 states and 27187 transitions. [2024-10-31 22:18:15,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:15,579 INFO L425 stractBuchiCegarLoop]: Abstraction has 19046 states and 27187 transitions. [2024-10-31 22:18:15,579 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 22:18:15,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19046 states and 27187 transitions. [2024-10-31 22:18:15,639 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18832 [2024-10-31 22:18:15,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:15,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:15,641 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:15,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:15,641 INFO L745 eck$LassoCheckResult]: Stem: 269843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 269844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 270456#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 270457#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 270426#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 270427#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 270090#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 269912#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 269913#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 269893#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 269894#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 270425#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 270220#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 270221#L769 assume !(0 == ~M_E~0); 270240#L769-2 assume !(0 == ~T1_E~0); 270241#L774-1 assume !(0 == ~T2_E~0); 270271#L779-1 assume !(0 == ~T3_E~0); 270407#L784-1 assume !(0 == ~T4_E~0); 270218#L789-1 assume !(0 == ~T5_E~0); 270219#L794-1 assume !(0 == ~T6_E~0); 270332#L799-1 assume !(0 == ~T7_E~0); 270223#L804-1 assume !(0 == ~E_M~0); 270224#L809-1 assume !(0 == ~E_1~0); 270266#L814-1 assume !(0 == ~E_2~0); 269636#L819-1 assume !(0 == ~E_3~0); 269637#L824-1 assume !(0 == ~E_4~0); 269984#L829-1 assume !(0 == ~E_5~0); 270499#L834-1 assume !(0 == ~E_6~0); 269766#L839-1 assume !(0 == ~E_7~0); 269767#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270170#L376 assume !(1 == ~m_pc~0); 270160#L376-2 is_master_triggered_~__retres1~0#1 := 0; 270159#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270389#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 269711#L955 assume !(0 != activate_threads_~tmp~1#1); 269712#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270083#L395 assume !(1 == ~t1_pc~0); 270242#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 270392#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 269664#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 269665#L963 assume !(0 != activate_threads_~tmp___0~0#1); 270176#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270177#L414 assume !(1 == ~t2_pc~0); 269769#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 269770#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 269991#L971 assume !(0 != activate_threads_~tmp___1~0#1); 270433#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270087#L433 assume !(1 == ~t3_pc~0); 269880#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 269881#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269630#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 269631#L979 assume !(0 != activate_threads_~tmp___2~0#1); 269735#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 269736#L452 assume !(1 == ~t4_pc~0); 269889#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 269890#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 269729#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 269730#L987 assume !(0 != activate_threads_~tmp___3~0#1); 269922#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 269923#L471 assume !(1 == ~t5_pc~0); 270316#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 269907#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 269908#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 270393#L995 assume !(0 != activate_threads_~tmp___4~0#1); 270489#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 270490#L490 assume !(1 == ~t6_pc~0); 270172#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 270173#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 269978#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 269979#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 270100#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 270063#L509 assume !(1 == ~t7_pc~0); 270064#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 269866#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 269867#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 269929#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 269930#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 270442#L857 assume !(1 == ~M_E~0); 269716#L857-2 assume !(1 == ~T1_E~0); 269717#L862-1 assume !(1 == ~T2_E~0); 269994#L867-1 assume !(1 == ~T3_E~0); 269999#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 270088#L877-1 assume !(1 == ~T5_E~0); 270290#L882-1 assume !(1 == ~T6_E~0); 270460#L887-1 assume !(1 == ~T7_E~0); 270353#L892-1 assume !(1 == ~E_M~0); 270354#L897-1 assume !(1 == ~E_1~0); 270017#L902-1 assume !(1 == ~E_2~0); 270018#L907-1 assume !(1 == ~E_3~0); 270305#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 270297#L917-1 assume !(1 == ~E_5~0); 270298#L922-1 assume !(1 == ~E_6~0); 270502#L927-1 assume !(1 == ~E_7~0); 270285#L932-1 assume { :end_inline_reset_delta_events } true; 270286#L1178-2 [2024-10-31 22:18:15,642 INFO L747 eck$LassoCheckResult]: Loop: 270286#L1178-2 assume !false; 276129#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 276127#L744-1 assume !false; 276124#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 275985#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 275976#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 275974#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 275971#L641 assume !(0 != eval_~tmp~0#1); 275968#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 275966#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 275964#L769-3 assume !(0 == ~M_E~0); 275962#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 275960#L774-3 assume !(0 == ~T2_E~0); 275958#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 275955#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 275944#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 275935#L794-3 assume !(0 == ~T6_E~0); 275924#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 275915#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 275913#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 275911#L814-3 assume !(0 == ~E_2~0); 275908#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 275906#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 275904#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 275902#L834-3 assume !(0 == ~E_6~0); 275900#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 275898#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 275896#L376-27 assume 1 == ~m_pc~0; 275893#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 275891#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 275889#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 275887#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 275885#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 275883#L395-27 assume !(1 == ~t1_pc~0); 275881#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 275879#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 275877#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 275875#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 275863#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 275859#L414-27 assume 1 == ~t2_pc~0; 275854#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 275849#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 275844#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 275840#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 275835#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 275831#L433-27 assume !(1 == ~t3_pc~0); 275827#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 275823#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 275818#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 275814#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 275810#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 275806#L452-27 assume 1 == ~t4_pc~0; 275801#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 275797#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 275792#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 275788#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 275784#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 275780#L471-27 assume !(1 == ~t5_pc~0); 275776#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 275772#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 275768#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 275764#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 275758#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 275753#L490-27 assume !(1 == ~t6_pc~0); 275748#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 275743#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 275738#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 275734#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 275730#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 275726#L509-27 assume 1 == ~t7_pc~0; 275721#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 275716#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 275710#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 275705#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 275700#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275696#L857-3 assume !(1 == ~M_E~0); 274108#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 275689#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 275685#L867-3 assume !(1 == ~T3_E~0); 275681#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 275676#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 275672#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 275667#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 275629#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 275618#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 275614#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 275610#L907-3 assume !(1 == ~E_3~0); 275607#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 275604#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 275600#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 275597#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 275596#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 275595#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 275585#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 275581#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 274362#L1197 assume !(0 == start_simulation_~tmp~3#1); 274363#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 276709#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 276700#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 276698#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 276695#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 276693#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 276692#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 276688#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 270286#L1178-2 [2024-10-31 22:18:15,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:15,642 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2024-10-31 22:18:15,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:15,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318072749] [2024-10-31 22:18:15,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:15,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:15,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:15,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:15,733 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318072749] [2024-10-31 22:18:15,733 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [318072749] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:15,733 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:15,733 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:15,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602665679] [2024-10-31 22:18:15,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:15,734 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:15,734 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:15,734 INFO L85 PathProgramCache]: Analyzing trace with hash 1617182998, now seen corresponding path program 1 times [2024-10-31 22:18:15,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:15,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569728609] [2024-10-31 22:18:15,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:15,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:15,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:15,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:15,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:15,797 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569728609] [2024-10-31 22:18:15,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [569728609] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:15,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:15,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:15,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246440753] [2024-10-31 22:18:15,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:15,798 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:15,798 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:15,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:15,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:15,799 INFO L87 Difference]: Start difference. First operand 19046 states and 27187 transitions. cyclomatic complexity: 8157 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:16,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:16,253 INFO L93 Difference]: Finished difference Result 30242 states and 43038 transitions. [2024-10-31 22:18:16,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30242 states and 43038 transitions. [2024-10-31 22:18:16,417 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 29888 [2024-10-31 22:18:16,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30242 states to 30242 states and 43038 transitions. [2024-10-31 22:18:16,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30242 [2024-10-31 22:18:16,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30242 [2024-10-31 22:18:16,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30242 states and 43038 transitions. [2024-10-31 22:18:16,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:16,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30242 states and 43038 transitions. [2024-10-31 22:18:16,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30242 states and 43038 transitions. [2024-10-31 22:18:16,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30242 to 21486. [2024-10-31 22:18:16,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21486 states, 21486 states have (on average 1.4271153309131528) internal successors, (30663), 21485 states have internal predecessors, (30663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:16,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21486 states to 21486 states and 30663 transitions. [2024-10-31 22:18:16,971 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21486 states and 30663 transitions. [2024-10-31 22:18:16,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:16,972 INFO L425 stractBuchiCegarLoop]: Abstraction has 21486 states and 30663 transitions. [2024-10-31 22:18:16,972 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-31 22:18:16,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21486 states and 30663 transitions. [2024-10-31 22:18:17,051 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21200 [2024-10-31 22:18:17,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:17,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:17,053 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:17,054 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:17,054 INFO L745 eck$LassoCheckResult]: Stem: 319139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 319140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 319783#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 319784#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 319748#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 319749#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 319394#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 319209#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 319210#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 319191#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 319192#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 319747#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 319532#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 319533#L769 assume !(0 == ~M_E~0); 319552#L769-2 assume !(0 == ~T1_E~0); 319553#L774-1 assume !(0 == ~T2_E~0); 319583#L779-1 assume !(0 == ~T3_E~0); 319728#L784-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 319729#L789-1 assume !(0 == ~T5_E~0); 319939#L794-1 assume !(0 == ~T6_E~0); 319916#L799-1 assume !(0 == ~T7_E~0); 319917#L804-1 assume !(0 == ~E_M~0); 319577#L809-1 assume !(0 == ~E_1~0); 319578#L814-1 assume !(0 == ~E_2~0); 318930#L819-1 assume !(0 == ~E_3~0); 318931#L824-1 assume !(0 == ~E_4~0); 319908#L829-1 assume !(0 == ~E_5~0); 319909#L834-1 assume !(0 == ~E_6~0); 319065#L839-1 assume !(0 == ~E_7~0); 319066#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 319646#L376 assume !(1 == ~m_pc~0); 319461#L376-2 is_master_triggered_~__retres1~0#1 := 0; 319460#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 319704#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 319705#L955 assume !(0 != activate_threads_~tmp~1#1); 319937#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319554#L395 assume !(1 == ~t1_pc~0); 319555#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 319730#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 319731#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 319774#L963 assume !(0 != activate_threads_~tmp___0~0#1); 319775#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 319925#L414 assume !(1 == ~t2_pc~0); 319926#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 319914#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 319915#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319755#L971 assume !(0 != activate_threads_~tmp___1~0#1); 319756#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 319936#L433 assume !(1 == ~t3_pc~0); 319178#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 319179#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 318928#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 318929#L979 assume !(0 != activate_threads_~tmp___2~0#1); 319033#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 319034#L452 assume !(1 == ~t4_pc~0); 319187#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 319188#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 319027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 319028#L987 assume !(0 != activate_threads_~tmp___3~0#1); 319219#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 319220#L471 assume !(1 == ~t5_pc~0); 319627#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 319202#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 319203#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 319912#L995 assume !(0 != activate_threads_~tmp___4~0#1); 319913#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 319863#L490 assume !(1 == ~t6_pc~0); 319864#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 319519#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 319520#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 319525#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 319526#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 319934#L509 assume !(1 == ~t7_pc~0); 319762#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 319933#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 319929#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 319930#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 319840#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319841#L857 assume !(1 == ~M_E~0); 319016#L857-2 assume !(1 == ~T1_E~0); 319017#L862-1 assume !(1 == ~T2_E~0); 319299#L867-1 assume !(1 == ~T3_E~0); 319300#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 319392#L877-1 assume !(1 == ~T5_E~0); 319602#L882-1 assume !(1 == ~T6_E~0); 319789#L887-1 assume !(1 == ~T7_E~0); 319664#L892-1 assume !(1 == ~E_M~0); 319665#L897-1 assume !(1 == ~E_1~0); 319316#L902-1 assume !(1 == ~E_2~0); 319317#L907-1 assume !(1 == ~E_3~0); 319617#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 319609#L917-1 assume !(1 == ~E_5~0); 319610#L922-1 assume !(1 == ~E_6~0); 319831#L927-1 assume !(1 == ~E_7~0); 319597#L932-1 assume { :end_inline_reset_delta_events } true; 319598#L1178-2 [2024-10-31 22:18:17,055 INFO L747 eck$LassoCheckResult]: Loop: 319598#L1178-2 assume !false; 324476#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 324469#L744-1 assume !false; 324327#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 323896#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 323887#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 323885#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 323882#L641 assume !(0 != eval_~tmp~0#1); 323880#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 323878#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 323875#L769-3 assume !(0 == ~M_E~0); 323873#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 323871#L774-3 assume !(0 == ~T2_E~0); 323869#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 323866#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 323865#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 323864#L794-3 assume !(0 == ~T6_E~0); 323863#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 323862#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 323861#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 323860#L814-3 assume !(0 == ~E_2~0); 323859#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 323858#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 323857#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 323856#L834-3 assume !(0 == ~E_6~0); 323855#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 323854#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 323853#L376-27 assume !(1 == ~m_pc~0); 323852#L376-29 is_master_triggered_~__retres1~0#1 := 0; 323850#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 323849#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 323848#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 323847#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 323846#L395-27 assume !(1 == ~t1_pc~0); 323845#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 323844#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 323843#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 323842#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 323841#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323840#L414-27 assume 1 == ~t2_pc~0; 323838#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 323837#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 323836#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 323835#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 323834#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 323833#L433-27 assume !(1 == ~t3_pc~0); 323832#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 323831#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 323830#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 323829#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 323828#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 323827#L452-27 assume 1 == ~t4_pc~0; 323825#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 323824#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 323823#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 323822#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 323821#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 323820#L471-27 assume !(1 == ~t5_pc~0); 323819#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 323818#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 323817#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 323816#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 323815#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 323814#L490-27 assume !(1 == ~t6_pc~0); 323813#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 323812#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 323811#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 323810#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 323809#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 323808#L509-27 assume 1 == ~t7_pc~0; 323806#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 323804#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 323802#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 323800#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 323799#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 323798#L857-3 assume !(1 == ~M_E~0); 322427#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 323797#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 323796#L867-3 assume !(1 == ~T3_E~0); 323794#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 323791#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 323789#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 323787#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 323784#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 323782#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 323780#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 323744#L907-3 assume !(1 == ~E_3~0); 322988#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 322987#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 322986#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 322985#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 322984#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 322980#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 322972#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 322817#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 322689#L1197 assume !(0 == start_simulation_~tmp~3#1); 322690#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 324520#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 324511#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 324509#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 324507#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 324505#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 324503#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 324501#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 319598#L1178-2 [2024-10-31 22:18:17,056 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:17,056 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2024-10-31 22:18:17,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:17,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516250826] [2024-10-31 22:18:17,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:17,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:17,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:17,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:17,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:17,143 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [516250826] [2024-10-31 22:18:17,143 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [516250826] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:17,143 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:17,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:17,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384266397] [2024-10-31 22:18:17,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:17,144 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:17,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:17,146 INFO L85 PathProgramCache]: Analyzing trace with hash -225130793, now seen corresponding path program 1 times [2024-10-31 22:18:17,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:17,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96208520] [2024-10-31 22:18:17,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:17,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:17,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:17,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:17,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:17,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96208520] [2024-10-31 22:18:17,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [96208520] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:17,217 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:17,217 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:17,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [60048020] [2024-10-31 22:18:17,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:17,217 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:17,218 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:17,218 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:17,218 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:17,219 INFO L87 Difference]: Start difference. First operand 21486 states and 30663 transitions. cyclomatic complexity: 9193 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:17,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:17,460 INFO L93 Difference]: Finished difference Result 27790 states and 39425 transitions. [2024-10-31 22:18:17,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27790 states and 39425 transitions. [2024-10-31 22:18:17,605 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27520 [2024-10-31 22:18:17,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27790 states to 27790 states and 39425 transitions. [2024-10-31 22:18:17,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27790 [2024-10-31 22:18:18,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27790 [2024-10-31 22:18:18,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27790 states and 39425 transitions. [2024-10-31 22:18:18,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:18,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27790 states and 39425 transitions. [2024-10-31 22:18:18,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27790 states and 39425 transitions. [2024-10-31 22:18:18,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27790 to 19046. [2024-10-31 22:18:18,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19046 states, 19046 states have (on average 1.4222933949385699) internal successors, (27089), 19045 states have internal predecessors, (27089), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:18,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19046 states to 19046 states and 27089 transitions. [2024-10-31 22:18:18,382 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19046 states and 27089 transitions. [2024-10-31 22:18:18,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:18,383 INFO L425 stractBuchiCegarLoop]: Abstraction has 19046 states and 27089 transitions. [2024-10-31 22:18:18,383 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-31 22:18:18,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19046 states and 27089 transitions. [2024-10-31 22:18:18,444 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18832 [2024-10-31 22:18:18,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:18,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:18,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:18,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:18,447 INFO L745 eck$LassoCheckResult]: Stem: 368425#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 368426#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 369026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 369027#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 369000#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 369001#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 368676#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 368495#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 368496#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 368477#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 368478#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 368999#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 368798#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 368799#L769 assume !(0 == ~M_E~0); 368819#L769-2 assume !(0 == ~T1_E~0); 368820#L774-1 assume !(0 == ~T2_E~0); 368853#L779-1 assume !(0 == ~T3_E~0); 368984#L784-1 assume !(0 == ~T4_E~0); 368796#L789-1 assume !(0 == ~T5_E~0); 368797#L794-1 assume !(0 == ~T6_E~0); 368909#L799-1 assume !(0 == ~T7_E~0); 368801#L804-1 assume !(0 == ~E_M~0); 368802#L809-1 assume !(0 == ~E_1~0); 368844#L814-1 assume !(0 == ~E_2~0); 368216#L819-1 assume !(0 == ~E_3~0); 368217#L824-1 assume !(0 == ~E_4~0); 368568#L829-1 assume !(0 == ~E_5~0); 369058#L834-1 assume !(0 == ~E_6~0); 368349#L839-1 assume !(0 == ~E_7~0); 368350#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 368750#L376 assume !(1 == ~m_pc~0); 368739#L376-2 is_master_triggered_~__retres1~0#1 := 0; 368738#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 368966#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 368293#L955 assume !(0 != activate_threads_~tmp~1#1); 368294#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 368668#L395 assume !(1 == ~t1_pc~0); 368821#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 368967#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 368246#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 368247#L963 assume !(0 != activate_threads_~tmp___0~0#1); 368754#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 368755#L414 assume !(1 == ~t2_pc~0); 368352#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 368353#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 368574#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 368575#L971 assume !(0 != activate_threads_~tmp___1~0#1); 369007#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 368673#L433 assume !(1 == ~t3_pc~0); 368465#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 368466#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 368214#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 368215#L979 assume !(0 != activate_threads_~tmp___2~0#1); 368318#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 368319#L452 assume !(1 == ~t4_pc~0); 368473#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 368474#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 368312#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 368313#L987 assume !(0 != activate_threads_~tmp___3~0#1); 368505#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 368506#L471 assume !(1 == ~t5_pc~0); 368896#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 368488#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 368489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 368971#L995 assume !(0 != activate_threads_~tmp___4~0#1); 369048#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 369049#L490 assume !(1 == ~t6_pc~0); 368752#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 368753#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 368562#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 368563#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 368683#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 368650#L509 assume !(1 == ~t7_pc~0); 368651#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 368448#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 368449#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 368512#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 368513#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 369015#L857 assume !(1 == ~M_E~0); 368300#L857-2 assume !(1 == ~T1_E~0); 368301#L862-1 assume !(1 == ~T2_E~0); 368578#L867-1 assume !(1 == ~T3_E~0); 368583#L872-1 assume !(1 == ~T4_E~0); 368674#L877-1 assume !(1 == ~T5_E~0); 368872#L882-1 assume !(1 == ~T6_E~0); 369030#L887-1 assume !(1 == ~T7_E~0); 368933#L892-1 assume !(1 == ~E_M~0); 368934#L897-1 assume !(1 == ~E_1~0); 368598#L902-1 assume !(1 == ~E_2~0); 368599#L907-1 assume !(1 == ~E_3~0); 368886#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 368879#L917-1 assume !(1 == ~E_5~0); 368880#L922-1 assume !(1 == ~E_6~0); 369063#L927-1 assume !(1 == ~E_7~0); 368867#L932-1 assume { :end_inline_reset_delta_events } true; 368868#L1178-2 [2024-10-31 22:18:18,448 INFO L747 eck$LassoCheckResult]: Loop: 368868#L1178-2 assume !false; 371020#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 371014#L744-1 assume !false; 371010#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 370820#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 370811#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 370808#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 370805#L641 assume !(0 != eval_~tmp~0#1); 370803#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 370801#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 370799#L769-3 assume !(0 == ~M_E~0); 370797#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 370794#L774-3 assume !(0 == ~T2_E~0); 370792#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 370790#L784-3 assume !(0 == ~T4_E~0); 370788#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 370786#L794-3 assume !(0 == ~T6_E~0); 370784#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 370782#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 370780#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 370778#L814-3 assume !(0 == ~E_2~0); 370776#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 370750#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 370737#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 370726#L834-3 assume !(0 == ~E_6~0); 370718#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 370711#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 370704#L376-27 assume !(1 == ~m_pc~0); 370699#L376-29 is_master_triggered_~__retres1~0#1 := 0; 370696#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 370694#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 370685#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 370683#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 370681#L395-27 assume !(1 == ~t1_pc~0); 370678#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 370676#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 370674#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 370672#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 370670#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 370668#L414-27 assume 1 == ~t2_pc~0; 370665#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 370663#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 370661#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 370659#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 370657#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 370655#L433-27 assume !(1 == ~t3_pc~0); 370653#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 370651#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 370649#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 370647#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 370645#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 370643#L452-27 assume !(1 == ~t4_pc~0); 370641#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 370638#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 370636#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 370633#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 370631#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 370629#L471-27 assume !(1 == ~t5_pc~0); 370627#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 370625#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 370623#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 370621#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 370619#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 370617#L490-27 assume !(1 == ~t6_pc~0); 370615#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 370613#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 370611#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 370608#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 370606#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 370604#L509-27 assume 1 == ~t7_pc~0; 370601#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 370598#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 370595#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 370592#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 370590#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 370588#L857-3 assume !(1 == ~M_E~0); 370443#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 370585#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 370583#L867-3 assume !(1 == ~T3_E~0); 370580#L872-3 assume !(1 == ~T4_E~0); 370578#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 370576#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 370574#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 370572#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 370570#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 370567#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 370565#L907-3 assume !(1 == ~E_3~0); 370563#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 370561#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 370559#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 370557#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 370555#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 370553#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 370544#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 370543#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 370503#L1197 assume !(0 == start_simulation_~tmp~3#1); 370504#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 371191#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 371182#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 371122#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 371115#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 371055#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 371046#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 371036#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 368868#L1178-2 [2024-10-31 22:18:18,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:18,448 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2024-10-31 22:18:18,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:18,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167823691] [2024-10-31 22:18:18,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:18,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:18,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:18,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:18,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:18,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1167823691] [2024-10-31 22:18:18,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1167823691] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:18,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:18,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:18,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121210797] [2024-10-31 22:18:18,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:18,537 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:18,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:18,537 INFO L85 PathProgramCache]: Analyzing trace with hash 1518702552, now seen corresponding path program 1 times [2024-10-31 22:18:18,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:18,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098811494] [2024-10-31 22:18:18,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:18,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:18,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:18,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:18,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:18,593 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098811494] [2024-10-31 22:18:18,593 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2098811494] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:18,593 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:18,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:18,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051913855] [2024-10-31 22:18:18,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:18,594 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:18,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:18,595 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:18,595 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:18,595 INFO L87 Difference]: Start difference. First operand 19046 states and 27089 transitions. cyclomatic complexity: 8059 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:18,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:18,989 INFO L93 Difference]: Finished difference Result 30270 states and 42575 transitions. [2024-10-31 22:18:18,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30270 states and 42575 transitions. [2024-10-31 22:18:19,115 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 29876 [2024-10-31 22:18:19,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30270 states to 30270 states and 42575 transitions. [2024-10-31 22:18:19,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30270 [2024-10-31 22:18:19,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30270 [2024-10-31 22:18:19,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30270 states and 42575 transitions. [2024-10-31 22:18:19,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:19,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30270 states and 42575 transitions. [2024-10-31 22:18:19,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30270 states and 42575 transitions. [2024-10-31 22:18:19,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30270 to 21486. [2024-10-31 22:18:19,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21486 states, 21486 states have (on average 1.412082286139812) internal successors, (30340), 21485 states have internal predecessors, (30340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:19,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21486 states to 21486 states and 30340 transitions. [2024-10-31 22:18:19,846 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21486 states and 30340 transitions. [2024-10-31 22:18:19,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:19,847 INFO L425 stractBuchiCegarLoop]: Abstraction has 21486 states and 30340 transitions. [2024-10-31 22:18:19,848 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-31 22:18:19,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21486 states and 30340 transitions. [2024-10-31 22:18:19,915 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21200 [2024-10-31 22:18:19,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:19,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:19,918 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:19,918 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:19,918 INFO L745 eck$LassoCheckResult]: Stem: 417749#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 417750#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 418397#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 418398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 418367#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 418368#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 418002#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 417817#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 417818#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 417799#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 417800#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 418366#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 418138#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 418139#L769 assume !(0 == ~M_E~0); 418158#L769-2 assume !(0 == ~T1_E~0); 418159#L774-1 assume !(0 == ~T2_E~0); 418191#L779-1 assume !(0 == ~T3_E~0); 418346#L784-1 assume !(0 == ~T4_E~0); 418136#L789-1 assume !(0 == ~T5_E~0); 418137#L794-1 assume !(0 == ~T6_E~0); 418256#L799-1 assume !(0 == ~T7_E~0); 418141#L804-1 assume !(0 == ~E_M~0); 418142#L809-1 assume !(0 == ~E_1~0); 418185#L814-1 assume !(0 == ~E_2~0); 417546#L819-1 assume !(0 == ~E_3~0); 417547#L824-1 assume 0 == ~E_4~0;~E_4~0 := 1; 417888#L829-1 assume !(0 == ~E_5~0); 418438#L834-1 assume !(0 == ~E_6~0); 418439#L839-1 assume !(0 == ~E_7~0); 418262#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 418263#L376 assume !(1 == ~m_pc~0); 418077#L376-2 is_master_triggered_~__retres1~0#1 := 0; 418076#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 418326#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 418327#L955 assume !(0 != activate_threads_~tmp~1#1); 417992#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 417993#L395 assume !(1 == ~t1_pc~0); 418330#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 418331#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 417574#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 417575#L963 assume !(0 != activate_threads_~tmp___0~0#1); 418094#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 418095#L414 assume !(1 == ~t2_pc~0); 417676#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 417677#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 417896#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 417897#L971 assume !(0 != activate_threads_~tmp___1~0#1); 418450#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 418451#L433 assume !(1 == ~t3_pc~0); 417789#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 417790#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 417540#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 417541#L979 assume !(0 != activate_threads_~tmp___2~0#1); 417642#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 417643#L452 assume !(1 == ~t4_pc~0); 418558#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 418557#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 418556#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 418555#L987 assume !(0 != activate_threads_~tmp___3~0#1); 418554#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 418553#L471 assume !(1 == ~t5_pc~0); 418552#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 418551#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 418550#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 418549#L995 assume !(0 != activate_threads_~tmp___4~0#1); 418548#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 418547#L490 assume !(1 == ~t6_pc~0); 418546#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 418545#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 418544#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 418543#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 418542#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 418541#L509 assume !(1 == ~t7_pc~0); 418539#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 418537#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 418535#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 418533#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 418532#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 418531#L857 assume !(1 == ~M_E~0); 418530#L857-2 assume !(1 == ~T1_E~0); 418529#L862-1 assume !(1 == ~T2_E~0); 418528#L867-1 assume !(1 == ~T3_E~0); 418527#L872-1 assume !(1 == ~T4_E~0); 418526#L877-1 assume !(1 == ~T5_E~0); 418525#L882-1 assume !(1 == ~T6_E~0); 418524#L887-1 assume !(1 == ~T7_E~0); 418523#L892-1 assume !(1 == ~E_M~0); 418522#L897-1 assume !(1 == ~E_1~0); 418521#L902-1 assume !(1 == ~E_2~0); 418520#L907-1 assume !(1 == ~E_3~0); 418519#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 418217#L917-1 assume !(1 == ~E_5~0); 418218#L922-1 assume !(1 == ~E_6~0); 418445#L927-1 assume !(1 == ~E_7~0); 418205#L932-1 assume { :end_inline_reset_delta_events } true; 418206#L1178-2 [2024-10-31 22:18:19,919 INFO L747 eck$LassoCheckResult]: Loop: 418206#L1178-2 assume !false; 426288#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 426285#L744-1 assume !false; 426283#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 426281#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 426267#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 426266#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 426264#L641 assume !(0 != eval_~tmp~0#1); 426265#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 427935#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 427927#L769-3 assume !(0 == ~M_E~0); 427920#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 427916#L774-3 assume !(0 == ~T2_E~0); 427907#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 427899#L784-3 assume !(0 == ~T4_E~0); 427892#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 427884#L794-3 assume !(0 == ~T6_E~0); 427877#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 427870#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 427862#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 427855#L814-3 assume !(0 == ~E_2~0); 427848#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 427838#L824-3 assume !(0 == ~E_4~0); 427839#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 428181#L834-3 assume !(0 == ~E_6~0); 428180#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 428179#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 428178#L376-27 assume 1 == ~m_pc~0; 428176#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 428175#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 428173#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 428171#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 428169#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 428167#L395-27 assume !(1 == ~t1_pc~0); 428164#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 428162#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 428160#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 428158#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 428156#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 428154#L414-27 assume 1 == ~t2_pc~0; 428151#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 428149#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 428147#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 428145#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 428143#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 428141#L433-27 assume !(1 == ~t3_pc~0); 428138#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 428136#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 428134#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 428132#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 428130#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 428078#L452-27 assume !(1 == ~t4_pc~0); 427805#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 427986#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 427985#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 427984#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 427982#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 427981#L471-27 assume !(1 == ~t5_pc~0); 427980#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 427979#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 427977#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 427975#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 427973#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 427970#L490-27 assume !(1 == ~t6_pc~0); 427968#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 427966#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 427964#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 427962#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 427960#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 427957#L509-27 assume 1 == ~t7_pc~0; 427956#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 427951#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 427946#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 427940#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 427934#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 427926#L857-3 assume !(1 == ~M_E~0); 421838#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 427915#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 427906#L867-3 assume !(1 == ~T3_E~0); 427898#L872-3 assume !(1 == ~T4_E~0); 427891#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 427883#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 427876#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 427869#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 427861#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 427854#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 427847#L907-3 assume !(1 == ~E_3~0); 427766#L912-3 assume !(1 == ~E_4~0); 427759#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 427752#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 427746#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 426733#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 426730#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 426721#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 426719#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 421662#L1197 assume !(0 == start_simulation_~tmp~3#1); 421663#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 426600#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 426591#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 426589#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 426586#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 426584#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 426582#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 426576#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 418206#L1178-2 [2024-10-31 22:18:19,919 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:19,920 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2024-10-31 22:18:19,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:19,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882267645] [2024-10-31 22:18:19,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:19,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:19,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:19,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:19,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:19,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882267645] [2024-10-31 22:18:19,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1882267645] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:19,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:19,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:19,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188096540] [2024-10-31 22:18:19,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:19,997 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:19,997 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:19,997 INFO L85 PathProgramCache]: Analyzing trace with hash -955540905, now seen corresponding path program 1 times [2024-10-31 22:18:19,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:19,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353820094] [2024-10-31 22:18:19,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:20,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:20,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:20,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:20,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:20,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353820094] [2024-10-31 22:18:20,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353820094] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:20,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:20,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:20,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1312071867] [2024-10-31 22:18:20,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:20,063 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:20,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:20,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:20,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:20,065 INFO L87 Difference]: Start difference. First operand 21486 states and 30340 transitions. cyclomatic complexity: 8870 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:20,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:20,316 INFO L93 Difference]: Finished difference Result 27322 states and 38330 transitions. [2024-10-31 22:18:20,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27322 states and 38330 transitions. [2024-10-31 22:18:20,433 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27044 [2024-10-31 22:18:20,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27322 states to 27322 states and 38330 transitions. [2024-10-31 22:18:20,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27322 [2024-10-31 22:18:20,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27322 [2024-10-31 22:18:20,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27322 states and 38330 transitions. [2024-10-31 22:18:20,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:20,565 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27322 states and 38330 transitions. [2024-10-31 22:18:20,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27322 states and 38330 transitions. [2024-10-31 22:18:20,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27322 to 19046. [2024-10-31 22:18:20,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19046 states, 19046 states have (on average 1.4053344534285415) internal successors, (26766), 19045 states have internal predecessors, (26766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:20,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19046 states to 19046 states and 26766 transitions. [2024-10-31 22:18:20,867 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19046 states and 26766 transitions. [2024-10-31 22:18:20,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:20,868 INFO L425 stractBuchiCegarLoop]: Abstraction has 19046 states and 26766 transitions. [2024-10-31 22:18:20,868 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-31 22:18:20,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19046 states and 26766 transitions. [2024-10-31 22:18:21,098 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18832 [2024-10-31 22:18:21,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:21,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:21,100 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:21,101 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:21,101 INFO L745 eck$LassoCheckResult]: Stem: 466568#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 466569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 467209#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 467210#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 467178#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 467179#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 466821#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 466638#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 466639#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 466621#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 466622#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 467176#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 466954#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 466955#L769 assume !(0 == ~M_E~0); 466977#L769-2 assume !(0 == ~T1_E~0); 466978#L774-1 assume !(0 == ~T2_E~0); 467012#L779-1 assume !(0 == ~T3_E~0); 467160#L784-1 assume !(0 == ~T4_E~0); 466952#L789-1 assume !(0 == ~T5_E~0); 466953#L794-1 assume !(0 == ~T6_E~0); 467078#L799-1 assume !(0 == ~T7_E~0); 466957#L804-1 assume !(0 == ~E_M~0); 466958#L809-1 assume !(0 == ~E_1~0); 467005#L814-1 assume !(0 == ~E_2~0); 466362#L819-1 assume !(0 == ~E_3~0); 466363#L824-1 assume !(0 == ~E_4~0); 466712#L829-1 assume !(0 == ~E_5~0); 467249#L834-1 assume !(0 == ~E_6~0); 466490#L839-1 assume !(0 == ~E_7~0); 466491#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 466905#L376 assume !(1 == ~m_pc~0); 466895#L376-2 is_master_triggered_~__retres1~0#1 := 0; 466894#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 467142#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 466437#L955 assume !(0 != activate_threads_~tmp~1#1); 466438#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 466813#L395 assume !(1 == ~t1_pc~0); 466979#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 467144#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 466390#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 466391#L963 assume !(0 != activate_threads_~tmp___0~0#1); 466910#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 466911#L414 assume !(1 == ~t2_pc~0); 466493#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 466494#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 466719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 466720#L971 assume !(0 != activate_threads_~tmp___1~0#1); 467185#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 466818#L433 assume !(1 == ~t3_pc~0); 466608#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 466609#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 466358#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 466359#L979 assume !(0 != activate_threads_~tmp___2~0#1); 466460#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 466461#L452 assume !(1 == ~t4_pc~0); 466617#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 466618#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 466454#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 466455#L987 assume !(0 != activate_threads_~tmp___3~0#1); 466648#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 466649#L471 assume !(1 == ~t5_pc~0); 467062#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 466631#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 466632#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 467146#L995 assume !(0 != activate_threads_~tmp___4~0#1); 467239#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 467240#L490 assume !(1 == ~t6_pc~0); 466907#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 466908#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 466706#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 466707#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 466832#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 466794#L509 assume !(1 == ~t7_pc~0); 466795#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 466594#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 466595#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 466655#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 466656#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 467193#L857 assume !(1 == ~M_E~0); 466442#L857-2 assume !(1 == ~T1_E~0); 466443#L862-1 assume !(1 == ~T2_E~0); 466723#L867-1 assume !(1 == ~T3_E~0); 466728#L872-1 assume !(1 == ~T4_E~0); 466819#L877-1 assume !(1 == ~T5_E~0); 467033#L882-1 assume !(1 == ~T6_E~0); 467215#L887-1 assume !(1 == ~T7_E~0); 467101#L892-1 assume !(1 == ~E_M~0); 467102#L897-1 assume !(1 == ~E_1~0); 466746#L902-1 assume !(1 == ~E_2~0); 466747#L907-1 assume !(1 == ~E_3~0); 467051#L912-1 assume !(1 == ~E_4~0); 467042#L917-1 assume !(1 == ~E_5~0); 467043#L922-1 assume !(1 == ~E_6~0); 467252#L927-1 assume !(1 == ~E_7~0); 467027#L932-1 assume { :end_inline_reset_delta_events } true; 467028#L1178-2 [2024-10-31 22:18:21,101 INFO L747 eck$LassoCheckResult]: Loop: 467028#L1178-2 assume !false; 478397#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 478395#L744-1 assume !false; 478386#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 478347#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 478336#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 478334#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 478331#L641 assume !(0 != eval_~tmp~0#1); 478332#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 480200#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 480196#L769-3 assume !(0 == ~M_E~0); 480154#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 480153#L774-3 assume !(0 == ~T2_E~0); 480150#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 480146#L784-3 assume !(0 == ~T4_E~0); 480141#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 480137#L794-3 assume !(0 == ~T6_E~0); 478855#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 478854#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 478853#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 478852#L814-3 assume !(0 == ~E_2~0); 478851#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 478850#L824-3 assume !(0 == ~E_4~0); 478849#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 478848#L834-3 assume !(0 == ~E_6~0); 478847#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 478846#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 478845#L376-27 assume !(1 == ~m_pc~0); 478844#L376-29 is_master_triggered_~__retres1~0#1 := 0; 478841#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 478840#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 478839#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 478838#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 478837#L395-27 assume !(1 == ~t1_pc~0); 478836#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 478835#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 478834#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 478833#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 478832#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 478831#L414-27 assume !(1 == ~t2_pc~0); 478830#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 478828#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 478827#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 478826#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 478825#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 478824#L433-27 assume !(1 == ~t3_pc~0); 478823#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 478822#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 478821#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 478820#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 478819#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 478817#L452-27 assume !(1 == ~t4_pc~0); 478815#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 478814#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 478813#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 478812#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 478811#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478810#L471-27 assume !(1 == ~t5_pc~0); 478808#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 478805#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 478803#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 478801#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 478799#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 478797#L490-27 assume !(1 == ~t6_pc~0); 478795#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 478792#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 478790#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 478788#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 478786#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 478784#L509-27 assume 1 == ~t7_pc~0; 478782#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 478783#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 478818#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 478772#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 478770#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 478768#L857-3 assume !(1 == ~M_E~0); 471017#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 478765#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 478763#L867-3 assume !(1 == ~T3_E~0); 478761#L872-3 assume !(1 == ~T4_E~0); 478759#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 478757#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 478754#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 478752#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 478750#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 478748#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 478746#L907-3 assume !(1 == ~E_3~0); 478744#L912-3 assume !(1 == ~E_4~0); 478742#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 478740#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 478738#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 478736#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 478734#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 478725#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 478723#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 471119#L1197 assume !(0 == start_simulation_~tmp~3#1); 471120#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 478717#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 478708#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 478706#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 478702#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 478700#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 478698#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 478696#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 467028#L1178-2 [2024-10-31 22:18:21,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:21,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2024-10-31 22:18:21,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:21,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061263786] [2024-10-31 22:18:21,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:21,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:21,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:21,124 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:21,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:21,199 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:21,199 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:21,200 INFO L85 PathProgramCache]: Analyzing trace with hash 1874755417, now seen corresponding path program 1 times [2024-10-31 22:18:21,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:21,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186700032] [2024-10-31 22:18:21,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:21,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:21,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:21,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:21,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:21,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186700032] [2024-10-31 22:18:21,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186700032] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:21,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:21,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:21,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1356889222] [2024-10-31 22:18:21,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:21,252 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:21,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:21,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:21,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:21,252 INFO L87 Difference]: Start difference. First operand 19046 states and 26766 transitions. cyclomatic complexity: 7736 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:21,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:21,386 INFO L93 Difference]: Finished difference Result 21486 states and 30175 transitions. [2024-10-31 22:18:21,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21486 states and 30175 transitions. [2024-10-31 22:18:21,481 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21200 [2024-10-31 22:18:21,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21486 states to 21486 states and 30175 transitions. [2024-10-31 22:18:21,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21486 [2024-10-31 22:18:21,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21486 [2024-10-31 22:18:21,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21486 states and 30175 transitions. [2024-10-31 22:18:21,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:21,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21486 states and 30175 transitions. [2024-10-31 22:18:21,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21486 states and 30175 transitions. [2024-10-31 22:18:21,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21486 to 21486. [2024-10-31 22:18:21,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21486 states, 21486 states have (on average 1.4044028669831519) internal successors, (30175), 21485 states have internal predecessors, (30175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:21,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21486 states to 21486 states and 30175 transitions. [2024-10-31 22:18:21,890 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21486 states and 30175 transitions. [2024-10-31 22:18:21,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:21,891 INFO L425 stractBuchiCegarLoop]: Abstraction has 21486 states and 30175 transitions. [2024-10-31 22:18:21,891 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-31 22:18:21,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21486 states and 30175 transitions. [2024-10-31 22:18:21,963 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21200 [2024-10-31 22:18:21,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:21,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:21,965 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:21,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:21,966 INFO L745 eck$LassoCheckResult]: Stem: 507110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 507111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 507759#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 507760#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 507722#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 507723#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 507368#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 507180#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 507181#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 507162#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 507163#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 507719#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 507506#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 507507#L769 assume !(0 == ~M_E~0); 507528#L769-2 assume !(0 == ~T1_E~0); 507529#L774-1 assume !(0 == ~T2_E~0); 507561#L779-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 507802#L784-1 assume !(0 == ~T4_E~0); 507504#L789-1 assume !(0 == ~T5_E~0); 507505#L794-1 assume !(0 == ~T6_E~0); 507621#L799-1 assume !(0 == ~T7_E~0); 507883#L804-1 assume !(0 == ~E_M~0); 507915#L809-1 assume !(0 == ~E_1~0); 507731#L814-1 assume !(0 == ~E_2~0); 507732#L819-1 assume !(0 == ~E_3~0); 507253#L824-1 assume !(0 == ~E_4~0); 507254#L829-1 assume !(0 == ~E_5~0); 507800#L834-1 assume !(0 == ~E_6~0); 507031#L839-1 assume !(0 == ~E_7~0); 507032#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 507626#L376 assume !(1 == ~m_pc~0); 507441#L376-2 is_master_triggered_~__retres1~0#1 := 0; 507440#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 507681#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 507682#L955 assume !(0 != activate_threads_~tmp~1#1); 507912#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 507530#L395 assume !(1 == ~t1_pc~0); 507531#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 507706#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 507707#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 507746#L963 assume !(0 != activate_threads_~tmp___0~0#1); 507747#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 507911#L414 assume !(1 == ~t2_pc~0); 507034#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 507035#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 507262#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 507263#L971 assume !(0 != activate_threads_~tmp___1~0#1); 507807#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 507365#L433 assume !(1 == ~t3_pc~0); 507152#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 507153#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 507908#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 507907#L979 assume !(0 != activate_threads_~tmp___2~0#1); 507906#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 507862#L452 assume !(1 == ~t4_pc~0); 507848#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 507491#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 506994#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 506995#L987 assume !(0 != activate_threads_~tmp___3~0#1); 507190#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 507191#L471 assume !(1 == ~t5_pc~0); 507605#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 507175#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 507176#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 507879#L995 assume !(0 != activate_threads_~tmp___4~0#1); 507880#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 507833#L490 assume !(1 == ~t6_pc~0); 507834#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 507496#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 507497#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 507899#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 507898#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 507897#L509 assume !(1 == ~t7_pc~0); 507896#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 507902#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 507856#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 507857#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 507891#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 507890#L857 assume !(1 == ~M_E~0); 507889#L857-2 assume !(1 == ~T1_E~0); 507266#L862-1 assume !(1 == ~T2_E~0); 507267#L867-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 507272#L872-1 assume !(1 == ~T4_E~0); 507366#L877-1 assume !(1 == ~T5_E~0); 507581#L882-1 assume !(1 == ~T6_E~0); 507766#L887-1 assume !(1 == ~T7_E~0); 507645#L892-1 assume !(1 == ~E_M~0); 507646#L897-1 assume !(1 == ~E_1~0); 507292#L902-1 assume !(1 == ~E_2~0); 507293#L907-1 assume !(1 == ~E_3~0); 507597#L912-1 assume !(1 == ~E_4~0); 507588#L917-1 assume !(1 == ~E_5~0); 507589#L922-1 assume !(1 == ~E_6~0); 507803#L927-1 assume !(1 == ~E_7~0); 507576#L932-1 assume { :end_inline_reset_delta_events } true; 507577#L1178-2 [2024-10-31 22:18:21,967 INFO L747 eck$LassoCheckResult]: Loop: 507577#L1178-2 assume !false; 511639#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 511638#L744-1 assume !false; 511637#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 511636#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 511627#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 511625#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 511622#L641 assume !(0 != eval_~tmp~0#1); 511620#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 511618#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 511616#L769-3 assume !(0 == ~M_E~0); 511614#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 511612#L774-3 assume !(0 == ~T2_E~0); 511609#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 511607#L784-3 assume !(0 == ~T4_E~0); 511605#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 511603#L794-3 assume !(0 == ~T6_E~0); 511601#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 511598#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 511596#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 511594#L814-3 assume !(0 == ~E_2~0); 511592#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 511590#L824-3 assume !(0 == ~E_4~0); 511588#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 511586#L834-3 assume !(0 == ~E_6~0); 511584#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 511582#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 511580#L376-27 assume !(1 == ~m_pc~0); 511578#L376-29 is_master_triggered_~__retres1~0#1 := 0; 511575#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 511572#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 511570#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 511568#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 511566#L395-27 assume !(1 == ~t1_pc~0); 511564#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 511562#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 511560#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 511558#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 511556#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 511554#L414-27 assume !(1 == ~t2_pc~0); 511552#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 511548#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 511546#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 511544#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 511542#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 511540#L433-27 assume !(1 == ~t3_pc~0); 511538#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 511536#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 511534#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 511532#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 511530#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 511528#L452-27 assume !(1 == ~t4_pc~0); 511525#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 511523#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 511521#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 511519#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 511517#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 511515#L471-27 assume !(1 == ~t5_pc~0); 511513#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 511509#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 511507#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 511505#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 511503#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 511500#L490-27 assume !(1 == ~t6_pc~0); 511498#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 511496#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 511495#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 511493#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 511492#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 511491#L509-27 assume 1 == ~t7_pc~0; 511490#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 511488#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 511486#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 511483#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 511482#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 511480#L857-3 assume !(1 == ~M_E~0); 511131#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 511476#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 511474#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 511471#L872-3 assume !(1 == ~T4_E~0); 511469#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 511467#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 511465#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 511463#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 511461#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 511459#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 511457#L907-3 assume !(1 == ~E_3~0); 511455#L912-3 assume !(1 == ~E_4~0); 511452#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 511450#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 511448#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 511446#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 511444#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 511435#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 511433#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 511430#L1197 assume !(0 == start_simulation_~tmp~3#1); 511431#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 511781#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 511773#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 511772#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 511771#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 511770#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 511769#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 511768#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 507577#L1178-2 [2024-10-31 22:18:21,967 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:21,968 INFO L85 PathProgramCache]: Analyzing trace with hash -1895340795, now seen corresponding path program 1 times [2024-10-31 22:18:21,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:21,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222883760] [2024-10-31 22:18:21,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:21,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:21,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:22,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:22,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:22,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222883760] [2024-10-31 22:18:22,038 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222883760] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:22,038 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:22,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:22,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1957524772] [2024-10-31 22:18:22,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:22,039 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:22,039 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:22,040 INFO L85 PathProgramCache]: Analyzing trace with hash 1812715803, now seen corresponding path program 1 times [2024-10-31 22:18:22,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:22,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731504358] [2024-10-31 22:18:22,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:22,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:22,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:22,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:22,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:22,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [731504358] [2024-10-31 22:18:22,096 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [731504358] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:22,096 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:22,096 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:22,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105283962] [2024-10-31 22:18:22,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:22,097 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:22,097 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:22,097 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:22,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:22,098 INFO L87 Difference]: Start difference. First operand 21486 states and 30175 transitions. cyclomatic complexity: 8705 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:22,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:22,310 INFO L93 Difference]: Finished difference Result 27803 states and 38940 transitions. [2024-10-31 22:18:22,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27803 states and 38940 transitions. [2024-10-31 22:18:22,636 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27520 [2024-10-31 22:18:22,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27803 states to 27803 states and 38940 transitions. [2024-10-31 22:18:22,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27803 [2024-10-31 22:18:22,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27803 [2024-10-31 22:18:22,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27803 states and 38940 transitions. [2024-10-31 22:18:22,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:22,805 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27803 states and 38940 transitions. [2024-10-31 22:18:22,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27803 states and 38940 transitions. [2024-10-31 22:18:23,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27803 to 19046. [2024-10-31 22:18:23,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19046 states, 19046 states have (on average 1.4036018061535231) internal successors, (26733), 19045 states have internal predecessors, (26733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:23,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19046 states to 19046 states and 26733 transitions. [2024-10-31 22:18:23,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19046 states and 26733 transitions. [2024-10-31 22:18:23,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:23,213 INFO L425 stractBuchiCegarLoop]: Abstraction has 19046 states and 26733 transitions. [2024-10-31 22:18:23,213 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-31 22:18:23,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19046 states and 26733 transitions. [2024-10-31 22:18:23,283 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18832 [2024-10-31 22:18:23,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:23,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:23,286 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:23,286 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:23,287 INFO L745 eck$LassoCheckResult]: Stem: 556407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 556408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 557041#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 557042#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 557008#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 557009#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 556659#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 556479#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 556480#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 556461#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 556462#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 557007#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 556787#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 556788#L769 assume !(0 == ~M_E~0); 556809#L769-2 assume !(0 == ~T1_E~0); 556810#L774-1 assume !(0 == ~T2_E~0); 556843#L779-1 assume !(0 == ~T3_E~0); 556989#L784-1 assume !(0 == ~T4_E~0); 556785#L789-1 assume !(0 == ~T5_E~0); 556786#L794-1 assume !(0 == ~T6_E~0); 556906#L799-1 assume !(0 == ~T7_E~0); 556790#L804-1 assume !(0 == ~E_M~0); 556791#L809-1 assume !(0 == ~E_1~0); 556834#L814-1 assume !(0 == ~E_2~0); 556197#L819-1 assume !(0 == ~E_3~0); 556198#L824-1 assume !(0 == ~E_4~0); 556552#L829-1 assume !(0 == ~E_5~0); 557085#L834-1 assume !(0 == ~E_6~0); 556331#L839-1 assume !(0 == ~E_7~0); 556332#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 556739#L376 assume !(1 == ~m_pc~0); 556724#L376-2 is_master_triggered_~__retres1~0#1 := 0; 556723#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 556968#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 556274#L955 assume !(0 != activate_threads_~tmp~1#1); 556275#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 556652#L395 assume !(1 == ~t1_pc~0); 556811#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 556969#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 556227#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 556228#L963 assume !(0 != activate_threads_~tmp___0~0#1); 556743#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 556744#L414 assume !(1 == ~t2_pc~0); 556334#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 556335#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 556559#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 556560#L971 assume !(0 != activate_threads_~tmp___1~0#1); 557016#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 556656#L433 assume !(1 == ~t3_pc~0); 556448#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 556449#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 556195#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 556196#L979 assume !(0 != activate_threads_~tmp___2~0#1); 556300#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 556301#L452 assume !(1 == ~t4_pc~0); 556457#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 556458#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 556294#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 556295#L987 assume !(0 != activate_threads_~tmp___3~0#1); 556490#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 556491#L471 assume !(1 == ~t5_pc~0); 556886#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 556472#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 556473#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 556973#L995 assume !(0 != activate_threads_~tmp___4~0#1); 557074#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 557075#L490 assume !(1 == ~t6_pc~0); 556741#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 556742#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 556546#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 556547#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 556666#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 556632#L509 assume !(1 == ~t7_pc~0); 556633#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 557017#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 557136#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 556497#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 556498#L1011-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 557027#L857 assume !(1 == ~M_E~0); 556281#L857-2 assume !(1 == ~T1_E~0); 556282#L862-1 assume !(1 == ~T2_E~0); 556563#L867-1 assume !(1 == ~T3_E~0); 556568#L872-1 assume !(1 == ~T4_E~0); 556657#L877-1 assume !(1 == ~T5_E~0); 556864#L882-1 assume !(1 == ~T6_E~0); 557045#L887-1 assume !(1 == ~T7_E~0); 556929#L892-1 assume !(1 == ~E_M~0); 556930#L897-1 assume !(1 == ~E_1~0); 556584#L902-1 assume !(1 == ~E_2~0); 556585#L907-1 assume !(1 == ~E_3~0); 556877#L912-1 assume !(1 == ~E_4~0); 556870#L917-1 assume !(1 == ~E_5~0); 556871#L922-1 assume !(1 == ~E_6~0); 557088#L927-1 assume !(1 == ~E_7~0); 556859#L932-1 assume { :end_inline_reset_delta_events } true; 556860#L1178-2 [2024-10-31 22:18:23,287 INFO L747 eck$LassoCheckResult]: Loop: 556860#L1178-2 assume !false; 565355#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 565353#L744-1 assume !false; 565351#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 565348#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 565331#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 565330#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 565326#L641 assume !(0 != eval_~tmp~0#1); 565327#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 567600#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 567598#L769-3 assume !(0 == ~M_E~0); 567596#L769-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 567594#L774-3 assume !(0 == ~T2_E~0); 567592#L779-3 assume !(0 == ~T3_E~0); 567590#L784-3 assume !(0 == ~T4_E~0); 567588#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 567586#L794-3 assume !(0 == ~T6_E~0); 567584#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 567581#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 567579#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 567577#L814-3 assume !(0 == ~E_2~0); 567575#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 567573#L824-3 assume !(0 == ~E_4~0); 567572#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 567568#L834-3 assume !(0 == ~E_6~0); 567566#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 567564#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567562#L376-27 assume 1 == ~m_pc~0; 567558#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 567556#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567555#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 567554#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 567550#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567548#L395-27 assume !(1 == ~t1_pc~0); 567546#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 567545#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567542#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 567541#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 567540#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567537#L414-27 assume 1 == ~t2_pc~0; 567533#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 567531#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567529#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567527#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 567525#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567523#L433-27 assume !(1 == ~t3_pc~0); 567522#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 567294#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567293#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 567292#L979-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 567291#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567289#L452-27 assume !(1 == ~t4_pc~0); 567286#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 567284#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567282#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 567280#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 567278#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567276#L471-27 assume !(1 == ~t5_pc~0); 567274#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 567272#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567270#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 567268#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 567266#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 567264#L490-27 assume !(1 == ~t6_pc~0); 567262#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 567260#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 567258#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 567256#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 567254#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 567252#L509-27 assume 1 == ~t7_pc~0; 567248#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 567245#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 567242#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 567239#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 567237#L1011-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567231#L857-3 assume !(1 == ~M_E~0); 562057#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 567227#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 567225#L867-3 assume !(1 == ~T3_E~0); 567223#L872-3 assume !(1 == ~T4_E~0); 567221#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 567182#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 567178#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 567175#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 567172#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 567169#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 567166#L907-3 assume !(1 == ~E_3~0); 567162#L912-3 assume !(1 == ~E_4~0); 567159#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 567157#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 567145#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 567142#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 567140#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 567131#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 567129#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 562209#L1197 assume !(0 == start_simulation_~tmp~3#1); 562210#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 566088#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 566079#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 566077#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 566075#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 566073#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 565961#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 565956#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 556860#L1178-2 [2024-10-31 22:18:23,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:23,288 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2024-10-31 22:18:23,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:23,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643781011] [2024-10-31 22:18:23,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:23,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:23,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:23,307 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:23,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:23,356 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:23,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:23,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1398844377, now seen corresponding path program 1 times [2024-10-31 22:18:23,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:23,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398010799] [2024-10-31 22:18:23,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:23,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:23,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:23,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:23,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:23,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398010799] [2024-10-31 22:18:23,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398010799] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:23,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:23,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:23,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986141318] [2024-10-31 22:18:23,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:23,424 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:23,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:23,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:23,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:23,425 INFO L87 Difference]: Start difference. First operand 19046 states and 26733 transitions. cyclomatic complexity: 7703 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:23,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:23,688 INFO L93 Difference]: Finished difference Result 28590 states and 39943 transitions. [2024-10-31 22:18:23,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28590 states and 39943 transitions. [2024-10-31 22:18:23,831 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28256 [2024-10-31 22:18:23,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28590 states to 28590 states and 39943 transitions. [2024-10-31 22:18:23,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28590 [2024-10-31 22:18:23,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28590 [2024-10-31 22:18:23,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28590 states and 39943 transitions. [2024-10-31 22:18:23,972 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:23,972 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28590 states and 39943 transitions. [2024-10-31 22:18:23,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28590 states and 39943 transitions. [2024-10-31 22:18:24,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28590 to 28574. [2024-10-31 22:18:24,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28574 states, 28574 states have (on average 1.3973192412682858) internal successors, (39927), 28573 states have internal predecessors, (39927), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)