./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:05:37,137 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:05:37,207 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:05:37,212 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:05:37,212 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:05:37,237 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:05:37,238 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:05:37,238 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:05:37,239 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:05:37,240 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:05:37,241 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:05:37,241 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:05:37,242 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:05:37,242 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:05:37,243 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:05:37,243 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:05:37,244 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:05:37,244 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:05:37,244 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:05:37,245 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:05:37,245 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:05:37,246 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:05:37,246 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:05:37,247 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:05:37,247 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:05:37,247 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:05:37,248 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:05:37,248 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:05:37,248 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:05:37,249 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:05:37,261 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:05:37,261 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:05:37,262 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:05:37,262 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:05:37,262 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:05:37,263 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:05:37,263 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:05:37,264 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:05:37,264 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:05:37,265 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2024-10-31 22:05:37,590 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:05:37,629 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:05:37,633 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:05:37,636 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:05:37,637 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:05:37,638 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c Unable to find full path for "g++" [2024-10-31 22:05:39,978 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:05:40,282 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:05:40,283 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2024-10-31 22:05:40,303 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/data/31079087a/17babb4e3a0745baadc6725c860ca0a8/FLAGf5b1db54a [2024-10-31 22:05:40,322 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/data/31079087a/17babb4e3a0745baadc6725c860ca0a8 [2024-10-31 22:05:40,325 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:05:40,327 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:05:40,329 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:05:40,329 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:05:40,337 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:05:40,338 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:40,340 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@66516f72 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40, skipping insertion in model container [2024-10-31 22:05:40,340 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:40,395 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:05:40,733 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:05:40,762 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:05:40,834 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:05:40,870 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:05:40,871 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40 WrapperNode [2024-10-31 22:05:40,871 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:05:40,872 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:05:40,872 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:05:40,872 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:05:40,879 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:40,891 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:40,978 INFO L138 Inliner]: procedures = 42, calls = 54, calls flagged for inlining = 49, calls inlined = 137, statements flattened = 2020 [2024-10-31 22:05:40,978 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:05:40,979 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:05:40,980 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:05:40,980 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:05:40,994 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:40,994 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:41,001 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:41,040 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:05:41,040 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:41,041 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:41,084 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:41,112 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:41,117 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:41,123 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:41,134 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:05:41,135 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:05:41,136 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:05:41,136 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:05:41,137 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (1/1) ... [2024-10-31 22:05:41,145 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:05:41,162 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:05:41,184 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:05:41,198 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_00aba30e-9a86-442b-81bc-f25138fd5b84/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:05:41,234 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:05:41,235 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:05:41,235 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:05:41,235 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:05:41,358 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:05:41,361 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:05:43,753 INFO L? ?]: Removed 396 outVars from TransFormulas that were not future-live. [2024-10-31 22:05:43,755 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:05:43,819 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:05:43,819 INFO L316 CfgBuilder]: Removed 10 assume(true) statements. [2024-10-31 22:05:43,820 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:05:43 BoogieIcfgContainer [2024-10-31 22:05:43,820 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:05:43,821 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:05:43,821 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:05:43,829 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:05:43,831 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:05:43,831 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:05:40" (1/3) ... [2024-10-31 22:05:43,832 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1798087b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:05:43, skipping insertion in model container [2024-10-31 22:05:43,832 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:05:43,832 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:05:40" (2/3) ... [2024-10-31 22:05:43,835 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1798087b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:05:43, skipping insertion in model container [2024-10-31 22:05:43,835 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:05:43,836 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:05:43" (3/3) ... [2024-10-31 22:05:43,837 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2024-10-31 22:05:43,951 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:05:43,955 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:05:43,955 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:05:43,955 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:05:43,955 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:05:43,956 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:05:43,956 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:05:43,956 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:05:43,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:44,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2024-10-31 22:05:44,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:44,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:44,054 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:44,054 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:44,054 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:05:44,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:44,073 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2024-10-31 22:05:44,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:44,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:44,079 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:44,079 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:44,090 INFO L745 eck$LassoCheckResult]: Stem: 127#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 784#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 622#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 782#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 807#L548true assume !(1 == ~m_i~0);~m_st~0 := 2; 213#L548-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 401#L553-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 295#L558-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 760#L563-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 153#L568-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 41#L573-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 791#L578-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 130#L583-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 505#L781true assume !(0 == ~M_E~0); 822#L781-2true assume !(0 == ~T1_E~0); 846#L786-1true assume !(0 == ~T2_E~0); 21#L791-1true assume !(0 == ~T3_E~0); 385#L796-1true assume !(0 == ~T4_E~0); 355#L801-1true assume !(0 == ~T5_E~0); 387#L806-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 766#L811-1true assume !(0 == ~T7_E~0); 134#L816-1true assume !(0 == ~E_M~0); 626#L821-1true assume !(0 == ~E_1~0); 37#L826-1true assume !(0 == ~E_2~0); 353#L831-1true assume !(0 == ~E_3~0); 210#L836-1true assume !(0 == ~E_4~0); 507#L841-1true assume !(0 == ~E_5~0); 107#L846-1true assume 0 == ~E_6~0;~E_6~0 := 1; 799#L851-1true assume !(0 == ~E_7~0); 119#L856-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 651#L388true assume !(1 == ~m_pc~0); 116#L388-2true is_master_triggered_~__retres1~0#1 := 0; 478#L399true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 545#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44#L967true assume !(0 != activate_threads_~tmp~1#1); 767#L967-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11#L407true assume 1 == ~t1_pc~0; 414#L408true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13#L418true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 618#L975true assume !(0 != activate_threads_~tmp___0~0#1); 644#L975-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 184#L426true assume !(1 == ~t2_pc~0); 662#L426-2true is_transmit2_triggered_~__retres1~2#1 := 0; 753#L437true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 745#L983true assume !(0 != activate_threads_~tmp___1~0#1); 847#L983-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 241#L445true assume 1 == ~t3_pc~0; 838#L446true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 517#L456true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 441#L991true assume !(0 != activate_threads_~tmp___2~0#1); 512#L991-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 415#L464true assume !(1 == ~t4_pc~0); 121#L464-2true is_transmit4_triggered_~__retres1~4#1 := 0; 52#L475true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 845#L999true assume !(0 != activate_threads_~tmp___3~0#1); 227#L999-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410#L483true assume 1 == ~t5_pc~0; 737#L484true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 593#L494true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 701#L1007true assume !(0 != activate_threads_~tmp___4~0#1); 175#L1007-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 461#L502true assume 1 == ~t6_pc~0; 383#L503true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73#L513true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 322#L1015true assume !(0 != activate_threads_~tmp___5~0#1); 560#L1015-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 711#L521true assume !(1 == ~t7_pc~0); 666#L521-2true is_transmit7_triggered_~__retres1~7#1 := 0; 42#L532true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 800#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 607#L1023true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 569#L1023-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 469#L869true assume !(1 == ~M_E~0); 223#L869-2true assume !(1 == ~T1_E~0); 738#L874-1true assume !(1 == ~T2_E~0); 686#L879-1true assume !(1 == ~T3_E~0); 272#L884-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 5#L889-1true assume !(1 == ~T5_E~0); 139#L894-1true assume !(1 == ~T6_E~0); 836#L899-1true assume !(1 == ~T7_E~0); 431#L904-1true assume !(1 == ~E_M~0); 239#L909-1true assume !(1 == ~E_1~0); 371#L914-1true assume !(1 == ~E_2~0); 394#L919-1true assume !(1 == ~E_3~0); 183#L924-1true assume 1 == ~E_4~0;~E_4~0 := 2; 90#L929-1true assume !(1 == ~E_5~0); 705#L934-1true assume !(1 == ~E_6~0); 225#L939-1true assume !(1 == ~E_7~0); 559#L944-1true assume { :end_inline_reset_delta_events } true; 555#L1190-2true [2024-10-31 22:05:44,093 INFO L747 eck$LassoCheckResult]: Loop: 555#L1190-2true assume !false; 135#L1191true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136#L756-1true assume false; 491#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 302#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 398#L781-3true assume 0 == ~M_E~0;~M_E~0 := 1; 59#L781-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 253#L786-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 308#L791-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 34#L796-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 632#L801-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L806-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 303#L811-3true assume !(0 == ~T7_E~0); 497#L816-3true assume 0 == ~E_M~0;~E_M~0 := 1; 663#L821-3true assume 0 == ~E_1~0;~E_1~0 := 1; 777#L826-3true assume 0 == ~E_2~0;~E_2~0 := 1; 437#L831-3true assume 0 == ~E_3~0;~E_3~0 := 1; 679#L836-3true assume 0 == ~E_4~0;~E_4~0 := 1; 112#L841-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L846-3true assume 0 == ~E_6~0;~E_6~0 := 1; 321#L851-3true assume !(0 == ~E_7~0); 55#L856-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 759#L388-27true assume 1 == ~m_pc~0; 608#L389-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 773#L399-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 458#is_master_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 709#L967-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L967-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 459#L407-27true assume 1 == ~t1_pc~0; 442#L408-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 540#L418-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 482#L975-27true assume !(0 != activate_threads_~tmp___0~0#1); 337#L975-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108#L426-27true assume !(1 == ~t2_pc~0); 851#L426-29true is_transmit2_triggered_~__retres1~2#1 := 0; 113#L437-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 438#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 707#L983-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 602#L983-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 298#L445-27true assume 1 == ~t3_pc~0; 278#L446-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32#L456-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 854#L991-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 376#L991-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171#L464-27true assume 1 == ~t4_pc~0; 483#L465-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65#L475-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304#L999-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104#L999-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796#L483-27true assume !(1 == ~t5_pc~0); 587#L483-29true is_transmit5_triggered_~__retres1~5#1 := 0; 56#L494-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 563#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552#L1007-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 824#L1007-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 717#L502-27true assume !(1 == ~t6_pc~0); 317#L502-29true is_transmit6_triggered_~__retres1~6#1 := 0; 706#L513-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 690#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 464#L1015-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 750#L1015-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6#L521-27true assume 1 == ~t7_pc~0; 193#L522-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 785#L532-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 162#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30#L1023-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 328#L1023-29true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 678#L869-3true assume 1 == ~M_E~0;~M_E~0 := 2; 462#L869-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 252#L874-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 291#L879-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 320#L884-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 284#L889-3true assume !(1 == ~T5_E~0); 85#L894-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 425#L899-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 97#L904-3true assume 1 == ~E_M~0;~E_M~0 := 2; 269#L909-3true assume 1 == ~E_1~0;~E_1~0 := 2; 74#L914-3true assume 1 == ~E_2~0;~E_2~0 := 2; 94#L919-3true assume 1 == ~E_3~0;~E_3~0 := 2; 619#L924-3true assume 1 == ~E_4~0;~E_4~0 := 2; 448#L929-3true assume !(1 == ~E_5~0); 374#L934-3true assume 1 == ~E_6~0;~E_6~0 := 2; 565#L939-3true assume 1 == ~E_7~0;~E_7~0 := 2; 100#L944-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 601#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 674#L638-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 169#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 790#L1209true assume !(0 == start_simulation_~tmp~3#1); 314#L1209-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 301#L596-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 544#L638-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 609#L1164true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25#L1171true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 315#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 128#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 555#L1190-2true [2024-10-31 22:05:44,101 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:44,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2024-10-31 22:05:44,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:44,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768310497] [2024-10-31 22:05:44,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:44,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:44,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:44,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:44,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:44,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768310497] [2024-10-31 22:05:44,533 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768310497] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:44,533 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:44,533 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:44,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164250015] [2024-10-31 22:05:44,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:44,544 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:44,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:44,546 INFO L85 PathProgramCache]: Analyzing trace with hash -41697262, now seen corresponding path program 1 times [2024-10-31 22:05:44,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:44,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608183589] [2024-10-31 22:05:44,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:44,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:44,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:44,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:44,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:44,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1608183589] [2024-10-31 22:05:44,661 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1608183589] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:44,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:44,662 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:05:44,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857261827] [2024-10-31 22:05:44,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:44,664 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:44,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:44,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:44,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:44,705 INFO L87 Difference]: Start difference. First operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:44,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:44,782 INFO L93 Difference]: Finished difference Result 849 states and 1263 transitions. [2024-10-31 22:05:44,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 849 states and 1263 transitions. [2024-10-31 22:05:44,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:44,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 849 states to 843 states and 1257 transitions. [2024-10-31 22:05:44,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-10-31 22:05:44,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-10-31 22:05:44,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1257 transitions. [2024-10-31 22:05:44,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:44,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2024-10-31 22:05:44,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1257 transitions. [2024-10-31 22:05:44,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-10-31 22:05:44,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.491103202846975) internal successors, (1257), 842 states have internal predecessors, (1257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:44,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1257 transitions. [2024-10-31 22:05:44,888 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2024-10-31 22:05:44,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:44,894 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1257 transitions. [2024-10-31 22:05:44,894 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:05:44,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1257 transitions. [2024-10-31 22:05:44,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:44,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:44,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:44,906 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:44,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:44,910 INFO L745 eck$LassoCheckResult]: Stem: 1961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2549#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2104#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2105#L553-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2227#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2228#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2005#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1796#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1797#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1966#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1967#L781 assume !(0 == ~M_E~0); 2444#L781-2 assume !(0 == ~T1_E~0); 2552#L786-1 assume !(0 == ~T2_E~0); 1756#L791-1 assume !(0 == ~T3_E~0); 1757#L796-1 assume !(0 == ~T4_E~0); 2296#L801-1 assume !(0 == ~T5_E~0); 2297#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2327#L811-1 assume !(0 == ~T7_E~0); 1973#L816-1 assume !(0 == ~E_M~0); 1974#L821-1 assume !(0 == ~E_1~0); 1787#L826-1 assume !(0 == ~E_2~0); 1788#L831-1 assume !(0 == ~E_3~0); 2099#L836-1 assume !(0 == ~E_4~0); 2100#L841-1 assume !(0 == ~E_5~0); 1924#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1925#L851-1 assume !(0 == ~E_7~0); 1948#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1949#L388 assume !(1 == ~m_pc~0); 1942#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1943#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2422#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1802#L967 assume !(0 != activate_threads_~tmp~1#1); 1803#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1732#L407 assume 1 == ~t1_pc~0; 1733#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1737#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1773#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2507#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2059#L426 assume !(1 == ~t2_pc~0); 2060#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2524#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2082#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2545#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2145#L445 assume 1 == ~t3_pc~0; 2146#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2450#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1730#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1731#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2386#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2354#L464 assume !(1 == ~t4_pc~0); 1952#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1822#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1823#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1834#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2124#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2125#L483 assume 1 == ~t5_pc~0; 2350#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2490#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2463#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2464#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2042#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2043#L502 assume 1 == ~t6_pc~0; 2324#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1862#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1863#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2067#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2264#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2473#L521 assume !(1 == ~t7_pc~0); 2504#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1798#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1799#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2498#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2477#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2413#L869 assume !(1 == ~M_E~0); 2118#L869-2 assume !(1 == ~T1_E~0); 2119#L874-1 assume !(1 == ~T2_E~0); 2532#L879-1 assume !(1 == ~T3_E~0); 2193#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1718#L889-1 assume !(1 == ~T5_E~0); 1719#L894-1 assume !(1 == ~T6_E~0); 1981#L899-1 assume !(1 == ~T7_E~0); 2375#L904-1 assume !(1 == ~E_M~0); 2142#L909-1 assume !(1 == ~E_1~0); 2143#L914-1 assume !(1 == ~E_2~0); 2312#L919-1 assume !(1 == ~E_3~0); 2058#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1895#L929-1 assume !(1 == ~E_5~0); 1896#L934-1 assume !(1 == ~E_6~0); 2120#L939-1 assume !(1 == ~E_7~0); 2121#L944-1 assume { :end_inline_reset_delta_events } true; 1964#L1190-2 [2024-10-31 22:05:44,911 INFO L747 eck$LassoCheckResult]: Loop: 1964#L1190-2 assume !false; 1975#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1976#L756-1 assume !false; 1977#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2550#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1815#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2106#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2107#L653 assume !(0 != eval_~tmp~0#1); 2158#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2237#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2238#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1835#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1836#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2164#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1781#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1782#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2044#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2045#L811-3 assume !(0 == ~T7_E~0); 2239#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2436#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2525#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2379#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2380#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1935#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1936#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2263#L851-3 assume !(0 == ~E_7~0); 1829#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1830#L388-27 assume 1 == ~m_pc~0; 2499#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2500#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2403#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2404#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2008#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2009#L407-27 assume 1 == ~t1_pc~0; 2387#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2388#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2306#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2307#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 2280#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1926#L426-27 assume 1 == ~t2_pc~0; 1927#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1940#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1941#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2381#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2496#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2231#L445-27 assume 1 == ~t3_pc~0; 2205#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1778#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1779#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2232#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2317#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2034#L464-27 assume !(1 == ~t4_pc~0); 1776#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1777#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1848#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2161#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1919#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1920#L483-27 assume 1 == ~t5_pc~0; 2455#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1831#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1832#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2468#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2469#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2536#L502-27 assume !(1 == ~t6_pc~0); 2257#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2258#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2533#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2409#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2410#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1720#L521-27 assume 1 == ~t7_pc~0; 1721#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2072#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2020#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1774#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1775#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2270#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2406#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2162#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2163#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2223#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2216#L889-3 assume !(1 == ~T5_E~0); 1885#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1886#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1906#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1907#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1864#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1865#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1901#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2393#L929-3 assume !(1 == ~E_5~0); 2314#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2315#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1911#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1912#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1740#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2031#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2032#L1209 assume !(0 == start_simulation_~tmp~3#1); 2253#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2236#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1879#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1770#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1765#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1766#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1963#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1964#L1190-2 [2024-10-31 22:05:44,912 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:44,912 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2024-10-31 22:05:44,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:44,913 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097607163] [2024-10-31 22:05:44,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:44,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:44,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:45,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:45,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:45,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097607163] [2024-10-31 22:05:45,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097607163] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:45,035 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:45,036 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:45,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427452384] [2024-10-31 22:05:45,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:45,037 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:45,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:45,038 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 1 times [2024-10-31 22:05:45,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:45,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429484606] [2024-10-31 22:05:45,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:45,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:45,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:45,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:45,225 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:45,225 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1429484606] [2024-10-31 22:05:45,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1429484606] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:45,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:45,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:45,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577088093] [2024-10-31 22:05:45,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:45,227 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:45,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:45,230 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:45,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:45,231 INFO L87 Difference]: Start difference. First operand 843 states and 1257 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:45,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:45,266 INFO L93 Difference]: Finished difference Result 843 states and 1256 transitions. [2024-10-31 22:05:45,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1256 transitions. [2024-10-31 22:05:45,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:45,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1256 transitions. [2024-10-31 22:05:45,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-10-31 22:05:45,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-10-31 22:05:45,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1256 transitions. [2024-10-31 22:05:45,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:45,291 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2024-10-31 22:05:45,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1256 transitions. [2024-10-31 22:05:45,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-10-31 22:05:45,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4899169632265719) internal successors, (1256), 842 states have internal predecessors, (1256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:45,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1256 transitions. [2024-10-31 22:05:45,331 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2024-10-31 22:05:45,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:45,333 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1256 transitions. [2024-10-31 22:05:45,333 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:05:45,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1256 transitions. [2024-10-31 22:05:45,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:45,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:45,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:45,343 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:45,343 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:45,344 INFO L745 eck$LassoCheckResult]: Stem: 3654#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4202#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4203#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4242#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3797#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3798#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3920#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3921#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3698#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3489#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3490#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3659#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3660#L781 assume !(0 == ~M_E~0); 4137#L781-2 assume !(0 == ~T1_E~0); 4245#L786-1 assume !(0 == ~T2_E~0); 3449#L791-1 assume !(0 == ~T3_E~0); 3450#L796-1 assume !(0 == ~T4_E~0); 3989#L801-1 assume !(0 == ~T5_E~0); 3990#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4020#L811-1 assume !(0 == ~T7_E~0); 3666#L816-1 assume !(0 == ~E_M~0); 3667#L821-1 assume !(0 == ~E_1~0); 3480#L826-1 assume !(0 == ~E_2~0); 3481#L831-1 assume !(0 == ~E_3~0); 3792#L836-1 assume !(0 == ~E_4~0); 3793#L841-1 assume !(0 == ~E_5~0); 3617#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3618#L851-1 assume !(0 == ~E_7~0); 3641#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3642#L388 assume !(1 == ~m_pc~0); 3635#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3636#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4115#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3495#L967 assume !(0 != activate_threads_~tmp~1#1); 3496#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3425#L407 assume 1 == ~t1_pc~0; 3426#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3430#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3431#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3466#L975 assume !(0 != activate_threads_~tmp___0~0#1); 4200#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3752#L426 assume !(1 == ~t2_pc~0); 3753#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4217#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3774#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3775#L983 assume !(0 != activate_threads_~tmp___1~0#1); 4238#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3838#L445 assume 1 == ~t3_pc~0; 3839#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4143#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3424#L991 assume !(0 != activate_threads_~tmp___2~0#1); 4079#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4047#L464 assume !(1 == ~t4_pc~0); 3645#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3515#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3516#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3527#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3817#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3818#L483 assume 1 == ~t5_pc~0; 4043#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4183#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4156#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4157#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3735#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3736#L502 assume 1 == ~t6_pc~0; 4017#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3555#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3556#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3760#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3957#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4166#L521 assume !(1 == ~t7_pc~0); 4197#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3491#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3492#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4191#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4170#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4106#L869 assume !(1 == ~M_E~0); 3811#L869-2 assume !(1 == ~T1_E~0); 3812#L874-1 assume !(1 == ~T2_E~0); 4225#L879-1 assume !(1 == ~T3_E~0); 3886#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3411#L889-1 assume !(1 == ~T5_E~0); 3412#L894-1 assume !(1 == ~T6_E~0); 3674#L899-1 assume !(1 == ~T7_E~0); 4068#L904-1 assume !(1 == ~E_M~0); 3835#L909-1 assume !(1 == ~E_1~0); 3836#L914-1 assume !(1 == ~E_2~0); 4005#L919-1 assume !(1 == ~E_3~0); 3751#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3588#L929-1 assume !(1 == ~E_5~0); 3589#L934-1 assume !(1 == ~E_6~0); 3813#L939-1 assume !(1 == ~E_7~0); 3814#L944-1 assume { :end_inline_reset_delta_events } true; 3657#L1190-2 [2024-10-31 22:05:45,344 INFO L747 eck$LassoCheckResult]: Loop: 3657#L1190-2 assume !false; 3668#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3669#L756-1 assume !false; 3670#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4243#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3508#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3799#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3800#L653 assume !(0 != eval_~tmp~0#1); 3851#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3930#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3931#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3528#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3529#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3857#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3474#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3475#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3737#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3738#L811-3 assume !(0 == ~T7_E~0); 3932#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4129#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4218#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4072#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4073#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3628#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3629#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3956#L851-3 assume !(0 == ~E_7~0); 3522#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3523#L388-27 assume 1 == ~m_pc~0; 4192#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4193#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4096#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4097#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3701#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3702#L407-27 assume 1 == ~t1_pc~0; 4080#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4081#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3999#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4000#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 3973#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3619#L426-27 assume 1 == ~t2_pc~0; 3620#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3633#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3634#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4074#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4189#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3924#L445-27 assume 1 == ~t3_pc~0; 3898#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3471#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3472#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3925#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4010#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3727#L464-27 assume 1 == ~t4_pc~0; 3728#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3470#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3541#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3854#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3612#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3613#L483-27 assume 1 == ~t5_pc~0; 4148#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3524#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3525#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4161#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4162#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4229#L502-27 assume 1 == ~t6_pc~0; 4230#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3951#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4226#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4102#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4103#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3413#L521-27 assume 1 == ~t7_pc~0; 3414#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3765#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3713#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3467#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3468#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3963#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4099#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3855#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3856#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3916#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3909#L889-3 assume !(1 == ~T5_E~0); 3578#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3579#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3599#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3600#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3557#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3558#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3594#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4086#L929-3 assume !(1 == ~E_5~0); 4007#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4008#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3604#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3605#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3433#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3724#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3725#L1209 assume !(0 == start_simulation_~tmp~3#1); 3946#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3929#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3572#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3462#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3463#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3458#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3459#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3656#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 3657#L1190-2 [2024-10-31 22:05:45,345 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:45,348 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2024-10-31 22:05:45,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:45,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841365845] [2024-10-31 22:05:45,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:45,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:45,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:45,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:45,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:45,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841365845] [2024-10-31 22:05:45,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841365845] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:45,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:45,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:45,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066571809] [2024-10-31 22:05:45,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:45,461 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:45,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:45,461 INFO L85 PathProgramCache]: Analyzing trace with hash -2135531812, now seen corresponding path program 1 times [2024-10-31 22:05:45,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:45,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729044167] [2024-10-31 22:05:45,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:45,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:45,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:45,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:45,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:45,584 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729044167] [2024-10-31 22:05:45,585 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729044167] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:45,585 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:45,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:45,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122953741] [2024-10-31 22:05:45,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:45,590 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:45,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:45,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:45,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:45,591 INFO L87 Difference]: Start difference. First operand 843 states and 1256 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:45,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:45,617 INFO L93 Difference]: Finished difference Result 843 states and 1255 transitions. [2024-10-31 22:05:45,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1255 transitions. [2024-10-31 22:05:45,625 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:45,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1255 transitions. [2024-10-31 22:05:45,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-10-31 22:05:45,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-10-31 22:05:45,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1255 transitions. [2024-10-31 22:05:45,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:45,635 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2024-10-31 22:05:45,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1255 transitions. [2024-10-31 22:05:45,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-10-31 22:05:45,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4887307236061684) internal successors, (1255), 842 states have internal predecessors, (1255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:45,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1255 transitions. [2024-10-31 22:05:45,654 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2024-10-31 22:05:45,655 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:45,656 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1255 transitions. [2024-10-31 22:05:45,657 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:05:45,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1255 transitions. [2024-10-31 22:05:45,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:45,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:45,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:45,666 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:45,666 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:45,667 INFO L745 eck$LassoCheckResult]: Stem: 5347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5895#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5896#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5935#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5490#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5491#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5613#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5614#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5391#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5182#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5183#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5352#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5353#L781 assume !(0 == ~M_E~0); 5830#L781-2 assume !(0 == ~T1_E~0); 5938#L786-1 assume !(0 == ~T2_E~0); 5142#L791-1 assume !(0 == ~T3_E~0); 5143#L796-1 assume !(0 == ~T4_E~0); 5682#L801-1 assume !(0 == ~T5_E~0); 5683#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5713#L811-1 assume !(0 == ~T7_E~0); 5359#L816-1 assume !(0 == ~E_M~0); 5360#L821-1 assume !(0 == ~E_1~0); 5173#L826-1 assume !(0 == ~E_2~0); 5174#L831-1 assume !(0 == ~E_3~0); 5485#L836-1 assume !(0 == ~E_4~0); 5486#L841-1 assume !(0 == ~E_5~0); 5310#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5311#L851-1 assume !(0 == ~E_7~0); 5334#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5335#L388 assume !(1 == ~m_pc~0); 5328#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5329#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5808#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5188#L967 assume !(0 != activate_threads_~tmp~1#1); 5189#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5118#L407 assume 1 == ~t1_pc~0; 5119#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5123#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5159#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5893#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5445#L426 assume !(1 == ~t2_pc~0); 5446#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5910#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5467#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5468#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5931#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5531#L445 assume 1 == ~t3_pc~0; 5532#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5836#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5117#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5772#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5740#L464 assume !(1 == ~t4_pc~0); 5338#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5208#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5209#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5220#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5510#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5511#L483 assume 1 == ~t5_pc~0; 5736#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5876#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5849#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5850#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5428#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5429#L502 assume 1 == ~t6_pc~0; 5710#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5248#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5453#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5650#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5859#L521 assume !(1 == ~t7_pc~0); 5890#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5184#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5185#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5884#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5863#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5799#L869 assume !(1 == ~M_E~0); 5504#L869-2 assume !(1 == ~T1_E~0); 5505#L874-1 assume !(1 == ~T2_E~0); 5918#L879-1 assume !(1 == ~T3_E~0); 5579#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5104#L889-1 assume !(1 == ~T5_E~0); 5105#L894-1 assume !(1 == ~T6_E~0); 5367#L899-1 assume !(1 == ~T7_E~0); 5761#L904-1 assume !(1 == ~E_M~0); 5528#L909-1 assume !(1 == ~E_1~0); 5529#L914-1 assume !(1 == ~E_2~0); 5698#L919-1 assume !(1 == ~E_3~0); 5444#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5281#L929-1 assume !(1 == ~E_5~0); 5282#L934-1 assume !(1 == ~E_6~0); 5506#L939-1 assume !(1 == ~E_7~0); 5507#L944-1 assume { :end_inline_reset_delta_events } true; 5350#L1190-2 [2024-10-31 22:05:45,668 INFO L747 eck$LassoCheckResult]: Loop: 5350#L1190-2 assume !false; 5361#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5362#L756-1 assume !false; 5363#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5936#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5201#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5492#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5493#L653 assume !(0 != eval_~tmp~0#1); 5544#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5624#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5221#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5222#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5550#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5167#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5168#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5430#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5431#L811-3 assume !(0 == ~T7_E~0); 5625#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5822#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5911#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5765#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5766#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5321#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5322#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5649#L851-3 assume !(0 == ~E_7~0); 5215#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5216#L388-27 assume 1 == ~m_pc~0; 5885#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5886#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5789#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5790#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5394#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5395#L407-27 assume 1 == ~t1_pc~0; 5773#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5774#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5692#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5693#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 5666#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5312#L426-27 assume 1 == ~t2_pc~0; 5313#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5326#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5327#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5767#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5882#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5617#L445-27 assume 1 == ~t3_pc~0; 5591#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5164#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5165#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5618#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5703#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5420#L464-27 assume !(1 == ~t4_pc~0); 5162#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5163#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5234#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5547#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5305#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5306#L483-27 assume 1 == ~t5_pc~0; 5841#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5217#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5218#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5854#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5855#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5922#L502-27 assume 1 == ~t6_pc~0; 5923#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5644#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5919#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5795#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5796#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5106#L521-27 assume 1 == ~t7_pc~0; 5107#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5458#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5406#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5160#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5161#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5656#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5792#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5548#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5549#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5609#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5602#L889-3 assume !(1 == ~T5_E~0); 5271#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5272#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5292#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5293#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5250#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5251#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5287#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5779#L929-3 assume !(1 == ~E_5~0); 5700#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5701#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5297#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5298#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5126#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5418#L1209 assume !(0 == start_simulation_~tmp~3#1); 5639#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5622#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5265#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5156#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5151#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5152#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5349#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5350#L1190-2 [2024-10-31 22:05:45,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:45,669 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2024-10-31 22:05:45,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:45,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760231580] [2024-10-31 22:05:45,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:45,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:45,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:45,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:45,745 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:45,745 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760231580] [2024-10-31 22:05:45,745 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760231580] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:45,745 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:45,746 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:45,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1311727777] [2024-10-31 22:05:45,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:45,748 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:45,749 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:45,749 INFO L85 PathProgramCache]: Analyzing trace with hash 1885656989, now seen corresponding path program 1 times [2024-10-31 22:05:45,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:45,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941158294] [2024-10-31 22:05:45,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:45,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:45,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:45,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:45,833 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:45,834 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941158294] [2024-10-31 22:05:45,834 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941158294] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:45,834 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:45,834 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:45,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360323778] [2024-10-31 22:05:45,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:45,835 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:45,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:45,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:45,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:45,836 INFO L87 Difference]: Start difference. First operand 843 states and 1255 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:45,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:45,858 INFO L93 Difference]: Finished difference Result 843 states and 1254 transitions. [2024-10-31 22:05:45,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1254 transitions. [2024-10-31 22:05:45,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:45,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1254 transitions. [2024-10-31 22:05:45,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-10-31 22:05:45,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-10-31 22:05:45,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1254 transitions. [2024-10-31 22:05:45,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:45,872 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2024-10-31 22:05:45,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1254 transitions. [2024-10-31 22:05:45,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-10-31 22:05:45,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4875444839857652) internal successors, (1254), 842 states have internal predecessors, (1254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:45,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1254 transitions. [2024-10-31 22:05:45,896 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2024-10-31 22:05:45,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:45,898 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1254 transitions. [2024-10-31 22:05:45,898 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:05:45,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1254 transitions. [2024-10-31 22:05:45,905 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:45,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:45,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:45,907 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:45,911 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:45,911 INFO L745 eck$LassoCheckResult]: Stem: 7040#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7588#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7589#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7628#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 7183#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7184#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7306#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7307#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7084#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6875#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6876#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7048#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7049#L781 assume !(0 == ~M_E~0); 7523#L781-2 assume !(0 == ~T1_E~0); 7631#L786-1 assume !(0 == ~T2_E~0); 6838#L791-1 assume !(0 == ~T3_E~0); 6839#L796-1 assume !(0 == ~T4_E~0); 7375#L801-1 assume !(0 == ~T5_E~0); 7376#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7406#L811-1 assume !(0 == ~T7_E~0); 7052#L816-1 assume !(0 == ~E_M~0); 7053#L821-1 assume !(0 == ~E_1~0); 6866#L826-1 assume !(0 == ~E_2~0); 6867#L831-1 assume !(0 == ~E_3~0); 7178#L836-1 assume !(0 == ~E_4~0); 7179#L841-1 assume !(0 == ~E_5~0); 7003#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7004#L851-1 assume !(0 == ~E_7~0); 7027#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7028#L388 assume !(1 == ~m_pc~0); 7021#L388-2 is_master_triggered_~__retres1~0#1 := 0; 7022#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7501#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6881#L967 assume !(0 != activate_threads_~tmp~1#1); 6882#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6811#L407 assume 1 == ~t1_pc~0; 6812#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6819#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6820#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6854#L975 assume !(0 != activate_threads_~tmp___0~0#1); 7586#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7138#L426 assume !(1 == ~t2_pc~0); 7139#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7603#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7160#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7161#L983 assume !(0 != activate_threads_~tmp___1~0#1); 7624#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7224#L445 assume 1 == ~t3_pc~0; 7225#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7529#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6809#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6810#L991 assume !(0 != activate_threads_~tmp___2~0#1); 7465#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7433#L464 assume !(1 == ~t4_pc~0); 7031#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6901#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6902#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6913#L999 assume !(0 != activate_threads_~tmp___3~0#1); 7203#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7204#L483 assume 1 == ~t5_pc~0; 7429#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7569#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7543#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 7123#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7124#L502 assume 1 == ~t6_pc~0; 7404#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6941#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6942#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7148#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 7343#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7552#L521 assume !(1 == ~t7_pc~0); 7583#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6877#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6878#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7577#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7556#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7494#L869 assume !(1 == ~M_E~0); 7197#L869-2 assume !(1 == ~T1_E~0); 7198#L874-1 assume !(1 == ~T2_E~0); 7611#L879-1 assume !(1 == ~T3_E~0); 7272#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6797#L889-1 assume !(1 == ~T5_E~0); 6798#L894-1 assume !(1 == ~T6_E~0); 7063#L899-1 assume !(1 == ~T7_E~0); 7455#L904-1 assume !(1 == ~E_M~0); 7221#L909-1 assume !(1 == ~E_1~0); 7222#L914-1 assume !(1 == ~E_2~0); 7392#L919-1 assume !(1 == ~E_3~0); 7137#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6974#L929-1 assume !(1 == ~E_5~0); 6975#L934-1 assume !(1 == ~E_6~0); 7201#L939-1 assume !(1 == ~E_7~0); 7202#L944-1 assume { :end_inline_reset_delta_events } true; 7043#L1190-2 [2024-10-31 22:05:45,912 INFO L747 eck$LassoCheckResult]: Loop: 7043#L1190-2 assume !false; 7054#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7055#L756-1 assume !false; 7056#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7629#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6896#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7186#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7187#L653 assume !(0 != eval_~tmp~0#1); 7240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7318#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6914#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6915#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7243#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6860#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6861#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7121#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7122#L811-3 assume !(0 == ~T7_E~0); 7316#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7515#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7604#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7458#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7459#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7014#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7015#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7342#L851-3 assume !(0 == ~E_7~0); 6908#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6909#L388-27 assume 1 == ~m_pc~0; 7578#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7579#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7482#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7483#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7087#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7088#L407-27 assume 1 == ~t1_pc~0; 7466#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7467#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7386#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 7359#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7005#L426-27 assume 1 == ~t2_pc~0; 7006#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7019#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7020#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7460#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7575#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7310#L445-27 assume 1 == ~t3_pc~0; 7282#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6857#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6858#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7311#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7395#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7113#L464-27 assume !(1 == ~t4_pc~0); 6855#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 6856#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6927#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7238#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6998#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6999#L483-27 assume 1 == ~t5_pc~0; 7534#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6910#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6911#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7547#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7548#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7615#L502-27 assume 1 == ~t6_pc~0; 7616#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7337#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7612#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7488#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7489#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6799#L521-27 assume 1 == ~t7_pc~0; 6800#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7151#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7099#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6852#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6853#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7349#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7485#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7241#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7242#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7302#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7295#L889-3 assume !(1 == ~T5_E~0); 6964#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6965#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6985#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6986#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6943#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6944#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6980#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7472#L929-3 assume !(1 == ~E_5~0); 7393#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7394#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6990#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6991#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6817#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7110#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7111#L1209 assume !(0 == start_simulation_~tmp~3#1); 7332#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7315#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6958#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6848#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6849#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6844#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6845#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 7042#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 7043#L1190-2 [2024-10-31 22:05:45,912 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:45,912 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2024-10-31 22:05:45,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:45,913 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721091900] [2024-10-31 22:05:45,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:45,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:45,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:45,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:45,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:45,971 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [721091900] [2024-10-31 22:05:45,971 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [721091900] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:45,971 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:45,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:45,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719369625] [2024-10-31 22:05:45,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:45,972 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:45,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:45,973 INFO L85 PathProgramCache]: Analyzing trace with hash 1885656989, now seen corresponding path program 2 times [2024-10-31 22:05:45,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:45,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386080724] [2024-10-31 22:05:45,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:45,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:45,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:46,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:46,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:46,052 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386080724] [2024-10-31 22:05:46,052 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386080724] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:46,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:46,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:46,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111083430] [2024-10-31 22:05:46,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:46,054 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:46,055 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:46,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:46,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:46,056 INFO L87 Difference]: Start difference. First operand 843 states and 1254 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:46,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:46,083 INFO L93 Difference]: Finished difference Result 843 states and 1253 transitions. [2024-10-31 22:05:46,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1253 transitions. [2024-10-31 22:05:46,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:46,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1253 transitions. [2024-10-31 22:05:46,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-10-31 22:05:46,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-10-31 22:05:46,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1253 transitions. [2024-10-31 22:05:46,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:46,099 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2024-10-31 22:05:46,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1253 transitions. [2024-10-31 22:05:46,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-10-31 22:05:46,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4863582443653618) internal successors, (1253), 842 states have internal predecessors, (1253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:46,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1253 transitions. [2024-10-31 22:05:46,120 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2024-10-31 22:05:46,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:46,123 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1253 transitions. [2024-10-31 22:05:46,124 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:05:46,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1253 transitions. [2024-10-31 22:05:46,129 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:46,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:46,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:46,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:46,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:46,133 INFO L745 eck$LassoCheckResult]: Stem: 8733#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9281#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9282#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9321#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 8876#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8877#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8999#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9000#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8777#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8568#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8569#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8741#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8742#L781 assume !(0 == ~M_E~0); 9216#L781-2 assume !(0 == ~T1_E~0); 9324#L786-1 assume !(0 == ~T2_E~0); 8528#L791-1 assume !(0 == ~T3_E~0); 8529#L796-1 assume !(0 == ~T4_E~0); 9068#L801-1 assume !(0 == ~T5_E~0); 9069#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9099#L811-1 assume !(0 == ~T7_E~0); 8745#L816-1 assume !(0 == ~E_M~0); 8746#L821-1 assume !(0 == ~E_1~0); 8559#L826-1 assume !(0 == ~E_2~0); 8560#L831-1 assume !(0 == ~E_3~0); 8871#L836-1 assume !(0 == ~E_4~0); 8872#L841-1 assume !(0 == ~E_5~0); 8696#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8697#L851-1 assume !(0 == ~E_7~0); 8720#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8721#L388 assume !(1 == ~m_pc~0); 8714#L388-2 is_master_triggered_~__retres1~0#1 := 0; 8715#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9194#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8574#L967 assume !(0 != activate_threads_~tmp~1#1); 8575#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8504#L407 assume 1 == ~t1_pc~0; 8505#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8512#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8513#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8547#L975 assume !(0 != activate_threads_~tmp___0~0#1); 9279#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8831#L426 assume !(1 == ~t2_pc~0); 8832#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9296#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8853#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8854#L983 assume !(0 != activate_threads_~tmp___1~0#1); 9317#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8917#L445 assume 1 == ~t3_pc~0; 8918#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9222#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8502#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8503#L991 assume !(0 != activate_threads_~tmp___2~0#1); 9158#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9126#L464 assume !(1 == ~t4_pc~0); 8724#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8594#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8595#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8606#L999 assume !(0 != activate_threads_~tmp___3~0#1); 8896#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8897#L483 assume 1 == ~t5_pc~0; 9122#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9262#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9235#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9236#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 8814#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L502 assume 1 == ~t6_pc~0; 9097#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8634#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8839#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 9036#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9245#L521 assume !(1 == ~t7_pc~0); 9276#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8570#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8571#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9270#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9249#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9185#L869 assume !(1 == ~M_E~0); 8890#L869-2 assume !(1 == ~T1_E~0); 8891#L874-1 assume !(1 == ~T2_E~0); 9304#L879-1 assume !(1 == ~T3_E~0); 8965#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8490#L889-1 assume !(1 == ~T5_E~0); 8491#L894-1 assume !(1 == ~T6_E~0); 8753#L899-1 assume !(1 == ~T7_E~0); 9148#L904-1 assume !(1 == ~E_M~0); 8914#L909-1 assume !(1 == ~E_1~0); 8915#L914-1 assume !(1 == ~E_2~0); 9084#L919-1 assume !(1 == ~E_3~0); 8830#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8667#L929-1 assume !(1 == ~E_5~0); 8668#L934-1 assume !(1 == ~E_6~0); 8892#L939-1 assume !(1 == ~E_7~0); 8893#L944-1 assume { :end_inline_reset_delta_events } true; 8736#L1190-2 [2024-10-31 22:05:46,133 INFO L747 eck$LassoCheckResult]: Loop: 8736#L1190-2 assume !false; 8747#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8748#L756-1 assume !false; 8749#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9322#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8589#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8879#L653 assume !(0 != eval_~tmp~0#1); 8931#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9009#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9010#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8607#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8608#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8936#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8553#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8554#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8816#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8817#L811-3 assume !(0 == ~T7_E~0); 9011#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9208#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9297#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9151#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9152#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8707#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8708#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9035#L851-3 assume !(0 == ~E_7~0); 8601#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8602#L388-27 assume 1 == ~m_pc~0; 9271#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9272#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9175#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9176#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8780#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8781#L407-27 assume 1 == ~t1_pc~0; 9159#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9160#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9078#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9079#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 9052#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8698#L426-27 assume 1 == ~t2_pc~0; 8699#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8712#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8713#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9153#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9268#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9003#L445-27 assume 1 == ~t3_pc~0; 8977#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8550#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9004#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9088#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8806#L464-27 assume !(1 == ~t4_pc~0); 8548#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 8549#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8618#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8929#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8691#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8692#L483-27 assume 1 == ~t5_pc~0; 9227#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8603#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8604#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9240#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9241#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9308#L502-27 assume !(1 == ~t6_pc~0); 9029#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9030#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9305#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9181#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9182#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8492#L521-27 assume 1 == ~t7_pc~0; 8493#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8844#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8792#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8545#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8546#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9040#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9178#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8934#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8935#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8995#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8988#L889-3 assume !(1 == ~T5_E~0); 8657#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8658#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8678#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8679#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8636#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8637#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8673#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9165#L929-3 assume !(1 == ~E_5~0); 9086#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9087#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8683#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8684#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8510#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8804#L1209 assume !(0 == start_simulation_~tmp~3#1); 9025#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9008#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8651#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8541#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8542#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 8537#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8538#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8735#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8736#L1190-2 [2024-10-31 22:05:46,134 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:46,134 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2024-10-31 22:05:46,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:46,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168879067] [2024-10-31 22:05:46,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:46,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:46,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:46,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:46,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:46,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168879067] [2024-10-31 22:05:46,199 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1168879067] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:46,200 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:46,200 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:46,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498152739] [2024-10-31 22:05:46,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:46,201 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:46,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:46,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 2 times [2024-10-31 22:05:46,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:46,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040197232] [2024-10-31 22:05:46,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:46,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:46,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:46,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:46,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:46,307 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040197232] [2024-10-31 22:05:46,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040197232] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:46,308 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:46,308 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:46,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922394824] [2024-10-31 22:05:46,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:46,310 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:46,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:46,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:46,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:46,312 INFO L87 Difference]: Start difference. First operand 843 states and 1253 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:46,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:46,338 INFO L93 Difference]: Finished difference Result 843 states and 1252 transitions. [2024-10-31 22:05:46,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1252 transitions. [2024-10-31 22:05:46,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:46,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1252 transitions. [2024-10-31 22:05:46,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-10-31 22:05:46,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-10-31 22:05:46,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1252 transitions. [2024-10-31 22:05:46,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:46,354 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2024-10-31 22:05:46,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1252 transitions. [2024-10-31 22:05:46,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-10-31 22:05:46,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4851720047449586) internal successors, (1252), 842 states have internal predecessors, (1252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:46,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1252 transitions. [2024-10-31 22:05:46,374 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2024-10-31 22:05:46,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:46,375 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1252 transitions. [2024-10-31 22:05:46,375 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:05:46,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1252 transitions. [2024-10-31 22:05:46,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:46,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:46,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:46,384 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:46,385 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:46,385 INFO L745 eck$LassoCheckResult]: Stem: 10426#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11014#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 10569#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10570#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10692#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10693#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10470#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10261#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10262#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10431#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10432#L781 assume !(0 == ~M_E~0); 10909#L781-2 assume !(0 == ~T1_E~0); 11017#L786-1 assume !(0 == ~T2_E~0); 10221#L791-1 assume !(0 == ~T3_E~0); 10222#L796-1 assume !(0 == ~T4_E~0); 10761#L801-1 assume !(0 == ~T5_E~0); 10762#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10792#L811-1 assume !(0 == ~T7_E~0); 10438#L816-1 assume !(0 == ~E_M~0); 10439#L821-1 assume !(0 == ~E_1~0); 10252#L826-1 assume !(0 == ~E_2~0); 10253#L831-1 assume !(0 == ~E_3~0); 10564#L836-1 assume !(0 == ~E_4~0); 10565#L841-1 assume !(0 == ~E_5~0); 10389#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10390#L851-1 assume !(0 == ~E_7~0); 10413#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10414#L388 assume !(1 == ~m_pc~0); 10407#L388-2 is_master_triggered_~__retres1~0#1 := 0; 10408#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10887#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10267#L967 assume !(0 != activate_threads_~tmp~1#1); 10268#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10197#L407 assume 1 == ~t1_pc~0; 10198#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10202#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10238#L975 assume !(0 != activate_threads_~tmp___0~0#1); 10972#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10524#L426 assume !(1 == ~t2_pc~0); 10525#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10989#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10546#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10547#L983 assume !(0 != activate_threads_~tmp___1~0#1); 11010#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10610#L445 assume 1 == ~t3_pc~0; 10611#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10915#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10195#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10196#L991 assume !(0 != activate_threads_~tmp___2~0#1); 10851#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10819#L464 assume !(1 == ~t4_pc~0); 10417#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10287#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10288#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10299#L999 assume !(0 != activate_threads_~tmp___3~0#1); 10589#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10590#L483 assume 1 == ~t5_pc~0; 10815#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10955#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10929#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 10507#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10508#L502 assume 1 == ~t6_pc~0; 10789#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10327#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10328#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10532#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 10729#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10938#L521 assume !(1 == ~t7_pc~0); 10969#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10263#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10264#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10963#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10942#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10878#L869 assume !(1 == ~M_E~0); 10583#L869-2 assume !(1 == ~T1_E~0); 10584#L874-1 assume !(1 == ~T2_E~0); 10997#L879-1 assume !(1 == ~T3_E~0); 10658#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10183#L889-1 assume !(1 == ~T5_E~0); 10184#L894-1 assume !(1 == ~T6_E~0); 10446#L899-1 assume !(1 == ~T7_E~0); 10840#L904-1 assume !(1 == ~E_M~0); 10607#L909-1 assume !(1 == ~E_1~0); 10608#L914-1 assume !(1 == ~E_2~0); 10777#L919-1 assume !(1 == ~E_3~0); 10523#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10360#L929-1 assume !(1 == ~E_5~0); 10361#L934-1 assume !(1 == ~E_6~0); 10585#L939-1 assume !(1 == ~E_7~0); 10586#L944-1 assume { :end_inline_reset_delta_events } true; 10429#L1190-2 [2024-10-31 22:05:46,388 INFO L747 eck$LassoCheckResult]: Loop: 10429#L1190-2 assume !false; 10440#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10441#L756-1 assume !false; 10442#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11015#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10280#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10571#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10572#L653 assume !(0 != eval_~tmp~0#1); 10623#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10703#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10300#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10301#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10629#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10246#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10247#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10509#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10510#L811-3 assume !(0 == ~T7_E~0); 10704#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10901#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10990#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10844#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10845#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10400#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10401#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10728#L851-3 assume !(0 == ~E_7~0); 10294#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10295#L388-27 assume 1 == ~m_pc~0; 10964#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10965#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10868#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10869#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10473#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10474#L407-27 assume 1 == ~t1_pc~0; 10852#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10853#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10771#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10772#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 10745#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10391#L426-27 assume 1 == ~t2_pc~0; 10392#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10405#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10406#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10846#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10961#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10696#L445-27 assume 1 == ~t3_pc~0; 10670#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10243#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10244#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10697#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10782#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10499#L464-27 assume !(1 == ~t4_pc~0); 10241#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 10242#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10313#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10626#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10384#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10385#L483-27 assume 1 == ~t5_pc~0; 10920#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10296#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10297#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10933#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10934#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11001#L502-27 assume !(1 == ~t6_pc~0); 10722#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 10723#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10998#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10874#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10875#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10185#L521-27 assume 1 == ~t7_pc~0; 10186#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10537#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10485#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10239#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10240#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10735#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10871#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10627#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10628#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10688#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10681#L889-3 assume !(1 == ~T5_E~0); 10350#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10351#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10371#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10372#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10329#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10330#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10366#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10858#L929-3 assume !(1 == ~E_5~0); 10779#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10780#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10376#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10377#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10205#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10497#L1209 assume !(0 == start_simulation_~tmp~3#1); 10718#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10701#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10344#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10234#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10235#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 10230#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10231#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10428#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 10429#L1190-2 [2024-10-31 22:05:46,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:46,391 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2024-10-31 22:05:46,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:46,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202607157] [2024-10-31 22:05:46,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:46,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:46,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:46,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:46,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:46,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202607157] [2024-10-31 22:05:46,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202607157] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:46,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:46,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:46,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864165800] [2024-10-31 22:05:46,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:46,444 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:46,445 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:46,445 INFO L85 PathProgramCache]: Analyzing trace with hash 1400482270, now seen corresponding path program 3 times [2024-10-31 22:05:46,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:46,445 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748102344] [2024-10-31 22:05:46,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:46,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:46,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:46,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:46,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:46,515 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748102344] [2024-10-31 22:05:46,515 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [748102344] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:46,516 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:46,516 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:46,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1634719428] [2024-10-31 22:05:46,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:46,517 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:46,517 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:46,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:46,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:46,518 INFO L87 Difference]: Start difference. First operand 843 states and 1252 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:46,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:46,545 INFO L93 Difference]: Finished difference Result 843 states and 1251 transitions. [2024-10-31 22:05:46,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1251 transitions. [2024-10-31 22:05:46,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:46,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1251 transitions. [2024-10-31 22:05:46,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-10-31 22:05:46,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-10-31 22:05:46,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1251 transitions. [2024-10-31 22:05:46,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:46,562 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2024-10-31 22:05:46,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1251 transitions. [2024-10-31 22:05:46,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-10-31 22:05:46,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4839857651245552) internal successors, (1251), 842 states have internal predecessors, (1251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:46,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1251 transitions. [2024-10-31 22:05:46,582 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2024-10-31 22:05:46,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:46,584 INFO L425 stractBuchiCegarLoop]: Abstraction has 843 states and 1251 transitions. [2024-10-31 22:05:46,584 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:05:46,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1251 transitions. [2024-10-31 22:05:46,591 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-10-31 22:05:46,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:46,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:46,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:46,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:46,594 INFO L745 eck$LassoCheckResult]: Stem: 12119#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12667#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12668#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12707#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12262#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12263#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12385#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12386#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12163#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11954#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11955#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12124#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12125#L781 assume !(0 == ~M_E~0); 12602#L781-2 assume !(0 == ~T1_E~0); 12710#L786-1 assume !(0 == ~T2_E~0); 11914#L791-1 assume !(0 == ~T3_E~0); 11915#L796-1 assume !(0 == ~T4_E~0); 12454#L801-1 assume !(0 == ~T5_E~0); 12455#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12485#L811-1 assume !(0 == ~T7_E~0); 12131#L816-1 assume !(0 == ~E_M~0); 12132#L821-1 assume !(0 == ~E_1~0); 11945#L826-1 assume !(0 == ~E_2~0); 11946#L831-1 assume !(0 == ~E_3~0); 12257#L836-1 assume !(0 == ~E_4~0); 12258#L841-1 assume !(0 == ~E_5~0); 12082#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12083#L851-1 assume !(0 == ~E_7~0); 12106#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12107#L388 assume !(1 == ~m_pc~0); 12100#L388-2 is_master_triggered_~__retres1~0#1 := 0; 12101#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12580#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11960#L967 assume !(0 != activate_threads_~tmp~1#1); 11961#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11890#L407 assume 1 == ~t1_pc~0; 11891#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11895#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11896#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11931#L975 assume !(0 != activate_threads_~tmp___0~0#1); 12665#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12217#L426 assume !(1 == ~t2_pc~0); 12218#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12682#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12240#L983 assume !(0 != activate_threads_~tmp___1~0#1); 12703#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12303#L445 assume 1 == ~t3_pc~0; 12304#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12608#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11888#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11889#L991 assume !(0 != activate_threads_~tmp___2~0#1); 12544#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12512#L464 assume !(1 == ~t4_pc~0); 12110#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11980#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11981#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11992#L999 assume !(0 != activate_threads_~tmp___3~0#1); 12282#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12283#L483 assume 1 == ~t5_pc~0; 12508#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12648#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12621#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12622#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 12200#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12201#L502 assume 1 == ~t6_pc~0; 12482#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12020#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12021#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12225#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 12422#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12631#L521 assume !(1 == ~t7_pc~0); 12662#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11956#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11957#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12656#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12635#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12571#L869 assume !(1 == ~M_E~0); 12276#L869-2 assume !(1 == ~T1_E~0); 12277#L874-1 assume !(1 == ~T2_E~0); 12690#L879-1 assume !(1 == ~T3_E~0); 12351#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11876#L889-1 assume !(1 == ~T5_E~0); 11877#L894-1 assume !(1 == ~T6_E~0); 12139#L899-1 assume !(1 == ~T7_E~0); 12533#L904-1 assume !(1 == ~E_M~0); 12300#L909-1 assume !(1 == ~E_1~0); 12301#L914-1 assume !(1 == ~E_2~0); 12470#L919-1 assume !(1 == ~E_3~0); 12216#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12053#L929-1 assume !(1 == ~E_5~0); 12054#L934-1 assume !(1 == ~E_6~0); 12278#L939-1 assume !(1 == ~E_7~0); 12279#L944-1 assume { :end_inline_reset_delta_events } true; 12122#L1190-2 [2024-10-31 22:05:46,594 INFO L747 eck$LassoCheckResult]: Loop: 12122#L1190-2 assume !false; 12133#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12134#L756-1 assume !false; 12135#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12708#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11973#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12264#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12265#L653 assume !(0 != eval_~tmp~0#1); 12316#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12395#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12396#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11993#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11994#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12322#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11939#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11940#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12202#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12203#L811-3 assume !(0 == ~T7_E~0); 12397#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12594#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12683#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12537#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12538#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12093#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12094#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12421#L851-3 assume !(0 == ~E_7~0); 11987#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11988#L388-27 assume 1 == ~m_pc~0; 12657#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12658#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12561#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12562#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12166#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12167#L407-27 assume 1 == ~t1_pc~0; 12545#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12546#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12464#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12465#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 12438#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12084#L426-27 assume 1 == ~t2_pc~0; 12085#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12098#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12099#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12539#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12654#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12389#L445-27 assume 1 == ~t3_pc~0; 12363#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11936#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11937#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12390#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12475#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12192#L464-27 assume 1 == ~t4_pc~0; 12193#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11935#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12006#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12319#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12077#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12078#L483-27 assume 1 == ~t5_pc~0; 12613#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11989#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11990#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12626#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12627#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12694#L502-27 assume 1 == ~t6_pc~0; 12695#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12416#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12691#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12567#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12568#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11878#L521-27 assume 1 == ~t7_pc~0; 11879#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12230#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12178#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11932#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11933#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12428#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12564#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12320#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12321#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12381#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12374#L889-3 assume !(1 == ~T5_E~0); 12043#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12044#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12064#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12065#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12022#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12023#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12059#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12551#L929-3 assume !(1 == ~E_5~0); 12472#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12473#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12069#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12070#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11898#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12189#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12190#L1209 assume !(0 == start_simulation_~tmp~3#1); 12411#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12394#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 12037#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11928#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11923#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11924#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12121#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 12122#L1190-2 [2024-10-31 22:05:46,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:46,596 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2024-10-31 22:05:46,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:46,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185882578] [2024-10-31 22:05:46,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:46,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:46,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:46,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:46,702 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:46,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185882578] [2024-10-31 22:05:46,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1185882578] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:46,707 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:46,707 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:46,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1157827572] [2024-10-31 22:05:46,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:46,708 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:46,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:46,708 INFO L85 PathProgramCache]: Analyzing trace with hash -2135531812, now seen corresponding path program 2 times [2024-10-31 22:05:46,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:46,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214364527] [2024-10-31 22:05:46,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:46,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:46,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:46,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:46,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:46,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214364527] [2024-10-31 22:05:46,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [214364527] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:46,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:46,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:46,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066784150] [2024-10-31 22:05:46,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:46,796 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:46,799 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:46,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:05:46,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:05:46,800 INFO L87 Difference]: Start difference. First operand 843 states and 1251 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:46,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:46,981 INFO L93 Difference]: Finished difference Result 1525 states and 2254 transitions. [2024-10-31 22:05:46,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1525 states and 2254 transitions. [2024-10-31 22:05:46,992 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2024-10-31 22:05:47,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1525 states to 1525 states and 2254 transitions. [2024-10-31 22:05:47,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1525 [2024-10-31 22:05:47,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1525 [2024-10-31 22:05:47,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1525 states and 2254 transitions. [2024-10-31 22:05:47,007 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:47,007 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2024-10-31 22:05:47,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1525 states and 2254 transitions. [2024-10-31 22:05:47,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1525 to 1525. [2024-10-31 22:05:47,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1525 states, 1525 states have (on average 1.4780327868852459) internal successors, (2254), 1524 states have internal predecessors, (2254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:47,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1525 states to 1525 states and 2254 transitions. [2024-10-31 22:05:47,052 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2024-10-31 22:05:47,053 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:05:47,054 INFO L425 stractBuchiCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2024-10-31 22:05:47,055 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:05:47,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1525 states and 2254 transitions. [2024-10-31 22:05:47,064 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2024-10-31 22:05:47,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:47,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:47,066 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:47,066 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:47,067 INFO L745 eck$LassoCheckResult]: Stem: 14498#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15072#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15073#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15121#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 14642#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14643#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14769#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14770#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14542#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14332#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14333#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14503#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14504#L781 assume !(0 == ~M_E~0); 15005#L781-2 assume !(0 == ~T1_E~0); 15127#L786-1 assume !(0 == ~T2_E~0); 14292#L791-1 assume !(0 == ~T3_E~0); 14293#L796-1 assume !(0 == ~T4_E~0); 14843#L801-1 assume !(0 == ~T5_E~0); 14844#L806-1 assume !(0 == ~T6_E~0); 14876#L811-1 assume !(0 == ~T7_E~0); 14510#L816-1 assume !(0 == ~E_M~0); 14511#L821-1 assume !(0 == ~E_1~0); 14323#L826-1 assume !(0 == ~E_2~0); 14324#L831-1 assume !(0 == ~E_3~0); 14637#L836-1 assume !(0 == ~E_4~0); 14638#L841-1 assume !(0 == ~E_5~0); 14460#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14461#L851-1 assume !(0 == ~E_7~0); 14484#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14485#L388 assume !(1 == ~m_pc~0); 14478#L388-2 is_master_triggered_~__retres1~0#1 := 0; 14479#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14981#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14338#L967 assume !(0 != activate_threads_~tmp~1#1); 14339#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14268#L407 assume 1 == ~t1_pc~0; 14269#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14273#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14274#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14309#L975 assume !(0 != activate_threads_~tmp___0~0#1); 15070#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14596#L426 assume !(1 == ~t2_pc~0); 14597#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15089#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14619#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14620#L983 assume !(0 != activate_threads_~tmp___1~0#1); 15116#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14684#L445 assume 1 == ~t3_pc~0; 14685#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15011#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14267#L991 assume !(0 != activate_threads_~tmp___2~0#1); 14942#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14908#L464 assume !(1 == ~t4_pc~0); 14488#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14358#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14359#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14370#L999 assume !(0 != activate_threads_~tmp___3~0#1); 14662#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14663#L483 assume 1 == ~t5_pc~0; 14904#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15053#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15024#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15025#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 14579#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14580#L502 assume 1 == ~t6_pc~0; 14873#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14398#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14399#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14605#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 14809#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15036#L521 assume !(1 == ~t7_pc~0); 15067#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14334#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14335#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15061#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15040#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14970#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 14656#L869-2 assume !(1 == ~T1_E~0); 14657#L874-1 assume !(1 == ~T2_E~0); 15101#L879-1 assume !(1 == ~T3_E~0); 14734#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14254#L889-1 assume !(1 == ~T5_E~0); 14255#L894-1 assume !(1 == ~T6_E~0); 14518#L899-1 assume !(1 == ~T7_E~0); 14930#L904-1 assume !(1 == ~E_M~0); 14681#L909-1 assume !(1 == ~E_1~0); 14682#L914-1 assume !(1 == ~E_2~0); 14860#L919-1 assume !(1 == ~E_3~0); 14595#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14431#L929-1 assume !(1 == ~E_5~0); 14432#L934-1 assume !(1 == ~E_6~0); 15105#L939-1 assume !(1 == ~E_7~0); 15035#L944-1 assume { :end_inline_reset_delta_events } true; 14501#L1190-2 [2024-10-31 22:05:47,067 INFO L747 eck$LassoCheckResult]: Loop: 14501#L1190-2 assume !false; 15139#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15138#L756-1 assume !false; 15137#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15136#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14899#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14900#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14696#L653 assume !(0 != eval_~tmp~0#1); 14698#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14780#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14781#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14371#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14372#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14704#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14317#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14318#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14581#L806-3 assume !(0 == ~T6_E~0); 14582#L811-3 assume !(0 == ~T7_E~0); 14782#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14997#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15090#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14935#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14936#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14471#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14472#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14808#L851-3 assume !(0 == ~E_7~0); 14365#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14366#L388-27 assume 1 == ~m_pc~0; 15062#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15063#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14959#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14960#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14545#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14546#L407-27 assume !(1 == ~t1_pc~0); 14945#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 14944#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14854#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14855#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 14826#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14462#L426-27 assume !(1 == ~t2_pc~0); 14464#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 14476#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14477#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14937#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15059#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14774#L445-27 assume 1 == ~t3_pc~0; 14746#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14314#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14315#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14775#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14866#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14571#L464-27 assume !(1 == ~t4_pc~0); 14312#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 14313#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14384#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14701#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14455#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14456#L483-27 assume 1 == ~t5_pc~0; 15016#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14367#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14368#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15029#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15030#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15107#L502-27 assume !(1 == ~t6_pc~0); 14802#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 14803#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15102#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14965#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14966#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14256#L521-27 assume 1 == ~t7_pc~0; 14257#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14610#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14557#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14310#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14311#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14816#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14962#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14702#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14703#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14764#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14757#L889-3 assume !(1 == ~T5_E~0); 14421#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14422#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14442#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14443#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14400#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14401#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14437#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14949#L929-3 assume !(1 == ~E_5~0); 14863#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14864#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14447#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14448#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14276#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15211#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15209#L1209 assume !(0 == start_simulation_~tmp~3#1); 14796#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14797#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15146#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15145#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15144#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 15143#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15142#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14500#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 14501#L1190-2 [2024-10-31 22:05:47,068 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:47,068 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2024-10-31 22:05:47,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:47,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739737753] [2024-10-31 22:05:47,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:47,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:47,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:47,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:47,215 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:47,215 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739737753] [2024-10-31 22:05:47,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739737753] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:47,216 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:47,216 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:47,216 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561439724] [2024-10-31 22:05:47,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:47,217 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:47,218 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:47,218 INFO L85 PathProgramCache]: Analyzing trace with hash -1171889826, now seen corresponding path program 1 times [2024-10-31 22:05:47,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:47,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295066756] [2024-10-31 22:05:47,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:47,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:47,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:47,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:47,310 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:47,310 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295066756] [2024-10-31 22:05:47,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295066756] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:47,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:47,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:47,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255768852] [2024-10-31 22:05:47,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:47,312 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:47,312 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:47,312 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:05:47,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:05:47,313 INFO L87 Difference]: Start difference. First operand 1525 states and 2254 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:47,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:47,572 INFO L93 Difference]: Finished difference Result 2755 states and 4059 transitions. [2024-10-31 22:05:47,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2755 states and 4059 transitions. [2024-10-31 22:05:47,597 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2024-10-31 22:05:47,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2755 states to 2755 states and 4059 transitions. [2024-10-31 22:05:47,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2755 [2024-10-31 22:05:47,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2755 [2024-10-31 22:05:47,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2755 states and 4059 transitions. [2024-10-31 22:05:47,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:47,622 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2755 states and 4059 transitions. [2024-10-31 22:05:47,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2755 states and 4059 transitions. [2024-10-31 22:05:47,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2755 to 2753. [2024-10-31 22:05:47,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2753 states, 2753 states have (on average 1.473665092626226) internal successors, (4057), 2752 states have internal predecessors, (4057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:47,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2753 states to 2753 states and 4057 transitions. [2024-10-31 22:05:47,690 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2024-10-31 22:05:47,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:05:47,692 INFO L425 stractBuchiCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2024-10-31 22:05:47,692 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:05:47,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2753 states and 4057 transitions. [2024-10-31 22:05:47,706 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2024-10-31 22:05:47,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:47,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:47,708 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:47,709 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:47,713 INFO L745 eck$LassoCheckResult]: Stem: 18788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19366#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19415#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 18933#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18934#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19061#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19062#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18833#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18622#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18623#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18796#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18797#L781 assume !(0 == ~M_E~0); 19290#L781-2 assume !(0 == ~T1_E~0); 19420#L786-1 assume !(0 == ~T2_E~0); 18585#L791-1 assume !(0 == ~T3_E~0); 18586#L796-1 assume !(0 == ~T4_E~0); 19135#L801-1 assume !(0 == ~T5_E~0); 19136#L806-1 assume !(0 == ~T6_E~0); 19167#L811-1 assume !(0 == ~T7_E~0); 18800#L816-1 assume !(0 == ~E_M~0); 18801#L821-1 assume !(0 == ~E_1~0); 18613#L826-1 assume !(0 == ~E_2~0); 18614#L831-1 assume !(0 == ~E_3~0); 18928#L836-1 assume !(0 == ~E_4~0); 18929#L841-1 assume !(0 == ~E_5~0); 18751#L846-1 assume !(0 == ~E_6~0); 18752#L851-1 assume !(0 == ~E_7~0); 18775#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18776#L388 assume !(1 == ~m_pc~0); 18769#L388-2 is_master_triggered_~__retres1~0#1 := 0; 18770#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19265#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18628#L967 assume !(0 != activate_threads_~tmp~1#1); 18629#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18558#L407 assume 1 == ~t1_pc~0; 18559#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18566#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18567#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18601#L975 assume !(0 != activate_threads_~tmp___0~0#1); 19363#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18888#L426 assume !(1 == ~t2_pc~0); 18889#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19385#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18910#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18911#L983 assume !(0 != activate_threads_~tmp___1~0#1); 19410#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18977#L445 assume 1 == ~t3_pc~0; 18978#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19300#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18557#L991 assume !(0 != activate_threads_~tmp___2~0#1); 19228#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19195#L464 assume !(1 == ~t4_pc~0); 18779#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18648#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18649#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18660#L999 assume !(0 != activate_threads_~tmp___3~0#1); 18955#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18956#L483 assume 1 == ~t5_pc~0; 19191#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19345#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19315#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19316#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 18871#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18872#L502 assume 1 == ~t6_pc~0; 19165#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18688#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18689#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18898#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 19102#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19325#L521 assume !(1 == ~t7_pc~0); 19360#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18624#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19354#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19332#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19257#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 19258#L869-2 assume !(1 == ~T1_E~0); 19591#L874-1 assume !(1 == ~T2_E~0); 19590#L879-1 assume !(1 == ~T3_E~0); 19589#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19588#L889-1 assume !(1 == ~T5_E~0); 19587#L894-1 assume !(1 == ~T6_E~0); 19585#L899-1 assume !(1 == ~T7_E~0); 19583#L904-1 assume !(1 == ~E_M~0); 19582#L909-1 assume !(1 == ~E_1~0); 19581#L914-1 assume !(1 == ~E_2~0); 19580#L919-1 assume !(1 == ~E_3~0); 19543#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19541#L929-1 assume !(1 == ~E_5~0); 19540#L934-1 assume !(1 == ~E_6~0); 19537#L939-1 assume !(1 == ~E_7~0); 19450#L944-1 assume { :end_inline_reset_delta_events } true; 19444#L1190-2 [2024-10-31 22:05:47,714 INFO L747 eck$LassoCheckResult]: Loop: 19444#L1190-2 assume !false; 19440#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19439#L756-1 assume !false; 19438#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19437#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19429#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19428#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19426#L653 assume !(0 != eval_~tmp~0#1); 19425#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19424#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19422#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19423#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19997#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19996#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19995#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19994#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19993#L806-3 assume !(0 == ~T6_E~0); 19941#L811-3 assume !(0 == ~T7_E~0); 19939#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19937#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19935#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19934#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19932#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19930#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19928#L846-3 assume !(0 == ~E_6~0); 19927#L851-3 assume !(0 == ~E_7~0); 19926#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19925#L388-27 assume !(1 == ~m_pc~0); 19922#L388-29 is_master_triggered_~__retres1~0#1 := 0; 19920#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19918#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19916#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19915#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19913#L407-27 assume 1 == ~t1_pc~0; 19910#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19908#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19905#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19862#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 19859#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19857#L426-27 assume 1 == ~t2_pc~0; 19854#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19851#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19849#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19847#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19845#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19843#L445-27 assume !(1 == ~t3_pc~0); 19815#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 19813#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19770#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19768#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19766#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19764#L464-27 assume 1 == ~t4_pc~0; 19760#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19758#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19756#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19754#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19752#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19750#L483-27 assume !(1 == ~t5_pc~0); 19723#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 19721#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19719#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19717#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19715#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19714#L502-27 assume 1 == ~t6_pc~0; 19712#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19711#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19664#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19663#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19636#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19633#L521-27 assume !(1 == ~t7_pc~0); 19630#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19628#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19626#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19607#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19593#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19550#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19390#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19546#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19544#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19529#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19526#L889-3 assume !(1 == ~T5_E~0); 19524#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18712#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19518#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19515#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19511#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19508#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19505#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19502#L929-3 assume !(1 == ~E_5~0); 19499#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19495#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19492#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19486#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19480#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19476#L1209 assume !(0 == start_simulation_~tmp~3#1); 19103#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19469#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19463#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 19459#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 19455#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19453#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 19451#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 19444#L1190-2 [2024-10-31 22:05:47,717 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:47,717 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2024-10-31 22:05:47,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:47,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159923645] [2024-10-31 22:05:47,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:47,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:47,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:47,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:47,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:47,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159923645] [2024-10-31 22:05:47,793 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159923645] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:47,793 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:47,793 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:05:47,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269426829] [2024-10-31 22:05:47,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:47,795 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:47,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:47,796 INFO L85 PathProgramCache]: Analyzing trace with hash 601568924, now seen corresponding path program 1 times [2024-10-31 22:05:47,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:47,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693519248] [2024-10-31 22:05:47,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:47,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:47,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:47,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:47,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:47,864 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693519248] [2024-10-31 22:05:47,864 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [693519248] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:47,864 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:47,864 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:47,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614347305] [2024-10-31 22:05:47,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:47,865 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:47,865 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:47,866 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:47,866 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:47,866 INFO L87 Difference]: Start difference. First operand 2753 states and 4057 transitions. cyclomatic complexity: 1308 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:48,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:48,025 INFO L93 Difference]: Finished difference Result 5107 states and 7472 transitions. [2024-10-31 22:05:48,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5107 states and 7472 transitions. [2024-10-31 22:05:48,075 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4969 [2024-10-31 22:05:48,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5107 states to 5107 states and 7472 transitions. [2024-10-31 22:05:48,109 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5107 [2024-10-31 22:05:48,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5107 [2024-10-31 22:05:48,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5107 states and 7472 transitions. [2024-10-31 22:05:48,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:48,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5107 states and 7472 transitions. [2024-10-31 22:05:48,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5107 states and 7472 transitions. [2024-10-31 22:05:48,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5107 to 5099. [2024-10-31 22:05:48,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5099 states, 5099 states have (on average 1.4638164345950186) internal successors, (7464), 5098 states have internal predecessors, (7464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:48,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5099 states to 5099 states and 7464 transitions. [2024-10-31 22:05:48,348 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5099 states and 7464 transitions. [2024-10-31 22:05:48,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:48,349 INFO L425 stractBuchiCegarLoop]: Abstraction has 5099 states and 7464 transitions. [2024-10-31 22:05:48,349 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:05:48,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5099 states and 7464 transitions. [2024-10-31 22:05:48,375 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4961 [2024-10-31 22:05:48,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:48,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:48,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:48,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:48,377 INFO L745 eck$LassoCheckResult]: Stem: 26658#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 27304#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27305#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27400#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 26808#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26809#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26945#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26946#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26705#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26488#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26489#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26666#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26667#L781 assume !(0 == ~M_E~0); 27209#L781-2 assume !(0 == ~T1_E~0); 27416#L786-1 assume !(0 == ~T2_E~0); 26448#L791-1 assume !(0 == ~T3_E~0); 26449#L796-1 assume !(0 == ~T4_E~0); 27023#L801-1 assume !(0 == ~T5_E~0); 27024#L806-1 assume !(0 == ~T6_E~0); 27061#L811-1 assume !(0 == ~T7_E~0); 26671#L816-1 assume !(0 == ~E_M~0); 26672#L821-1 assume !(0 == ~E_1~0); 26479#L826-1 assume !(0 == ~E_2~0); 26480#L831-1 assume !(0 == ~E_3~0); 26803#L836-1 assume !(0 == ~E_4~0); 26804#L841-1 assume !(0 == ~E_5~0); 26620#L846-1 assume !(0 == ~E_6~0); 26621#L851-1 assume !(0 == ~E_7~0); 26644#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26645#L388 assume !(1 == ~m_pc~0); 26638#L388-2 is_master_triggered_~__retres1~0#1 := 0; 26639#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27177#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26494#L967 assume !(0 != activate_threads_~tmp~1#1); 26495#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26425#L407 assume !(1 == ~t1_pc~0); 26426#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26432#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26467#L975 assume !(0 != activate_threads_~tmp___0~0#1); 27302#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26763#L426 assume !(1 == ~t2_pc~0); 26764#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27333#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26785#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26786#L983 assume !(0 != activate_threads_~tmp___1~0#1); 27384#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26855#L445 assume 1 == ~t3_pc~0; 26856#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27218#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26424#L991 assume !(0 != activate_threads_~tmp___2~0#1); 27131#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27092#L464 assume !(1 == ~t4_pc~0); 26648#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26514#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26515#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26526#L999 assume !(0 != activate_threads_~tmp___3~0#1); 26833#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26834#L483 assume 1 == ~t5_pc~0; 27087#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27282#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27240#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27241#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 26744#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26745#L502 assume 1 == ~t6_pc~0; 27059#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26554#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26555#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26771#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 26982#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27254#L521 assume !(1 == ~t7_pc~0); 27299#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26490#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26491#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27293#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27262#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27165#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 27166#L869-2 assume !(1 == ~T1_E~0); 28230#L874-1 assume !(1 == ~T2_E~0); 27348#L879-1 assume !(1 == ~T3_E~0); 27349#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28193#L889-1 assume !(1 == ~T5_E~0); 28191#L894-1 assume !(1 == ~T6_E~0); 28190#L899-1 assume !(1 == ~T7_E~0); 28160#L904-1 assume !(1 == ~E_M~0); 28139#L909-1 assume !(1 == ~E_1~0); 28137#L914-1 assume !(1 == ~E_2~0); 28135#L919-1 assume !(1 == ~E_3~0); 28134#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26589#L929-1 assume !(1 == ~E_5~0); 26590#L934-1 assume !(1 == ~E_6~0); 28111#L939-1 assume !(1 == ~E_7~0); 28103#L944-1 assume { :end_inline_reset_delta_events } true; 28097#L1190-2 [2024-10-31 22:05:48,378 INFO L747 eck$LassoCheckResult]: Loop: 28097#L1190-2 assume !false; 28093#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28092#L756-1 assume !false; 28091#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28090#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28082#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28081#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28079#L653 assume !(0 != eval_~tmp~0#1); 28078#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28077#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28074#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28075#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29633#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29632#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29631#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29630#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29629#L806-3 assume !(0 == ~T6_E~0); 29628#L811-3 assume !(0 == ~T7_E~0); 29627#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29625#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29623#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29621#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29619#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29617#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29615#L846-3 assume !(0 == ~E_6~0); 29613#L851-3 assume !(0 == ~E_7~0); 29611#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29609#L388-27 assume !(1 == ~m_pc~0); 29605#L388-29 is_master_triggered_~__retres1~0#1 := 0; 29603#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29601#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29599#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29597#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29595#L407-27 assume !(1 == ~t1_pc~0); 29593#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 29591#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29589#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29586#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 29584#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29582#L426-27 assume 1 == ~t2_pc~0; 29579#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29577#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29575#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29573#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29571#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29569#L445-27 assume !(1 == ~t3_pc~0); 29566#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 29564#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29562#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29559#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29557#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29555#L464-27 assume 1 == ~t4_pc~0; 29552#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29550#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29548#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29545#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29543#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29541#L483-27 assume !(1 == ~t5_pc~0); 29538#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 29536#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29534#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29531#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29529#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29527#L502-27 assume 1 == ~t6_pc~0; 29524#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29522#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29520#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29517#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29515#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29513#L521-27 assume !(1 == ~t7_pc~0); 27954#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 27951#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27948#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27945#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27943#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27939#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27936#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27933#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27929#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27930#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28364#L889-3 assume !(1 == ~T5_E~0); 28346#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28269#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28267#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28266#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28265#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28263#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28261#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28259#L929-3 assume !(1 == ~E_5~0); 28229#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28226#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28196#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28172#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28167#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28166#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 28165#L1209 assume !(0 == start_simulation_~tmp~3#1); 27788#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28148#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28140#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28138#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 28125#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 28121#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28112#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 28104#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 28097#L1190-2 [2024-10-31 22:05:48,378 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:48,379 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2024-10-31 22:05:48,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:48,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179032571] [2024-10-31 22:05:48,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:48,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:48,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:48,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:48,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:48,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179032571] [2024-10-31 22:05:48,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179032571] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:48,466 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:48,466 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:05:48,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611770120] [2024-10-31 22:05:48,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:48,467 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:48,468 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:48,469 INFO L85 PathProgramCache]: Analyzing trace with hash -1353752291, now seen corresponding path program 1 times [2024-10-31 22:05:48,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:48,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594162463] [2024-10-31 22:05:48,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:48,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:48,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:48,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:48,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:48,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [594162463] [2024-10-31 22:05:48,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [594162463] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:48,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:48,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:48,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308070361] [2024-10-31 22:05:48,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:48,532 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:48,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:48,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:48,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:48,534 INFO L87 Difference]: Start difference. First operand 5099 states and 7464 transitions. cyclomatic complexity: 2373 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:48,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:48,688 INFO L93 Difference]: Finished difference Result 9533 states and 13868 transitions. [2024-10-31 22:05:48,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9533 states and 13868 transitions. [2024-10-31 22:05:48,747 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9380 [2024-10-31 22:05:48,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9533 states to 9533 states and 13868 transitions. [2024-10-31 22:05:48,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9533 [2024-10-31 22:05:48,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9533 [2024-10-31 22:05:48,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9533 states and 13868 transitions. [2024-10-31 22:05:48,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:48,819 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9533 states and 13868 transitions. [2024-10-31 22:05:48,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9533 states and 13868 transitions. [2024-10-31 22:05:49,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9533 to 9517. [2024-10-31 22:05:49,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9517 states, 9517 states have (on average 1.4555006829883366) internal successors, (13852), 9516 states have internal predecessors, (13852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:49,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9517 states to 9517 states and 13852 transitions. [2024-10-31 22:05:49,216 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9517 states and 13852 transitions. [2024-10-31 22:05:49,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:49,217 INFO L425 stractBuchiCegarLoop]: Abstraction has 9517 states and 13852 transitions. [2024-10-31 22:05:49,218 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:05:49,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9517 states and 13852 transitions. [2024-10-31 22:05:49,331 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9364 [2024-10-31 22:05:49,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:49,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:49,333 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:49,333 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:49,333 INFO L745 eck$LassoCheckResult]: Stem: 41298#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 41299#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 41920#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41921#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42009#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 41448#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41449#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41580#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41581#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41344#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41126#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41127#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41306#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41307#L781 assume !(0 == ~M_E~0); 41839#L781-2 assume !(0 == ~T1_E~0); 42025#L786-1 assume !(0 == ~T2_E~0); 41089#L791-1 assume !(0 == ~T3_E~0); 41090#L796-1 assume !(0 == ~T4_E~0); 41660#L801-1 assume !(0 == ~T5_E~0); 41661#L806-1 assume !(0 == ~T6_E~0); 41697#L811-1 assume !(0 == ~T7_E~0); 41311#L816-1 assume !(0 == ~E_M~0); 41312#L821-1 assume !(0 == ~E_1~0); 41117#L826-1 assume !(0 == ~E_2~0); 41118#L831-1 assume !(0 == ~E_3~0); 41443#L836-1 assume !(0 == ~E_4~0); 41444#L841-1 assume !(0 == ~E_5~0); 41261#L846-1 assume !(0 == ~E_6~0); 41262#L851-1 assume !(0 == ~E_7~0); 41285#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41286#L388 assume !(1 == ~m_pc~0); 41279#L388-2 is_master_triggered_~__retres1~0#1 := 0; 41280#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41811#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41132#L967 assume !(0 != activate_threads_~tmp~1#1); 41133#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41064#L407 assume !(1 == ~t1_pc~0); 41065#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41071#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41105#L975 assume !(0 != activate_threads_~tmp___0~0#1); 41918#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41401#L426 assume !(1 == ~t2_pc~0); 41402#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41948#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41424#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41425#L983 assume !(0 != activate_threads_~tmp___1~0#1); 41993#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41491#L445 assume !(1 == ~t3_pc~0); 41492#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41847#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41062#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41063#L991 assume !(0 != activate_threads_~tmp___2~0#1); 41768#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41732#L464 assume !(1 == ~t4_pc~0); 41289#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41152#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41153#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41168#L999 assume !(0 != activate_threads_~tmp___3~0#1); 41469#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41470#L483 assume 1 == ~t5_pc~0; 41728#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41895#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41863#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41864#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 41385#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41386#L502 assume 1 == ~t6_pc~0; 41695#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41194#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41195#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41411#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 41620#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41877#L521 assume !(1 == ~t7_pc~0); 41912#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41128#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41129#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41906#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41882#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41802#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 41803#L869-2 assume !(1 == ~T1_E~0); 43992#L874-1 assume !(1 == ~T2_E~0); 43991#L879-1 assume !(1 == ~T3_E~0); 43990#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43989#L889-1 assume !(1 == ~T5_E~0); 43988#L894-1 assume !(1 == ~T6_E~0); 43987#L899-1 assume !(1 == ~T7_E~0); 43986#L904-1 assume !(1 == ~E_M~0); 43985#L909-1 assume !(1 == ~E_1~0); 43984#L914-1 assume !(1 == ~E_2~0); 41708#L919-1 assume !(1 == ~E_3~0); 41709#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43799#L929-1 assume !(1 == ~E_5~0); 43798#L934-1 assume !(1 == ~E_6~0); 43795#L939-1 assume !(1 == ~E_7~0); 43794#L944-1 assume { :end_inline_reset_delta_events } true; 43793#L1190-2 [2024-10-31 22:05:49,334 INFO L747 eck$LassoCheckResult]: Loop: 43793#L1190-2 assume !false; 43767#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43737#L756-1 assume !false; 43735#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43707#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43672#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43670#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43644#L653 assume !(0 != eval_~tmp~0#1); 43645#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46454#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46452#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46450#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46448#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46446#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46444#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46442#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46440#L806-3 assume !(0 == ~T6_E~0); 46438#L811-3 assume !(0 == ~T7_E~0); 46436#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46434#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46432#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46430#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46428#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46426#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46424#L846-3 assume !(0 == ~E_6~0); 46422#L851-3 assume !(0 == ~E_7~0); 46420#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46418#L388-27 assume !(1 == ~m_pc~0); 46414#L388-29 is_master_triggered_~__retres1~0#1 := 0; 46412#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46410#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46408#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46406#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46404#L407-27 assume !(1 == ~t1_pc~0); 46402#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 46400#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46398#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46396#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 46394#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46392#L426-27 assume 1 == ~t2_pc~0; 46388#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46386#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46384#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46382#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46380#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46378#L445-27 assume !(1 == ~t3_pc~0); 46376#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 46374#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46372#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46370#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46368#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46366#L464-27 assume 1 == ~t4_pc~0; 46362#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46360#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46358#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46356#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46354#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46352#L483-27 assume !(1 == ~t5_pc~0); 46348#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 46346#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46344#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46341#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46338#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46335#L502-27 assume 1 == ~t6_pc~0; 46330#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46327#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46325#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46322#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46319#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46315#L521-27 assume !(1 == ~t7_pc~0); 46308#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 46305#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46302#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46196#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46195#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46148#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44800#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46143#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46141#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46138#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46136#L889-3 assume !(1 == ~T5_E~0); 46134#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44786#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46131#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46129#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46127#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46125#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46123#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46057#L929-3 assume !(1 == ~E_5~0); 46058#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46053#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46054#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42170#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42166#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42155#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 42156#L1209 assume !(0 == start_simulation_~tmp~3#1); 43171#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43172#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43160#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43161#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 43156#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 43157#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43146#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 43147#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 43793#L1190-2 [2024-10-31 22:05:49,334 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:49,335 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2024-10-31 22:05:49,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:49,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111720351] [2024-10-31 22:05:49,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:49,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:49,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:49,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:49,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:49,419 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111720351] [2024-10-31 22:05:49,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111720351] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:49,419 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:49,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:05:49,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842818504] [2024-10-31 22:05:49,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:49,423 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:49,423 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:49,423 INFO L85 PathProgramCache]: Analyzing trace with hash -1353752291, now seen corresponding path program 2 times [2024-10-31 22:05:49,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:49,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106986599] [2024-10-31 22:05:49,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:49,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:49,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:49,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:49,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:49,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106986599] [2024-10-31 22:05:49,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106986599] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:49,482 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:49,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:49,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591015341] [2024-10-31 22:05:49,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:49,483 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:49,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:49,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:49,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:49,484 INFO L87 Difference]: Start difference. First operand 9517 states and 13852 transitions. cyclomatic complexity: 4351 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:49,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:49,757 INFO L93 Difference]: Finished difference Result 18316 states and 26485 transitions. [2024-10-31 22:05:49,757 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18316 states and 26485 transitions. [2024-10-31 22:05:49,878 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18108 [2024-10-31 22:05:49,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18316 states to 18316 states and 26485 transitions. [2024-10-31 22:05:49,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18316 [2024-10-31 22:05:49,973 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18316 [2024-10-31 22:05:49,974 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18316 states and 26485 transitions. [2024-10-31 22:05:50,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:50,001 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18316 states and 26485 transitions. [2024-10-31 22:05:50,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18316 states and 26485 transitions. [2024-10-31 22:05:50,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18316 to 18284. [2024-10-31 22:05:50,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18284 states, 18284 states have (on average 1.4467840735068913) internal successors, (26453), 18283 states have internal predecessors, (26453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:50,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18284 states to 18284 states and 26453 transitions. [2024-10-31 22:05:50,481 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18284 states and 26453 transitions. [2024-10-31 22:05:50,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:50,483 INFO L425 stractBuchiCegarLoop]: Abstraction has 18284 states and 26453 transitions. [2024-10-31 22:05:50,484 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:05:50,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18284 states and 26453 transitions. [2024-10-31 22:05:50,556 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18076 [2024-10-31 22:05:50,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:50,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:50,558 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:50,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:50,559 INFO L745 eck$LassoCheckResult]: Stem: 69133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 69134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 69745#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69746#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69824#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 69280#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69281#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69413#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69414#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69180#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68965#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68966#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69141#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69142#L781 assume !(0 == ~M_E~0); 69660#L781-2 assume !(0 == ~T1_E~0); 69843#L786-1 assume !(0 == ~T2_E~0); 68926#L791-1 assume !(0 == ~T3_E~0); 68927#L796-1 assume !(0 == ~T4_E~0); 69491#L801-1 assume !(0 == ~T5_E~0); 69492#L806-1 assume !(0 == ~T6_E~0); 69527#L811-1 assume !(0 == ~T7_E~0); 69146#L816-1 assume !(0 == ~E_M~0); 69147#L821-1 assume !(0 == ~E_1~0); 68957#L826-1 assume !(0 == ~E_2~0); 68958#L831-1 assume !(0 == ~E_3~0); 69275#L836-1 assume !(0 == ~E_4~0); 69276#L841-1 assume !(0 == ~E_5~0); 69095#L846-1 assume !(0 == ~E_6~0); 69096#L851-1 assume !(0 == ~E_7~0); 69119#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69120#L388 assume !(1 == ~m_pc~0); 69113#L388-2 is_master_triggered_~__retres1~0#1 := 0; 69114#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69633#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68971#L967 assume !(0 != activate_threads_~tmp~1#1); 68972#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68904#L407 assume !(1 == ~t1_pc~0); 68905#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68911#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68912#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68945#L975 assume !(0 != activate_threads_~tmp___0~0#1); 69742#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69234#L426 assume !(1 == ~t2_pc~0); 69235#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69770#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69256#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69257#L983 assume !(0 != activate_threads_~tmp___1~0#1); 69814#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69325#L445 assume !(1 == ~t3_pc~0); 69326#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69667#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68902#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68903#L991 assume !(0 != activate_threads_~tmp___2~0#1); 69591#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69557#L464 assume !(1 == ~t4_pc~0); 69123#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68991#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68992#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69003#L999 assume !(0 != activate_threads_~tmp___3~0#1); 69303#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69304#L483 assume !(1 == ~t5_pc~0); 69554#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69724#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69687#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69688#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 69217#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69218#L502 assume 1 == ~t6_pc~0; 69525#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69031#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69032#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69242#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 69454#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69699#L521 assume !(1 == ~t7_pc~0); 69738#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68967#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68968#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69732#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69706#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69622#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 69297#L869-2 assume !(1 == ~T1_E~0); 69298#L874-1 assume !(1 == ~T2_E~0); 69809#L879-1 assume !(1 == ~T3_E~0); 69375#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69376#L889-1 assume !(1 == ~T5_E~0); 69154#L894-1 assume !(1 == ~T6_E~0); 69155#L899-1 assume !(1 == ~T7_E~0); 69581#L904-1 assume !(1 == ~E_M~0); 69322#L909-1 assume !(1 == ~E_1~0); 69323#L914-1 assume !(1 == ~E_2~0); 69510#L919-1 assume !(1 == ~E_3~0); 69536#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69065#L929-1 assume !(1 == ~E_5~0); 69066#L934-1 assume !(1 == ~E_6~0); 73409#L939-1 assume !(1 == ~E_7~0); 73399#L944-1 assume { :end_inline_reset_delta_events } true; 73392#L1190-2 [2024-10-31 22:05:50,559 INFO L747 eck$LassoCheckResult]: Loop: 73392#L1190-2 assume !false; 73387#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73385#L756-1 assume !false; 73383#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73381#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73373#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73370#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 73368#L653 assume !(0 != eval_~tmp~0#1); 73369#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 73982#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 73979#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 73976#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 73973#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73970#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 73967#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 73964#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 73961#L806-3 assume !(0 == ~T6_E~0); 73958#L811-3 assume !(0 == ~T7_E~0); 73955#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 73952#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73949#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 73946#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 73943#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 73940#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 73937#L846-3 assume !(0 == ~E_6~0); 73934#L851-3 assume !(0 == ~E_7~0); 73931#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73928#L388-27 assume !(1 == ~m_pc~0); 73923#L388-29 is_master_triggered_~__retres1~0#1 := 0; 73919#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73916#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73913#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 73910#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73907#L407-27 assume !(1 == ~t1_pc~0); 73904#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 73901#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73898#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73895#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 73892#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73889#L426-27 assume !(1 == ~t2_pc~0); 73885#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 73880#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73877#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 73874#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 73871#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73868#L445-27 assume !(1 == ~t3_pc~0); 73865#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 73862#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73859#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73855#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 73851#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73847#L464-27 assume 1 == ~t4_pc~0; 73841#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73836#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73832#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73828#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 73823#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73819#L483-27 assume !(1 == ~t5_pc~0); 73815#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 73811#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73807#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73803#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 73799#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73795#L502-27 assume 1 == ~t6_pc~0; 73789#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73784#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73780#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73776#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73771#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73766#L521-27 assume 1 == ~t7_pc~0; 73759#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 73752#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73747#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73742#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73736#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73731#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 69775#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73720#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73710#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73704#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73698#L889-3 assume !(1 == ~T5_E~0); 73693#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69055#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 73680#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 73675#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 73670#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73665#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 73660#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73655#L929-3 assume !(1 == ~E_5~0); 73650#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 73644#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73642#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73590#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73582#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73579#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 73575#L1209 assume !(0 == start_simulation_~tmp~3#1); 73573#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73457#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73443#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73433#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 73428#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 73419#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73410#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 73400#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 73392#L1190-2 [2024-10-31 22:05:50,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:50,560 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2024-10-31 22:05:50,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:50,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561599293] [2024-10-31 22:05:50,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:50,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:50,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:50,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:50,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:50,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561599293] [2024-10-31 22:05:50,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561599293] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:50,622 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:50,622 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:05:50,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923720823] [2024-10-31 22:05:50,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:50,624 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:50,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:50,624 INFO L85 PathProgramCache]: Analyzing trace with hash -2027558563, now seen corresponding path program 1 times [2024-10-31 22:05:50,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:50,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598327589] [2024-10-31 22:05:50,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:50,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:50,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:50,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:50,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:50,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598327589] [2024-10-31 22:05:50,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [598327589] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:50,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:50,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:50,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112858670] [2024-10-31 22:05:50,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:50,676 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:50,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:50,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:50,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:50,678 INFO L87 Difference]: Start difference. First operand 18284 states and 26453 transitions. cyclomatic complexity: 8201 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:51,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:51,047 INFO L93 Difference]: Finished difference Result 34391 states and 49534 transitions. [2024-10-31 22:05:51,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34391 states and 49534 transitions. [2024-10-31 22:05:51,202 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 34040 [2024-10-31 22:05:51,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34391 states to 34391 states and 49534 transitions. [2024-10-31 22:05:51,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34391 [2024-10-31 22:05:51,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34391 [2024-10-31 22:05:51,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34391 states and 49534 transitions. [2024-10-31 22:05:51,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:51,503 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34391 states and 49534 transitions. [2024-10-31 22:05:51,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34391 states and 49534 transitions. [2024-10-31 22:05:51,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34391 to 34327. [2024-10-31 22:05:52,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34327 states, 34327 states have (on average 1.4411396276983133) internal successors, (49470), 34326 states have internal predecessors, (49470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:52,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34327 states to 34327 states and 49470 transitions. [2024-10-31 22:05:52,256 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34327 states and 49470 transitions. [2024-10-31 22:05:52,257 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:52,258 INFO L425 stractBuchiCegarLoop]: Abstraction has 34327 states and 49470 transitions. [2024-10-31 22:05:52,258 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:05:52,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34327 states and 49470 transitions. [2024-10-31 22:05:52,407 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 33976 [2024-10-31 22:05:52,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:52,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:52,409 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:52,410 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:52,410 INFO L745 eck$LassoCheckResult]: Stem: 121814#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 121815#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 122417#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122418#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122502#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 121960#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121961#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122090#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122091#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121861#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 121647#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121648#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121819#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121820#L781 assume !(0 == ~M_E~0); 122333#L781-2 assume !(0 == ~T1_E~0); 122511#L786-1 assume !(0 == ~T2_E~0); 121608#L791-1 assume !(0 == ~T3_E~0); 121609#L796-1 assume !(0 == ~T4_E~0); 122164#L801-1 assume !(0 == ~T5_E~0); 122165#L806-1 assume !(0 == ~T6_E~0); 122197#L811-1 assume !(0 == ~T7_E~0); 121827#L816-1 assume !(0 == ~E_M~0); 121828#L821-1 assume !(0 == ~E_1~0); 121639#L826-1 assume !(0 == ~E_2~0); 121640#L831-1 assume !(0 == ~E_3~0); 121955#L836-1 assume !(0 == ~E_4~0); 121956#L841-1 assume !(0 == ~E_5~0); 121777#L846-1 assume !(0 == ~E_6~0); 121778#L851-1 assume !(0 == ~E_7~0); 121800#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121801#L388 assume !(1 == ~m_pc~0); 121794#L388-2 is_master_triggered_~__retres1~0#1 := 0; 121795#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122307#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 121653#L967 assume !(0 != activate_threads_~tmp~1#1); 121654#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121586#L407 assume !(1 == ~t1_pc~0); 121587#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 121590#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121591#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 121625#L975 assume !(0 != activate_threads_~tmp___0~0#1); 122414#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121916#L426 assume !(1 == ~t2_pc~0); 121917#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 122445#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121938#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121939#L983 assume !(0 != activate_threads_~tmp___1~0#1); 122492#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122001#L445 assume !(1 == ~t3_pc~0); 122002#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122342#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121584#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121585#L991 assume !(0 != activate_threads_~tmp___2~0#1); 122266#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122230#L464 assume !(1 == ~t4_pc~0); 121804#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 121673#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121674#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121685#L999 assume !(0 != activate_threads_~tmp___3~0#1); 121981#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121982#L483 assume !(1 == ~t5_pc~0); 122227#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122392#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122361#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122362#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 121898#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121899#L502 assume !(1 == ~t6_pc~0); 121755#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121713#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121714#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 121924#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 122128#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122373#L521 assume !(1 == ~t7_pc~0); 122409#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 121649#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 121650#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 122403#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 122378#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122297#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 122298#L869-2 assume !(1 == ~T1_E~0); 122487#L874-1 assume !(1 == ~T2_E~0); 122457#L879-1 assume !(1 == ~T3_E~0); 122458#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123702#L889-1 assume !(1 == ~T5_E~0); 123700#L894-1 assume !(1 == ~T6_E~0); 123698#L899-1 assume !(1 == ~T7_E~0); 123697#L904-1 assume !(1 == ~E_M~0); 123696#L909-1 assume !(1 == ~E_1~0); 123695#L914-1 assume !(1 == ~E_2~0); 122206#L919-1 assume !(1 == ~E_3~0); 121915#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 121747#L929-1 assume !(1 == ~E_5~0); 121748#L934-1 assume !(1 == ~E_6~0); 123590#L939-1 assume !(1 == ~E_7~0); 123585#L944-1 assume { :end_inline_reset_delta_events } true; 123576#L1190-2 [2024-10-31 22:05:52,411 INFO L747 eck$LassoCheckResult]: Loop: 123576#L1190-2 assume !false; 123545#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 123543#L756-1 assume !false; 123489#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 123487#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123479#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123469#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 123459#L653 assume !(0 != eval_~tmp~0#1); 123460#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124177#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 124176#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 124175#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 124174#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 124173#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 124172#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 124171#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 124170#L806-3 assume !(0 == ~T6_E~0); 124169#L811-3 assume !(0 == ~T7_E~0); 124167#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 124166#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 124165#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 124164#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 124163#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 124162#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 124153#L846-3 assume !(0 == ~E_6~0); 124151#L851-3 assume !(0 == ~E_7~0); 124149#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124147#L388-27 assume !(1 == ~m_pc~0); 124109#L388-29 is_master_triggered_~__retres1~0#1 := 0; 124107#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124105#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 124103#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 124101#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124099#L407-27 assume !(1 == ~t1_pc~0); 124097#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 124095#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124093#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 124091#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 124089#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124087#L426-27 assume 1 == ~t2_pc~0; 124083#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 124081#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124079#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124077#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 124075#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124073#L445-27 assume !(1 == ~t3_pc~0); 124071#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 124069#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124067#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124065#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 124063#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124061#L464-27 assume 1 == ~t4_pc~0; 124057#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 124055#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124053#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 124051#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124049#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124047#L483-27 assume !(1 == ~t5_pc~0); 124045#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 124043#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124041#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124039#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 124037#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124035#L502-27 assume !(1 == ~t6_pc~0); 124033#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 124031#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124029#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 124027#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 124025#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124023#L521-27 assume !(1 == ~t7_pc~0); 124019#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 124017#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124015#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124013#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 124011#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124009#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 124005#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124003#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124001#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123999#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123997#L889-3 assume !(1 == ~T5_E~0); 123993#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 123989#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 123987#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 123985#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 123983#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123981#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 123979#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 123977#L929-3 assume !(1 == ~E_5~0); 123976#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123973#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 123972#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 123968#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123963#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123954#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 123951#L1209 assume !(0 == start_simulation_~tmp~3#1); 123949#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 123852#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123822#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123802#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 123795#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 123689#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123688#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 123586#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 123576#L1190-2 [2024-10-31 22:05:52,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:52,412 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2024-10-31 22:05:52,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:52,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040660560] [2024-10-31 22:05:52,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:52,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:52,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:52,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:52,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:52,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040660560] [2024-10-31 22:05:52,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040660560] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:52,648 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:52,648 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:05:52,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521284010] [2024-10-31 22:05:52,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:52,651 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:52,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:52,651 INFO L85 PathProgramCache]: Analyzing trace with hash -1838927010, now seen corresponding path program 1 times [2024-10-31 22:05:52,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:52,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412548040] [2024-10-31 22:05:52,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:52,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:52,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:52,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:52,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:52,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412548040] [2024-10-31 22:05:52,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412548040] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:52,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:52,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:52,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686440094] [2024-10-31 22:05:52,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:52,705 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:52,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:52,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:05:52,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:05:52,706 INFO L87 Difference]: Start difference. First operand 34327 states and 49470 transitions. cyclomatic complexity: 15207 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:53,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:53,176 INFO L93 Difference]: Finished difference Result 35674 states and 50817 transitions. [2024-10-31 22:05:53,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35674 states and 50817 transitions. [2024-10-31 22:05:53,552 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35320 [2024-10-31 22:05:53,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35674 states to 35674 states and 50817 transitions. [2024-10-31 22:05:53,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35674 [2024-10-31 22:05:53,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35674 [2024-10-31 22:05:53,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35674 states and 50817 transitions. [2024-10-31 22:05:53,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:53,739 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2024-10-31 22:05:53,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35674 states and 50817 transitions. [2024-10-31 22:05:54,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35674 to 35674. [2024-10-31 22:05:54,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35674 states, 35674 states have (on average 1.4244828166171442) internal successors, (50817), 35673 states have internal predecessors, (50817), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:54,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35674 states to 35674 states and 50817 transitions. [2024-10-31 22:05:54,513 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2024-10-31 22:05:54,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:05:54,514 INFO L425 stractBuchiCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2024-10-31 22:05:54,514 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:05:54,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35674 states and 50817 transitions. [2024-10-31 22:05:54,651 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35320 [2024-10-31 22:05:54,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:54,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:54,653 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:54,653 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:54,654 INFO L745 eck$LassoCheckResult]: Stem: 191828#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 191829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 192470#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 192471#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 192552#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 191977#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 191978#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 192110#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 192111#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 191874#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 191658#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 191659#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 191833#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 191834#L781 assume !(0 == ~M_E~0); 192376#L781-2 assume !(0 == ~T1_E~0); 192566#L786-1 assume !(0 == ~T2_E~0); 191618#L791-1 assume !(0 == ~T3_E~0); 191619#L796-1 assume !(0 == ~T4_E~0); 192193#L801-1 assume !(0 == ~T5_E~0); 192194#L806-1 assume !(0 == ~T6_E~0); 192232#L811-1 assume !(0 == ~T7_E~0); 191841#L816-1 assume !(0 == ~E_M~0); 191842#L821-1 assume !(0 == ~E_1~0); 191649#L826-1 assume !(0 == ~E_2~0); 191650#L831-1 assume !(0 == ~E_3~0); 191972#L836-1 assume !(0 == ~E_4~0); 191973#L841-1 assume !(0 == ~E_5~0); 191790#L846-1 assume !(0 == ~E_6~0); 191791#L851-1 assume !(0 == ~E_7~0); 191814#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 191815#L388 assume !(1 == ~m_pc~0); 191808#L388-2 is_master_triggered_~__retres1~0#1 := 0; 191809#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192347#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 191664#L967 assume !(0 != activate_threads_~tmp~1#1); 191665#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 191596#L407 assume !(1 == ~t1_pc~0); 191597#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 191600#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 191601#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 191635#L975 assume !(0 != activate_threads_~tmp___0~0#1); 192467#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191930#L426 assume !(1 == ~t2_pc~0); 191931#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 192495#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191953#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 191954#L983 assume !(0 != activate_threads_~tmp___1~0#1); 192538#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192020#L445 assume !(1 == ~t3_pc~0); 192021#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 192385#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 191594#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 191595#L991 assume !(0 != activate_threads_~tmp___2~0#1); 192300#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192260#L464 assume !(1 == ~t4_pc~0); 191818#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 191684#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 191685#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 191696#L999 assume !(0 != activate_threads_~tmp___3~0#1); 191998#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 191999#L483 assume !(1 == ~t5_pc~0); 192257#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 192447#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192406#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 192407#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 191913#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 191914#L502 assume !(1 == ~t6_pc~0); 191766#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 191724#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191725#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 191938#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 192151#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 192420#L521 assume !(1 == ~t7_pc~0); 192463#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 191660#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 191661#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 192455#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 192430#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192336#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 191992#L869-2 assume !(1 == ~T1_E~0); 191993#L874-1 assume !(1 == ~T2_E~0); 192511#L879-1 assume !(1 == ~T3_E~0); 192073#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 191582#L889-1 assume !(1 == ~T5_E~0); 191583#L894-1 assume !(1 == ~T6_E~0); 191849#L899-1 assume !(1 == ~T7_E~0); 192287#L904-1 assume !(1 == ~E_M~0); 192017#L909-1 assume !(1 == ~E_1~0); 192018#L914-1 assume !(1 == ~E_2~0); 192215#L919-1 assume !(1 == ~E_3~0); 191929#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 191759#L929-1 assume !(1 == ~E_5~0); 191760#L934-1 assume !(1 == ~E_6~0); 192518#L939-1 assume !(1 == ~E_7~0); 194520#L944-1 assume { :end_inline_reset_delta_events } true; 194512#L1190-2 [2024-10-31 22:05:54,654 INFO L747 eck$LassoCheckResult]: Loop: 194512#L1190-2 assume !false; 194506#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 194502#L756-1 assume !false; 194499#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 194435#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 194332#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 194318#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 194310#L653 assume !(0 != eval_~tmp~0#1); 194311#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 198922#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 198921#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 198915#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 198913#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 198911#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 198909#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 198906#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 198904#L806-3 assume !(0 == ~T6_E~0); 198902#L811-3 assume !(0 == ~T7_E~0); 198900#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 198898#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 198896#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 198894#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 198892#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 198890#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 198888#L846-3 assume !(0 == ~E_6~0); 198886#L851-3 assume !(0 == ~E_7~0); 198884#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 198881#L388-27 assume 1 == ~m_pc~0; 198879#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 198876#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 198874#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 198872#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 198870#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 198867#L407-27 assume !(1 == ~t1_pc~0); 198865#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 198863#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 198861#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 198859#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 198857#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 198856#L426-27 assume !(1 == ~t2_pc~0); 198853#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 198850#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198848#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 198846#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 198844#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 198842#L445-27 assume !(1 == ~t3_pc~0); 198840#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 198838#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 198836#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198834#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 193081#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 193079#L464-27 assume 1 == ~t4_pc~0; 193076#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 193073#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 193074#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 198530#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 198526#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 198522#L483-27 assume !(1 == ~t5_pc~0); 198517#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 198515#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 198513#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 198504#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 198502#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 198500#L502-27 assume !(1 == ~t6_pc~0); 198497#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 198495#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198493#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 198491#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 198489#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 198487#L521-27 assume !(1 == ~t7_pc~0); 198485#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 198799#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 198797#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 198442#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 198439#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198437#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 193018#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 198433#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 198431#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 198429#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 198427#L889-3 assume !(1 == ~T5_E~0); 198259#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 193006#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 198256#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 198254#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 198251#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 198249#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 198247#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 198242#L929-3 assume !(1 == ~E_5~0); 194892#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 194888#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 194885#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 194566#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 194560#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 194558#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 194556#L1209 assume !(0 == start_simulation_~tmp~3#1); 194553#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 194540#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 194534#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 194531#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 194529#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 194525#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 194523#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 194521#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 194512#L1190-2 [2024-10-31 22:05:54,655 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:54,655 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2024-10-31 22:05:54,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:54,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621241810] [2024-10-31 22:05:54,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:54,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:54,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:54,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:54,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:54,873 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621241810] [2024-10-31 22:05:54,873 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621241810] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:54,873 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:54,873 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:05:54,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352119092] [2024-10-31 22:05:54,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:54,874 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:54,874 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:54,874 INFO L85 PathProgramCache]: Analyzing trace with hash 1082629472, now seen corresponding path program 1 times [2024-10-31 22:05:54,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:54,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697577675] [2024-10-31 22:05:54,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:54,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:54,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:54,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:54,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:54,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697577675] [2024-10-31 22:05:54,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [697577675] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:54,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:54,945 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:54,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304941344] [2024-10-31 22:05:54,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:54,946 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:54,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:54,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:05:54,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:05:54,946 INFO L87 Difference]: Start difference. First operand 35674 states and 50817 transitions. cyclomatic complexity: 15207 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:55,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:55,141 INFO L93 Difference]: Finished difference Result 44740 states and 63748 transitions. [2024-10-31 22:05:55,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44740 states and 63748 transitions. [2024-10-31 22:05:55,491 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 44344 [2024-10-31 22:05:55,644 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44740 states to 44740 states and 63748 transitions. [2024-10-31 22:05:55,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44740 [2024-10-31 22:05:55,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44740 [2024-10-31 22:05:55,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44740 states and 63748 transitions. [2024-10-31 22:05:55,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:55,710 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44740 states and 63748 transitions. [2024-10-31 22:05:55,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44740 states and 63748 transitions. [2024-10-31 22:05:56,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44740 to 19206. [2024-10-31 22:05:56,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.4305425387899615) internal successors, (27475), 19205 states have internal predecessors, (27475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:56,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27475 transitions. [2024-10-31 22:05:56,272 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27475 transitions. [2024-10-31 22:05:56,273 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:05:56,273 INFO L425 stractBuchiCegarLoop]: Abstraction has 19206 states and 27475 transitions. [2024-10-31 22:05:56,273 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 22:05:56,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27475 transitions. [2024-10-31 22:05:56,519 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-10-31 22:05:56,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:56,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:56,521 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:56,521 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:56,522 INFO L745 eck$LassoCheckResult]: Stem: 272247#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 272248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 272842#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 272843#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 272915#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 272395#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 272396#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 272523#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 272524#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 272293#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 272080#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 272081#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 272255#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 272256#L781 assume !(0 == ~M_E~0); 272766#L781-2 assume !(0 == ~T1_E~0); 272928#L786-1 assume !(0 == ~T2_E~0); 272043#L791-1 assume !(0 == ~T3_E~0); 272044#L796-1 assume !(0 == ~T4_E~0); 272597#L801-1 assume !(0 == ~T5_E~0); 272598#L806-1 assume !(0 == ~T6_E~0); 272630#L811-1 assume !(0 == ~T7_E~0); 272259#L816-1 assume !(0 == ~E_M~0); 272260#L821-1 assume !(0 == ~E_1~0); 272071#L826-1 assume !(0 == ~E_2~0); 272072#L831-1 assume !(0 == ~E_3~0); 272390#L836-1 assume !(0 == ~E_4~0); 272391#L841-1 assume !(0 == ~E_5~0); 272210#L846-1 assume !(0 == ~E_6~0); 272211#L851-1 assume !(0 == ~E_7~0); 272234#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272235#L388 assume !(1 == ~m_pc~0); 272228#L388-2 is_master_triggered_~__retres1~0#1 := 0; 272229#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272739#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 272086#L967 assume !(0 != activate_threads_~tmp~1#1); 272087#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 272017#L407 assume !(1 == ~t1_pc~0); 272018#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 272024#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272025#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 272059#L975 assume !(0 != activate_threads_~tmp___0~0#1); 272839#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272349#L426 assume !(1 == ~t2_pc~0); 272350#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 272867#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272371#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 272372#L983 assume !(0 != activate_threads_~tmp___1~0#1); 272907#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 272436#L445 assume !(1 == ~t3_pc~0); 272437#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 272773#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272015#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 272016#L991 assume !(0 != activate_threads_~tmp___2~0#1); 272695#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272659#L464 assume !(1 == ~t4_pc~0); 272240#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 272106#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 272107#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 272120#L999 assume !(0 != activate_threads_~tmp___3~0#1); 272416#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272417#L483 assume !(1 == ~t5_pc~0); 272656#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 272821#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272787#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 272788#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 272334#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272335#L502 assume !(1 == ~t6_pc~0); 272186#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 272146#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 272147#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 272359#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 272561#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 272799#L521 assume !(1 == ~t7_pc~0); 272836#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 272871#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 272932#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 272830#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 272804#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 272730#L869 assume !(1 == ~M_E~0); 272410#L869-2 assume !(1 == ~T1_E~0); 272411#L874-1 assume !(1 == ~T2_E~0); 272884#L879-1 assume !(1 == ~T3_E~0); 272486#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 272003#L889-1 assume !(1 == ~T5_E~0); 272004#L894-1 assume !(1 == ~T6_E~0); 272270#L899-1 assume !(1 == ~T7_E~0); 272684#L904-1 assume !(1 == ~E_M~0); 272433#L909-1 assume !(1 == ~E_1~0); 272434#L914-1 assume !(1 == ~E_2~0); 272616#L919-1 assume !(1 == ~E_3~0); 272348#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 272179#L929-1 assume !(1 == ~E_5~0); 272180#L934-1 assume !(1 == ~E_6~0); 272414#L939-1 assume !(1 == ~E_7~0); 272415#L944-1 assume { :end_inline_reset_delta_events } true; 272798#L1190-2 [2024-10-31 22:05:56,522 INFO L747 eck$LassoCheckResult]: Loop: 272798#L1190-2 assume !false; 278617#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 278612#L756-1 assume !false; 278610#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278608#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278592#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278590#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 278587#L653 assume !(0 != eval_~tmp~0#1); 278584#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 278580#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 278576#L781-3 assume !(0 == ~M_E~0); 278572#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 278568#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 278564#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 278561#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 278558#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 278557#L806-3 assume !(0 == ~T6_E~0); 278556#L811-3 assume !(0 == ~T7_E~0); 278493#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 278491#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 278489#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 278488#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 278485#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 278484#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 278483#L846-3 assume !(0 == ~E_6~0); 278481#L851-3 assume !(0 == ~E_7~0); 278480#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 278479#L388-27 assume !(1 == ~m_pc~0); 278477#L388-29 is_master_triggered_~__retres1~0#1 := 0; 278476#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278475#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 278474#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 278473#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278472#L407-27 assume !(1 == ~t1_pc~0); 278471#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 278470#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278469#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 278468#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 278467#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278466#L426-27 assume 1 == ~t2_pc~0; 278464#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 278462#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 278461#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 278460#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 278459#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278458#L445-27 assume !(1 == ~t3_pc~0); 278457#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 278456#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278454#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 278453#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 278452#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278451#L464-27 assume 1 == ~t4_pc~0; 278449#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 278448#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 278447#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 278445#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 278442#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 278440#L483-27 assume !(1 == ~t5_pc~0); 278438#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 278436#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 278434#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 278432#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 278430#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 278428#L502-27 assume !(1 == ~t6_pc~0); 278426#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 278424#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 278422#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278420#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 278417#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 278415#L521-27 assume 1 == ~t7_pc~0; 278413#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 278414#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 278455#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 278404#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 278401#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 278399#L869-3 assume !(1 == ~M_E~0); 276159#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 278396#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 278394#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 278392#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 278389#L889-3 assume !(1 == ~T5_E~0); 278387#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 278385#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 278383#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 278381#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 278379#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 278377#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 278375#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 278373#L929-3 assume !(1 == ~E_5~0); 278371#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 278369#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 278367#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278061#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278044#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278038#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 273240#L1209 assume !(0 == start_simulation_~tmp~3#1); 273241#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278861#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278855#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278853#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 278851#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 278848#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 278846#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 278844#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 272798#L1190-2 [2024-10-31 22:05:56,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:56,523 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2024-10-31 22:05:56,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:56,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411596607] [2024-10-31 22:05:56,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:56,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:56,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:56,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:56,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:56,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411596607] [2024-10-31 22:05:56,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411596607] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:56,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:56,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:56,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795617807] [2024-10-31 22:05:56,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:56,628 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:56,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:56,628 INFO L85 PathProgramCache]: Analyzing trace with hash 1171819677, now seen corresponding path program 1 times [2024-10-31 22:05:56,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:56,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270417331] [2024-10-31 22:05:56,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:56,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:56,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:56,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:56,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:56,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [270417331] [2024-10-31 22:05:56,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [270417331] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:56,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:56,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:56,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106564168] [2024-10-31 22:05:56,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:56,697 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:56,698 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:56,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:05:56,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:05:56,699 INFO L87 Difference]: Start difference. First operand 19206 states and 27475 transitions. cyclomatic complexity: 8285 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:56,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:56,946 INFO L93 Difference]: Finished difference Result 30482 states and 43470 transitions. [2024-10-31 22:05:56,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30482 states and 43470 transitions. [2024-10-31 22:05:57,108 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30128 [2024-10-31 22:05:57,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30482 states to 30482 states and 43470 transitions. [2024-10-31 22:05:57,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30482 [2024-10-31 22:05:57,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30482 [2024-10-31 22:05:57,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30482 states and 43470 transitions. [2024-10-31 22:05:57,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:57,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30482 states and 43470 transitions. [2024-10-31 22:05:57,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30482 states and 43470 transitions. [2024-10-31 22:05:57,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30482 to 21646. [2024-10-31 22:05:57,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4298715698050448) internal successors, (30951), 21645 states have internal predecessors, (30951), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:57,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30951 transitions. [2024-10-31 22:05:57,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30951 transitions. [2024-10-31 22:05:57,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:05:57,964 INFO L425 stractBuchiCegarLoop]: Abstraction has 21646 states and 30951 transitions. [2024-10-31 22:05:57,964 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-31 22:05:57,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30951 transitions. [2024-10-31 22:05:58,041 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-10-31 22:05:58,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:58,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:58,043 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:58,043 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:58,044 INFO L745 eck$LassoCheckResult]: Stem: 321943#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 321944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 322548#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 322549#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 322651#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 322089#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 322090#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 322217#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 322218#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 321988#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 321777#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 321778#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 321948#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 321949#L781 assume !(0 == ~M_E~0); 322463#L781-2 assume !(0 == ~T1_E~0); 322670#L786-1 assume !(0 == ~T2_E~0); 321737#L791-1 assume !(0 == ~T3_E~0); 321738#L796-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 322295#L801-1 assume !(0 == ~T5_E~0); 322296#L806-1 assume !(0 == ~T6_E~0); 322640#L811-1 assume !(0 == ~T7_E~0); 322641#L816-1 assume !(0 == ~E_M~0); 322551#L821-1 assume !(0 == ~E_1~0); 322552#L826-1 assume !(0 == ~E_2~0); 322293#L831-1 assume !(0 == ~E_3~0); 322294#L836-1 assume !(0 == ~E_4~0); 322698#L841-1 assume !(0 == ~E_5~0); 321906#L846-1 assume !(0 == ~E_6~0); 321907#L851-1 assume !(0 == ~E_7~0); 322697#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 322572#L388 assume !(1 == ~m_pc~0); 322573#L388-2 is_master_triggered_~__retres1~0#1 := 0; 322696#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 322486#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 322487#L967 assume !(0 != activate_threads_~tmp~1#1); 322642#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 322643#L407 assume !(1 == ~t1_pc~0); 322650#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 321719#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 321720#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 321754#L975 assume !(0 != activate_threads_~tmp___0~0#1); 322568#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 322569#L426 assume !(1 == ~t2_pc~0); 322580#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 322581#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 322066#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 322067#L983 assume !(0 != activate_threads_~tmp___1~0#1); 322693#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 322692#L445 assume !(1 == ~t3_pc~0); 322671#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 322473#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 322474#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 322690#L991 assume !(0 != activate_threads_~tmp___2~0#1); 322689#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 322360#L464 assume !(1 == ~t4_pc~0); 321933#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 321934#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 322686#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 322685#L999 assume !(0 != activate_threads_~tmp___3~0#1); 322684#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 322356#L483 assume !(1 == ~t5_pc~0); 322357#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 322523#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 322524#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 322600#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 322601#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 322683#L502 assume !(1 == ~t6_pc~0); 321883#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 321884#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 322051#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 322052#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 322502#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 322503#L521 assume !(1 == ~t7_pc~0); 322541#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 321779#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 321780#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 322675#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 322507#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 322429#L869 assume !(1 == ~M_E~0); 322104#L869-2 assume !(1 == ~T1_E~0); 322105#L874-1 assume !(1 == ~T2_E~0); 322596#L879-1 assume !(1 == ~T3_E~0); 322597#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 321701#L889-1 assume !(1 == ~T5_E~0); 321702#L894-1 assume !(1 == ~T6_E~0); 321963#L899-1 assume !(1 == ~T7_E~0); 322382#L904-1 assume !(1 == ~E_M~0); 322129#L909-1 assume !(1 == ~E_1~0); 322130#L914-1 assume !(1 == ~E_2~0); 322314#L919-1 assume !(1 == ~E_3~0); 322042#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 321876#L929-1 assume !(1 == ~E_5~0); 321877#L934-1 assume !(1 == ~E_6~0); 322106#L939-1 assume !(1 == ~E_7~0); 322107#L944-1 assume { :end_inline_reset_delta_events } true; 322501#L1190-2 [2024-10-31 22:05:58,044 INFO L747 eck$LassoCheckResult]: Loop: 322501#L1190-2 assume !false; 336372#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 336370#L756-1 assume !false; 336367#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 336365#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 336356#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 336355#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 336351#L653 assume !(0 != eval_~tmp~0#1); 336352#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 342590#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 342585#L781-3 assume !(0 == ~M_E~0); 342579#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 342574#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 342568#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 342562#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 342561#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 342560#L806-3 assume !(0 == ~T6_E~0); 342559#L811-3 assume !(0 == ~T7_E~0); 342558#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 342557#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 342556#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 342555#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 342554#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 342553#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 342552#L846-3 assume !(0 == ~E_6~0); 342551#L851-3 assume !(0 == ~E_7~0); 342550#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 342549#L388-27 assume 1 == ~m_pc~0; 342548#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 342546#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 342545#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 342544#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 342543#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 342542#L407-27 assume !(1 == ~t1_pc~0); 342541#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 342540#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 342539#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 342538#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 342537#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 342536#L426-27 assume !(1 == ~t2_pc~0); 342535#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 342533#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 342532#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 342531#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 342530#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 342529#L445-27 assume !(1 == ~t3_pc~0); 342528#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 342527#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 342526#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 342525#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 342524#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 342523#L464-27 assume 1 == ~t4_pc~0; 342521#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 342520#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 342519#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 342518#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 342517#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 342516#L483-27 assume !(1 == ~t5_pc~0); 342515#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 342514#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 342513#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 342512#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 342511#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 342510#L502-27 assume !(1 == ~t6_pc~0); 342509#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 342508#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 342507#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 342506#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 342505#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 342504#L521-27 assume !(1 == ~t7_pc~0); 342503#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 342501#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 342499#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 342497#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 342495#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 342494#L869-3 assume !(1 == ~M_E~0); 329222#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 342493#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 342492#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 342490#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 342485#L889-3 assume !(1 == ~T5_E~0); 342481#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 342476#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 342471#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 342467#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 342385#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 342384#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 342371#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 342370#L929-3 assume !(1 == ~E_5~0); 342369#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 342368#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 342367#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 342363#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 342350#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 342348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 329116#L1209 assume !(0 == start_simulation_~tmp~3#1); 329117#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 336510#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 336504#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 336501#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 336500#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 336499#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 336498#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 336497#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 322501#L1190-2 [2024-10-31 22:05:58,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:58,045 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2024-10-31 22:05:58,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:58,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5057676] [2024-10-31 22:05:58,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:58,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:58,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:58,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:58,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:58,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5057676] [2024-10-31 22:05:58,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5057676] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:58,123 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:58,123 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:58,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93229594] [2024-10-31 22:05:58,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:58,123 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:58,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:58,124 INFO L85 PathProgramCache]: Analyzing trace with hash 849857952, now seen corresponding path program 1 times [2024-10-31 22:05:58,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:58,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777445126] [2024-10-31 22:05:58,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:58,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:58,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:58,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:58,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:58,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [777445126] [2024-10-31 22:05:58,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [777445126] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:58,172 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:58,172 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:58,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888593179] [2024-10-31 22:05:58,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:58,173 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:58,173 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:58,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:05:58,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:05:58,173 INFO L87 Difference]: Start difference. First operand 21646 states and 30951 transitions. cyclomatic complexity: 9321 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:58,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:58,328 INFO L93 Difference]: Finished difference Result 28030 states and 39857 transitions. [2024-10-31 22:05:58,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28030 states and 39857 transitions. [2024-10-31 22:05:58,440 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27760 [2024-10-31 22:05:58,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28030 states to 28030 states and 39857 transitions. [2024-10-31 22:05:58,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28030 [2024-10-31 22:05:58,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28030 [2024-10-31 22:05:58,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28030 states and 39857 transitions. [2024-10-31 22:05:58,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:58,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28030 states and 39857 transitions. [2024-10-31 22:05:58,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28030 states and 39857 transitions. [2024-10-31 22:05:59,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28030 to 19206. [2024-10-31 22:05:59,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.42543996667708) internal successors, (27377), 19205 states have internal predecessors, (27377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:59,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27377 transitions. [2024-10-31 22:05:59,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27377 transitions. [2024-10-31 22:05:59,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:05:59,263 INFO L425 stractBuchiCegarLoop]: Abstraction has 19206 states and 27377 transitions. [2024-10-31 22:05:59,263 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-31 22:05:59,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27377 transitions. [2024-10-31 22:05:59,318 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-10-31 22:05:59,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:05:59,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:05:59,320 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:59,320 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:05:59,320 INFO L745 eck$LassoCheckResult]: Stem: 371631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 371632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 372252#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 372253#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 372329#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 371778#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 371779#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 371908#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 371909#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 371678#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 371463#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 371464#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 371636#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 371637#L781 assume !(0 == ~M_E~0); 372158#L781-2 assume !(0 == ~T1_E~0); 372347#L786-1 assume !(0 == ~T2_E~0); 371423#L791-1 assume !(0 == ~T3_E~0); 371424#L796-1 assume !(0 == ~T4_E~0); 371986#L801-1 assume !(0 == ~T5_E~0); 371987#L806-1 assume !(0 == ~T6_E~0); 372021#L811-1 assume !(0 == ~T7_E~0); 371643#L816-1 assume !(0 == ~E_M~0); 371644#L821-1 assume !(0 == ~E_1~0); 371454#L826-1 assume !(0 == ~E_2~0); 371455#L831-1 assume !(0 == ~E_3~0); 371773#L836-1 assume !(0 == ~E_4~0); 371774#L841-1 assume !(0 == ~E_5~0); 371594#L846-1 assume !(0 == ~E_6~0); 371595#L851-1 assume !(0 == ~E_7~0); 371618#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371619#L388 assume !(1 == ~m_pc~0); 371612#L388-2 is_master_triggered_~__retres1~0#1 := 0; 371613#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 372132#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 371469#L967 assume !(0 != activate_threads_~tmp~1#1); 371470#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 371401#L407 assume !(1 == ~t1_pc~0); 371402#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 371405#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 371406#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371440#L975 assume !(0 != activate_threads_~tmp___0~0#1); 372250#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 371734#L426 assume !(1 == ~t2_pc~0); 371735#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 372274#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 371756#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 371757#L983 assume !(0 != activate_threads_~tmp___1~0#1); 372316#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 371823#L445 assume !(1 == ~t3_pc~0); 371824#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 372165#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 371399#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 371400#L991 assume !(0 != activate_threads_~tmp___2~0#1); 372086#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372049#L464 assume !(1 == ~t4_pc~0); 371622#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 371489#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 371490#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 371501#L999 assume !(0 != activate_threads_~tmp___3~0#1); 371801#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371802#L483 assume !(1 == ~t5_pc~0); 372046#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 372227#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 372191#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 372192#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 371718#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 371719#L502 assume !(1 == ~t6_pc~0); 371569#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 371529#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 371530#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 371742#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 371948#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 372204#L521 assume !(1 == ~t7_pc~0); 372246#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 371465#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 371466#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 372239#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 372210#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 372121#L869 assume !(1 == ~M_E~0); 371795#L869-2 assume !(1 == ~T1_E~0); 371796#L874-1 assume !(1 == ~T2_E~0); 372287#L879-1 assume !(1 == ~T3_E~0); 371873#L884-1 assume !(1 == ~T4_E~0); 371387#L889-1 assume !(1 == ~T5_E~0); 371388#L894-1 assume !(1 == ~T6_E~0); 371651#L899-1 assume !(1 == ~T7_E~0); 372072#L904-1 assume !(1 == ~E_M~0); 371820#L909-1 assume !(1 == ~E_1~0); 371821#L914-1 assume !(1 == ~E_2~0); 372007#L919-1 assume !(1 == ~E_3~0); 371733#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 371562#L929-1 assume !(1 == ~E_5~0); 371563#L934-1 assume !(1 == ~E_6~0); 371797#L939-1 assume !(1 == ~E_7~0); 371798#L944-1 assume { :end_inline_reset_delta_events } true; 372203#L1190-2 [2024-10-31 22:05:59,321 INFO L747 eck$LassoCheckResult]: Loop: 372203#L1190-2 assume !false; 384809#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 384807#L756-1 assume !false; 384805#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 384803#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 384793#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 384791#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 384788#L653 assume !(0 != eval_~tmp~0#1); 384789#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 390368#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 390364#L781-3 assume !(0 == ~M_E~0); 390360#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 390356#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 390351#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 390346#L796-3 assume !(0 == ~T4_E~0); 390342#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 390338#L806-3 assume !(0 == ~T6_E~0); 390334#L811-3 assume !(0 == ~T7_E~0); 390330#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 390326#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 390321#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 390317#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 390313#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 390309#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 390304#L846-3 assume !(0 == ~E_6~0); 390301#L851-3 assume !(0 == ~E_7~0); 390299#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 390297#L388-27 assume 1 == ~m_pc~0; 390295#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 390292#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 390290#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 390288#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 390286#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 390284#L407-27 assume !(1 == ~t1_pc~0); 390282#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 390280#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 390278#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390272#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 390267#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390263#L426-27 assume !(1 == ~t2_pc~0); 390259#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 390254#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 390250#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 390246#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 390242#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 390238#L445-27 assume !(1 == ~t3_pc~0); 390234#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 390229#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 390226#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 390224#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 390222#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 390220#L464-27 assume 1 == ~t4_pc~0; 390217#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 390215#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 390213#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 390211#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 390209#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 390207#L483-27 assume !(1 == ~t5_pc~0); 390205#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 390203#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 390198#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 390194#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 390189#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 390185#L502-27 assume !(1 == ~t6_pc~0); 390181#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 390177#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 390169#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 390163#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 390160#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 390158#L521-27 assume 1 == ~t7_pc~0; 390156#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 390157#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 390167#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 390148#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 390143#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 390138#L869-3 assume !(1 == ~M_E~0); 379251#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 390130#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 390126#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 390123#L884-3 assume !(1 == ~T4_E~0); 390118#L889-3 assume !(1 == ~T5_E~0); 390113#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 390108#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 390102#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 390099#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 390096#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 390094#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 390093#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 390092#L929-3 assume !(1 == ~E_5~0); 390090#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 390088#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 390086#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 389908#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 389903#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 389553#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 379370#L1209 assume !(0 == start_simulation_~tmp~3#1); 379371#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 384895#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 384889#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 384887#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 384885#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 384883#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 384881#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 384879#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 372203#L1190-2 [2024-10-31 22:05:59,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:59,322 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2024-10-31 22:05:59,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:59,322 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522020518] [2024-10-31 22:05:59,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:59,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:59,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:59,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:59,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:59,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522020518] [2024-10-31 22:05:59,402 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522020518] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:59,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:59,403 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:59,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [580424741] [2024-10-31 22:05:59,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:59,404 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:05:59,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:05:59,404 INFO L85 PathProgramCache]: Analyzing trace with hash 1114420829, now seen corresponding path program 1 times [2024-10-31 22:05:59,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:05:59,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286016850] [2024-10-31 22:05:59,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:05:59,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:05:59,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:05:59,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:05:59,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:05:59,454 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286016850] [2024-10-31 22:05:59,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286016850] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:05:59,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:05:59,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:05:59,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099762735] [2024-10-31 22:05:59,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:05:59,456 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:05:59,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:05:59,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:05:59,456 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:05:59,457 INFO L87 Difference]: Start difference. First operand 19206 states and 27377 transitions. cyclomatic complexity: 8187 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:05:59,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:05:59,685 INFO L93 Difference]: Finished difference Result 30510 states and 43007 transitions. [2024-10-31 22:05:59,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30510 states and 43007 transitions. [2024-10-31 22:05:59,801 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30116 [2024-10-31 22:05:59,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30510 states to 30510 states and 43007 transitions. [2024-10-31 22:05:59,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30510 [2024-10-31 22:05:59,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30510 [2024-10-31 22:05:59,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30510 states and 43007 transitions. [2024-10-31 22:05:59,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:05:59,935 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30510 states and 43007 transitions. [2024-10-31 22:05:59,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30510 states and 43007 transitions. [2024-10-31 22:06:00,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30510 to 21646. [2024-10-31 22:06:00,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4149496442760787) internal successors, (30628), 21645 states have internal predecessors, (30628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:06:00,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30628 transitions. [2024-10-31 22:06:00,495 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30628 transitions. [2024-10-31 22:06:00,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:06:00,496 INFO L425 stractBuchiCegarLoop]: Abstraction has 21646 states and 30628 transitions. [2024-10-31 22:06:00,496 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-31 22:06:00,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30628 transitions. [2024-10-31 22:06:00,556 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-10-31 22:06:00,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:06:00,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:06:00,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:00,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:00,559 INFO L745 eck$LassoCheckResult]: Stem: 421355#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 421356#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 421985#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 421986#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 422085#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 421506#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 421507#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 421638#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 421639#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 421402#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 421190#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 421191#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 421363#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 421364#L781 assume !(0 == ~M_E~0); 421889#L781-2 assume !(0 == ~T1_E~0); 422096#L786-1 assume !(0 == ~T2_E~0); 421153#L791-1 assume !(0 == ~T3_E~0); 421154#L796-1 assume !(0 == ~T4_E~0); 421719#L801-1 assume !(0 == ~T5_E~0); 421720#L806-1 assume !(0 == ~T6_E~0); 421752#L811-1 assume !(0 == ~T7_E~0); 421367#L816-1 assume !(0 == ~E_M~0); 421368#L821-1 assume !(0 == ~E_1~0); 421181#L826-1 assume !(0 == ~E_2~0); 421182#L831-1 assume !(0 == ~E_3~0); 421500#L836-1 assume 0 == ~E_4~0;~E_4~0 := 1; 421501#L841-1 assume !(0 == ~E_5~0); 421318#L846-1 assume !(0 == ~E_6~0); 421319#L851-1 assume !(0 == ~E_7~0); 422152#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 422008#L388 assume !(1 == ~m_pc~0); 422009#L388-2 is_master_triggered_~__retres1~0#1 := 0; 422151#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 421917#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 421918#L967 assume !(0 != activate_threads_~tmp~1#1); 422076#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 422077#L407 assume !(1 == ~t1_pc~0); 422084#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 421134#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 421135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 421169#L975 assume !(0 != activate_threads_~tmp___0~0#1); 422003#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 422004#L426 assume !(1 == ~t2_pc~0); 422017#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 422018#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 421481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 421482#L983 assume !(0 != activate_threads_~tmp___1~0#1); 422147#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422146#L445 assume !(1 == ~t3_pc~0); 422145#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 422144#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 421125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 421126#L991 assume !(0 != activate_threads_~tmp___2~0#1); 421819#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 421895#L464 assume !(1 == ~t4_pc~0); 422140#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 422139#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 422138#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422137#L999 assume !(0 != activate_threads_~tmp___3~0#1); 422136#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 422135#L483 assume !(1 == ~t5_pc~0); 422134#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 422133#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 422132#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 422131#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 422130#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 422129#L502 assume !(1 == ~t6_pc~0); 422128#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 422127#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 422126#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 422125#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 422124#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 422123#L521 assume !(1 == ~t7_pc~0); 422121#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 422119#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 422117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 422115#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 422114#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422113#L869 assume !(1 == ~M_E~0); 422112#L869-2 assume !(1 == ~T1_E~0); 422111#L874-1 assume !(1 == ~T2_E~0); 422110#L879-1 assume !(1 == ~T3_E~0); 422109#L884-1 assume !(1 == ~T4_E~0); 422108#L889-1 assume !(1 == ~T5_E~0); 422107#L894-1 assume !(1 == ~T6_E~0); 422106#L899-1 assume !(1 == ~T7_E~0); 422105#L904-1 assume !(1 == ~E_M~0); 422104#L909-1 assume !(1 == ~E_1~0); 422103#L914-1 assume !(1 == ~E_2~0); 422102#L919-1 assume !(1 == ~E_3~0); 422101#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 421289#L929-1 assume !(1 == ~E_5~0); 421290#L934-1 assume !(1 == ~E_6~0); 421528#L939-1 assume !(1 == ~E_7~0); 421529#L944-1 assume { :end_inline_reset_delta_events } true; 421936#L1190-2 [2024-10-31 22:06:00,560 INFO L747 eck$LassoCheckResult]: Loop: 421936#L1190-2 assume !false; 434492#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 434490#L756-1 assume !false; 434488#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 434486#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 434476#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 434466#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 434456#L653 assume !(0 != eval_~tmp~0#1); 434457#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 442268#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 442266#L781-3 assume !(0 == ~M_E~0); 442265#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 442263#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 442261#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 442259#L796-3 assume !(0 == ~T4_E~0); 442257#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 441948#L806-3 assume !(0 == ~T6_E~0); 441938#L811-3 assume !(0 == ~T7_E~0); 441933#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 441928#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 441921#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 441920#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 441918#L836-3 assume !(0 == ~E_4~0); 441919#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 442363#L846-3 assume !(0 == ~E_6~0); 442362#L851-3 assume !(0 == ~E_7~0); 442361#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 442360#L388-27 assume !(1 == ~m_pc~0); 442358#L388-29 is_master_triggered_~__retres1~0#1 := 0; 442357#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 442356#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 442355#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 442354#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 442352#L407-27 assume !(1 == ~t1_pc~0); 442350#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 442348#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 442346#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 442343#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 442341#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 442339#L426-27 assume 1 == ~t2_pc~0; 442336#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 442334#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 442332#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 442329#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 442327#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 442325#L445-27 assume !(1 == ~t3_pc~0); 442323#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 442321#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 442319#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 442316#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 442314#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 442312#L464-27 assume !(1 == ~t4_pc~0); 441885#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 442308#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 442306#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 442303#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 442301#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 442299#L483-27 assume !(1 == ~t5_pc~0); 442297#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 442295#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 442292#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 442291#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 442289#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 442287#L502-27 assume !(1 == ~t6_pc~0); 442285#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 442283#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 442282#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 442281#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 442279#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 442278#L521-27 assume !(1 == ~t7_pc~0); 442276#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 442274#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 442272#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 442271#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 442269#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 442267#L869-3 assume !(1 == ~M_E~0); 425629#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 442264#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 442262#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 442260#L884-3 assume !(1 == ~T4_E~0); 442258#L889-3 assume !(1 == ~T5_E~0); 441940#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 441936#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 441931#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 441927#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 441926#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 441925#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 441846#L924-3 assume !(1 == ~E_4~0); 441843#L929-3 assume !(1 == ~E_5~0); 441842#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 441841#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 441840#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 441824#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 441818#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 441816#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 425906#L1209 assume !(0 == start_simulation_~tmp~3#1); 425907#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 434633#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 434627#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 434625#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 434623#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 434620#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 434619#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 434618#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 421936#L1190-2 [2024-10-31 22:06:00,561 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:00,561 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2024-10-31 22:06:00,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:00,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025359290] [2024-10-31 22:06:00,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:00,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:00,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:06:00,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:06:00,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:06:00,625 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025359290] [2024-10-31 22:06:00,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025359290] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:06:00,625 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:06:00,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:06:00,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496341802] [2024-10-31 22:06:00,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:06:00,626 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:06:00,626 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:00,627 INFO L85 PathProgramCache]: Analyzing trace with hash 352144737, now seen corresponding path program 1 times [2024-10-31 22:06:00,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:00,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817276493] [2024-10-31 22:06:00,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:00,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:00,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:06:00,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:06:00,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:06:00,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817276493] [2024-10-31 22:06:00,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817276493] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:06:00,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:06:00,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:06:00,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [250714833] [2024-10-31 22:06:00,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:06:00,683 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:06:00,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:06:00,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:06:00,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:06:00,684 INFO L87 Difference]: Start difference. First operand 21646 states and 30628 transitions. cyclomatic complexity: 8998 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:06:00,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:06:00,877 INFO L93 Difference]: Finished difference Result 27562 states and 38762 transitions. [2024-10-31 22:06:00,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27562 states and 38762 transitions. [2024-10-31 22:06:00,989 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27284 [2024-10-31 22:06:01,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27562 states to 27562 states and 38762 transitions. [2024-10-31 22:06:01,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27562 [2024-10-31 22:06:01,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27562 [2024-10-31 22:06:01,095 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27562 states and 38762 transitions. [2024-10-31 22:06:01,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:06:01,115 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27562 states and 38762 transitions. [2024-10-31 22:06:01,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27562 states and 38762 transitions. [2024-10-31 22:06:01,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27562 to 19206. [2024-10-31 22:06:01,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.408622305529522) internal successors, (27054), 19205 states have internal predecessors, (27054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:06:01,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27054 transitions. [2024-10-31 22:06:01,713 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27054 transitions. [2024-10-31 22:06:01,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:06:01,714 INFO L425 stractBuchiCegarLoop]: Abstraction has 19206 states and 27054 transitions. [2024-10-31 22:06:01,714 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-31 22:06:01,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27054 transitions. [2024-10-31 22:06:01,788 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-10-31 22:06:01,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:06:01,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:06:01,790 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:01,791 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:01,791 INFO L745 eck$LassoCheckResult]: Stem: 470573#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 470574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 471194#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 471195#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 471290#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 470716#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 470717#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 470842#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 470843#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 470620#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 470408#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 470409#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 470579#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 470580#L781 assume !(0 == ~M_E~0); 471099#L781-2 assume !(0 == ~T1_E~0); 471305#L786-1 assume !(0 == ~T2_E~0); 470371#L791-1 assume !(0 == ~T3_E~0); 470372#L796-1 assume !(0 == ~T4_E~0); 470921#L801-1 assume !(0 == ~T5_E~0); 470922#L806-1 assume !(0 == ~T6_E~0); 470953#L811-1 assume !(0 == ~T7_E~0); 470585#L816-1 assume !(0 == ~E_M~0); 470586#L821-1 assume !(0 == ~E_1~0); 470399#L826-1 assume !(0 == ~E_2~0); 470400#L831-1 assume !(0 == ~E_3~0); 470711#L836-1 assume !(0 == ~E_4~0); 470712#L841-1 assume !(0 == ~E_5~0); 470536#L846-1 assume !(0 == ~E_6~0); 470537#L851-1 assume !(0 == ~E_7~0); 470560#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 470561#L388 assume !(1 == ~m_pc~0); 470554#L388-2 is_master_triggered_~__retres1~0#1 := 0; 470555#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471069#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 470414#L967 assume !(0 != activate_threads_~tmp~1#1); 470415#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 470345#L407 assume !(1 == ~t1_pc~0); 470346#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 470352#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 470353#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 470387#L975 assume !(0 != activate_threads_~tmp___0~0#1); 471192#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 470672#L426 assume !(1 == ~t2_pc~0); 470673#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 471225#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 470694#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 470695#L983 assume !(0 != activate_threads_~tmp___1~0#1); 471282#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 470756#L445 assume !(1 == ~t3_pc~0); 470757#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 471106#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 470343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 470344#L991 assume !(0 != activate_threads_~tmp___2~0#1); 471022#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 470984#L464 assume !(1 == ~t4_pc~0); 470566#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 470434#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 470435#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 470448#L999 assume !(0 != activate_threads_~tmp___3~0#1); 470736#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 470737#L483 assume !(1 == ~t5_pc~0); 470981#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 471166#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 471129#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 471130#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 470659#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 470660#L502 assume !(1 == ~t6_pc~0); 470514#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 470474#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 470475#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 470683#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 470881#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 471144#L521 assume !(1 == ~t7_pc~0); 471189#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 470410#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 470411#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 471180#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 471150#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 471059#L869 assume !(1 == ~M_E~0); 470730#L869-2 assume !(1 == ~T1_E~0); 470731#L874-1 assume !(1 == ~T2_E~0); 471245#L879-1 assume !(1 == ~T3_E~0); 470806#L884-1 assume !(1 == ~T4_E~0); 470331#L889-1 assume !(1 == ~T5_E~0); 470332#L894-1 assume !(1 == ~T6_E~0); 470596#L899-1 assume !(1 == ~T7_E~0); 471010#L904-1 assume !(1 == ~E_M~0); 470753#L909-1 assume !(1 == ~E_1~0); 470754#L914-1 assume !(1 == ~E_2~0); 470940#L919-1 assume !(1 == ~E_3~0); 470671#L924-1 assume !(1 == ~E_4~0); 470507#L929-1 assume !(1 == ~E_5~0); 470508#L934-1 assume !(1 == ~E_6~0); 470734#L939-1 assume !(1 == ~E_7~0); 470735#L944-1 assume { :end_inline_reset_delta_events } true; 471143#L1190-2 [2024-10-31 22:06:01,792 INFO L747 eck$LassoCheckResult]: Loop: 471143#L1190-2 assume !false; 477129#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 477127#L756-1 assume !false; 477125#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 477122#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 477113#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 477111#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 477108#L653 assume !(0 != eval_~tmp~0#1); 477106#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 477104#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 477102#L781-3 assume !(0 == ~M_E~0); 477100#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 477098#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 477096#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 477041#L796-3 assume !(0 == ~T4_E~0); 477036#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 477031#L806-3 assume !(0 == ~T6_E~0); 477025#L811-3 assume !(0 == ~T7_E~0); 477020#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 477015#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 477010#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 477004#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 476998#L836-3 assume !(0 == ~E_4~0); 476993#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 476988#L846-3 assume !(0 == ~E_6~0); 476982#L851-3 assume !(0 == ~E_7~0); 476977#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 476972#L388-27 assume 1 == ~m_pc~0; 476967#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 476961#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 476956#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 476950#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 476945#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 476939#L407-27 assume !(1 == ~t1_pc~0); 476933#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 476928#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 476923#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 476917#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 476911#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 476906#L426-27 assume !(1 == ~t2_pc~0); 476901#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 476895#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 476890#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 476885#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 476878#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 476872#L445-27 assume !(1 == ~t3_pc~0); 476867#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 476862#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 476856#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 476851#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 476845#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 476839#L464-27 assume !(1 == ~t4_pc~0); 476833#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 476828#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 476823#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 476817#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 476812#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 476807#L483-27 assume !(1 == ~t5_pc~0); 476801#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 476796#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 476791#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 476785#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 476780#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 476774#L502-27 assume !(1 == ~t6_pc~0); 476767#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 476760#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 476753#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 476746#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 476740#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 476735#L521-27 assume !(1 == ~t7_pc~0); 476730#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 476724#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 476718#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 476713#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 476707#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 476702#L869-3 assume !(1 == ~M_E~0); 476431#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 476693#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 476688#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 476683#L884-3 assume !(1 == ~T4_E~0); 476677#L889-3 assume !(1 == ~T5_E~0); 476671#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 476666#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 476661#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 476657#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 476578#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 476577#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 476576#L924-3 assume !(1 == ~E_4~0); 476575#L929-3 assume !(1 == ~E_5~0); 476574#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 476573#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 476572#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 476542#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 476534#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 476532#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 476486#L1209 assume !(0 == start_simulation_~tmp~3#1); 476487#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 477166#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 477153#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 477151#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 477149#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 477147#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 477145#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 477143#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 471143#L1190-2 [2024-10-31 22:06:01,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:01,793 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2024-10-31 22:06:01,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:01,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862163005] [2024-10-31 22:06:01,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:01,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:01,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:06:01,815 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:06:01,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:06:01,882 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:06:01,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:01,883 INFO L85 PathProgramCache]: Analyzing trace with hash -1722865951, now seen corresponding path program 1 times [2024-10-31 22:06:01,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:01,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984854511] [2024-10-31 22:06:01,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:01,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:01,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:06:01,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:06:01,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:06:01,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1984854511] [2024-10-31 22:06:01,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1984854511] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:06:01,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:06:01,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:06:01,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336857442] [2024-10-31 22:06:01,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:06:01,948 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:06:01,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:06:01,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:06:01,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:06:01,949 INFO L87 Difference]: Start difference. First operand 19206 states and 27054 transitions. cyclomatic complexity: 7864 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:06:02,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:06:02,061 INFO L93 Difference]: Finished difference Result 21646 states and 30463 transitions. [2024-10-31 22:06:02,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21646 states and 30463 transitions. [2024-10-31 22:06:02,166 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-10-31 22:06:02,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21646 states to 21646 states and 30463 transitions. [2024-10-31 22:06:02,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21646 [2024-10-31 22:06:02,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21646 [2024-10-31 22:06:02,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21646 states and 30463 transitions. [2024-10-31 22:06:02,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:06:02,276 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30463 transitions. [2024-10-31 22:06:02,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21646 states and 30463 transitions. [2024-10-31 22:06:02,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21646 to 21646. [2024-10-31 22:06:02,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4073269888201054) internal successors, (30463), 21645 states have internal predecessors, (30463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:06:02,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30463 transitions. [2024-10-31 22:06:02,613 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30463 transitions. [2024-10-31 22:06:02,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:06:02,614 INFO L425 stractBuchiCegarLoop]: Abstraction has 21646 states and 30463 transitions. [2024-10-31 22:06:02,614 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-31 22:06:02,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30463 transitions. [2024-10-31 22:06:02,692 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-10-31 22:06:02,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:06:02,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:06:02,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:02,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:02,696 INFO L745 eck$LassoCheckResult]: Stem: 511431#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 511432#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 512046#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 512047#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 512137#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 511574#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 511575#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 511700#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 511701#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 511477#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 511265#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 511266#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 511438#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 511439#L781 assume !(0 == ~M_E~0); 511952#L781-2 assume !(0 == ~T1_E~0); 512154#L786-1 assume !(0 == ~T2_E~0); 511228#L791-1 assume !(0 == ~T3_E~0); 511229#L796-1 assume !(0 == ~T4_E~0); 511779#L801-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 511780#L806-1 assume !(0 == ~T6_E~0); 511815#L811-1 assume !(0 == ~T7_E~0); 511442#L816-1 assume !(0 == ~E_M~0); 511443#L821-1 assume !(0 == ~E_1~0); 511257#L826-1 assume !(0 == ~E_2~0); 511258#L831-1 assume !(0 == ~E_3~0); 512198#L836-1 assume !(0 == ~E_4~0); 512197#L841-1 assume !(0 == ~E_5~0); 512196#L846-1 assume !(0 == ~E_6~0); 512143#L851-1 assume !(0 == ~E_7~0); 511417#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 511418#L388 assume !(1 == ~m_pc~0); 511411#L388-2 is_master_triggered_~__retres1~0#1 := 0; 511412#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 511929#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 511271#L967 assume !(0 != activate_threads_~tmp~1#1); 511272#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 511203#L407 assume !(1 == ~t1_pc~0); 511204#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 512193#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 512192#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 512042#L975 assume !(0 != activate_threads_~tmp___0~0#1); 512043#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 511529#L426 assume !(1 == ~t2_pc~0); 511530#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 512121#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 511551#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 511552#L983 assume !(0 != activate_threads_~tmp___1~0#1); 512190#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 512189#L445 assume !(1 == ~t3_pc~0); 512188#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 512187#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 511201#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 511202#L991 assume !(0 != activate_threads_~tmp___2~0#1); 511884#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 511958#L464 assume !(1 == ~t4_pc~0); 512183#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 511291#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 511292#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 511305#L999 assume !(0 != activate_threads_~tmp___3~0#1); 511594#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 511595#L483 assume !(1 == ~t5_pc~0); 511842#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 512019#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 512020#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 512093#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 512094#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 512178#L502 assume !(1 == ~t6_pc~0); 511371#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 511372#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 512176#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 512175#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 512174#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 512173#L521 assume !(1 == ~t7_pc~0); 512078#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 512079#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 512177#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 512168#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 512167#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 512166#L869 assume !(1 == ~M_E~0); 512165#L869-2 assume !(1 == ~T1_E~0); 512164#L874-1 assume !(1 == ~T2_E~0); 512163#L879-1 assume !(1 == ~T3_E~0); 512162#L884-1 assume !(1 == ~T4_E~0); 511189#L889-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 511190#L894-1 assume !(1 == ~T6_E~0); 511453#L899-1 assume !(1 == ~T7_E~0); 511874#L904-1 assume !(1 == ~E_M~0); 511612#L909-1 assume !(1 == ~E_1~0); 511613#L914-1 assume !(1 == ~E_2~0); 511802#L919-1 assume !(1 == ~E_3~0); 511528#L924-1 assume !(1 == ~E_4~0); 511364#L929-1 assume !(1 == ~E_5~0); 511365#L934-1 assume !(1 == ~E_6~0); 511592#L939-1 assume !(1 == ~E_7~0); 511593#L944-1 assume { :end_inline_reset_delta_events } true; 511995#L1190-2 [2024-10-31 22:06:02,696 INFO L747 eck$LassoCheckResult]: Loop: 511995#L1190-2 assume !false; 515875#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 515873#L756-1 assume !false; 515871#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 515869#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 515860#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 515857#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 515854#L653 assume !(0 != eval_~tmp~0#1); 515855#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 516863#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 516862#L781-3 assume !(0 == ~M_E~0); 516861#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 516860#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 516859#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 516857#L796-3 assume !(0 == ~T4_E~0); 516853#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 516854#L806-3 assume !(0 == ~T6_E~0); 518423#L811-3 assume !(0 == ~T7_E~0); 518421#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 518419#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 518417#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 518415#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 518413#L836-3 assume !(0 == ~E_4~0); 518411#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 518409#L846-3 assume !(0 == ~E_6~0); 518407#L851-3 assume !(0 == ~E_7~0); 518405#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 518402#L388-27 assume 1 == ~m_pc~0; 518367#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 518364#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 518362#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 518360#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 518357#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 518353#L407-27 assume !(1 == ~t1_pc~0); 518351#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 518349#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 518347#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 518344#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 517692#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 517691#L426-27 assume !(1 == ~t2_pc~0); 517690#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 516571#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 516567#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 516565#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 516563#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 516562#L445-27 assume !(1 == ~t3_pc~0); 516559#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 516550#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 516548#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 516546#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 516544#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 516542#L464-27 assume !(1 == ~t4_pc~0); 516539#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 516537#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 516536#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 516533#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 516531#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 516529#L483-27 assume !(1 == ~t5_pc~0); 516527#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 516525#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 516523#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 516521#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 516519#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 516517#L502-27 assume !(1 == ~t6_pc~0); 516515#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 516513#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 516511#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 516508#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 516506#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 516504#L521-27 assume 1 == ~t7_pc~0; 516502#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 516503#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 516715#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 516493#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 516491#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516489#L869-3 assume !(1 == ~M_E~0); 516132#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 516486#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 516483#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 516481#L884-3 assume !(1 == ~T4_E~0); 516479#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 516476#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 516474#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 516472#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 516470#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 516467#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 516465#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 516463#L924-3 assume !(1 == ~E_4~0); 516461#L929-3 assume !(1 == ~E_5~0); 516459#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 516457#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 516455#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 516442#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 516436#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 516433#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 516430#L1209 assume !(0 == start_simulation_~tmp~3#1); 516431#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 516555#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 516549#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 516547#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 516545#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 516543#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 516540#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 516538#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 511995#L1190-2 [2024-10-31 22:06:02,697 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:02,697 INFO L85 PathProgramCache]: Analyzing trace with hash 1343517957, now seen corresponding path program 1 times [2024-10-31 22:06:02,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:02,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846532203] [2024-10-31 22:06:02,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:02,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:02,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:06:02,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:06:02,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:06:02,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846532203] [2024-10-31 22:06:02,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846532203] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:06:02,777 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:06:02,777 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:06:02,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769254156] [2024-10-31 22:06:02,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:06:02,778 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:06:02,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:02,779 INFO L85 PathProgramCache]: Analyzing trace with hash 953065888, now seen corresponding path program 1 times [2024-10-31 22:06:02,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:02,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819059055] [2024-10-31 22:06:02,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:02,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:02,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:06:02,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:06:02,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:06:02,842 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [819059055] [2024-10-31 22:06:02,842 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [819059055] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:06:02,842 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:06:02,842 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:06:02,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040946042] [2024-10-31 22:06:02,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:06:02,843 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:06:02,843 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:06:02,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:06:02,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:06:02,844 INFO L87 Difference]: Start difference. First operand 21646 states and 30463 transitions. cyclomatic complexity: 8833 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:06:03,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:06:03,040 INFO L93 Difference]: Finished difference Result 28041 states and 39369 transitions. [2024-10-31 22:06:03,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28041 states and 39369 transitions. [2024-10-31 22:06:03,379 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27760 [2024-10-31 22:06:03,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28041 states to 28041 states and 39369 transitions. [2024-10-31 22:06:03,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28041 [2024-10-31 22:06:03,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28041 [2024-10-31 22:06:03,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28041 states and 39369 transitions. [2024-10-31 22:06:03,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:06:03,485 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28041 states and 39369 transitions. [2024-10-31 22:06:03,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28041 states and 39369 transitions. [2024-10-31 22:06:03,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28041 to 19206. [2024-10-31 22:06:03,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.4069040924711027) internal successors, (27021), 19205 states have internal predecessors, (27021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:06:03,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27021 transitions. [2024-10-31 22:06:03,736 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27021 transitions. [2024-10-31 22:06:03,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:06:03,737 INFO L425 stractBuchiCegarLoop]: Abstraction has 19206 states and 27021 transitions. [2024-10-31 22:06:03,737 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-31 22:06:03,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27021 transitions. [2024-10-31 22:06:03,797 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-10-31 22:06:03,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:06:03,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:06:03,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:03,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:03,801 INFO L745 eck$LassoCheckResult]: Stem: 561126#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 561127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 561723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 561724#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 561801#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 561270#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 561271#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 561401#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 561402#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 561172#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 560962#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 560963#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 561131#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 561132#L781 assume !(0 == ~M_E~0); 561639#L781-2 assume !(0 == ~T1_E~0); 561814#L786-1 assume !(0 == ~T2_E~0); 560923#L791-1 assume !(0 == ~T3_E~0); 560924#L796-1 assume !(0 == ~T4_E~0); 561476#L801-1 assume !(0 == ~T5_E~0); 561477#L806-1 assume !(0 == ~T6_E~0); 561508#L811-1 assume !(0 == ~T7_E~0); 561137#L816-1 assume !(0 == ~E_M~0); 561138#L821-1 assume !(0 == ~E_1~0); 560954#L826-1 assume !(0 == ~E_2~0); 560955#L831-1 assume !(0 == ~E_3~0); 561265#L836-1 assume !(0 == ~E_4~0); 561266#L841-1 assume !(0 == ~E_5~0); 561089#L846-1 assume !(0 == ~E_6~0); 561090#L851-1 assume !(0 == ~E_7~0); 561112#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 561113#L388 assume !(1 == ~m_pc~0); 561106#L388-2 is_master_triggered_~__retres1~0#1 := 0; 561107#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 561613#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 560968#L967 assume !(0 != activate_threads_~tmp~1#1); 560969#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 560900#L407 assume !(1 == ~t1_pc~0); 560901#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 560904#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 560905#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 560940#L975 assume !(0 != activate_threads_~tmp___0~0#1); 561720#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 561227#L426 assume !(1 == ~t2_pc~0); 561228#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 561744#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 561248#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 561249#L983 assume !(0 != activate_threads_~tmp___1~0#1); 561791#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 561313#L445 assume !(1 == ~t3_pc~0); 561314#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 561647#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 560898#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 560899#L991 assume !(0 != activate_threads_~tmp___2~0#1); 561571#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 561536#L464 assume !(1 == ~t4_pc~0); 561116#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 560988#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 560989#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 561000#L999 assume !(0 != activate_threads_~tmp___3~0#1); 561292#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 561293#L483 assume !(1 == ~t5_pc~0); 561533#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 561700#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 561665#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 561666#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 561210#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 561211#L502 assume !(1 == ~t6_pc~0); 561067#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 561027#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 561028#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 561235#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 561440#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 561676#L521 assume !(1 == ~t7_pc~0); 561717#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 561749#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 561821#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 561710#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 561682#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 561603#L869 assume !(1 == ~M_E~0); 561286#L869-2 assume !(1 == ~T1_E~0); 561287#L874-1 assume !(1 == ~T2_E~0); 561760#L879-1 assume !(1 == ~T3_E~0); 561364#L884-1 assume !(1 == ~T4_E~0); 560886#L889-1 assume !(1 == ~T5_E~0); 560887#L894-1 assume !(1 == ~T6_E~0); 561145#L899-1 assume !(1 == ~T7_E~0); 561558#L904-1 assume !(1 == ~E_M~0); 561310#L909-1 assume !(1 == ~E_1~0); 561311#L914-1 assume !(1 == ~E_2~0); 561494#L919-1 assume !(1 == ~E_3~0); 561226#L924-1 assume !(1 == ~E_4~0); 561060#L929-1 assume !(1 == ~E_5~0); 561061#L934-1 assume !(1 == ~E_6~0); 561288#L939-1 assume !(1 == ~E_7~0); 561289#L944-1 assume { :end_inline_reset_delta_events } true; 561675#L1190-2 [2024-10-31 22:06:03,802 INFO L747 eck$LassoCheckResult]: Loop: 561675#L1190-2 assume !false; 570970#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 570968#L756-1 assume !false; 570967#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 570403#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 567747#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 567744#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 567741#L653 assume !(0 != eval_~tmp~0#1); 567739#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 567737#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 567735#L781-3 assume !(0 == ~M_E~0); 567733#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 567730#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 567728#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 567726#L796-3 assume !(0 == ~T4_E~0); 567724#L801-3 assume !(0 == ~T5_E~0); 567722#L806-3 assume !(0 == ~T6_E~0); 567719#L811-3 assume !(0 == ~T7_E~0); 567717#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 567715#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 567713#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 567711#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 567709#L836-3 assume !(0 == ~E_4~0); 567707#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 567704#L846-3 assume !(0 == ~E_6~0); 567702#L851-3 assume !(0 == ~E_7~0); 567700#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567698#L388-27 assume !(1 == ~m_pc~0); 567695#L388-29 is_master_triggered_~__retres1~0#1 := 0; 567693#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567691#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 567689#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 567687#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567685#L407-27 assume !(1 == ~t1_pc~0); 567683#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 567681#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567678#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567676#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 567674#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567673#L426-27 assume !(1 == ~t2_pc~0); 567672#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 567670#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567668#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 567667#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 567666#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567662#L445-27 assume !(1 == ~t3_pc~0); 567660#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 567658#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567656#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 567077#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 567068#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567066#L464-27 assume !(1 == ~t4_pc~0); 567063#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 567060#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567058#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 567056#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 567054#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567052#L483-27 assume !(1 == ~t5_pc~0); 567050#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 567048#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567046#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 567044#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 567042#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 567040#L502-27 assume !(1 == ~t6_pc~0); 567038#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 567036#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 567034#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 567032#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 567030#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 567028#L521-27 assume !(1 == ~t7_pc~0); 567024#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 567022#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 567020#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 567018#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 567014#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567012#L869-3 assume !(1 == ~M_E~0); 564151#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 567009#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 567007#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 567005#L884-3 assume !(1 == ~T4_E~0); 567003#L889-3 assume !(1 == ~T5_E~0); 567001#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 566999#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 566997#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 566995#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 566993#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 566772#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 566757#L924-3 assume !(1 == ~E_4~0); 566750#L929-3 assume !(1 == ~E_5~0); 566742#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 566678#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 566674#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 566661#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 566652#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 566647#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 564254#L1209 assume !(0 == start_simulation_~tmp~3#1); 564255#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 571196#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 571190#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 571188#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 571186#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 571183#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 571181#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 571177#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 561675#L1190-2 [2024-10-31 22:06:03,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:03,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2024-10-31 22:06:03,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:03,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210378727] [2024-10-31 22:06:03,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:03,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:03,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:06:03,818 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:06:03,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:06:03,863 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:06:03,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:03,865 INFO L85 PathProgramCache]: Analyzing trace with hash -40946012, now seen corresponding path program 1 times [2024-10-31 22:06:03,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:03,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205944408] [2024-10-31 22:06:03,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:03,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:03,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:06:03,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:06:03,913 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:06:03,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205944408] [2024-10-31 22:06:03,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205944408] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:06:03,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:06:03,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:06:03,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648957890] [2024-10-31 22:06:03,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:06:03,914 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:06:03,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:06:03,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:06:03,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:06:03,915 INFO L87 Difference]: Start difference. First operand 19206 states and 27021 transitions. cyclomatic complexity: 7831 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:06:04,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:06:04,100 INFO L93 Difference]: Finished difference Result 28778 states and 40307 transitions. [2024-10-31 22:06:04,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28778 states and 40307 transitions. [2024-10-31 22:06:04,232 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28452 [2024-10-31 22:06:04,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28778 states to 28778 states and 40307 transitions. [2024-10-31 22:06:04,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28778 [2024-10-31 22:06:04,337 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28778 [2024-10-31 22:06:04,337 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28778 states and 40307 transitions. [2024-10-31 22:06:04,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:06:04,357 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28778 states and 40307 transitions. [2024-10-31 22:06:04,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28778 states and 40307 transitions. [2024-10-31 22:06:04,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28778 to 28762. [2024-10-31 22:06:04,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28762 states, 28762 states have (on average 1.400841387942424) internal successors, (40291), 28761 states have internal predecessors, (40291), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:06:05,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28762 states to 28762 states and 40291 transitions. [2024-10-31 22:06:05,016 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28762 states and 40291 transitions. [2024-10-31 22:06:05,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:06:05,017 INFO L425 stractBuchiCegarLoop]: Abstraction has 28762 states and 40291 transitions. [2024-10-31 22:06:05,017 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-31 22:06:05,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28762 states and 40291 transitions. [2024-10-31 22:06:05,099 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28436 [2024-10-31 22:06:05,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:06:05,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:06:05,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:05,102 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:06:05,102 INFO L745 eck$LassoCheckResult]: Stem: 609120#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 609121#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 609744#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 609745#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 609836#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 609266#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 609267#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 609398#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 609399#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 609166#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 608953#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 608954#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 609127#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 609128#L781 assume !(0 == ~M_E~0); 609646#L781-2 assume !(0 == ~T1_E~0); 609847#L786-1 assume !(0 == ~T2_E~0); 608916#L791-1 assume !(0 == ~T3_E~0); 608917#L796-1 assume !(0 == ~T4_E~0); 609476#L801-1 assume !(0 == ~T5_E~0); 609477#L806-1 assume !(0 == ~T6_E~0); 609510#L811-1 assume !(0 == ~T7_E~0); 609131#L816-1 assume !(0 == ~E_M~0); 609132#L821-1 assume !(0 == ~E_1~0); 608944#L826-1 assume !(0 == ~E_2~0); 608945#L831-1 assume !(0 == ~E_3~0); 609261#L836-1 assume !(0 == ~E_4~0); 609262#L841-1 assume 0 == ~E_5~0;~E_5~0 := 1; 609084#L846-1 assume !(0 == ~E_6~0); 609085#L851-1 assume !(0 == ~E_7~0); 609886#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 609767#L388 assume !(1 == ~m_pc~0); 609768#L388-2 is_master_triggered_~__retres1~0#1 := 0; 609885#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 609676#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 609677#L967 assume !(0 != activate_threads_~tmp~1#1); 609830#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 609831#L407 assume !(1 == ~t1_pc~0); 609835#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 608897#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 608898#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 608932#L975 assume !(0 != activate_threads_~tmp___0~0#1); 609760#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 609761#L426 assume !(1 == ~t2_pc~0); 609775#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 609776#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 609882#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 609823#L983 assume !(0 != activate_threads_~tmp___1~0#1); 609824#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 609310#L445 assume !(1 == ~t3_pc~0); 609311#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 609879#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 608888#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 608889#L991 assume !(0 != activate_threads_~tmp___2~0#1); 609578#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 609540#L464 assume !(1 == ~t4_pc~0); 609113#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 609114#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 609873#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 609872#L999 assume !(0 != activate_threads_~tmp___3~0#1); 609871#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 609536#L483 assume !(1 == ~t5_pc~0); 609537#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 609715#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 609716#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 609797#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 609798#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 609870#L502 assume !(1 == ~t6_pc~0); 609060#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 609061#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 609231#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 609232#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 609694#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 609695#L521 assume !(1 == ~t7_pc~0); 609737#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 608955#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 608956#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 609729#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 609730#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 609868#L869 assume !(1 == ~M_E~0); 609867#L869-2 assume !(1 == ~T1_E~0); 609818#L874-1 assume !(1 == ~T2_E~0); 609819#L879-1 assume !(1 == ~T3_E~0); 609361#L884-1 assume !(1 == ~T4_E~0); 609362#L889-1 assume !(1 == ~T5_E~0); 609141#L894-1 assume !(1 == ~T6_E~0); 609142#L899-1 assume !(1 == ~T7_E~0); 609568#L904-1 assume !(1 == ~E_M~0); 609307#L909-1 assume !(1 == ~E_1~0); 609308#L914-1 assume !(1 == ~E_2~0); 609520#L919-1 assume !(1 == ~E_3~0); 609217#L924-1 assume !(1 == ~E_4~0); 609053#L929-1 assume 1 == ~E_5~0;~E_5~0 := 2; 609054#L934-1 assume !(1 == ~E_6~0); 609288#L939-1 assume !(1 == ~E_7~0); 609289#L944-1 assume { :end_inline_reset_delta_events } true; 609693#L1190-2 [2024-10-31 22:06:05,102 INFO L747 eck$LassoCheckResult]: Loop: 609693#L1190-2 assume !false; 614758#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 614755#L756-1 assume !false; 614753#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 614751#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 614743#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 614740#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 614738#L653 assume !(0 != eval_~tmp~0#1); 614739#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 615092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 615090#L781-3 assume !(0 == ~M_E~0); 615088#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 615086#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 615084#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 615082#L796-3 assume !(0 == ~T4_E~0); 615080#L801-3 assume !(0 == ~T5_E~0); 615078#L806-3 assume !(0 == ~T6_E~0); 615076#L811-3 assume !(0 == ~T7_E~0); 615072#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 615070#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 615068#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 615066#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 615063#L836-3 assume !(0 == ~E_4~0); 615060#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 615059#L846-3 assume !(0 == ~E_6~0); 615058#L851-3 assume !(0 == ~E_7~0); 615056#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 615055#L388-27 assume !(1 == ~m_pc~0); 615053#L388-29 is_master_triggered_~__retres1~0#1 := 0; 615052#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 615051#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 615050#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 615049#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 615048#L407-27 assume !(1 == ~t1_pc~0); 615047#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 615046#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 615044#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 615041#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 615039#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 615037#L426-27 assume !(1 == ~t2_pc~0); 615035#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 615032#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 615030#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 615028#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 615026#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 615024#L445-27 assume !(1 == ~t3_pc~0); 615022#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 615020#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 615018#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 615015#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 615013#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 615011#L464-27 assume !(1 == ~t4_pc~0); 615008#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 615006#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 615004#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 615002#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 615000#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 614998#L483-27 assume !(1 == ~t5_pc~0); 614996#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 614994#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 614991#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 614989#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 614987#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 614985#L502-27 assume !(1 == ~t6_pc~0); 614983#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 614981#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 614979#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 614977#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 614975#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 614973#L521-27 assume !(1 == ~t7_pc~0); 614969#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 614967#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 614965#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 614963#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 614960#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 614958#L869-3 assume !(1 == ~M_E~0); 614954#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 614952#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 614948#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 614946#L884-3 assume !(1 == ~T4_E~0); 614944#L889-3 assume !(1 == ~T5_E~0); 614942#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 614939#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 614937#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 614934#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 614932#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 614930#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 614928#L924-3 assume !(1 == ~E_4~0); 614926#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 614923#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 614921#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 614919#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 614909#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 614903#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 614901#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 614900#L1209 assume !(0 == start_simulation_~tmp~3#1); 614898#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 614894#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 614889#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 614888#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 614887#L1164 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 614886#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 614885#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 614884#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 609693#L1190-2 [2024-10-31 22:06:05,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:05,103 INFO L85 PathProgramCache]: Analyzing trace with hash 2121315589, now seen corresponding path program 1 times [2024-10-31 22:06:05,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:05,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039139275] [2024-10-31 22:06:05,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:05,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:05,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:06:05,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:06:05,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:06:05,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039139275] [2024-10-31 22:06:05,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039139275] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:06:05,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:06:05,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:06:05,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948411887] [2024-10-31 22:06:05,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:06:05,163 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:06:05,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:06:05,163 INFO L85 PathProgramCache]: Analyzing trace with hash 980122342, now seen corresponding path program 1 times [2024-10-31 22:06:05,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:06:05,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175259354] [2024-10-31 22:06:05,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:06:05,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:06:05,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:06:05,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:06:05,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:06:05,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175259354] [2024-10-31 22:06:05,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175259354] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:06:05,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:06:05,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:06:05,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1978338751] [2024-10-31 22:06:05,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:06:05,249 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:06:05,249 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:06:05,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:06:05,250 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:06:05,250 INFO L87 Difference]: Start difference. First operand 28762 states and 40291 transitions. cyclomatic complexity: 11545 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)