./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:04:24,358 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:04:24,453 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:04:24,460 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:04:24,461 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:04:24,502 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:04:24,503 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:04:24,504 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:04:24,505 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:04:24,506 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:04:24,507 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:04:24,508 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:04:24,508 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:04:24,510 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:04:24,511 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:04:24,511 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:04:24,512 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:04:24,512 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:04:24,512 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:04:24,513 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:04:24,517 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:04:24,518 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:04:24,518 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:04:24,519 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:04:24,519 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:04:24,519 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:04:24,520 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:04:24,520 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:04:24,521 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:04:24,522 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:04:24,522 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:04:24,523 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:04:24,523 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:04:24,524 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:04:24,525 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:04:24,525 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:04:24,525 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:04:24,526 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:04:24,526 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:04:24,527 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 [2024-10-31 22:04:24,829 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:04:24,891 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:04:24,896 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:04:24,898 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:04:24,898 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:04:24,900 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c Unable to find full path for "g++" [2024-10-31 22:04:26,904 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:04:27,144 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:04:27,145 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2024-10-31 22:04:27,159 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/data/82e910322/780ebc458a0f464287e4025a64a8414f/FLAGe3e80a319 [2024-10-31 22:04:27,179 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/data/82e910322/780ebc458a0f464287e4025a64a8414f [2024-10-31 22:04:27,182 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:04:27,184 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:04:27,185 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:04:27,186 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:04:27,192 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:04:27,193 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,197 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@39771c0c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27, skipping insertion in model container [2024-10-31 22:04:27,197 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,251 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:04:27,579 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:04:27,596 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:04:27,689 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:04:27,715 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:04:27,715 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27 WrapperNode [2024-10-31 22:04:27,716 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:04:27,717 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:04:27,717 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:04:27,717 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:04:27,726 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,738 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,822 INFO L138 Inliner]: procedures = 44, calls = 56, calls flagged for inlining = 51, calls inlined = 158, statements flattened = 2377 [2024-10-31 22:04:27,822 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:04:27,823 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:04:27,823 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:04:27,824 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:04:27,837 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,837 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,847 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,892 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:04:27,896 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,897 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,954 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:27,996 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:28,003 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:28,013 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:28,028 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:04:28,029 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:04:28,030 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:04:28,030 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:04:28,031 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (1/1) ... [2024-10-31 22:04:28,037 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:04:28,048 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:04:28,063 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:04:28,067 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cdc3d504-d6df-432c-9fcb-34039eccd8bf/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:04:28,102 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:04:28,103 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:04:28,103 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:04:28,103 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:04:28,250 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:04:28,253 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:04:30,406 INFO L? ?]: Removed 474 outVars from TransFormulas that were not future-live. [2024-10-31 22:04:30,406 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:04:30,454 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:04:30,455 INFO L316 CfgBuilder]: Removed 11 assume(true) statements. [2024-10-31 22:04:30,455 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:04:30 BoogieIcfgContainer [2024-10-31 22:04:30,458 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:04:30,459 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:04:30,459 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:04:30,464 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:04:30,465 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:04:30,466 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:04:27" (1/3) ... [2024-10-31 22:04:30,468 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6ec93e13 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:04:30, skipping insertion in model container [2024-10-31 22:04:30,468 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:04:30,468 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:04:27" (2/3) ... [2024-10-31 22:04:30,468 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6ec93e13 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:04:30, skipping insertion in model container [2024-10-31 22:04:30,468 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:04:30,469 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:04:30" (3/3) ... [2024-10-31 22:04:30,470 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-1.c [2024-10-31 22:04:30,578 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:04:30,578 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:04:30,578 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:04:30,579 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:04:30,579 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:04:30,579 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:04:30,579 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:04:30,579 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:04:30,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:30,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2024-10-31 22:04:30,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:30,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:30,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,711 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:04:30,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:30,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2024-10-31 22:04:30,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:30,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:30,744 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,744 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:30,758 INFO L745 eck$LassoCheckResult]: Stem: 155#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 920#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 743#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 916#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 867#L597true assume !(1 == ~m_i~0);~m_st~0 := 2; 447#L597-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 987#L602-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 163#L607-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 494#L612-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 129#L617-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 284#L622-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 970#L627-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 265#L632-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 567#L637-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 504#L854true assume !(0 == ~M_E~0); 332#L854-2true assume !(0 == ~T1_E~0); 639#L859-1true assume !(0 == ~T2_E~0); 68#L864-1true assume !(0 == ~T3_E~0); 123#L869-1true assume !(0 == ~T4_E~0); 877#L874-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 815#L879-1true assume !(0 == ~T6_E~0); 325#L884-1true assume !(0 == ~T7_E~0); 8#L889-1true assume !(0 == ~T8_E~0); 171#L894-1true assume !(0 == ~E_M~0); 981#L899-1true assume !(0 == ~E_1~0); 509#L904-1true assume !(0 == ~E_2~0); 277#L909-1true assume !(0 == ~E_3~0); 438#L914-1true assume 0 == ~E_4~0;~E_4~0 := 1; 463#L919-1true assume !(0 == ~E_5~0); 218#L924-1true assume !(0 == ~E_6~0); 115#L929-1true assume !(0 == ~E_7~0); 834#L934-1true assume !(0 == ~E_8~0); 263#L939-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16#L418true assume !(1 == ~m_pc~0); 903#L418-2true is_master_triggered_~__retres1~0#1 := 0; 717#L429true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 642#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 626#L1061true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 532#L1061-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 890#L437true assume 1 == ~t1_pc~0; 974#L438true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 632#L448true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 188#L1069true assume !(0 != activate_threads_~tmp___0~0#1); 826#L1069-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 617#L456true assume !(1 == ~t2_pc~0); 436#L456-2true is_transmit2_triggered_~__retres1~2#1 := 0; 882#L467true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 240#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 661#L1077true assume !(0 != activate_threads_~tmp___1~0#1); 358#L1077-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66#L475true assume 1 == ~t3_pc~0; 298#L476true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 97#L486true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 797#L1085true assume !(0 != activate_threads_~tmp___2~0#1); 190#L1085-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 713#L494true assume !(1 == ~t4_pc~0); 214#L494-2true is_transmit4_triggered_~__retres1~4#1 := 0; 417#L505true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 953#L1093true assume !(0 != activate_threads_~tmp___3~0#1); 460#L1093-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95#L513true assume 1 == ~t5_pc~0; 584#L514true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 911#L524true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 645#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71#L1101true assume !(0 != activate_threads_~tmp___4~0#1); 895#L1101-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51#L532true assume !(1 == ~t6_pc~0); 407#L532-2true is_transmit6_triggered_~__retres1~6#1 := 0; 303#L543true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 227#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 849#L1109true assume !(0 != activate_threads_~tmp___5~0#1); 175#L1109-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 665#L551true assume 1 == ~t7_pc~0; 675#L552true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 465#L562true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 934#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1007#L1117true assume !(0 != activate_threads_~tmp___6~0#1); 945#L1117-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 292#L570true assume 1 == ~t8_pc~0; 379#L571true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 749#L581true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 585#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 376#L1125true assume !(0 != activate_threads_~tmp___7~0#1); 63#L1125-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 636#L952true assume 1 == ~M_E~0;~M_E~0 := 2; 38#L952-2true assume !(1 == ~T1_E~0); 597#L957-1true assume !(1 == ~T2_E~0); 899#L962-1true assume !(1 == ~T3_E~0); 391#L967-1true assume !(1 == ~T4_E~0); 869#L972-1true assume !(1 == ~T5_E~0); 668#L977-1true assume !(1 == ~T6_E~0); 950#L982-1true assume !(1 == ~T7_E~0); 126#L987-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 130#L992-1true assume !(1 == ~E_M~0); 356#L997-1true assume !(1 == ~E_1~0); 821#L1002-1true assume !(1 == ~E_2~0); 346#L1007-1true assume !(1 == ~E_3~0); 9#L1012-1true assume !(1 == ~E_4~0); 564#L1017-1true assume !(1 == ~E_5~0); 349#L1022-1true assume !(1 == ~E_6~0); 370#L1027-1true assume 1 == ~E_7~0;~E_7~0 := 2; 823#L1032-1true assume !(1 == ~E_8~0); 487#L1037-1true assume { :end_inline_reset_delta_events } true; 588#L1303-2true [2024-10-31 22:04:30,760 INFO L747 eck$LassoCheckResult]: Loop: 588#L1303-2true assume !false; 627#L1304true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 982#L829-1true assume !true; 589#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 375#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 475#L854-3true assume !(0 == ~M_E~0); 453#L854-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 965#L859-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 926#L864-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 809#L869-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 304#L874-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 357#L879-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 390#L884-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 342#L889-3true assume !(0 == ~T8_E~0); 110#L894-3true assume 0 == ~E_M~0;~E_M~0 := 1; 499#L899-3true assume 0 == ~E_1~0;~E_1~0 := 1; 128#L904-3true assume 0 == ~E_2~0;~E_2~0 := 1; 323#L909-3true assume 0 == ~E_3~0;~E_3~0 := 1; 100#L914-3true assume 0 == ~E_4~0;~E_4~0 := 1; 121#L919-3true assume 0 == ~E_5~0;~E_5~0 := 1; 730#L924-3true assume 0 == ~E_6~0;~E_6~0 := 1; 537#L929-3true assume !(0 == ~E_7~0); 440#L934-3true assume 0 == ~E_8~0;~E_8~0 := 1; 670#L939-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 569#L418-30true assume !(1 == ~m_pc~0); 384#L418-32true is_master_triggered_~__retres1~0#1 := 0; 581#L429-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 249#is_master_triggered_returnLabel#11true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 839#L1061-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146#L1061-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216#L437-30true assume !(1 == ~t1_pc~0); 679#L437-32true is_transmit1_triggered_~__retres1~1#1 := 0; 374#L448-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 402#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 909#L1069-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 883#L1069-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193#L456-30true assume 1 == ~t2_pc~0; 719#L457-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 527#L467-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89#L1077-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 285#L1077-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 766#L475-30true assume !(1 == ~t3_pc~0); 30#L475-32true is_transmit3_triggered_~__retres1~3#1 := 0; 452#L486-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 389#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 901#L1085-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 206#L1085-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 999#L494-30true assume 1 == ~t4_pc~0; 200#L495-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3#L505-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 833#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 919#L1093-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 698#L1093-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 956#L513-30true assume 1 == ~t5_pc~0; 988#L514-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 340#L524-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 474#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552#L1101-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 796#L1101-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295#L532-30true assume 1 == ~t6_pc~0; 957#L533-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65#L543-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 629#L1109-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 105#L1109-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133#L551-30true assume 1 == ~t7_pc~0; 165#L552-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 643#L562-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 540#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10#L1117-30true assume !(0 != activate_threads_~tmp___6~0#1); 191#L1117-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 758#L570-30true assume 1 == ~t8_pc~0; 634#L571-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 131#L581-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 973#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36#L1125-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 236#L1125-32true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261#L952-3true assume 1 == ~M_E~0;~M_E~0 := 2; 958#L952-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 752#L957-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 769#L962-3true assume !(1 == ~T3_E~0); 615#L967-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 800#L972-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 508#L977-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 996#L982-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 977#L987-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 226#L992-3true assume 1 == ~E_M~0;~E_M~0 := 2; 365#L997-3true assume 1 == ~E_1~0;~E_1~0 := 2; 224#L1002-3true assume !(1 == ~E_2~0); 464#L1007-3true assume 1 == ~E_3~0;~E_3~0 := 2; 117#L1012-3true assume 1 == ~E_4~0;~E_4~0 := 2; 170#L1017-3true assume 1 == ~E_5~0;~E_5~0 := 2; 324#L1022-3true assume 1 == ~E_6~0;~E_6~0 := 2; 347#L1027-3true assume 1 == ~E_7~0;~E_7~0 := 2; 23#L1032-3true assume 1 == ~E_8~0;~E_8~0 := 2; 434#L1037-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 141#L650-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 768#L697-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 205#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 830#L1322true assume !(0 == start_simulation_~tmp~3#1); 246#L1322-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 61#L650-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 753#L697-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 17#L1277true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 510#L1284true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 388#stop_simulation_returnLabel#1true start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 673#L1335true assume !(0 != start_simulation_~tmp___0~1#1); 588#L1303-2true [2024-10-31 22:04:30,774 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:30,774 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2024-10-31 22:04:30,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:30,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851561190] [2024-10-31 22:04:30,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:30,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:30,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:31,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:31,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:31,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851561190] [2024-10-31 22:04:31,179 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1851561190] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:31,179 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:31,179 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:31,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367110829] [2024-10-31 22:04:31,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:31,189 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:31,189 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:31,190 INFO L85 PathProgramCache]: Analyzing trace with hash -118307812, now seen corresponding path program 1 times [2024-10-31 22:04:31,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:31,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754648752] [2024-10-31 22:04:31,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:31,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:31,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:31,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:31,287 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:31,288 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754648752] [2024-10-31 22:04:31,288 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754648752] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:31,288 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:31,288 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:31,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677333627] [2024-10-31 22:04:31,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:31,290 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:31,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:31,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:31,328 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:31,333 INFO L87 Difference]: Start difference. First operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:31,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:31,490 INFO L93 Difference]: Finished difference Result 1007 states and 1495 transitions. [2024-10-31 22:04:31,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1495 transitions. [2024-10-31 22:04:31,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:31,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1002 states and 1490 transitions. [2024-10-31 22:04:31,525 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-10-31 22:04:31,527 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-10-31 22:04:31,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1490 transitions. [2024-10-31 22:04:31,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:31,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2024-10-31 22:04:31,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1490 transitions. [2024-10-31 22:04:31,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-10-31 22:04:31,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4870259481037924) internal successors, (1490), 1001 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:31,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1490 transitions. [2024-10-31 22:04:31,616 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2024-10-31 22:04:31,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:31,625 INFO L425 stractBuchiCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2024-10-31 22:04:31,625 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:04:31,626 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1490 transitions. [2024-10-31 22:04:31,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:31,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:31,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:31,638 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:31,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:31,639 INFO L745 eck$LassoCheckResult]: Stem: 2347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3011#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2766#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2767#L602-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2364#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2365#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2297#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2298#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2560#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2532#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2533#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2816#L854 assume !(0 == ~M_E~0); 2623#L854-2 assume !(0 == ~T1_E~0); 2624#L859-1 assume !(0 == ~T2_E~0); 2177#L864-1 assume !(0 == ~T3_E~0); 2178#L869-1 assume !(0 == ~T4_E~0); 2288#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2997#L879-1 assume !(0 == ~T6_E~0); 2613#L884-1 assume !(0 == ~T7_E~0); 2040#L889-1 assume !(0 == ~T8_E~0); 2041#L894-1 assume !(0 == ~E_M~0); 2377#L899-1 assume !(0 == ~E_1~0); 2822#L904-1 assume !(0 == ~E_2~0); 2550#L909-1 assume !(0 == ~E_3~0); 2551#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2757#L919-1 assume !(0 == ~E_5~0); 2456#L924-1 assume !(0 == ~E_6~0); 2270#L929-1 assume !(0 == ~E_7~0); 2271#L934-1 assume !(0 == ~E_8~0); 2529#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2057#L418 assume !(1 == ~m_pc~0); 2032#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2031#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2926#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2912#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2845#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2846#L437 assume 1 == ~t1_pc~0; 3014#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2919#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2080#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2081#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2406#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2902#L456 assume !(1 == ~t2_pc~0); 2328#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2327#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2488#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2489#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2661#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2171#L475 assume 1 == ~t3_pc~0; 2172#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2235#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2049#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2409#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2410#L494 assume !(1 == ~t4_pc~0); 2450#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2451#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2188#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2781#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2230#L513 assume 1 == ~t5_pc~0; 2231#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2452#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2184#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2185#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2137#L532 assume !(1 == ~t6_pc~0); 2138#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2289#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2470#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2471#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2381#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2382#L551 assume 1 == ~t7_pc~0; 2939#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2783#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2784#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3023#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 3024#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2571#L570 assume 1 == ~t8_pc~0; 2572#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2687#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2877#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2683#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2165#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2166#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 2106#L952-2 assume !(1 == ~T1_E~0); 2107#L957-1 assume !(1 == ~T2_E~0); 2883#L962-1 assume !(1 == ~T3_E~0); 2699#L967-1 assume !(1 == ~T4_E~0); 2700#L972-1 assume !(1 == ~T5_E~0); 2942#L977-1 assume !(1 == ~T6_E~0); 2943#L982-1 assume !(1 == ~T7_E~0); 2291#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2292#L992-1 assume !(1 == ~E_M~0); 2299#L997-1 assume !(1 == ~E_1~0); 2659#L1002-1 assume !(1 == ~E_2~0); 2644#L1007-1 assume !(1 == ~E_3~0); 2042#L1012-1 assume !(1 == ~E_4~0); 2043#L1017-1 assume !(1 == ~E_5~0); 2647#L1022-1 assume !(1 == ~E_6~0); 2648#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2673#L1032-1 assume !(1 == ~E_8~0); 2804#L1037-1 assume { :end_inline_reset_delta_events } true; 2805#L1303-2 [2024-10-31 22:04:31,640 INFO L747 eck$LassoCheckResult]: Loop: 2805#L1303-2 assume !false; 2879#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2546#L829-1 assume !false; 2842#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2432#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2367#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2510#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2511#L712 assume !(0 != eval_~tmp~0#1); 2772#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2682#L854-3 assume !(0 == ~M_E~0); 2773#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2774#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3022#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2996#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2589#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2590#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2660#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2638#L889-3 assume !(0 == ~T8_E~0); 2261#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2262#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2295#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2296#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2240#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2241#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2284#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2848#L929-3 assume !(0 == ~E_7~0); 2759#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2760#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2867#L418-30 assume 1 == ~m_pc~0; 2124#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2125#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2501#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2502#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2329#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2330#L437-30 assume 1 == ~t1_pc~0; 2453#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2679#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2680#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2717#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3013#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2413#L456-30 assume !(1 == ~t2_pc~0); 2414#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2840#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2412#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2218#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2219#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2561#L475-30 assume 1 == ~t3_pc~0; 2935#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2089#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2697#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2698#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2436#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2437#L494-30 assume !(1 == ~t4_pc~0); 2245#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2028#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2029#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3001#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2951#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2952#L513-30 assume 1 == ~t5_pc~0; 3025#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2567#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2636#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2793#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2859#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2579#L532-30 assume 1 == ~t6_pc~0; 2580#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2169#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2170#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2194#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2250#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2251#L551-30 assume 1 == ~t7_pc~0; 2304#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2369#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2849#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2044#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 2045#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2411#L570-30 assume 1 == ~t8_pc~0; 2920#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2300#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2301#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2102#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2103#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2482#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2526#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2977#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2978#L962-3 assume !(1 == ~T3_E~0); 2900#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2901#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2820#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2821#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3026#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2468#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2469#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2464#L1002-3 assume !(1 == ~E_2~0); 2465#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2274#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2275#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2376#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2612#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2072#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2073#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2318#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2319#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2434#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2435#L1322 assume !(0 == start_simulation_~tmp~3#1); 2496#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2159#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2160#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2076#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2058#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2059#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2695#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2696#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2805#L1303-2 [2024-10-31 22:04:31,641 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:31,642 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2024-10-31 22:04:31,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:31,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580845290] [2024-10-31 22:04:31,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:31,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:31,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:31,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:31,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:31,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580845290] [2024-10-31 22:04:31,812 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [580845290] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:31,812 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:31,812 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:31,812 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894954291] [2024-10-31 22:04:31,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:31,814 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:31,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:31,816 INFO L85 PathProgramCache]: Analyzing trace with hash -221898915, now seen corresponding path program 1 times [2024-10-31 22:04:31,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:31,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540243667] [2024-10-31 22:04:31,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:31,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:31,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:31,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:31,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:31,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540243667] [2024-10-31 22:04:31,990 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540243667] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:31,990 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:31,991 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:31,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [11562914] [2024-10-31 22:04:31,991 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:31,993 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:31,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:31,994 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:31,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:31,994 INFO L87 Difference]: Start difference. First operand 1002 states and 1490 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:32,023 INFO L93 Difference]: Finished difference Result 1002 states and 1489 transitions. [2024-10-31 22:04:32,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1489 transitions. [2024-10-31 22:04:32,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:32,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1489 transitions. [2024-10-31 22:04:32,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-10-31 22:04:32,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-10-31 22:04:32,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1489 transitions. [2024-10-31 22:04:32,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:32,042 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2024-10-31 22:04:32,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1489 transitions. [2024-10-31 22:04:32,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-10-31 22:04:32,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4860279441117765) internal successors, (1489), 1001 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1489 transitions. [2024-10-31 22:04:32,076 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2024-10-31 22:04:32,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:32,079 INFO L425 stractBuchiCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2024-10-31 22:04:32,080 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:04:32,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1489 transitions. [2024-10-31 22:04:32,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:32,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:32,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:32,091 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,092 INFO L745 eck$LassoCheckResult]: Stem: 4358#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5022#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 4777#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4778#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4375#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4376#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4308#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4309#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4571#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4543#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4544#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4827#L854 assume !(0 == ~M_E~0); 4634#L854-2 assume !(0 == ~T1_E~0); 4635#L859-1 assume !(0 == ~T2_E~0); 4188#L864-1 assume !(0 == ~T3_E~0); 4189#L869-1 assume !(0 == ~T4_E~0); 4299#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5008#L879-1 assume !(0 == ~T6_E~0); 4624#L884-1 assume !(0 == ~T7_E~0); 4051#L889-1 assume !(0 == ~T8_E~0); 4052#L894-1 assume !(0 == ~E_M~0); 4388#L899-1 assume !(0 == ~E_1~0); 4833#L904-1 assume !(0 == ~E_2~0); 4561#L909-1 assume !(0 == ~E_3~0); 4562#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4768#L919-1 assume !(0 == ~E_5~0); 4467#L924-1 assume !(0 == ~E_6~0); 4281#L929-1 assume !(0 == ~E_7~0); 4282#L934-1 assume !(0 == ~E_8~0); 4540#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4068#L418 assume !(1 == ~m_pc~0); 4043#L418-2 is_master_triggered_~__retres1~0#1 := 0; 4042#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4937#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4923#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4856#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4857#L437 assume 1 == ~t1_pc~0; 5025#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4930#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4091#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4092#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 4417#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4913#L456 assume !(1 == ~t2_pc~0); 4339#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4338#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4500#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 4672#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4182#L475 assume 1 == ~t3_pc~0; 4183#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4246#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4059#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4060#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 4420#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4421#L494 assume !(1 == ~t4_pc~0); 4461#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4462#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4198#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4199#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 4792#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4241#L513 assume 1 == ~t5_pc~0; 4242#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4463#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4939#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4195#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 4196#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4148#L532 assume !(1 == ~t6_pc~0); 4149#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4300#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4481#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4482#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 4392#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4393#L551 assume 1 == ~t7_pc~0; 4950#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4794#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5034#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 5035#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4582#L570 assume 1 == ~t8_pc~0; 4583#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4698#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4888#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4694#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 4176#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4177#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 4117#L952-2 assume !(1 == ~T1_E~0); 4118#L957-1 assume !(1 == ~T2_E~0); 4894#L962-1 assume !(1 == ~T3_E~0); 4710#L967-1 assume !(1 == ~T4_E~0); 4711#L972-1 assume !(1 == ~T5_E~0); 4953#L977-1 assume !(1 == ~T6_E~0); 4954#L982-1 assume !(1 == ~T7_E~0); 4302#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4303#L992-1 assume !(1 == ~E_M~0); 4310#L997-1 assume !(1 == ~E_1~0); 4670#L1002-1 assume !(1 == ~E_2~0); 4655#L1007-1 assume !(1 == ~E_3~0); 4053#L1012-1 assume !(1 == ~E_4~0); 4054#L1017-1 assume !(1 == ~E_5~0); 4658#L1022-1 assume !(1 == ~E_6~0); 4659#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4684#L1032-1 assume !(1 == ~E_8~0); 4815#L1037-1 assume { :end_inline_reset_delta_events } true; 4816#L1303-2 [2024-10-31 22:04:32,095 INFO L747 eck$LassoCheckResult]: Loop: 4816#L1303-2 assume !false; 4890#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4557#L829-1 assume !false; 4853#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4443#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4378#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4521#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4522#L712 assume !(0 != eval_~tmp~0#1); 4783#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4693#L854-3 assume !(0 == ~M_E~0); 4784#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4785#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5033#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5007#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4600#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4601#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4671#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4649#L889-3 assume !(0 == ~T8_E~0); 4272#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4273#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4306#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4307#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4251#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4252#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4295#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4859#L929-3 assume !(0 == ~E_7~0); 4770#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4771#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4878#L418-30 assume 1 == ~m_pc~0; 4135#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4136#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4512#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4513#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4340#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4341#L437-30 assume 1 == ~t1_pc~0; 4464#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4690#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4691#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4728#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5024#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4424#L456-30 assume !(1 == ~t2_pc~0); 4425#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 4851#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4423#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4229#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4230#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4572#L475-30 assume 1 == ~t3_pc~0; 4946#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4100#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4708#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4709#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4447#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4448#L494-30 assume !(1 == ~t4_pc~0); 4256#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4039#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4040#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5012#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4962#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4963#L513-30 assume !(1 == ~t5_pc~0); 4577#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4578#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4647#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4804#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4870#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4590#L532-30 assume !(1 == ~t6_pc~0); 4592#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4180#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4181#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4205#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4261#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4262#L551-30 assume !(1 == ~t7_pc~0); 4314#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4380#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4860#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4055#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 4056#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4422#L570-30 assume 1 == ~t8_pc~0; 4931#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4311#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4312#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4113#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4114#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4493#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4537#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4988#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4989#L962-3 assume !(1 == ~T3_E~0); 4911#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4912#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4831#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4832#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5037#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4479#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4480#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4475#L1002-3 assume !(1 == ~E_2~0); 4476#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4285#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4286#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4387#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4623#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4083#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4084#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4329#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4330#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4445#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4446#L1322 assume !(0 == start_simulation_~tmp~3#1); 4507#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4170#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4171#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4087#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 4069#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4070#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4706#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4707#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 4816#L1303-2 [2024-10-31 22:04:32,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,096 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2024-10-31 22:04:32,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886720220] [2024-10-31 22:04:32,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,201 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,201 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886720220] [2024-10-31 22:04:32,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886720220] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,202 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:32,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670849941] [2024-10-31 22:04:32,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,203 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:32,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,203 INFO L85 PathProgramCache]: Analyzing trace with hash 2036706080, now seen corresponding path program 1 times [2024-10-31 22:04:32,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436964041] [2024-10-31 22:04:32,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,323 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [436964041] [2024-10-31 22:04:32,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [436964041] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,325 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,325 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:32,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752471210] [2024-10-31 22:04:32,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,326 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:32,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:32,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:32,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:32,327 INFO L87 Difference]: Start difference. First operand 1002 states and 1489 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:32,358 INFO L93 Difference]: Finished difference Result 1002 states and 1488 transitions. [2024-10-31 22:04:32,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1488 transitions. [2024-10-31 22:04:32,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:32,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1488 transitions. [2024-10-31 22:04:32,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-10-31 22:04:32,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-10-31 22:04:32,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1488 transitions. [2024-10-31 22:04:32,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:32,377 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2024-10-31 22:04:32,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1488 transitions. [2024-10-31 22:04:32,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-10-31 22:04:32,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4850299401197604) internal successors, (1488), 1001 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1488 transitions. [2024-10-31 22:04:32,400 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2024-10-31 22:04:32,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:32,403 INFO L425 stractBuchiCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2024-10-31 22:04:32,403 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:04:32,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1488 transitions. [2024-10-31 22:04:32,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:32,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:32,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:32,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,414 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,414 INFO L745 eck$LassoCheckResult]: Stem: 6369#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7033#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 6788#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6789#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6386#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6387#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6319#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6320#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6582#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6554#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6555#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6838#L854 assume !(0 == ~M_E~0); 6645#L854-2 assume !(0 == ~T1_E~0); 6646#L859-1 assume !(0 == ~T2_E~0); 6199#L864-1 assume !(0 == ~T3_E~0); 6200#L869-1 assume !(0 == ~T4_E~0); 6310#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7019#L879-1 assume !(0 == ~T6_E~0); 6635#L884-1 assume !(0 == ~T7_E~0); 6062#L889-1 assume !(0 == ~T8_E~0); 6063#L894-1 assume !(0 == ~E_M~0); 6399#L899-1 assume !(0 == ~E_1~0); 6844#L904-1 assume !(0 == ~E_2~0); 6572#L909-1 assume !(0 == ~E_3~0); 6573#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6779#L919-1 assume !(0 == ~E_5~0); 6478#L924-1 assume !(0 == ~E_6~0); 6292#L929-1 assume !(0 == ~E_7~0); 6293#L934-1 assume !(0 == ~E_8~0); 6551#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6079#L418 assume !(1 == ~m_pc~0); 6054#L418-2 is_master_triggered_~__retres1~0#1 := 0; 6053#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6948#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6934#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6867#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6868#L437 assume 1 == ~t1_pc~0; 7036#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6941#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6103#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 6428#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6924#L456 assume !(1 == ~t2_pc~0); 6350#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6349#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6510#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6511#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 6683#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6193#L475 assume 1 == ~t3_pc~0; 6194#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6257#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6070#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6071#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 6431#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6432#L494 assume !(1 == ~t4_pc~0); 6472#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6473#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6209#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6210#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 6803#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6252#L513 assume 1 == ~t5_pc~0; 6253#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6474#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6950#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6206#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 6207#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6159#L532 assume !(1 == ~t6_pc~0); 6160#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6311#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6493#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 6403#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6404#L551 assume 1 == ~t7_pc~0; 6961#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6805#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6806#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7045#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 7046#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6593#L570 assume 1 == ~t8_pc~0; 6594#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6709#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6899#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6705#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 6187#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6188#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 6128#L952-2 assume !(1 == ~T1_E~0); 6129#L957-1 assume !(1 == ~T2_E~0); 6905#L962-1 assume !(1 == ~T3_E~0); 6721#L967-1 assume !(1 == ~T4_E~0); 6722#L972-1 assume !(1 == ~T5_E~0); 6964#L977-1 assume !(1 == ~T6_E~0); 6965#L982-1 assume !(1 == ~T7_E~0); 6313#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6314#L992-1 assume !(1 == ~E_M~0); 6321#L997-1 assume !(1 == ~E_1~0); 6681#L1002-1 assume !(1 == ~E_2~0); 6666#L1007-1 assume !(1 == ~E_3~0); 6064#L1012-1 assume !(1 == ~E_4~0); 6065#L1017-1 assume !(1 == ~E_5~0); 6669#L1022-1 assume !(1 == ~E_6~0); 6670#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6695#L1032-1 assume !(1 == ~E_8~0); 6826#L1037-1 assume { :end_inline_reset_delta_events } true; 6827#L1303-2 [2024-10-31 22:04:32,418 INFO L747 eck$LassoCheckResult]: Loop: 6827#L1303-2 assume !false; 6901#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6568#L829-1 assume !false; 6864#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6454#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6389#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6532#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6533#L712 assume !(0 != eval_~tmp~0#1); 6794#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6703#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6704#L854-3 assume !(0 == ~M_E~0); 6795#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6796#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7044#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7018#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6611#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6612#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6682#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6660#L889-3 assume !(0 == ~T8_E~0); 6283#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6284#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6317#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6318#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6262#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6263#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6306#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6870#L929-3 assume !(0 == ~E_7~0); 6781#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6782#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6889#L418-30 assume 1 == ~m_pc~0; 6146#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6147#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6523#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6524#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6351#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6352#L437-30 assume 1 == ~t1_pc~0; 6475#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6701#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6702#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6739#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7035#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6435#L456-30 assume !(1 == ~t2_pc~0); 6436#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 6862#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6434#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6240#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6241#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6583#L475-30 assume 1 == ~t3_pc~0; 6957#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6111#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6719#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6720#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6458#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6459#L494-30 assume 1 == ~t4_pc~0; 6449#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6050#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6051#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7023#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6973#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6974#L513-30 assume 1 == ~t5_pc~0; 7047#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6589#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6658#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6815#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6881#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6601#L532-30 assume 1 == ~t6_pc~0; 6602#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6191#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6192#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6216#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6272#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6273#L551-30 assume !(1 == ~t7_pc~0); 6325#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 6391#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6871#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6066#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 6067#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6433#L570-30 assume !(1 == ~t8_pc~0); 6787#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6322#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6323#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6124#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6125#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6504#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6548#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6999#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7000#L962-3 assume !(1 == ~T3_E~0); 6922#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6923#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6842#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6843#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7048#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6490#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6491#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6486#L1002-3 assume !(1 == ~E_2~0); 6487#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6296#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6297#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6398#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6634#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6094#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6095#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6340#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6341#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6456#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6457#L1322 assume !(0 == start_simulation_~tmp~3#1); 6518#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6181#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6182#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 6080#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6081#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6717#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6718#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 6827#L1303-2 [2024-10-31 22:04:32,419 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,419 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2024-10-31 22:04:32,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105747475] [2024-10-31 22:04:32,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105747475] [2024-10-31 22:04:32,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1105747475] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:32,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790882243] [2024-10-31 22:04:32,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,481 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:32,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,482 INFO L85 PathProgramCache]: Analyzing trace with hash 1773359198, now seen corresponding path program 1 times [2024-10-31 22:04:32,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523453366] [2024-10-31 22:04:32,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,561 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523453366] [2024-10-31 22:04:32,561 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1523453366] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,561 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:32,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339667535] [2024-10-31 22:04:32,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,562 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:32,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:32,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:32,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:32,563 INFO L87 Difference]: Start difference. First operand 1002 states and 1488 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:32,590 INFO L93 Difference]: Finished difference Result 1002 states and 1487 transitions. [2024-10-31 22:04:32,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1487 transitions. [2024-10-31 22:04:32,597 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:32,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1487 transitions. [2024-10-31 22:04:32,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-10-31 22:04:32,604 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-10-31 22:04:32,604 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1487 transitions. [2024-10-31 22:04:32,606 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:32,606 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2024-10-31 22:04:32,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1487 transitions. [2024-10-31 22:04:32,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-10-31 22:04:32,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4840319361277445) internal successors, (1487), 1001 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1487 transitions. [2024-10-31 22:04:32,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2024-10-31 22:04:32,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:32,633 INFO L425 stractBuchiCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2024-10-31 22:04:32,633 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:04:32,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1487 transitions. [2024-10-31 22:04:32,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:32,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:32,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:32,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,644 INFO L745 eck$LassoCheckResult]: Stem: 8380#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9005#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9006#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9044#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 8799#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8800#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8397#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8398#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8330#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8331#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8593#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8565#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8566#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8849#L854 assume !(0 == ~M_E~0); 8656#L854-2 assume !(0 == ~T1_E~0); 8657#L859-1 assume !(0 == ~T2_E~0); 8210#L864-1 assume !(0 == ~T3_E~0); 8211#L869-1 assume !(0 == ~T4_E~0); 8321#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9030#L879-1 assume !(0 == ~T6_E~0); 8646#L884-1 assume !(0 == ~T7_E~0); 8073#L889-1 assume !(0 == ~T8_E~0); 8074#L894-1 assume !(0 == ~E_M~0); 8410#L899-1 assume !(0 == ~E_1~0); 8855#L904-1 assume !(0 == ~E_2~0); 8583#L909-1 assume !(0 == ~E_3~0); 8584#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8790#L919-1 assume !(0 == ~E_5~0); 8489#L924-1 assume !(0 == ~E_6~0); 8303#L929-1 assume !(0 == ~E_7~0); 8304#L934-1 assume !(0 == ~E_8~0); 8562#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8090#L418 assume !(1 == ~m_pc~0); 8065#L418-2 is_master_triggered_~__retres1~0#1 := 0; 8064#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8959#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8945#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8878#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8879#L437 assume 1 == ~t1_pc~0; 9047#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8952#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8113#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8114#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 8439#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8935#L456 assume !(1 == ~t2_pc~0); 8361#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8360#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8521#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8522#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 8694#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8204#L475 assume 1 == ~t3_pc~0; 8205#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8268#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8081#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8082#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 8442#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8443#L494 assume !(1 == ~t4_pc~0); 8483#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8484#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8221#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 8814#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8263#L513 assume 1 == ~t5_pc~0; 8264#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8485#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8217#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 8218#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8170#L532 assume !(1 == ~t6_pc~0); 8171#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8322#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8503#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8504#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 8414#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8415#L551 assume 1 == ~t7_pc~0; 8972#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8816#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8817#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9056#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 9057#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8604#L570 assume 1 == ~t8_pc~0; 8605#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8720#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8910#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8716#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 8198#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8199#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 8139#L952-2 assume !(1 == ~T1_E~0); 8140#L957-1 assume !(1 == ~T2_E~0); 8916#L962-1 assume !(1 == ~T3_E~0); 8732#L967-1 assume !(1 == ~T4_E~0); 8733#L972-1 assume !(1 == ~T5_E~0); 8975#L977-1 assume !(1 == ~T6_E~0); 8976#L982-1 assume !(1 == ~T7_E~0); 8324#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8325#L992-1 assume !(1 == ~E_M~0); 8332#L997-1 assume !(1 == ~E_1~0); 8692#L1002-1 assume !(1 == ~E_2~0); 8677#L1007-1 assume !(1 == ~E_3~0); 8075#L1012-1 assume !(1 == ~E_4~0); 8076#L1017-1 assume !(1 == ~E_5~0); 8680#L1022-1 assume !(1 == ~E_6~0); 8681#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8706#L1032-1 assume !(1 == ~E_8~0); 8837#L1037-1 assume { :end_inline_reset_delta_events } true; 8838#L1303-2 [2024-10-31 22:04:32,645 INFO L747 eck$LassoCheckResult]: Loop: 8838#L1303-2 assume !false; 8912#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8579#L829-1 assume !false; 8875#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8465#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8400#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8543#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8544#L712 assume !(0 != eval_~tmp~0#1); 8805#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8714#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8715#L854-3 assume !(0 == ~M_E~0); 8806#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8807#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9055#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9029#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8622#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8623#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8693#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8671#L889-3 assume !(0 == ~T8_E~0); 8294#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8295#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8328#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8329#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8273#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8274#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8317#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8881#L929-3 assume !(0 == ~E_7~0); 8792#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8793#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8900#L418-30 assume 1 == ~m_pc~0; 8157#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8158#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8534#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8535#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8362#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8363#L437-30 assume 1 == ~t1_pc~0; 8486#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8712#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8713#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8750#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9046#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8446#L456-30 assume 1 == ~t2_pc~0; 8448#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8873#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8445#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8251#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8252#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8594#L475-30 assume 1 == ~t3_pc~0; 8968#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8122#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8730#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8731#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8469#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8470#L494-30 assume !(1 == ~t4_pc~0); 8278#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8061#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8062#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9034#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8984#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8985#L513-30 assume 1 == ~t5_pc~0; 9058#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8600#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8669#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8826#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8892#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8612#L532-30 assume 1 == ~t6_pc~0; 8613#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8202#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8203#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8227#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8283#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8284#L551-30 assume !(1 == ~t7_pc~0); 8336#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 8402#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8882#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8077#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 8078#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8444#L570-30 assume 1 == ~t8_pc~0; 8953#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8333#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8334#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8135#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8136#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8515#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8559#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9010#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9011#L962-3 assume !(1 == ~T3_E~0); 8933#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8934#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8853#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8854#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9059#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8501#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8502#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8497#L1002-3 assume !(1 == ~E_2~0); 8498#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8307#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8308#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8409#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8645#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8105#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8106#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8351#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8352#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8467#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8468#L1322 assume !(0 == start_simulation_~tmp~3#1); 8529#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8192#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8193#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8109#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 8091#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8092#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8728#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8729#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 8838#L1303-2 [2024-10-31 22:04:32,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,645 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2024-10-31 22:04:32,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830882601] [2024-10-31 22:04:32,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830882601] [2024-10-31 22:04:32,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830882601] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:32,722 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109560861] [2024-10-31 22:04:32,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,722 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:32,722 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,723 INFO L85 PathProgramCache]: Analyzing trace with hash -455356643, now seen corresponding path program 1 times [2024-10-31 22:04:32,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342442370] [2024-10-31 22:04:32,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,797 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342442370] [2024-10-31 22:04:32,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1342442370] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,798 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,798 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:32,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1630513323] [2024-10-31 22:04:32,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,799 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:32,800 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:32,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:32,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:32,801 INFO L87 Difference]: Start difference. First operand 1002 states and 1487 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:32,827 INFO L93 Difference]: Finished difference Result 1002 states and 1486 transitions. [2024-10-31 22:04:32,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1486 transitions. [2024-10-31 22:04:32,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:32,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1486 transitions. [2024-10-31 22:04:32,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-10-31 22:04:32,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-10-31 22:04:32,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1486 transitions. [2024-10-31 22:04:32,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:32,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2024-10-31 22:04:32,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1486 transitions. [2024-10-31 22:04:32,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-10-31 22:04:32,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4830339321357286) internal successors, (1486), 1001 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:32,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1486 transitions. [2024-10-31 22:04:32,893 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2024-10-31 22:04:32,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:32,896 INFO L425 stractBuchiCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2024-10-31 22:04:32,896 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:04:32,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1486 transitions. [2024-10-31 22:04:32,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:32,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:32,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:32,904 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,904 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:32,904 INFO L745 eck$LassoCheckResult]: Stem: 10391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11016#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11017#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11055#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 10810#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10811#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10408#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10409#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10341#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10342#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10604#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10576#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10577#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10860#L854 assume !(0 == ~M_E~0); 10667#L854-2 assume !(0 == ~T1_E~0); 10668#L859-1 assume !(0 == ~T2_E~0); 10221#L864-1 assume !(0 == ~T3_E~0); 10222#L869-1 assume !(0 == ~T4_E~0); 10332#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11041#L879-1 assume !(0 == ~T6_E~0); 10657#L884-1 assume !(0 == ~T7_E~0); 10084#L889-1 assume !(0 == ~T8_E~0); 10085#L894-1 assume !(0 == ~E_M~0); 10421#L899-1 assume !(0 == ~E_1~0); 10866#L904-1 assume !(0 == ~E_2~0); 10594#L909-1 assume !(0 == ~E_3~0); 10595#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10801#L919-1 assume !(0 == ~E_5~0); 10500#L924-1 assume !(0 == ~E_6~0); 10314#L929-1 assume !(0 == ~E_7~0); 10315#L934-1 assume !(0 == ~E_8~0); 10573#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10101#L418 assume !(1 == ~m_pc~0); 10076#L418-2 is_master_triggered_~__retres1~0#1 := 0; 10075#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10970#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10956#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10889#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10890#L437 assume 1 == ~t1_pc~0; 11058#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10963#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10125#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 10450#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10946#L456 assume !(1 == ~t2_pc~0); 10372#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10371#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10532#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10533#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 10705#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10215#L475 assume 1 == ~t3_pc~0; 10216#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10279#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10092#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10093#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 10453#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10454#L494 assume !(1 == ~t4_pc~0); 10494#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10495#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10231#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10232#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 10825#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10274#L513 assume 1 == ~t5_pc~0; 10275#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10496#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10972#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10228#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 10229#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10181#L532 assume !(1 == ~t6_pc~0); 10182#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10333#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10515#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 10425#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10426#L551 assume 1 == ~t7_pc~0; 10983#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10827#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10828#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11067#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 11068#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10615#L570 assume 1 == ~t8_pc~0; 10616#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10731#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10921#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10727#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 10209#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10210#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 10150#L952-2 assume !(1 == ~T1_E~0); 10151#L957-1 assume !(1 == ~T2_E~0); 10927#L962-1 assume !(1 == ~T3_E~0); 10743#L967-1 assume !(1 == ~T4_E~0); 10744#L972-1 assume !(1 == ~T5_E~0); 10986#L977-1 assume !(1 == ~T6_E~0); 10987#L982-1 assume !(1 == ~T7_E~0); 10335#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10336#L992-1 assume !(1 == ~E_M~0); 10343#L997-1 assume !(1 == ~E_1~0); 10703#L1002-1 assume !(1 == ~E_2~0); 10688#L1007-1 assume !(1 == ~E_3~0); 10086#L1012-1 assume !(1 == ~E_4~0); 10087#L1017-1 assume !(1 == ~E_5~0); 10691#L1022-1 assume !(1 == ~E_6~0); 10692#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10717#L1032-1 assume !(1 == ~E_8~0); 10848#L1037-1 assume { :end_inline_reset_delta_events } true; 10849#L1303-2 [2024-10-31 22:04:32,905 INFO L747 eck$LassoCheckResult]: Loop: 10849#L1303-2 assume !false; 10923#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10590#L829-1 assume !false; 10886#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10476#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10411#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10554#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10555#L712 assume !(0 != eval_~tmp~0#1); 10816#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10725#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10726#L854-3 assume !(0 == ~M_E~0); 10817#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10818#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11066#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11040#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10633#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10634#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10704#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10682#L889-3 assume !(0 == ~T8_E~0); 10305#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10306#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10339#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10340#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10284#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10285#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10328#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10892#L929-3 assume !(0 == ~E_7~0); 10803#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10804#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10911#L418-30 assume 1 == ~m_pc~0; 10168#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10169#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10545#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10546#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10373#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10374#L437-30 assume 1 == ~t1_pc~0; 10497#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10723#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10724#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10761#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11057#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10457#L456-30 assume !(1 == ~t2_pc~0); 10458#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 10884#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10456#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10262#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10263#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10605#L475-30 assume 1 == ~t3_pc~0; 10979#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10133#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10741#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10742#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10480#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10481#L494-30 assume !(1 == ~t4_pc~0); 10289#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10072#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10073#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11045#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10995#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10996#L513-30 assume !(1 == ~t5_pc~0); 10610#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10611#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10680#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10837#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10903#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10623#L532-30 assume 1 == ~t6_pc~0; 10624#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10213#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10214#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10238#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10294#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10295#L551-30 assume !(1 == ~t7_pc~0); 10347#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 10413#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10893#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10088#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 10089#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10455#L570-30 assume 1 == ~t8_pc~0; 10964#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10344#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10345#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10146#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10147#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10526#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10570#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11021#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11022#L962-3 assume !(1 == ~T3_E~0); 10944#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10945#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10864#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10865#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11070#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10512#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10513#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10508#L1002-3 assume !(1 == ~E_2~0); 10509#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10318#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10319#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10420#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10656#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10116#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10117#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10362#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10363#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10479#L1322 assume !(0 == start_simulation_~tmp~3#1); 10540#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10203#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10204#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10120#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 10102#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10103#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10739#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10740#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 10849#L1303-2 [2024-10-31 22:04:32,906 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,906 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2024-10-31 22:04:32,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855507779] [2024-10-31 22:04:32,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:32,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:32,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:32,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855507779] [2024-10-31 22:04:32,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855507779] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:32,964 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:32,965 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:32,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799765880] [2024-10-31 22:04:32,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:32,965 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:32,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:32,966 INFO L85 PathProgramCache]: Analyzing trace with hash 568502751, now seen corresponding path program 1 times [2024-10-31 22:04:32,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:32,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771491471] [2024-10-31 22:04:32,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:32,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:32,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:33,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:33,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:33,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771491471] [2024-10-31 22:04:33,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771491471] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:33,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:33,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:33,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [784086927] [2024-10-31 22:04:33,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:33,040 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:33,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:33,041 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:33,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:33,042 INFO L87 Difference]: Start difference. First operand 1002 states and 1486 transitions. cyclomatic complexity: 485 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:33,068 INFO L93 Difference]: Finished difference Result 1002 states and 1485 transitions. [2024-10-31 22:04:33,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1485 transitions. [2024-10-31 22:04:33,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:33,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1485 transitions. [2024-10-31 22:04:33,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-10-31 22:04:33,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-10-31 22:04:33,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1485 transitions. [2024-10-31 22:04:33,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:33,083 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2024-10-31 22:04:33,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1485 transitions. [2024-10-31 22:04:33,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-10-31 22:04:33,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4820359281437125) internal successors, (1485), 1001 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1485 transitions. [2024-10-31 22:04:33,102 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2024-10-31 22:04:33,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:33,103 INFO L425 stractBuchiCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2024-10-31 22:04:33,104 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:04:33,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1485 transitions. [2024-10-31 22:04:33,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:33,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:33,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:33,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,112 INFO L745 eck$LassoCheckResult]: Stem: 12402#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12403#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13027#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13028#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13066#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 12821#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12822#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12419#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12420#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12352#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12353#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12615#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12587#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12588#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12871#L854 assume !(0 == ~M_E~0); 12678#L854-2 assume !(0 == ~T1_E~0); 12679#L859-1 assume !(0 == ~T2_E~0); 12232#L864-1 assume !(0 == ~T3_E~0); 12233#L869-1 assume !(0 == ~T4_E~0); 12343#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13052#L879-1 assume !(0 == ~T6_E~0); 12668#L884-1 assume !(0 == ~T7_E~0); 12095#L889-1 assume !(0 == ~T8_E~0); 12096#L894-1 assume !(0 == ~E_M~0); 12432#L899-1 assume !(0 == ~E_1~0); 12877#L904-1 assume !(0 == ~E_2~0); 12605#L909-1 assume !(0 == ~E_3~0); 12606#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12812#L919-1 assume !(0 == ~E_5~0); 12511#L924-1 assume !(0 == ~E_6~0); 12325#L929-1 assume !(0 == ~E_7~0); 12326#L934-1 assume !(0 == ~E_8~0); 12584#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12112#L418 assume !(1 == ~m_pc~0); 12087#L418-2 is_master_triggered_~__retres1~0#1 := 0; 12086#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12981#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12967#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12900#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12901#L437 assume 1 == ~t1_pc~0; 13069#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12974#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12136#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 12461#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12957#L456 assume !(1 == ~t2_pc~0); 12383#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12382#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12543#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12544#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 12716#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12226#L475 assume 1 == ~t3_pc~0; 12227#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12290#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12104#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 12464#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12465#L494 assume !(1 == ~t4_pc~0); 12505#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12506#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12242#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12243#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 12836#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12285#L513 assume 1 == ~t5_pc~0; 12286#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12507#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12983#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12239#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 12240#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12192#L532 assume !(1 == ~t6_pc~0); 12193#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12344#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12525#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12526#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 12436#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12437#L551 assume 1 == ~t7_pc~0; 12994#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12838#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12839#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13078#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 13079#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12626#L570 assume 1 == ~t8_pc~0; 12627#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12742#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12932#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12738#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 12220#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12221#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 12161#L952-2 assume !(1 == ~T1_E~0); 12162#L957-1 assume !(1 == ~T2_E~0); 12938#L962-1 assume !(1 == ~T3_E~0); 12754#L967-1 assume !(1 == ~T4_E~0); 12755#L972-1 assume !(1 == ~T5_E~0); 12997#L977-1 assume !(1 == ~T6_E~0); 12998#L982-1 assume !(1 == ~T7_E~0); 12346#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12347#L992-1 assume !(1 == ~E_M~0); 12354#L997-1 assume !(1 == ~E_1~0); 12714#L1002-1 assume !(1 == ~E_2~0); 12699#L1007-1 assume !(1 == ~E_3~0); 12097#L1012-1 assume !(1 == ~E_4~0); 12098#L1017-1 assume !(1 == ~E_5~0); 12702#L1022-1 assume !(1 == ~E_6~0); 12703#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12728#L1032-1 assume !(1 == ~E_8~0); 12859#L1037-1 assume { :end_inline_reset_delta_events } true; 12860#L1303-2 [2024-10-31 22:04:33,112 INFO L747 eck$LassoCheckResult]: Loop: 12860#L1303-2 assume !false; 12934#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12601#L829-1 assume !false; 12897#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12487#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12422#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12565#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12566#L712 assume !(0 != eval_~tmp~0#1); 12827#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12737#L854-3 assume !(0 == ~M_E~0); 12828#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12829#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13077#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13051#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12644#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12645#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12715#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12693#L889-3 assume !(0 == ~T8_E~0); 12316#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12317#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12350#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12351#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12295#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12296#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12339#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12903#L929-3 assume !(0 == ~E_7~0); 12814#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12815#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12922#L418-30 assume 1 == ~m_pc~0; 12179#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12180#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12556#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12557#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12384#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12385#L437-30 assume 1 == ~t1_pc~0; 12508#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12734#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12735#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12772#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13068#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12468#L456-30 assume !(1 == ~t2_pc~0); 12469#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 12895#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12467#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12273#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12274#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12616#L475-30 assume 1 == ~t3_pc~0; 12990#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12144#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12752#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12753#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12491#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12492#L494-30 assume 1 == ~t4_pc~0; 12482#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12083#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12084#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13056#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13006#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13007#L513-30 assume 1 == ~t5_pc~0; 13080#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12622#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12691#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12848#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12914#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12634#L532-30 assume 1 == ~t6_pc~0; 12635#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12224#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12225#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12249#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12305#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12306#L551-30 assume !(1 == ~t7_pc~0); 12358#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 12424#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12904#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12099#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 12100#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12466#L570-30 assume !(1 == ~t8_pc~0); 12820#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 12355#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12356#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12157#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12158#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12537#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12581#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13032#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13033#L962-3 assume !(1 == ~T3_E~0); 12955#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12956#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12875#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12876#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13081#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12523#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12524#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12519#L1002-3 assume !(1 == ~E_2~0); 12520#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12329#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12330#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12431#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12667#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12127#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12128#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12373#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12374#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12490#L1322 assume !(0 == start_simulation_~tmp~3#1); 12551#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12214#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12215#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12131#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 12113#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12114#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12750#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12751#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 12860#L1303-2 [2024-10-31 22:04:33,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,113 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2024-10-31 22:04:33,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635804647] [2024-10-31 22:04:33,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:33,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:33,163 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:33,164 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635804647] [2024-10-31 22:04:33,164 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [635804647] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:33,164 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:33,164 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:33,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994337580] [2024-10-31 22:04:33,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:33,165 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:33,166 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,166 INFO L85 PathProgramCache]: Analyzing trace with hash 1773359198, now seen corresponding path program 2 times [2024-10-31 22:04:33,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001069051] [2024-10-31 22:04:33,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:33,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:33,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:33,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001069051] [2024-10-31 22:04:33,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001069051] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:33,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:33,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:33,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207821398] [2024-10-31 22:04:33,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:33,240 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:33,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:33,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:33,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:33,241 INFO L87 Difference]: Start difference. First operand 1002 states and 1485 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:33,267 INFO L93 Difference]: Finished difference Result 1002 states and 1484 transitions. [2024-10-31 22:04:33,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1484 transitions. [2024-10-31 22:04:33,273 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:33,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1484 transitions. [2024-10-31 22:04:33,279 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-10-31 22:04:33,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-10-31 22:04:33,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1484 transitions. [2024-10-31 22:04:33,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:33,282 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2024-10-31 22:04:33,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1484 transitions. [2024-10-31 22:04:33,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-10-31 22:04:33,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4810379241516967) internal successors, (1484), 1001 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1484 transitions. [2024-10-31 22:04:33,302 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2024-10-31 22:04:33,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:33,304 INFO L425 stractBuchiCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2024-10-31 22:04:33,304 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:04:33,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1484 transitions. [2024-10-31 22:04:33,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:33,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:33,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:33,311 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,312 INFO L745 eck$LassoCheckResult]: Stem: 14413#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15038#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15039#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15077#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 14832#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14833#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14430#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14431#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14363#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14364#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14626#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14598#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14599#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14882#L854 assume !(0 == ~M_E~0); 14689#L854-2 assume !(0 == ~T1_E~0); 14690#L859-1 assume !(0 == ~T2_E~0); 14243#L864-1 assume !(0 == ~T3_E~0); 14244#L869-1 assume !(0 == ~T4_E~0); 14354#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15063#L879-1 assume !(0 == ~T6_E~0); 14679#L884-1 assume !(0 == ~T7_E~0); 14106#L889-1 assume !(0 == ~T8_E~0); 14107#L894-1 assume !(0 == ~E_M~0); 14443#L899-1 assume !(0 == ~E_1~0); 14888#L904-1 assume !(0 == ~E_2~0); 14616#L909-1 assume !(0 == ~E_3~0); 14617#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14823#L919-1 assume !(0 == ~E_5~0); 14522#L924-1 assume !(0 == ~E_6~0); 14336#L929-1 assume !(0 == ~E_7~0); 14337#L934-1 assume !(0 == ~E_8~0); 14595#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14123#L418 assume !(1 == ~m_pc~0); 14098#L418-2 is_master_triggered_~__retres1~0#1 := 0; 14097#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14992#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14978#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14911#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14912#L437 assume 1 == ~t1_pc~0; 15080#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14985#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14147#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 14472#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14968#L456 assume !(1 == ~t2_pc~0); 14394#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14393#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14554#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14555#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 14727#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14237#L475 assume 1 == ~t3_pc~0; 14238#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14301#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14114#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14115#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 14475#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14476#L494 assume !(1 == ~t4_pc~0); 14516#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14517#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14253#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14254#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 14847#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14296#L513 assume 1 == ~t5_pc~0; 14297#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14518#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14994#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14250#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 14251#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14203#L532 assume !(1 == ~t6_pc~0); 14204#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14355#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14536#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14537#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 14447#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14448#L551 assume 1 == ~t7_pc~0; 15005#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14849#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14850#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15089#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 15090#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14637#L570 assume 1 == ~t8_pc~0; 14638#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14753#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14943#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14749#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 14231#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14232#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 14172#L952-2 assume !(1 == ~T1_E~0); 14173#L957-1 assume !(1 == ~T2_E~0); 14949#L962-1 assume !(1 == ~T3_E~0); 14765#L967-1 assume !(1 == ~T4_E~0); 14766#L972-1 assume !(1 == ~T5_E~0); 15008#L977-1 assume !(1 == ~T6_E~0); 15009#L982-1 assume !(1 == ~T7_E~0); 14357#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14358#L992-1 assume !(1 == ~E_M~0); 14365#L997-1 assume !(1 == ~E_1~0); 14725#L1002-1 assume !(1 == ~E_2~0); 14710#L1007-1 assume !(1 == ~E_3~0); 14108#L1012-1 assume !(1 == ~E_4~0); 14109#L1017-1 assume !(1 == ~E_5~0); 14713#L1022-1 assume !(1 == ~E_6~0); 14714#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14739#L1032-1 assume !(1 == ~E_8~0); 14870#L1037-1 assume { :end_inline_reset_delta_events } true; 14871#L1303-2 [2024-10-31 22:04:33,313 INFO L747 eck$LassoCheckResult]: Loop: 14871#L1303-2 assume !false; 14945#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14612#L829-1 assume !false; 14908#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14498#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14433#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14577#L712 assume !(0 != eval_~tmp~0#1); 14838#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14748#L854-3 assume !(0 == ~M_E~0); 14839#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14840#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15088#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15062#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14655#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14656#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14726#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14704#L889-3 assume !(0 == ~T8_E~0); 14327#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14328#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14361#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14362#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14306#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14307#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14350#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14914#L929-3 assume !(0 == ~E_7~0); 14825#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14826#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14933#L418-30 assume !(1 == ~m_pc~0); 14192#L418-32 is_master_triggered_~__retres1~0#1 := 0; 14191#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14567#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14568#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14395#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14396#L437-30 assume 1 == ~t1_pc~0; 14519#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14745#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14746#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14783#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15079#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14479#L456-30 assume !(1 == ~t2_pc~0); 14480#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 14906#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14478#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14284#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14285#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14627#L475-30 assume 1 == ~t3_pc~0; 15001#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14155#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14763#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14764#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14502#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14503#L494-30 assume !(1 == ~t4_pc~0); 14311#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14094#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14095#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15067#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15017#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15018#L513-30 assume 1 == ~t5_pc~0; 15091#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14633#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14702#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14859#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14925#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14645#L532-30 assume 1 == ~t6_pc~0; 14646#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14235#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14236#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14260#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14316#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14317#L551-30 assume !(1 == ~t7_pc~0); 14369#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 14435#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14915#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14110#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 14111#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14477#L570-30 assume 1 == ~t8_pc~0; 14986#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14366#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14367#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14168#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14169#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14548#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14592#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15043#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15044#L962-3 assume !(1 == ~T3_E~0); 14966#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14967#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14886#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14887#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15092#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14534#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14535#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14530#L1002-3 assume !(1 == ~E_2~0); 14531#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14340#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14341#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14442#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14678#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14138#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14139#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14384#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14385#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14500#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14501#L1322 assume !(0 == start_simulation_~tmp~3#1); 14562#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14225#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14226#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14142#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 14124#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14125#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14761#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14762#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 14871#L1303-2 [2024-10-31 22:04:33,313 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,314 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2024-10-31 22:04:33,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905118053] [2024-10-31 22:04:33,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:33,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:33,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:33,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905118053] [2024-10-31 22:04:33,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905118053] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:33,392 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:33,393 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:33,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089038443] [2024-10-31 22:04:33,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:33,393 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:33,394 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,394 INFO L85 PathProgramCache]: Analyzing trace with hash 459444767, now seen corresponding path program 1 times [2024-10-31 22:04:33,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,395 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857688739] [2024-10-31 22:04:33,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:33,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:33,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:33,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857688739] [2024-10-31 22:04:33,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857688739] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:33,458 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:33,458 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:33,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446328468] [2024-10-31 22:04:33,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:33,459 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:33,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:33,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:33,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:33,460 INFO L87 Difference]: Start difference. First operand 1002 states and 1484 transitions. cyclomatic complexity: 483 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:33,486 INFO L93 Difference]: Finished difference Result 1002 states and 1483 transitions. [2024-10-31 22:04:33,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1483 transitions. [2024-10-31 22:04:33,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:33,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1483 transitions. [2024-10-31 22:04:33,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-10-31 22:04:33,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-10-31 22:04:33,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1483 transitions. [2024-10-31 22:04:33,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:33,501 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2024-10-31 22:04:33,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1483 transitions. [2024-10-31 22:04:33,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-10-31 22:04:33,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4800399201596806) internal successors, (1483), 1001 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:33,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1483 transitions. [2024-10-31 22:04:33,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2024-10-31 22:04:33,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:33,524 INFO L425 stractBuchiCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2024-10-31 22:04:33,524 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:04:33,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1483 transitions. [2024-10-31 22:04:33,533 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-10-31 22:04:33,537 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:33,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:33,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:33,540 INFO L745 eck$LassoCheckResult]: Stem: 16424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17088#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 16843#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16844#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16441#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16442#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16374#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16375#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16637#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16609#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16610#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16893#L854 assume !(0 == ~M_E~0); 16700#L854-2 assume !(0 == ~T1_E~0); 16701#L859-1 assume !(0 == ~T2_E~0); 16254#L864-1 assume !(0 == ~T3_E~0); 16255#L869-1 assume !(0 == ~T4_E~0); 16365#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17074#L879-1 assume !(0 == ~T6_E~0); 16690#L884-1 assume !(0 == ~T7_E~0); 16117#L889-1 assume !(0 == ~T8_E~0); 16118#L894-1 assume !(0 == ~E_M~0); 16454#L899-1 assume !(0 == ~E_1~0); 16899#L904-1 assume !(0 == ~E_2~0); 16627#L909-1 assume !(0 == ~E_3~0); 16628#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16834#L919-1 assume !(0 == ~E_5~0); 16533#L924-1 assume !(0 == ~E_6~0); 16347#L929-1 assume !(0 == ~E_7~0); 16348#L934-1 assume !(0 == ~E_8~0); 16606#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16134#L418 assume !(1 == ~m_pc~0); 16109#L418-2 is_master_triggered_~__retres1~0#1 := 0; 16108#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17003#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16989#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16922#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16923#L437 assume 1 == ~t1_pc~0; 17091#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16996#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16158#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 16483#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16979#L456 assume !(1 == ~t2_pc~0); 16405#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16404#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16565#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16566#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 16738#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16248#L475 assume 1 == ~t3_pc~0; 16249#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16312#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16126#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 16486#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16487#L494 assume !(1 == ~t4_pc~0); 16527#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16528#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16264#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16265#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 16858#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16307#L513 assume 1 == ~t5_pc~0; 16308#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16529#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17005#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16261#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 16262#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16214#L532 assume !(1 == ~t6_pc~0); 16215#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16366#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16547#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16548#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 16458#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16459#L551 assume 1 == ~t7_pc~0; 17016#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16860#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16861#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17100#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 17101#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16648#L570 assume 1 == ~t8_pc~0; 16649#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16764#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16954#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16760#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 16242#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16243#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 16183#L952-2 assume !(1 == ~T1_E~0); 16184#L957-1 assume !(1 == ~T2_E~0); 16960#L962-1 assume !(1 == ~T3_E~0); 16776#L967-1 assume !(1 == ~T4_E~0); 16777#L972-1 assume !(1 == ~T5_E~0); 17019#L977-1 assume !(1 == ~T6_E~0); 17020#L982-1 assume !(1 == ~T7_E~0); 16368#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16369#L992-1 assume !(1 == ~E_M~0); 16376#L997-1 assume !(1 == ~E_1~0); 16736#L1002-1 assume !(1 == ~E_2~0); 16721#L1007-1 assume !(1 == ~E_3~0); 16119#L1012-1 assume !(1 == ~E_4~0); 16120#L1017-1 assume !(1 == ~E_5~0); 16724#L1022-1 assume !(1 == ~E_6~0); 16725#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16750#L1032-1 assume !(1 == ~E_8~0); 16881#L1037-1 assume { :end_inline_reset_delta_events } true; 16882#L1303-2 [2024-10-31 22:04:33,540 INFO L747 eck$LassoCheckResult]: Loop: 16882#L1303-2 assume !false; 16956#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16623#L829-1 assume !false; 16919#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16509#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16444#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16587#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16588#L712 assume !(0 != eval_~tmp~0#1); 16849#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16758#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16759#L854-3 assume !(0 == ~M_E~0); 16850#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16851#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17099#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17073#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16666#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16667#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16737#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16715#L889-3 assume !(0 == ~T8_E~0); 16338#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16339#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16372#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16373#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16317#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16318#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16361#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16925#L929-3 assume !(0 == ~E_7~0); 16836#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16837#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16944#L418-30 assume 1 == ~m_pc~0; 16201#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16202#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16578#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16579#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16406#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16407#L437-30 assume 1 == ~t1_pc~0; 16530#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16756#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16757#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16794#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17090#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16490#L456-30 assume !(1 == ~t2_pc~0); 16491#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 16917#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16489#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16295#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16296#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16638#L475-30 assume 1 == ~t3_pc~0; 17012#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16166#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16774#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16775#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16513#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16514#L494-30 assume !(1 == ~t4_pc~0); 16322#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16105#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16106#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17078#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17028#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17029#L513-30 assume !(1 == ~t5_pc~0); 16643#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 16644#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16713#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16870#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16936#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16656#L532-30 assume 1 == ~t6_pc~0; 16657#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16246#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16247#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16271#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16327#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16328#L551-30 assume !(1 == ~t7_pc~0); 16380#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 16446#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16926#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16121#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 16122#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16488#L570-30 assume 1 == ~t8_pc~0; 16997#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16377#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16378#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16179#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16180#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16559#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16603#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17054#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17055#L962-3 assume !(1 == ~T3_E~0); 16977#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16978#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16897#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16898#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17103#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16545#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16546#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16541#L1002-3 assume !(1 == ~E_2~0); 16542#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16351#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16352#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16453#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16689#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16149#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16150#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16395#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16396#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16511#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 16512#L1322 assume !(0 == start_simulation_~tmp~3#1); 16573#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16236#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16237#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16153#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 16135#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16136#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16772#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16773#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 16882#L1303-2 [2024-10-31 22:04:33,540 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,540 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2024-10-31 22:04:33,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451049210] [2024-10-31 22:04:33,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:33,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:33,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:33,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451049210] [2024-10-31 22:04:33,647 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [451049210] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:33,647 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:33,647 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:33,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535286568] [2024-10-31 22:04:33,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:33,648 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:33,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:33,649 INFO L85 PathProgramCache]: Analyzing trace with hash 568502751, now seen corresponding path program 2 times [2024-10-31 22:04:33,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:33,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794834087] [2024-10-31 22:04:33,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:33,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:33,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:33,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:33,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:33,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794834087] [2024-10-31 22:04:33,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1794834087] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:33,791 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:33,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:33,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56468043] [2024-10-31 22:04:33,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:33,792 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:33,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:33,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:33,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:33,793 INFO L87 Difference]: Start difference. First operand 1002 states and 1483 transitions. cyclomatic complexity: 482 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:34,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:34,089 INFO L93 Difference]: Finished difference Result 1824 states and 2689 transitions. [2024-10-31 22:04:34,090 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1824 states and 2689 transitions. [2024-10-31 22:04:34,102 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1691 [2024-10-31 22:04:34,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1824 states to 1824 states and 2689 transitions. [2024-10-31 22:04:34,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1824 [2024-10-31 22:04:34,113 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1824 [2024-10-31 22:04:34,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1824 states and 2689 transitions. [2024-10-31 22:04:34,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:34,117 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2024-10-31 22:04:34,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1824 states and 2689 transitions. [2024-10-31 22:04:34,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1824 to 1824. [2024-10-31 22:04:34,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1824 states, 1824 states have (on average 1.4742324561403508) internal successors, (2689), 1823 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:34,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1824 states to 1824 states and 2689 transitions. [2024-10-31 22:04:34,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2024-10-31 22:04:34,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:34,205 INFO L425 stractBuchiCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2024-10-31 22:04:34,206 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:04:34,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1824 states and 2689 transitions. [2024-10-31 22:04:34,216 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1691 [2024-10-31 22:04:34,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:34,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:34,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:34,219 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:34,219 INFO L745 eck$LassoCheckResult]: Stem: 19262#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19263#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19933#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19934#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19980#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 19692#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19693#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19279#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19280#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19211#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19212#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19481#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19451#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19452#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19747#L854 assume !(0 == ~M_E~0); 19547#L854-2 assume !(0 == ~T1_E~0); 19548#L859-1 assume !(0 == ~T2_E~0); 19090#L864-1 assume !(0 == ~T3_E~0); 19091#L869-1 assume !(0 == ~T4_E~0); 19202#L874-1 assume !(0 == ~T5_E~0); 19965#L879-1 assume !(0 == ~T6_E~0); 19537#L884-1 assume !(0 == ~T7_E~0); 18953#L889-1 assume !(0 == ~T8_E~0); 18954#L894-1 assume !(0 == ~E_M~0); 19292#L899-1 assume !(0 == ~E_1~0); 19753#L904-1 assume !(0 == ~E_2~0); 19470#L909-1 assume !(0 == ~E_3~0); 19471#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19683#L919-1 assume !(0 == ~E_5~0); 19373#L924-1 assume !(0 == ~E_6~0); 19184#L929-1 assume !(0 == ~E_7~0); 19185#L934-1 assume !(0 == ~E_8~0); 19448#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18970#L418 assume !(1 == ~m_pc~0); 18945#L418-2 is_master_triggered_~__retres1~0#1 := 0; 18944#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19877#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19861#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19781#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19782#L437 assume 1 == ~t1_pc~0; 19985#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19869#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18993#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18994#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 19322#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19851#L456 assume !(1 == ~t2_pc~0); 19243#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19242#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19408#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 19585#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19084#L475 assume 1 == ~t3_pc~0; 19085#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19149#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18961#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18962#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 19325#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19326#L494 assume !(1 == ~t4_pc~0); 19367#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19368#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19100#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19101#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 19708#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19143#L513 assume 1 == ~t5_pc~0; 19144#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19369#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19097#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 19098#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19050#L532 assume !(1 == ~t6_pc~0); 19051#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19203#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19388#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19389#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 19297#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19298#L551 assume 1 == ~t7_pc~0; 19892#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19710#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19711#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19994#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 19995#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19492#L570 assume 1 == ~t8_pc~0; 19493#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19611#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19819#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19607#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 19078#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19079#L952 assume !(1 == ~M_E~0); 19019#L952-2 assume !(1 == ~T1_E~0); 19020#L957-1 assume !(1 == ~T2_E~0); 20076#L962-1 assume !(1 == ~T3_E~0); 20074#L967-1 assume !(1 == ~T4_E~0); 20073#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19895#L977-1 assume !(1 == ~T6_E~0); 19896#L982-1 assume !(1 == ~T7_E~0); 19205#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19206#L992-1 assume !(1 == ~E_M~0); 19213#L997-1 assume !(1 == ~E_1~0); 19583#L1002-1 assume !(1 == ~E_2~0); 19568#L1007-1 assume !(1 == ~E_3~0); 18955#L1012-1 assume !(1 == ~E_4~0); 18956#L1017-1 assume !(1 == ~E_5~0); 19571#L1022-1 assume !(1 == ~E_6~0); 19572#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19597#L1032-1 assume !(1 == ~E_8~0); 19734#L1037-1 assume { :end_inline_reset_delta_events } true; 19735#L1303-2 [2024-10-31 22:04:34,220 INFO L747 eck$LassoCheckResult]: Loop: 19735#L1303-2 assume !false; 19862#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19466#L829-1 assume !false; 19999#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20008#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19897#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19898#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20003#L712 assume !(0 != eval_~tmp~0#1); 19823#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19605#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19606#L854-3 assume !(0 == ~M_E~0); 20001#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20585#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20584#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20583#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20582#L874-3 assume !(0 == ~T5_E~0); 20581#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20580#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20579#L889-3 assume !(0 == ~T8_E~0); 20578#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20577#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20576#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20575#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20574#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20573#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20572#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20571#L929-3 assume !(0 == ~E_7~0); 20570#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20569#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20568#L418-30 assume 1 == ~m_pc~0; 20566#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20565#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20564#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20563#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20562#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20561#L437-30 assume !(1 == ~t1_pc~0); 20560#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 20558#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20557#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20556#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20555#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20554#L456-30 assume !(1 == ~t2_pc~0); 20552#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 20551#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20550#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20549#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20548#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20547#L475-30 assume 1 == ~t3_pc~0; 20545#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20544#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20543#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20542#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20541#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20540#L494-30 assume !(1 == ~t4_pc~0); 20538#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 20537#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20536#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20535#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20534#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20533#L513-30 assume 1 == ~t5_pc~0; 20531#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20530#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20529#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20528#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20527#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20526#L532-30 assume !(1 == ~t6_pc~0); 20524#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 20523#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20522#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20521#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20520#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20519#L551-30 assume 1 == ~t7_pc~0; 20517#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20516#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20515#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18957#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 18958#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19327#L570-30 assume !(1 == ~t8_pc~0); 19691#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 19214#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19215#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19015#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19016#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19401#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19445#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19938#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19939#L962-3 assume !(1 == ~T3_E~0); 19848#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19849#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19751#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19752#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19998#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19386#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19387#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19382#L1002-3 assume !(1 == ~E_2~0); 19383#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19188#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19189#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19291#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19536#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18985#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18986#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19233#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19234#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20199#L1322 assume !(0 == start_simulation_~tmp~3#1); 19771#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20088#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19940#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18989#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 18971#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18972#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20060#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19900#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 19735#L1303-2 [2024-10-31 22:04:34,221 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:34,221 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2024-10-31 22:04:34,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:34,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296962781] [2024-10-31 22:04:34,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:34,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:34,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:34,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:34,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:34,332 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296962781] [2024-10-31 22:04:34,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296962781] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:34,334 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:34,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:34,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093052671] [2024-10-31 22:04:34,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:34,335 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:34,336 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:34,336 INFO L85 PathProgramCache]: Analyzing trace with hash -1829389214, now seen corresponding path program 1 times [2024-10-31 22:04:34,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:34,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52945258] [2024-10-31 22:04:34,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:34,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:34,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:34,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:34,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:34,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [52945258] [2024-10-31 22:04:34,411 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [52945258] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:34,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:34,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:34,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113510394] [2024-10-31 22:04:34,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:34,412 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:34,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:34,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:34,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:34,413 INFO L87 Difference]: Start difference. First operand 1824 states and 2689 transitions. cyclomatic complexity: 867 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:34,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:34,631 INFO L93 Difference]: Finished difference Result 3322 states and 4884 transitions. [2024-10-31 22:04:34,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3322 states and 4884 transitions. [2024-10-31 22:04:34,650 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3169 [2024-10-31 22:04:34,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3322 states to 3322 states and 4884 transitions. [2024-10-31 22:04:34,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3322 [2024-10-31 22:04:34,671 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3322 [2024-10-31 22:04:34,671 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3322 states and 4884 transitions. [2024-10-31 22:04:34,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:34,677 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3322 states and 4884 transitions. [2024-10-31 22:04:34,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states and 4884 transitions. [2024-10-31 22:04:34,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 3320. [2024-10-31 22:04:34,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3320 states, 3320 states have (on average 1.4704819277108434) internal successors, (4882), 3319 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:34,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3320 states to 3320 states and 4882 transitions. [2024-10-31 22:04:34,748 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3320 states and 4882 transitions. [2024-10-31 22:04:34,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:34,750 INFO L425 stractBuchiCegarLoop]: Abstraction has 3320 states and 4882 transitions. [2024-10-31 22:04:34,750 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:04:34,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3320 states and 4882 transitions. [2024-10-31 22:04:34,763 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3169 [2024-10-31 22:04:34,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:34,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:34,766 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:34,766 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:34,766 INFO L745 eck$LassoCheckResult]: Stem: 24421#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25092#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25093#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25141#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 24856#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24857#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24438#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24439#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24371#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24372#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24643#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24615#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24616#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24910#L854 assume !(0 == ~M_E~0); 24709#L854-2 assume !(0 == ~T1_E~0); 24710#L859-1 assume !(0 == ~T2_E~0); 24250#L864-1 assume !(0 == ~T3_E~0); 24251#L869-1 assume !(0 == ~T4_E~0); 24362#L874-1 assume !(0 == ~T5_E~0); 25125#L879-1 assume !(0 == ~T6_E~0); 24699#L884-1 assume !(0 == ~T7_E~0); 24109#L889-1 assume !(0 == ~T8_E~0); 24110#L894-1 assume !(0 == ~E_M~0); 24453#L899-1 assume !(0 == ~E_1~0); 24916#L904-1 assume !(0 == ~E_2~0); 24633#L909-1 assume !(0 == ~E_3~0); 24634#L914-1 assume !(0 == ~E_4~0); 24846#L919-1 assume !(0 == ~E_5~0); 24536#L924-1 assume !(0 == ~E_6~0); 24344#L929-1 assume !(0 == ~E_7~0); 24345#L934-1 assume !(0 == ~E_8~0); 24612#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24127#L418 assume !(1 == ~m_pc~0); 24101#L418-2 is_master_triggered_~__retres1~0#1 := 0; 24100#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25035#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25020#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24940#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24941#L437 assume 1 == ~t1_pc~0; 25148#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25027#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24150#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24151#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 24484#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25008#L456 assume !(1 == ~t2_pc~0); 24402#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24401#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24570#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24571#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 24749#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24244#L475 assume 1 == ~t3_pc~0; 24245#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24309#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24118#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24119#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 24487#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24488#L494 assume !(1 == ~t4_pc~0); 24530#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24531#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24260#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24261#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 24871#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24304#L513 assume 1 == ~t5_pc~0; 24305#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24532#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24257#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 24258#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24208#L532 assume !(1 == ~t6_pc~0); 24209#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24363#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24552#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24553#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 24459#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24460#L551 assume 1 == ~t7_pc~0; 25050#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24875#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24876#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25167#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 25168#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24656#L570 assume 1 == ~t8_pc~0; 24657#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24776#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24981#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24772#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 24238#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24239#L952 assume !(1 == ~M_E~0); 25031#L952-2 assume !(1 == ~T1_E~0); 24987#L957-1 assume !(1 == ~T2_E~0); 24988#L962-1 assume !(1 == ~T3_E~0); 24788#L967-1 assume !(1 == ~T4_E~0); 24789#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25615#L977-1 assume !(1 == ~T6_E~0); 25613#L982-1 assume !(1 == ~T7_E~0); 25611#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25609#L992-1 assume !(1 == ~E_M~0); 24746#L997-1 assume !(1 == ~E_1~0); 24747#L1002-1 assume !(1 == ~E_2~0); 24730#L1007-1 assume !(1 == ~E_3~0); 24731#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25277#L1017-1 assume !(1 == ~E_5~0); 25251#L1022-1 assume !(1 == ~E_6~0); 25235#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25223#L1032-1 assume !(1 == ~E_8~0); 25214#L1037-1 assume { :end_inline_reset_delta_events } true; 25207#L1303-2 [2024-10-31 22:04:34,767 INFO L747 eck$LassoCheckResult]: Loop: 25207#L1303-2 assume !false; 25201#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25197#L829-1 assume !false; 25196#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25191#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25186#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25185#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25183#L712 assume !(0 != eval_~tmp~0#1); 25182#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25181#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25180#L854-3 assume !(0 == ~M_E~0); 24863#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24864#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25163#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25122#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24674#L874-3 assume !(0 == ~T5_E~0); 24675#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24748#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24724#L889-3 assume !(0 == ~T8_E~0); 24335#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24336#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24369#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24370#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24314#L914-3 assume !(0 == ~E_4~0); 24315#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24358#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24943#L929-3 assume !(0 == ~E_7~0); 24849#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24850#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24967#L418-30 assume 1 == ~m_pc~0; 24195#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24196#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24583#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24584#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24403#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24404#L437-30 assume 1 == ~t1_pc~0; 24533#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24768#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24769#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24806#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25157#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26466#L456-30 assume !(1 == ~t2_pc~0); 26462#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 26460#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26458#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26456#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26454#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26452#L475-30 assume 1 == ~t3_pc~0; 26448#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26446#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26444#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26442#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26440#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26438#L494-30 assume !(1 == ~t4_pc~0); 26434#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 26432#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26430#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26428#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26426#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26424#L513-30 assume 1 == ~t5_pc~0; 26420#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26418#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26416#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26414#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26412#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26410#L532-30 assume !(1 == ~t6_pc~0); 26406#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 26404#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26402#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26400#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26398#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26397#L551-30 assume 1 == ~t7_pc~0; 26392#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26390#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26388#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26387#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 26386#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26385#L570-30 assume !(1 == ~t8_pc~0); 26384#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 26382#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26381#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26380#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26379#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26378#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24608#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26377#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26376#L962-3 assume !(1 == ~T3_E~0); 26374#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26373#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25120#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26369#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26367#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26365#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26363#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26361#L1002-3 assume !(1 == ~E_2~0); 24873#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24874#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25698#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25692#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25686#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25680#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25677#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25667#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25654#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25648#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25642#L1322 assume !(0 == start_simulation_~tmp~3#1); 24930#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25346#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25315#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 25253#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25236#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25224#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25215#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 25207#L1303-2 [2024-10-31 22:04:34,767 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:34,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2024-10-31 22:04:34,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:34,768 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849699995] [2024-10-31 22:04:34,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:34,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:34,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:34,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:34,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:34,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849699995] [2024-10-31 22:04:34,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [849699995] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:34,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:34,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:04:34,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [617576741] [2024-10-31 22:04:34,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:34,900 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:34,900 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:34,901 INFO L85 PathProgramCache]: Analyzing trace with hash 1462023267, now seen corresponding path program 1 times [2024-10-31 22:04:34,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:34,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633703772] [2024-10-31 22:04:34,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:34,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:34,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:34,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:34,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:34,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633703772] [2024-10-31 22:04:34,962 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [633703772] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:34,962 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:34,962 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:34,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787322370] [2024-10-31 22:04:34,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:34,963 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:34,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:34,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:04:34,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:04:34,964 INFO L87 Difference]: Start difference. First operand 3320 states and 4882 transitions. cyclomatic complexity: 1566 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:35,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:35,281 INFO L93 Difference]: Finished difference Result 3440 states and 5002 transitions. [2024-10-31 22:04:35,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3440 states and 5002 transitions. [2024-10-31 22:04:35,299 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3286 [2024-10-31 22:04:35,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3440 states to 3440 states and 5002 transitions. [2024-10-31 22:04:35,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3440 [2024-10-31 22:04:35,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3440 [2024-10-31 22:04:35,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3440 states and 5002 transitions. [2024-10-31 22:04:35,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:35,325 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2024-10-31 22:04:35,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3440 states and 5002 transitions. [2024-10-31 22:04:35,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3440 to 3440. [2024-10-31 22:04:35,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3440 states, 3440 states have (on average 1.4540697674418606) internal successors, (5002), 3439 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:35,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3440 states to 3440 states and 5002 transitions. [2024-10-31 22:04:35,399 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2024-10-31 22:04:35,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:04:35,400 INFO L425 stractBuchiCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2024-10-31 22:04:35,400 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:04:35,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3440 states and 5002 transitions. [2024-10-31 22:04:35,413 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3286 [2024-10-31 22:04:35,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:35,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:35,415 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:35,416 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:35,416 INFO L745 eck$LassoCheckResult]: Stem: 31188#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 31189#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 31880#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31881#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31937#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 31624#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31625#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31205#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31206#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31138#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31139#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31410#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31382#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31383#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31678#L854 assume !(0 == ~M_E~0); 31476#L854-2 assume !(0 == ~T1_E~0); 31477#L859-1 assume !(0 == ~T2_E~0); 31017#L864-1 assume !(0 == ~T3_E~0); 31018#L869-1 assume !(0 == ~T4_E~0); 31129#L874-1 assume !(0 == ~T5_E~0); 31919#L879-1 assume !(0 == ~T6_E~0); 31466#L884-1 assume !(0 == ~T7_E~0); 30878#L889-1 assume !(0 == ~T8_E~0); 30879#L894-1 assume !(0 == ~E_M~0); 31220#L899-1 assume !(0 == ~E_1~0); 31684#L904-1 assume !(0 == ~E_2~0); 31400#L909-1 assume !(0 == ~E_3~0); 31401#L914-1 assume !(0 == ~E_4~0); 31615#L919-1 assume !(0 == ~E_5~0); 31303#L924-1 assume !(0 == ~E_6~0); 31111#L929-1 assume !(0 == ~E_7~0); 31112#L934-1 assume !(0 == ~E_8~0); 31379#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30896#L418 assume !(1 == ~m_pc~0); 30870#L418-2 is_master_triggered_~__retres1~0#1 := 0; 31946#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31974#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31794#L1061 assume !(0 != activate_threads_~tmp~1#1); 31710#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31711#L437 assume 1 == ~t1_pc~0; 31943#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31801#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30919#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30920#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 31251#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31782#L456 assume !(1 == ~t2_pc~0); 31169#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31168#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31337#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31338#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 31515#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31011#L475 assume 1 == ~t3_pc~0; 31012#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31076#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30887#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30888#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 31254#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31255#L494 assume !(1 == ~t4_pc~0); 31297#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31298#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31028#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 31639#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31071#L513 assume 1 == ~t5_pc~0; 31072#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31299#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31812#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31024#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 31025#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30977#L532 assume !(1 == ~t6_pc~0); 30978#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31130#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31319#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31320#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 31226#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31227#L551 assume 1 == ~t7_pc~0; 31830#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31641#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31642#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31959#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 31963#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31423#L570 assume 1 == ~t8_pc~0; 31424#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31542#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31753#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31538#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 31005#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31006#L952 assume !(1 == ~M_E~0); 31805#L952-2 assume !(1 == ~T1_E~0); 32128#L957-1 assume !(1 == ~T2_E~0); 32127#L962-1 assume !(1 == ~T3_E~0); 32126#L967-1 assume !(1 == ~T4_E~0); 32124#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32125#L977-1 assume !(1 == ~T6_E~0); 32161#L982-1 assume !(1 == ~T7_E~0); 32160#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32159#L992-1 assume !(1 == ~E_M~0); 32158#L997-1 assume !(1 == ~E_1~0); 32156#L1002-1 assume !(1 == ~E_2~0); 32154#L1007-1 assume !(1 == ~E_3~0); 32113#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 32089#L1017-1 assume !(1 == ~E_5~0); 32087#L1022-1 assume !(1 == ~E_6~0); 32055#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 32040#L1032-1 assume !(1 == ~E_8~0); 32031#L1037-1 assume { :end_inline_reset_delta_events } true; 32024#L1303-2 [2024-10-31 22:04:35,416 INFO L747 eck$LassoCheckResult]: Loop: 32024#L1303-2 assume !false; 32018#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32014#L829-1 assume !false; 32013#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32008#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32003#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32002#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 32000#L712 assume !(0 != eval_~tmp~0#1); 31999#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31998#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31996#L854-3 assume !(0 == ~M_E~0); 31997#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33624#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33615#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33612#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33609#L874-3 assume !(0 == ~T5_E~0); 33606#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33603#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33600#L889-3 assume !(0 == ~T8_E~0); 33596#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33593#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33590#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33585#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33581#L914-3 assume !(0 == ~E_4~0); 33577#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33572#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33567#L929-3 assume !(0 == ~E_7~0); 33562#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33555#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33549#L418-30 assume 1 == ~m_pc~0; 33543#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33534#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33525#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33519#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33514#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33503#L437-30 assume 1 == ~t1_pc~0; 33494#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33488#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33482#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33477#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33472#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33467#L456-30 assume !(1 == ~t2_pc~0); 33459#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 33453#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33447#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33442#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33420#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33417#L475-30 assume 1 == ~t3_pc~0; 33414#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33412#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33410#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33408#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33406#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33405#L494-30 assume !(1 == ~t4_pc~0); 33403#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 33400#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33398#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33396#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33394#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33392#L513-30 assume 1 == ~t5_pc~0; 33389#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33354#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33351#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33349#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33348#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33346#L532-30 assume 1 == ~t6_pc~0; 33344#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33333#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33325#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33318#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33316#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33314#L551-30 assume 1 == ~t7_pc~0; 33305#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33298#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33243#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33241#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 33239#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33237#L570-30 assume 1 == ~t8_pc~0; 33211#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33206#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33202#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33196#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33192#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33188#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31375#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33181#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33177#L962-3 assume !(1 == ~T3_E~0); 33171#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33167#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31913#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33159#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33155#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33152#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33148#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32872#L1002-3 assume !(1 == ~E_2~0); 32870#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32645#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32641#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32639#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32548#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32500#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32497#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32173#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32164#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32163#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 32162#L1322 assume !(0 == start_simulation_~tmp~3#1); 31700#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32094#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32088#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32086#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 32057#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32056#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32041#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 32032#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 32024#L1303-2 [2024-10-31 22:04:35,417 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:35,417 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2024-10-31 22:04:35,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:35,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153704442] [2024-10-31 22:04:35,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:35,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:35,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:35,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:35,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:35,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153704442] [2024-10-31 22:04:35,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [153704442] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:35,482 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:35,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:35,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449192298] [2024-10-31 22:04:35,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:35,483 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:35,483 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:35,483 INFO L85 PathProgramCache]: Analyzing trace with hash -1131440031, now seen corresponding path program 1 times [2024-10-31 22:04:35,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:35,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930391915] [2024-10-31 22:04:35,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:35,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:35,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:35,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:35,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:35,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930391915] [2024-10-31 22:04:35,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930391915] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:35,544 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:35,544 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:35,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255677538] [2024-10-31 22:04:35,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:35,545 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:35,545 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:35,545 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:35,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:35,545 INFO L87 Difference]: Start difference. First operand 3440 states and 5002 transitions. cyclomatic complexity: 1566 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:35,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:35,732 INFO L93 Difference]: Finished difference Result 6414 states and 9260 transitions. [2024-10-31 22:04:35,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6414 states and 9260 transitions. [2024-10-31 22:04:35,763 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6253 [2024-10-31 22:04:35,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6414 states to 6414 states and 9260 transitions. [2024-10-31 22:04:35,800 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6414 [2024-10-31 22:04:35,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6414 [2024-10-31 22:04:35,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6414 states and 9260 transitions. [2024-10-31 22:04:35,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:35,815 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6414 states and 9260 transitions. [2024-10-31 22:04:35,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6414 states and 9260 transitions. [2024-10-31 22:04:35,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6414 to 6406. [2024-10-31 22:04:35,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6406 states, 6406 states have (on average 1.444270995941305) internal successors, (9252), 6405 states have internal predecessors, (9252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:35,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6406 states to 6406 states and 9252 transitions. [2024-10-31 22:04:35,966 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6406 states and 9252 transitions. [2024-10-31 22:04:35,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:35,967 INFO L425 stractBuchiCegarLoop]: Abstraction has 6406 states and 9252 transitions. [2024-10-31 22:04:35,967 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:04:35,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6406 states and 9252 transitions. [2024-10-31 22:04:35,995 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6245 [2024-10-31 22:04:35,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:35,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:35,997 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:35,997 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:35,998 INFO L745 eck$LassoCheckResult]: Stem: 41050#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 41051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 41818#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41819#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41899#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 41515#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41516#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41067#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41068#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40997#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40998#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41277#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41245#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41246#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41592#L854 assume !(0 == ~M_E~0); 41351#L854-2 assume !(0 == ~T1_E~0); 41352#L859-1 assume !(0 == ~T2_E~0); 40876#L864-1 assume !(0 == ~T3_E~0); 40877#L869-1 assume !(0 == ~T4_E~0); 40988#L874-1 assume !(0 == ~T5_E~0); 41874#L879-1 assume !(0 == ~T6_E~0); 41340#L884-1 assume !(0 == ~T7_E~0); 40739#L889-1 assume !(0 == ~T8_E~0); 40740#L894-1 assume !(0 == ~E_M~0); 41081#L899-1 assume !(0 == ~E_1~0); 41598#L904-1 assume !(0 == ~E_2~0); 41266#L909-1 assume !(0 == ~E_3~0); 41267#L914-1 assume !(0 == ~E_4~0); 41503#L919-1 assume !(0 == ~E_5~0); 41164#L924-1 assume !(0 == ~E_6~0); 40970#L929-1 assume !(0 == ~E_7~0); 40971#L934-1 assume !(0 == ~E_8~0); 41242#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40756#L418 assume !(1 == ~m_pc~0); 40731#L418-2 is_master_triggered_~__retres1~0#1 := 0; 41797#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41741#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41722#L1061 assume !(0 != activate_threads_~tmp~1#1); 41626#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41627#L437 assume !(1 == ~t1_pc~0); 41858#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41730#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40779#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40780#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 41112#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41710#L456 assume !(1 == ~t2_pc~0); 41029#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41028#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41199#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41200#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 41392#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40870#L475 assume 1 == ~t3_pc~0; 40871#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40935#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40747#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40748#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 41115#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41116#L494 assume !(1 == ~t4_pc~0); 41159#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41160#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40886#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40887#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 41531#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40929#L513 assume 1 == ~t5_pc~0; 40930#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41161#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41744#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40883#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 40884#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40836#L532 assume !(1 == ~t6_pc~0); 40837#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40989#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41181#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41182#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 41087#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41088#L551 assume 1 == ~t7_pc~0; 41760#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41536#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41537#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41924#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 41931#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41292#L570 assume 1 == ~t8_pc~0; 41293#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41421#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41674#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41416#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 40864#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40865#L952 assume !(1 == ~M_E~0); 41734#L952-2 assume !(1 == ~T1_E~0); 41687#L957-1 assume !(1 == ~T2_E~0); 41688#L962-1 assume !(1 == ~T3_E~0); 41435#L967-1 assume !(1 == ~T4_E~0); 41436#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44301#L977-1 assume !(1 == ~T6_E~0); 44300#L982-1 assume !(1 == ~T7_E~0); 44299#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44298#L992-1 assume !(1 == ~E_M~0); 44296#L997-1 assume !(1 == ~E_1~0); 44294#L1002-1 assume !(1 == ~E_2~0); 44292#L1007-1 assume !(1 == ~E_3~0); 44267#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40742#L1017-1 assume !(1 == ~E_5~0); 46412#L1022-1 assume !(1 == ~E_6~0); 46411#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46410#L1032-1 assume !(1 == ~E_8~0); 46408#L1037-1 assume { :end_inline_reset_delta_events } true; 46407#L1303-2 [2024-10-31 22:04:35,998 INFO L747 eck$LassoCheckResult]: Loop: 46407#L1303-2 assume !false; 42391#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41262#L829-1 assume !false; 42387#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 42388#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 42250#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 42251#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42242#L712 assume !(0 != eval_~tmp~0#1); 42244#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41414#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41415#L854-3 assume !(0 == ~M_E~0); 41523#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41524#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41918#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41870#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41312#L874-3 assume !(0 == ~T5_E~0); 41313#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44649#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44618#L889-3 assume !(0 == ~T8_E~0); 44608#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44607#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44606#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44605#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44604#L914-3 assume !(0 == ~E_4~0); 44603#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44602#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44601#L929-3 assume !(0 == ~E_7~0); 44600#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44599#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44598#L418-30 assume !(1 == ~m_pc~0); 44596#L418-32 is_master_triggered_~__retres1~0#1 := 0; 44594#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44592#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44591#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 44589#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44588#L437-30 assume !(1 == ~t1_pc~0); 44587#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 44586#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44585#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44584#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44583#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44582#L456-30 assume !(1 == ~t2_pc~0); 44580#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 44579#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44578#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44577#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44576#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44575#L475-30 assume 1 == ~t3_pc~0; 44573#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44572#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44571#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44570#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44569#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44568#L494-30 assume !(1 == ~t4_pc~0); 44566#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 44565#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44564#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44563#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44562#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44561#L513-30 assume !(1 == ~t5_pc~0); 44560#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 44558#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44557#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44556#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44555#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44554#L532-30 assume !(1 == ~t6_pc~0); 44552#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 44551#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44550#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44549#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44548#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44547#L551-30 assume 1 == ~t7_pc~0; 44545#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44544#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44543#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44542#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 44541#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44538#L570-30 assume 1 == ~t8_pc~0; 44539#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47001#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47000#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46999#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46998#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46997#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41238#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46996#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46995#L962-3 assume !(1 == ~T3_E~0); 46994#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46993#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41862#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46992#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46991#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46990#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46989#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46988#L1002-3 assume !(1 == ~E_2~0); 46987#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46986#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44427#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46985#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46984#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46983#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42585#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 42586#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 46974#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 46973#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 46972#L1322 assume !(0 == start_simulation_~tmp~3#1); 42429#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 46967#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 46962#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 46961#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 46960#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46959#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46958#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 46409#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 46407#L1303-2 [2024-10-31 22:04:35,999 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:35,999 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2024-10-31 22:04:35,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:35,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578932895] [2024-10-31 22:04:35,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:36,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:36,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:36,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:36,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:36,084 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578932895] [2024-10-31 22:04:36,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1578932895] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:36,084 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:36,084 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:36,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364467967] [2024-10-31 22:04:36,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:36,085 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:36,086 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:36,086 INFO L85 PathProgramCache]: Analyzing trace with hash 311550055, now seen corresponding path program 1 times [2024-10-31 22:04:36,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:36,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49478359] [2024-10-31 22:04:36,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:36,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:36,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:36,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:36,145 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:36,145 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [49478359] [2024-10-31 22:04:36,145 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [49478359] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:36,146 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:36,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:36,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2089611962] [2024-10-31 22:04:36,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:36,146 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:36,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:36,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:36,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:36,147 INFO L87 Difference]: Start difference. First operand 6406 states and 9252 transitions. cyclomatic complexity: 2854 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:36,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:36,352 INFO L93 Difference]: Finished difference Result 12302 states and 17640 transitions. [2024-10-31 22:04:36,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12302 states and 17640 transitions. [2024-10-31 22:04:36,411 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12126 [2024-10-31 22:04:36,456 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12302 states to 12302 states and 17640 transitions. [2024-10-31 22:04:36,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12302 [2024-10-31 22:04:36,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12302 [2024-10-31 22:04:36,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12302 states and 17640 transitions. [2024-10-31 22:04:36,483 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:36,483 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12302 states and 17640 transitions. [2024-10-31 22:04:36,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12302 states and 17640 transitions. [2024-10-31 22:04:36,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12302 to 12286. [2024-10-31 22:04:36,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12286 states, 12286 states have (on average 1.434478267947257) internal successors, (17624), 12285 states have internal predecessors, (17624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:36,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12286 states to 12286 states and 17624 transitions. [2024-10-31 22:04:36,862 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12286 states and 17624 transitions. [2024-10-31 22:04:36,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:36,864 INFO L425 stractBuchiCegarLoop]: Abstraction has 12286 states and 17624 transitions. [2024-10-31 22:04:36,864 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:04:36,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12286 states and 17624 transitions. [2024-10-31 22:04:36,920 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12110 [2024-10-31 22:04:36,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:36,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:36,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:36,923 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:36,923 INFO L745 eck$LassoCheckResult]: Stem: 59764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 59765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 60471#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60472#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60547#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 60212#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60213#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59780#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59781#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59711#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59712#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59983#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59954#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59955#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60272#L854 assume !(0 == ~M_E~0); 60051#L854-2 assume !(0 == ~T1_E~0); 60052#L859-1 assume !(0 == ~T2_E~0); 59589#L864-1 assume !(0 == ~T3_E~0); 59590#L869-1 assume !(0 == ~T4_E~0); 59702#L874-1 assume !(0 == ~T5_E~0); 60520#L879-1 assume !(0 == ~T6_E~0); 60041#L884-1 assume !(0 == ~T7_E~0); 59454#L889-1 assume !(0 == ~T8_E~0); 59455#L894-1 assume !(0 == ~E_M~0); 59793#L899-1 assume !(0 == ~E_1~0); 60278#L904-1 assume !(0 == ~E_2~0); 59973#L909-1 assume !(0 == ~E_3~0); 59974#L914-1 assume !(0 == ~E_4~0); 60201#L919-1 assume !(0 == ~E_5~0); 59875#L924-1 assume !(0 == ~E_6~0); 59684#L929-1 assume !(0 == ~E_7~0); 59685#L934-1 assume !(0 == ~E_8~0); 59951#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59471#L418 assume !(1 == ~m_pc~0); 59446#L418-2 is_master_triggered_~__retres1~0#1 := 0; 60557#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60593#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60390#L1061 assume !(0 != activate_threads_~tmp~1#1); 60302#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60303#L437 assume !(1 == ~t1_pc~0); 60507#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60398#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59494#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59495#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 59822#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60380#L456 assume !(1 == ~t2_pc~0); 59742#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59741#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59909#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59910#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 60090#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59584#L475 assume !(1 == ~t3_pc~0); 59585#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59648#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59462#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59463#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 59825#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59826#L494 assume !(1 == ~t4_pc~0); 59869#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59870#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59599#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59600#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 60227#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59642#L513 assume 1 == ~t5_pc~0; 59643#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59871#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60410#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59596#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 59597#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59550#L532 assume !(1 == ~t6_pc~0); 59551#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 59703#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59890#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59891#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 59797#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59798#L551 assume 1 == ~t7_pc~0; 60428#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 60229#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60230#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60572#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 60577#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59994#L570 assume 1 == ~t8_pc~0; 59995#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60119#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60348#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60114#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 59578#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59579#L952 assume !(1 == ~M_E~0); 59519#L952-2 assume !(1 == ~T1_E~0); 59520#L957-1 assume !(1 == ~T2_E~0); 60356#L962-1 assume !(1 == ~T3_E~0); 63708#L967-1 assume !(1 == ~T4_E~0); 63705#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63703#L977-1 assume !(1 == ~T6_E~0); 63701#L982-1 assume !(1 == ~T7_E~0); 63699#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63697#L992-1 assume !(1 == ~E_M~0); 63694#L997-1 assume !(1 == ~E_1~0); 63692#L1002-1 assume !(1 == ~E_2~0); 63690#L1007-1 assume !(1 == ~E_3~0); 63688#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 59457#L1017-1 assume !(1 == ~E_5~0); 60075#L1022-1 assume !(1 == ~E_6~0); 60076#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 60103#L1032-1 assume !(1 == ~E_8~0); 63053#L1037-1 assume { :end_inline_reset_delta_events } true; 63051#L1303-2 [2024-10-31 22:04:36,924 INFO L747 eck$LassoCheckResult]: Loop: 63051#L1303-2 assume !false; 63049#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63044#L829-1 assume !false; 63042#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 63012#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 62972#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 62934#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 62865#L712 assume !(0 != eval_~tmp~0#1); 62866#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67046#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67043#L854-3 assume !(0 == ~M_E~0); 67041#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67039#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67037#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67035#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67033#L874-3 assume !(0 == ~T5_E~0); 67031#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67029#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67027#L889-3 assume !(0 == ~T8_E~0); 67024#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 67022#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67020#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67018#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67016#L914-3 assume !(0 == ~E_4~0); 67014#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66861#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 66748#L929-3 assume !(0 == ~E_7~0); 66747#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66746#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66745#L418-30 assume !(1 == ~m_pc~0); 66743#L418-32 is_master_triggered_~__retres1~0#1 := 0; 66741#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66739#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66738#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 66736#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66735#L437-30 assume !(1 == ~t1_pc~0); 66734#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 66733#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66732#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66731#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66730#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66729#L456-30 assume !(1 == ~t2_pc~0); 66727#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 66726#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66725#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 66723#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66721#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66720#L475-30 assume !(1 == ~t3_pc~0); 66719#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 66718#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66717#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 66716#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66715#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66714#L494-30 assume !(1 == ~t4_pc~0); 66711#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 66710#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66709#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66708#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66707#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66703#L513-30 assume !(1 == ~t5_pc~0); 66701#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 66698#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66696#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66693#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 66691#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66689#L532-30 assume 1 == ~t6_pc~0; 66687#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66684#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66682#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66680#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66678#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66676#L551-30 assume !(1 == ~t7_pc~0); 66673#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 66670#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66668#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66666#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 66664#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66662#L570-30 assume 1 == ~t8_pc~0; 66659#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 66657#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66655#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66653#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66651#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66649#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64912#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66645#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66643#L962-3 assume !(1 == ~T3_E~0); 66641#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66639#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66271#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66635#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 66633#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66631#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66629#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66627#L1002-3 assume !(1 == ~E_2~0); 66625#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66622#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64880#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66619#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 66617#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66615#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 66613#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 63150#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 63139#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 63137#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 63135#L1322 assume !(0 == start_simulation_~tmp~3#1); 60292#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 63070#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 63064#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 63062#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 63060#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63058#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63056#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 63054#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 63051#L1303-2 [2024-10-31 22:04:36,925 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:36,925 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2024-10-31 22:04:36,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:36,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449813738] [2024-10-31 22:04:36,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:36,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:36,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:37,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:37,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:37,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449813738] [2024-10-31 22:04:37,018 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1449813738] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:37,018 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:37,018 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:37,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992931298] [2024-10-31 22:04:37,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:37,019 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:37,020 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:37,022 INFO L85 PathProgramCache]: Analyzing trace with hash -1415595992, now seen corresponding path program 1 times [2024-10-31 22:04:37,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:37,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510742820] [2024-10-31 22:04:37,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:37,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:37,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:37,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:37,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:37,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510742820] [2024-10-31 22:04:37,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [510742820] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:37,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:37,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:37,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [162454646] [2024-10-31 22:04:37,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:37,109 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:37,109 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:37,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:37,110 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:37,111 INFO L87 Difference]: Start difference. First operand 12286 states and 17624 transitions. cyclomatic complexity: 5354 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:37,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:37,367 INFO L93 Difference]: Finished difference Result 23203 states and 33115 transitions. [2024-10-31 22:04:37,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23203 states and 33115 transitions. [2024-10-31 22:04:37,628 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22972 [2024-10-31 22:04:37,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23203 states to 23203 states and 33115 transitions. [2024-10-31 22:04:37,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23203 [2024-10-31 22:04:37,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23203 [2024-10-31 22:04:37,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23203 states and 33115 transitions. [2024-10-31 22:04:37,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:37,825 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23203 states and 33115 transitions. [2024-10-31 22:04:37,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23203 states and 33115 transitions. [2024-10-31 22:04:38,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23203 to 23171. [2024-10-31 22:04:38,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23171 states, 23171 states have (on average 1.4277760994346382) internal successors, (33083), 23170 states have internal predecessors, (33083), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:38,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23171 states to 23171 states and 33083 transitions. [2024-10-31 22:04:38,275 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23171 states and 33083 transitions. [2024-10-31 22:04:38,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:38,276 INFO L425 stractBuchiCegarLoop]: Abstraction has 23171 states and 33083 transitions. [2024-10-31 22:04:38,276 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:04:38,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23171 states and 33083 transitions. [2024-10-31 22:04:38,435 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22940 [2024-10-31 22:04:38,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:38,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:38,437 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:38,440 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:38,442 INFO L745 eck$LassoCheckResult]: Stem: 95260#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 95261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 96025#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96026#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96098#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 95726#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95727#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95277#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95278#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95210#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95211#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95489#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95460#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95461#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95796#L854 assume !(0 == ~M_E~0); 95557#L854-2 assume !(0 == ~T1_E~0); 95558#L859-1 assume !(0 == ~T2_E~0); 95087#L864-1 assume !(0 == ~T3_E~0); 95088#L869-1 assume !(0 == ~T4_E~0); 95201#L874-1 assume !(0 == ~T5_E~0); 96076#L879-1 assume !(0 == ~T6_E~0); 95547#L884-1 assume !(0 == ~T7_E~0); 94949#L889-1 assume !(0 == ~T8_E~0); 94950#L894-1 assume !(0 == ~E_M~0); 95294#L899-1 assume !(0 == ~E_1~0); 95803#L904-1 assume !(0 == ~E_2~0); 95478#L909-1 assume !(0 == ~E_3~0); 95479#L914-1 assume !(0 == ~E_4~0); 95715#L919-1 assume !(0 == ~E_5~0); 95378#L924-1 assume !(0 == ~E_6~0); 95181#L929-1 assume !(0 == ~E_7~0); 95182#L934-1 assume !(0 == ~E_8~0); 95457#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94967#L418 assume !(1 == ~m_pc~0); 94941#L418-2 is_master_triggered_~__retres1~0#1 := 0; 96002#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96003#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95929#L1061 assume !(0 != activate_threads_~tmp~1#1); 95829#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95830#L437 assume !(1 == ~t1_pc~0); 96064#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95938#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94990#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94991#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 95326#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95917#L456 assume !(1 == ~t2_pc~0); 95242#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95241#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95413#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95414#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 95600#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95082#L475 assume !(1 == ~t3_pc~0); 95083#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95146#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94958#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94959#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 95329#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95330#L494 assume !(1 == ~t4_pc~0); 95371#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 95372#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95097#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95098#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 95746#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95141#L513 assume !(1 == ~t5_pc~0); 95142#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 95373#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95950#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95094#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 95095#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95048#L532 assume !(1 == ~t6_pc~0); 95049#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95202#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95393#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95394#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 95298#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95299#L551 assume 1 == ~t7_pc~0; 95965#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95749#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95750#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96125#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 96131#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95501#L570 assume 1 == ~t8_pc~0; 95502#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 95631#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 95882#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95627#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 95076#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95077#L952 assume !(1 == ~M_E~0); 95017#L952-2 assume !(1 == ~T1_E~0); 95018#L957-1 assume !(1 == ~T2_E~0); 96110#L962-1 assume !(1 == ~T3_E~0); 95651#L967-1 assume !(1 == ~T4_E~0); 95652#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98315#L977-1 assume !(1 == ~T6_E~0); 96133#L982-1 assume !(1 == ~T7_E~0); 95204#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 95205#L992-1 assume !(1 == ~E_M~0); 98029#L997-1 assume !(1 == ~E_1~0); 98027#L1002-1 assume !(1 == ~E_2~0); 98025#L1007-1 assume !(1 == ~E_3~0); 98001#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 97880#L1017-1 assume !(1 == ~E_5~0); 97878#L1022-1 assume !(1 == ~E_6~0); 97855#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 97671#L1032-1 assume !(1 == ~E_8~0); 97521#L1037-1 assume { :end_inline_reset_delta_events } true; 97520#L1303-2 [2024-10-31 22:04:38,443 INFO L747 eck$LassoCheckResult]: Loop: 97520#L1303-2 assume !false; 97519#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97514#L829-1 assume !false; 97511#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 97444#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 97433#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 97426#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 97416#L712 assume !(0 != eval_~tmp~0#1); 97417#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98284#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98282#L854-3 assume !(0 == ~M_E~0); 98281#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 98280#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98278#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 98275#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98273#L874-3 assume !(0 == ~T5_E~0); 98271#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 98268#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 98266#L889-3 assume !(0 == ~T8_E~0); 98264#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 98262#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 98260#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 98258#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98256#L914-3 assume !(0 == ~E_4~0); 98254#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 98252#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 98249#L929-3 assume !(0 == ~E_7~0); 98247#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 98245#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 98243#L418-30 assume !(1 == ~m_pc~0); 98241#L418-32 is_master_triggered_~__retres1~0#1 := 0; 98226#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98223#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 98221#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 98218#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98216#L437-30 assume !(1 == ~t1_pc~0); 98214#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 98212#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98210#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98208#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 98206#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98204#L456-30 assume !(1 == ~t2_pc~0); 98201#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 98199#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98196#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 98194#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98192#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98190#L475-30 assume !(1 == ~t3_pc~0); 98188#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 98187#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98186#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 98185#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 98184#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98182#L494-30 assume !(1 == ~t4_pc~0); 98179#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 98178#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98177#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 98175#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 98172#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98170#L513-30 assume !(1 == ~t5_pc~0); 98168#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 98165#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98163#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 98161#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98159#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98157#L532-30 assume 1 == ~t6_pc~0; 98155#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 98152#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 98150#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 98149#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 98147#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 98145#L551-30 assume !(1 == ~t7_pc~0); 98144#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 98140#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 98138#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98136#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 98134#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 98132#L570-30 assume 1 == ~t8_pc~0; 98123#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 98121#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98119#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 98117#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 98115#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98113#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 98086#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98108#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98106#L962-3 assume !(1 == ~T3_E~0); 98104#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98103#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98099#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98097#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 98095#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 98093#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98091#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 98000#L1002-3 assume !(1 == ~E_2~0); 97997#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97995#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97991#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97990#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 97978#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 97972#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 97966#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 97725#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 97716#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 97715#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 97714#L1322 assume !(0 == start_simulation_~tmp~3#1); 97711#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 97541#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 97535#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 97534#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 97531#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97530#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97526#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 97522#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 97520#L1303-2 [2024-10-31 22:04:38,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:38,444 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2024-10-31 22:04:38,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:38,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970322307] [2024-10-31 22:04:38,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:38,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:38,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:38,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:38,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:38,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970322307] [2024-10-31 22:04:38,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970322307] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:38,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:38,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:38,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095214561] [2024-10-31 22:04:38,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:38,551 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:38,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:38,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1415595992, now seen corresponding path program 2 times [2024-10-31 22:04:38,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:38,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113991064] [2024-10-31 22:04:38,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:38,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:38,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:38,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:38,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:38,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113991064] [2024-10-31 22:04:38,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113991064] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:38,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:38,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:38,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144484279] [2024-10-31 22:04:38,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:38,628 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:38,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:38,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:38,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:38,629 INFO L87 Difference]: Start difference. First operand 23171 states and 33083 transitions. cyclomatic complexity: 9944 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:39,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:39,232 INFO L93 Difference]: Finished difference Result 54194 states and 76824 transitions. [2024-10-31 22:04:39,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54194 states and 76824 transitions. [2024-10-31 22:04:39,483 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 53740 [2024-10-31 22:04:39,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54194 states to 54194 states and 76824 transitions. [2024-10-31 22:04:39,807 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54194 [2024-10-31 22:04:39,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54194 [2024-10-31 22:04:39,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54194 states and 76824 transitions. [2024-10-31 22:04:39,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:39,911 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54194 states and 76824 transitions. [2024-10-31 22:04:39,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54194 states and 76824 transitions. [2024-10-31 22:04:40,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54194 to 43726. [2024-10-31 22:04:40,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43726 states, 43726 states have (on average 1.4220372318529022) internal successors, (62180), 43725 states have internal predecessors, (62180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:40,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43726 states to 43726 states and 62180 transitions. [2024-10-31 22:04:40,955 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43726 states and 62180 transitions. [2024-10-31 22:04:40,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:40,956 INFO L425 stractBuchiCegarLoop]: Abstraction has 43726 states and 62180 transitions. [2024-10-31 22:04:40,956 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 22:04:40,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43726 states and 62180 transitions. [2024-10-31 22:04:41,148 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43416 [2024-10-31 22:04:41,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:41,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:41,151 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:41,151 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:41,152 INFO L745 eck$LassoCheckResult]: Stem: 172636#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 172637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 173425#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 173426#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 173527#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 173119#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173120#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172661#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172662#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 172585#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 172586#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 172878#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 172847#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 172848#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 173185#L854 assume !(0 == ~M_E~0); 172953#L854-2 assume !(0 == ~T1_E~0); 172954#L859-1 assume !(0 == ~T2_E~0); 172462#L864-1 assume !(0 == ~T3_E~0); 172463#L869-1 assume !(0 == ~T4_E~0); 172574#L874-1 assume !(0 == ~T5_E~0); 173487#L879-1 assume !(0 == ~T6_E~0); 172938#L884-1 assume !(0 == ~T7_E~0); 172324#L889-1 assume !(0 == ~T8_E~0); 172325#L894-1 assume !(0 == ~E_M~0); 172674#L899-1 assume !(0 == ~E_1~0); 173191#L904-1 assume !(0 == ~E_2~0); 172870#L909-1 assume !(0 == ~E_3~0); 172871#L914-1 assume !(0 == ~E_4~0); 173107#L919-1 assume !(0 == ~E_5~0); 172761#L924-1 assume !(0 == ~E_6~0); 172560#L929-1 assume !(0 == ~E_7~0); 172561#L934-1 assume !(0 == ~E_8~0); 172846#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172342#L418 assume !(1 == ~m_pc~0); 172316#L418-2 is_master_triggered_~__retres1~0#1 := 0; 173541#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173610#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 173323#L1061 assume !(0 != activate_threads_~tmp~1#1); 173218#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173219#L437 assume !(1 == ~t1_pc~0); 173470#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 173330#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 172367#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 172368#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 172705#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 173314#L456 assume !(1 == ~t2_pc~0); 172620#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 172619#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172797#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 172798#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 172990#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 172457#L475 assume !(1 == ~t3_pc~0); 172458#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 172523#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172333#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 172334#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 172708#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172709#L494 assume !(1 == ~t4_pc~0); 172755#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 172756#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172472#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 172473#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 173136#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172519#L513 assume !(1 == ~t5_pc~0); 172520#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 172760#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 173341#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 172469#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 172470#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 172423#L532 assume !(1 == ~t6_pc~0); 172424#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 172575#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 172778#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 172779#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 172678#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 172679#L551 assume !(1 == ~t7_pc~0); 173192#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 173140#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173141#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173563#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 173573#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 172893#L570 assume 1 == ~t8_pc~0; 172894#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 173019#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 173274#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173017#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 172455#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172456#L952 assume !(1 == ~M_E~0); 173335#L952-2 assume !(1 == ~T1_E~0); 173289#L957-1 assume !(1 == ~T2_E~0); 173290#L962-1 assume !(1 == ~T3_E~0); 173035#L967-1 assume !(1 == ~T4_E~0); 173036#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 173365#L977-1 assume !(1 == ~T6_E~0); 173366#L982-1 assume !(1 == ~T7_E~0); 172577#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 172578#L992-1 assume !(1 == ~E_M~0); 172987#L997-1 assume !(1 == ~E_1~0); 172988#L1002-1 assume !(1 == ~E_2~0); 188157#L1007-1 assume !(1 == ~E_3~0); 187956#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 187955#L1017-1 assume !(1 == ~E_5~0); 187954#L1022-1 assume !(1 == ~E_6~0); 187953#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 187952#L1032-1 assume !(1 == ~E_8~0); 187950#L1037-1 assume { :end_inline_reset_delta_events } true; 187947#L1303-2 [2024-10-31 22:04:41,152 INFO L747 eck$LassoCheckResult]: Loop: 187947#L1303-2 assume !false; 187945#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 187940#L829-1 assume !false; 187938#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 187804#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 187795#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 187790#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 187783#L712 assume !(0 != eval_~tmp~0#1); 187784#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 194478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 194477#L854-3 assume !(0 == ~M_E~0); 194476#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 194475#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 194474#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 194473#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 194472#L874-3 assume !(0 == ~T5_E~0); 194471#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 194470#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 194469#L889-3 assume !(0 == ~T8_E~0); 194468#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 194467#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 194466#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 194465#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 194464#L914-3 assume !(0 == ~E_4~0); 194463#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 194462#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 194461#L929-3 assume !(0 == ~E_7~0); 194460#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 194459#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 194458#L418-30 assume 1 == ~m_pc~0; 194456#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 194454#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 194452#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 194450#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 194449#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 194448#L437-30 assume !(1 == ~t1_pc~0); 194447#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 194446#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 194445#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 194444#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 194443#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194442#L456-30 assume !(1 == ~t2_pc~0); 194440#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 194439#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 194438#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 194437#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 194436#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 194433#L475-30 assume !(1 == ~t3_pc~0); 194431#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 194429#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194427#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 194424#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 194421#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194418#L494-30 assume !(1 == ~t4_pc~0); 194414#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 194412#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 194410#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 194408#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 194406#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 194404#L513-30 assume !(1 == ~t5_pc~0); 194402#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 194400#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 194398#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 194395#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 194393#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 194391#L532-30 assume !(1 == ~t6_pc~0); 194388#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 194386#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 194384#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 194382#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 194380#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 194378#L551-30 assume !(1 == ~t7_pc~0); 182266#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 194375#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 194373#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 194370#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 194368#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 194366#L570-30 assume 1 == ~t8_pc~0; 194363#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 194361#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 194359#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 194357#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 194355#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194353#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 188622#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 194350#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 194348#L962-3 assume !(1 == ~T3_E~0); 194345#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 194343#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 189356#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 194337#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 194333#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 189795#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 189794#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 189790#L1002-3 assume !(1 == ~E_2~0); 189788#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 189785#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 188591#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189780#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 189777#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 189774#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 188502#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 188257#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 188239#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 188231#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 188223#L1322 assume !(0 == start_simulation_~tmp~3#1); 188216#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 188189#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 188175#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 188170#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 188164#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 188159#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 188153#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 187951#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 187947#L1303-2 [2024-10-31 22:04:41,153 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:41,153 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2024-10-31 22:04:41,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:41,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669084597] [2024-10-31 22:04:41,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:41,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:41,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:41,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:41,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:41,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669084597] [2024-10-31 22:04:41,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669084597] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:41,437 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:41,437 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:04:41,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046053502] [2024-10-31 22:04:41,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:41,437 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:41,438 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:41,438 INFO L85 PathProgramCache]: Analyzing trace with hash -1967335258, now seen corresponding path program 1 times [2024-10-31 22:04:41,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:41,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621702202] [2024-10-31 22:04:41,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:41,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:41,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:41,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:41,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:41,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621702202] [2024-10-31 22:04:41,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621702202] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:41,497 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:41,497 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:41,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486848071] [2024-10-31 22:04:41,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:41,498 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:41,498 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:41,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:04:41,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:04:41,499 INFO L87 Difference]: Start difference. First operand 43726 states and 62180 transitions. cyclomatic complexity: 18486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:42,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:42,218 INFO L93 Difference]: Finished difference Result 82565 states and 116953 transitions. [2024-10-31 22:04:42,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82565 states and 116953 transitions. [2024-10-31 22:04:42,823 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 81968 [2024-10-31 22:04:43,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82565 states to 82565 states and 116953 transitions. [2024-10-31 22:04:43,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82565 [2024-10-31 22:04:43,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82565 [2024-10-31 22:04:43,331 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82565 states and 116953 transitions. [2024-10-31 22:04:43,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:43,448 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82565 states and 116953 transitions. [2024-10-31 22:04:43,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82565 states and 116953 transitions. [2024-10-31 22:04:44,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82565 to 82437. [2024-10-31 22:04:44,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82437 states, 82437 states have (on average 1.417142787825855) internal successors, (116825), 82436 states have internal predecessors, (116825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:45,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82437 states to 82437 states and 116825 transitions. [2024-10-31 22:04:45,192 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82437 states and 116825 transitions. [2024-10-31 22:04:45,193 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:04:45,193 INFO L425 stractBuchiCegarLoop]: Abstraction has 82437 states and 116825 transitions. [2024-10-31 22:04:45,193 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-31 22:04:45,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82437 states and 116825 transitions. [2024-10-31 22:04:45,454 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 81840 [2024-10-31 22:04:45,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:45,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:45,456 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:45,456 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:45,457 INFO L745 eck$LassoCheckResult]: Stem: 298931#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 298932#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 299657#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 299658#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 299727#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 299375#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 299376#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 298950#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 298951#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 298880#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 298881#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 299151#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 299122#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 299123#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 299441#L854 assume !(0 == ~M_E~0); 299222#L854-2 assume !(0 == ~T1_E~0); 299223#L859-1 assume !(0 == ~T2_E~0); 298758#L864-1 assume !(0 == ~T3_E~0); 298759#L869-1 assume !(0 == ~T4_E~0); 298869#L874-1 assume !(0 == ~T5_E~0); 299705#L879-1 assume !(0 == ~T6_E~0); 299210#L884-1 assume !(0 == ~T7_E~0); 298622#L889-1 assume !(0 == ~T8_E~0); 298623#L894-1 assume !(0 == ~E_M~0); 298964#L899-1 assume !(0 == ~E_1~0); 299447#L904-1 assume !(0 == ~E_2~0); 299145#L909-1 assume !(0 == ~E_3~0); 299146#L914-1 assume !(0 == ~E_4~0); 299365#L919-1 assume !(0 == ~E_5~0); 299043#L924-1 assume !(0 == ~E_6~0); 298855#L929-1 assume !(0 == ~E_7~0); 298856#L934-1 assume !(0 == ~E_8~0); 299119#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 298639#L418 assume !(1 == ~m_pc~0); 298614#L418-2 is_master_triggered_~__retres1~0#1 := 0; 299640#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 299641#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 299567#L1061 assume !(0 != activate_threads_~tmp~1#1); 299472#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 299473#L437 assume !(1 == ~t1_pc~0); 299692#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 299576#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 298664#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 298665#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 298993#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 299557#L456 assume !(1 == ~t2_pc~0); 298914#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 298913#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 299077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 299078#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 299258#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 298753#L475 assume !(1 == ~t3_pc~0); 298754#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 298818#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 298630#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 298631#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 298996#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 298997#L494 assume !(1 == ~t4_pc~0); 299038#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 299039#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 298768#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 298769#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 299390#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 298811#L513 assume !(1 == ~t5_pc~0); 298812#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 299042#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 299590#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 298765#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 298766#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 298719#L532 assume !(1 == ~t6_pc~0); 298720#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 298870#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 299058#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 299059#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 298966#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 298967#L551 assume !(1 == ~t7_pc~0); 299448#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 299392#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 299393#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 299750#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 299756#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 299165#L570 assume !(1 == ~t8_pc~0); 299166#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 299662#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 299519#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 299284#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 298751#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 298752#L952 assume !(1 == ~M_E~0); 299582#L952-2 assume !(1 == ~T1_E~0); 309933#L957-1 assume !(1 == ~T2_E~0); 309930#L962-1 assume !(1 == ~T3_E~0); 309926#L967-1 assume !(1 == ~T4_E~0); 309921#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 309922#L977-1 assume !(1 == ~T6_E~0); 312358#L982-1 assume !(1 == ~T7_E~0); 312356#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 312354#L992-1 assume !(1 == ~E_M~0); 312352#L997-1 assume !(1 == ~E_1~0); 312350#L1002-1 assume !(1 == ~E_2~0); 312347#L1007-1 assume !(1 == ~E_3~0); 312345#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 298625#L1017-1 assume !(1 == ~E_5~0); 299244#L1022-1 assume !(1 == ~E_6~0); 299245#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 299271#L1032-1 assume !(1 == ~E_8~0); 299425#L1037-1 assume { :end_inline_reset_delta_events } true; 299426#L1303-2 [2024-10-31 22:04:45,457 INFO L747 eck$LassoCheckResult]: Loop: 299426#L1303-2 assume !false; 316764#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 316759#L829-1 assume !false; 316757#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 316745#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 316737#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 316733#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 316728#L712 assume !(0 != eval_~tmp~0#1); 316729#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 317085#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 317084#L854-3 assume !(0 == ~M_E~0); 317083#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 317082#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 317081#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 317080#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 317079#L874-3 assume !(0 == ~T5_E~0); 317078#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 317077#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 317076#L889-3 assume !(0 == ~T8_E~0); 317075#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 317074#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 317073#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 317072#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 317071#L914-3 assume !(0 == ~E_4~0); 317070#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 317069#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 317068#L929-3 assume !(0 == ~E_7~0); 317067#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 317066#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 317065#L418-30 assume 1 == ~m_pc~0; 317063#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 317061#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 317059#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 317057#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 317056#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 317055#L437-30 assume !(1 == ~t1_pc~0); 317054#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 317053#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 317052#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 317051#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 317050#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 317049#L456-30 assume !(1 == ~t2_pc~0); 317047#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 317046#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 317045#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 317044#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 317043#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 317042#L475-30 assume !(1 == ~t3_pc~0); 317041#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 317040#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 317039#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 317038#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 317037#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 317036#L494-30 assume !(1 == ~t4_pc~0); 317034#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 317033#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 317032#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 317031#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 317030#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 317029#L513-30 assume !(1 == ~t5_pc~0); 317027#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 317025#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 317023#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 317021#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 317019#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 317017#L532-30 assume !(1 == ~t6_pc~0); 317012#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 317010#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 317008#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 317006#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 317004#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 317001#L551-30 assume !(1 == ~t7_pc~0); 313101#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 316994#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 316990#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 316986#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 316983#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 316980#L570-30 assume !(1 == ~t8_pc~0); 316978#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 316976#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 316974#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 316972#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 316969#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 316966#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 308446#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 316962#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 316959#L962-3 assume !(1 == ~T3_E~0); 316955#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 316952#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 313766#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 316948#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 316944#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 316941#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 316938#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 316935#L1002-3 assume !(1 == ~E_2~0); 316931#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 316926#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 312305#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 316919#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 316916#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 316914#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 316912#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 316832#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 316820#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 316816#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 316812#L1322 assume !(0 == start_simulation_~tmp~3#1); 316808#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 316800#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 316792#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 316787#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 316783#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 316778#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 316773#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 316770#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 299426#L1303-2 [2024-10-31 22:04:45,457 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:45,457 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2024-10-31 22:04:45,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:45,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070813515] [2024-10-31 22:04:45,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:45,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:45,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:45,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:45,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:45,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070813515] [2024-10-31 22:04:45,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070813515] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:45,549 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:45,549 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:45,549 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579923641] [2024-10-31 22:04:45,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:45,550 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:45,550 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:45,550 INFO L85 PathProgramCache]: Analyzing trace with hash -842075289, now seen corresponding path program 1 times [2024-10-31 22:04:45,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:45,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628301549] [2024-10-31 22:04:45,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:45,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:45,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:45,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:45,604 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:45,604 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628301549] [2024-10-31 22:04:45,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628301549] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:45,605 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:45,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:45,605 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890568980] [2024-10-31 22:04:45,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:45,605 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:45,606 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:45,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:45,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:45,606 INFO L87 Difference]: Start difference. First operand 82437 states and 116825 transitions. cyclomatic complexity: 34452 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:46,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:46,365 INFO L93 Difference]: Finished difference Result 63030 states and 89131 transitions. [2024-10-31 22:04:46,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63030 states and 89131 transitions. [2024-10-31 22:04:46,649 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 62576 [2024-10-31 22:04:47,217 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63030 states to 63030 states and 89131 transitions. [2024-10-31 22:04:47,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63030 [2024-10-31 22:04:47,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63030 [2024-10-31 22:04:47,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63030 states and 89131 transitions. [2024-10-31 22:04:47,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:47,349 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63030 states and 89131 transitions. [2024-10-31 22:04:47,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63030 states and 89131 transitions. [2024-10-31 22:04:47,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63030 to 43649. [2024-10-31 22:04:48,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.4146028545900249) internal successors, (61746), 43648 states have internal predecessors, (61746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:48,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61746 transitions. [2024-10-31 22:04:48,138 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61746 transitions. [2024-10-31 22:04:48,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:48,139 INFO L425 stractBuchiCegarLoop]: Abstraction has 43649 states and 61746 transitions. [2024-10-31 22:04:48,139 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-31 22:04:48,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61746 transitions. [2024-10-31 22:04:48,324 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2024-10-31 22:04:48,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:48,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:48,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:48,327 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:48,327 INFO L745 eck$LassoCheckResult]: Stem: 444411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 444412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 445145#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 445146#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 445213#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 444860#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 444861#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 444436#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 444437#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 444361#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 444362#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 444641#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 444610#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 444611#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 444921#L854 assume !(0 == ~M_E~0); 444710#L854-2 assume !(0 == ~T1_E~0); 444711#L859-1 assume !(0 == ~T2_E~0); 444237#L864-1 assume !(0 == ~T3_E~0); 444238#L869-1 assume !(0 == ~T4_E~0); 444350#L874-1 assume !(0 == ~T5_E~0); 445188#L879-1 assume !(0 == ~T6_E~0); 444694#L884-1 assume !(0 == ~T7_E~0); 444099#L889-1 assume !(0 == ~T8_E~0); 444100#L894-1 assume !(0 == ~E_M~0); 444449#L899-1 assume !(0 == ~E_1~0); 444927#L904-1 assume !(0 == ~E_2~0); 444633#L909-1 assume !(0 == ~E_3~0); 444634#L914-1 assume !(0 == ~E_4~0); 444850#L919-1 assume !(0 == ~E_5~0); 444533#L924-1 assume !(0 == ~E_6~0); 444336#L929-1 assume !(0 == ~E_7~0); 444337#L934-1 assume !(0 == ~E_8~0); 444609#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 444116#L418 assume !(1 == ~m_pc~0); 444091#L418-2 is_master_triggered_~__retres1~0#1 := 0; 445128#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 445129#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 445049#L1061 assume !(0 != activate_threads_~tmp~1#1); 444952#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 444953#L437 assume !(1 == ~t1_pc~0); 445177#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 445056#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 444141#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 444142#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 444480#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 445040#L456 assume !(1 == ~t2_pc~0); 444392#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 444391#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 444565#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 444566#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 444742#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 444232#L475 assume !(1 == ~t3_pc~0); 444233#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 444297#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 444107#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 444108#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 444483#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 444484#L494 assume !(1 == ~t4_pc~0); 444528#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 444529#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 444247#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 444248#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 444876#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 444293#L513 assume !(1 == ~t5_pc~0); 444294#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 444532#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 445068#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 444244#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 444245#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 444198#L532 assume !(1 == ~t6_pc~0); 444199#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 444351#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 444547#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 444548#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 444452#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 444453#L551 assume !(1 == ~t7_pc~0); 444928#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 444878#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 444879#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 445230#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 445235#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 444655#L570 assume !(1 == ~t8_pc~0); 444656#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 445151#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 444999#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 444769#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 444230#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 444231#L952 assume !(1 == ~M_E~0); 444165#L952-2 assume !(1 == ~T1_E~0); 444166#L957-1 assume !(1 == ~T2_E~0); 445012#L962-1 assume !(1 == ~T3_E~0); 444786#L967-1 assume !(1 == ~T4_E~0); 444787#L972-1 assume !(1 == ~T5_E~0); 445088#L977-1 assume !(1 == ~T6_E~0); 445089#L982-1 assume !(1 == ~T7_E~0); 444353#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 444354#L992-1 assume !(1 == ~E_M~0); 444363#L997-1 assume !(1 == ~E_1~0); 444740#L1002-1 assume !(1 == ~E_2~0); 444725#L1007-1 assume !(1 == ~E_3~0); 444101#L1012-1 assume !(1 == ~E_4~0); 444102#L1017-1 assume !(1 == ~E_5~0); 444731#L1022-1 assume !(1 == ~E_6~0); 444732#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 444756#L1032-1 assume !(1 == ~E_8~0); 444909#L1037-1 assume { :end_inline_reset_delta_events } true; 444910#L1303-2 [2024-10-31 22:04:48,328 INFO L747 eck$LassoCheckResult]: Loop: 444910#L1303-2 assume !false; 457394#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 457386#L829-1 assume !false; 457382#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 457214#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 457201#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 457193#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 457185#L712 assume !(0 != eval_~tmp~0#1); 457186#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 465653#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 465646#L854-3 assume !(0 == ~M_E~0); 465641#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 465636#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 465630#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 465625#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 465619#L874-3 assume !(0 == ~T5_E~0); 465614#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 465609#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 465604#L889-3 assume !(0 == ~T8_E~0); 465598#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 465593#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 465588#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 465582#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 465577#L914-3 assume !(0 == ~E_4~0); 465572#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 465567#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 465562#L929-3 assume !(0 == ~E_7~0); 465556#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 465550#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 465545#L418-30 assume !(1 == ~m_pc~0); 465540#L418-32 is_master_triggered_~__retres1~0#1 := 0; 465533#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 465527#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 465520#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 465513#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 465508#L437-30 assume !(1 == ~t1_pc~0); 465504#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 465501#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 465460#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 465442#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 465437#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 465431#L456-30 assume 1 == ~t2_pc~0; 465424#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 465418#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 465414#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 465409#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 465405#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 465400#L475-30 assume !(1 == ~t3_pc~0); 465394#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 465390#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 465386#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 465381#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 465376#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 465369#L494-30 assume 1 == ~t4_pc~0; 465362#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 465355#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 465349#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 465344#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 465339#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 465332#L513-30 assume !(1 == ~t5_pc~0); 465326#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 465321#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 465316#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 464799#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 464795#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 464792#L532-30 assume 1 == ~t6_pc~0; 464789#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 464785#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 464782#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 464778#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 464775#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 464773#L551-30 assume !(1 == ~t7_pc~0); 453628#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 464770#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 464768#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 464766#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 464764#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 464762#L570-30 assume !(1 == ~t8_pc~0); 464760#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 464757#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 464755#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 464753#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 464751#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 464749#L952-3 assume !(1 == ~M_E~0); 464747#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 464744#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 464742#L962-3 assume !(1 == ~T3_E~0); 464740#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 464738#L972-3 assume !(1 == ~T5_E~0); 464736#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 464734#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 464731#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 464729#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 464727#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 464725#L1002-3 assume !(1 == ~E_2~0); 464723#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 464721#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 464718#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 464716#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 464714#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 462236#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 454401#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 454123#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 454113#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 453445#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 453404#L1322 assume !(0 == start_simulation_~tmp~3#1); 453405#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 457594#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 457588#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 457532#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 457431#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 457420#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 457410#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 457403#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 444910#L1303-2 [2024-10-31 22:04:48,329 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:48,329 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2024-10-31 22:04:48,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:48,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022855897] [2024-10-31 22:04:48,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:48,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:48,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:48,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:48,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:48,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022855897] [2024-10-31 22:04:48,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1022855897] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:48,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:48,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:48,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103404773] [2024-10-31 22:04:48,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:48,446 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:48,446 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:48,446 INFO L85 PathProgramCache]: Analyzing trace with hash 1607750567, now seen corresponding path program 1 times [2024-10-31 22:04:48,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:48,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418141220] [2024-10-31 22:04:48,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:48,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:48,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:48,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:48,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:48,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [418141220] [2024-10-31 22:04:48,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [418141220] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:48,517 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:48,517 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:48,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806331417] [2024-10-31 22:04:48,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:48,518 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:48,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:48,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:48,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:48,520 INFO L87 Difference]: Start difference. First operand 43649 states and 61746 transitions. cyclomatic complexity: 18129 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:49,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:49,209 INFO L93 Difference]: Finished difference Result 69451 states and 98228 transitions. [2024-10-31 22:04:49,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69451 states and 98228 transitions. [2024-10-31 22:04:49,509 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 68912 [2024-10-31 22:04:49,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69451 states to 69451 states and 98228 transitions. [2024-10-31 22:04:49,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69451 [2024-10-31 22:04:49,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69451 [2024-10-31 22:04:49,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69451 states and 98228 transitions. [2024-10-31 22:04:49,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:49,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69451 states and 98228 transitions. [2024-10-31 22:04:49,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69451 states and 98228 transitions. [2024-10-31 22:04:50,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69451 to 49009. [2024-10-31 22:04:50,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49009 states, 49009 states have (on average 1.4169030178130548) internal successors, (69441), 49008 states have internal predecessors, (69441), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:50,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49009 states to 49009 states and 69441 transitions. [2024-10-31 22:04:50,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49009 states and 69441 transitions. [2024-10-31 22:04:50,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:50,973 INFO L425 stractBuchiCegarLoop]: Abstraction has 49009 states and 69441 transitions. [2024-10-31 22:04:50,973 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-31 22:04:50,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49009 states and 69441 transitions. [2024-10-31 22:04:51,128 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48592 [2024-10-31 22:04:51,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:04:51,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:04:51,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:51,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:04:51,131 INFO L745 eck$LassoCheckResult]: Stem: 557524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 557525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 558261#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 558262#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 558349#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 557980#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 557981#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 557548#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 557549#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 557474#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 557475#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 557752#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 557723#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 557724#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 558042#L854 assume !(0 == ~M_E~0); 557820#L854-2 assume !(0 == ~T1_E~0); 557821#L859-1 assume !(0 == ~T2_E~0); 557348#L864-1 assume !(0 == ~T3_E~0); 557349#L869-1 assume !(0 == ~T4_E~0); 557463#L874-1 assume !(0 == ~T5_E~0); 558321#L879-1 assume !(0 == ~T6_E~0); 557805#L884-1 assume !(0 == ~T7_E~0); 557209#L889-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 557210#L894-1 assume !(0 == ~E_M~0); 558394#L899-1 assume !(0 == ~E_1~0); 558049#L904-1 assume !(0 == ~E_2~0); 558050#L909-1 assume !(0 == ~E_3~0); 557970#L914-1 assume !(0 == ~E_4~0); 557971#L919-1 assume !(0 == ~E_5~0); 557644#L924-1 assume !(0 == ~E_6~0); 557645#L929-1 assume !(0 == ~E_7~0); 558333#L934-1 assume !(0 == ~E_8~0); 558334#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 558445#L418 assume !(1 == ~m_pc~0); 558364#L418-2 is_master_triggered_~__retres1~0#1 := 0; 558365#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 558442#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 558439#L1061 assume !(0 != activate_threads_~tmp~1#1); 558438#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558361#L437 assume !(1 == ~t1_pc~0); 558362#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 558176#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 558177#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 557591#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 557592#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 558159#L456 assume !(1 == ~t2_pc~0); 558160#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 558357#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 558358#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 558198#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 558199#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 557343#L475 assume !(1 == ~t3_pc~0); 557344#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 558437#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 557218#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 557219#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 557595#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 557596#L494 assume !(1 == ~t4_pc~0); 557639#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 557640#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 557358#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 557359#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 557996#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 557405#L513 assume !(1 == ~t5_pc~0); 557406#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 557643#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 558188#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 557355#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 557356#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 557309#L532 assume !(1 == ~t6_pc~0); 557310#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 557464#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 557658#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 557659#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 557562#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 557563#L551 assume !(1 == ~t7_pc~0); 558051#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 558000#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 558001#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 558377#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 558384#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 557765#L570 assume !(1 == ~t8_pc~0); 557766#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 558271#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 558125#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 557886#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 557341#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 557342#L952 assume !(1 == ~M_E~0); 558182#L952-2 assume !(1 == ~T1_E~0); 558408#L957-1 assume !(1 == ~T2_E~0); 558407#L962-1 assume !(1 == ~T3_E~0); 558406#L967-1 assume !(1 == ~T4_E~0); 558405#L972-1 assume !(1 == ~T5_E~0); 558404#L977-1 assume !(1 == ~T6_E~0); 558403#L982-1 assume !(1 == ~T7_E~0); 558402#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 557467#L992-1 assume !(1 == ~E_M~0); 557476#L997-1 assume !(1 == ~E_1~0); 557856#L1002-1 assume !(1 == ~E_2~0); 557841#L1007-1 assume !(1 == ~E_3~0); 557212#L1012-1 assume !(1 == ~E_4~0); 557213#L1017-1 assume !(1 == ~E_5~0); 557847#L1022-1 assume !(1 == ~E_6~0); 557848#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 557874#L1032-1 assume !(1 == ~E_8~0); 558029#L1037-1 assume { :end_inline_reset_delta_events } true; 558030#L1303-2 [2024-10-31 22:04:51,132 INFO L747 eck$LassoCheckResult]: Loop: 558030#L1303-2 assume !false; 576661#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 576657#L829-1 assume !false; 576654#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 576638#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 576632#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 576630#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 576627#L712 assume !(0 != eval_~tmp~0#1); 576628#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 581377#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 581375#L854-3 assume !(0 == ~M_E~0); 581373#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 581370#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 581368#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 581365#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 581362#L874-3 assume !(0 == ~T5_E~0); 581359#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 581356#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 581352#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 581353#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 602550#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 602549#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 602548#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 602547#L914-3 assume !(0 == ~E_4~0); 602546#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 602545#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 602544#L929-3 assume !(0 == ~E_7~0); 579484#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 579485#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 579434#L418-30 assume !(1 == ~m_pc~0); 579435#L418-32 is_master_triggered_~__retres1~0#1 := 0; 579424#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 579425#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 579411#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 579410#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 579402#L437-30 assume !(1 == ~t1_pc~0); 579403#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 579396#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 579397#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 579390#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 579391#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 579383#L456-30 assume !(1 == ~t2_pc~0); 579384#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 579374#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 579375#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 579362#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 579363#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 579358#L475-30 assume !(1 == ~t3_pc~0); 579359#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 579351#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 579352#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 579345#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 579346#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 579333#L494-30 assume !(1 == ~t4_pc~0); 579334#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 579320#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 579321#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 579307#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 579308#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 579295#L513-30 assume !(1 == ~t5_pc~0); 579296#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 579283#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 579284#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 579269#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 579270#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 579255#L532-30 assume 1 == ~t6_pc~0; 579256#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 579245#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 579246#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 579239#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 579240#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 579223#L551-30 assume !(1 == ~t7_pc~0); 579222#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 579221#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 579220#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 579219#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 579218#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 579217#L570-30 assume !(1 == ~t8_pc~0); 579216#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 579215#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 579214#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 579213#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 579212#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 579211#L952-3 assume !(1 == ~M_E~0); 579210#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 579209#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 579208#L962-3 assume !(1 == ~T3_E~0); 579207#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 579206#L972-3 assume !(1 == ~T5_E~0); 579205#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 579204#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 579202#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 579201#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 579197#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 579195#L1002-3 assume !(1 == ~E_2~0); 579193#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 579191#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 579115#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 579114#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 579083#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 579070#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 579048#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 577838#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 577828#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 577796#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 568916#L1322 assume !(0 == start_simulation_~tmp~3#1); 568917#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 576677#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 576672#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 576671#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 576670#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 576669#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 576668#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 576664#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 558030#L1303-2 [2024-10-31 22:04:51,132 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:51,133 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2024-10-31 22:04:51,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:51,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921384502] [2024-10-31 22:04:51,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:51,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:51,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:51,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:51,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:51,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [921384502] [2024-10-31 22:04:51,199 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [921384502] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:51,199 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:51,200 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:51,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1131878073] [2024-10-31 22:04:51,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:51,201 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:04:51,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:04:51,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1530034667, now seen corresponding path program 1 times [2024-10-31 22:04:51,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:04:51,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806120886] [2024-10-31 22:04:51,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:04:51,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:04:51,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:04:51,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:04:51,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:04:51,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806120886] [2024-10-31 22:04:51,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806120886] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:04:51,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:04:51,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:04:51,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [768625565] [2024-10-31 22:04:51,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:04:51,256 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:04:51,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:04:51,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:04:51,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:04:51,256 INFO L87 Difference]: Start difference. First operand 49009 states and 69441 transitions. cyclomatic complexity: 20464 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:51,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:04:51,516 INFO L93 Difference]: Finished difference Result 43649 states and 61584 transitions. [2024-10-31 22:04:51,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43649 states and 61584 transitions. [2024-10-31 22:04:52,094 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2024-10-31 22:04:52,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43649 states to 43649 states and 61584 transitions. [2024-10-31 22:04:52,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43649 [2024-10-31 22:04:52,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43649 [2024-10-31 22:04:52,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43649 states and 61584 transitions. [2024-10-31 22:04:52,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:04:52,306 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61584 transitions. [2024-10-31 22:04:52,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43649 states and 61584 transitions. [2024-10-31 22:04:52,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43649 to 43649. [2024-10-31 22:04:52,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.4108914293569155) internal successors, (61584), 43648 states have internal predecessors, (61584), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:04:52,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61584 transitions. [2024-10-31 22:04:52,776 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61584 transitions. [2024-10-31 22:04:52,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:04:52,777 INFO L425 stractBuchiCegarLoop]: Abstraction has 43649 states and 61584 transitions. [2024-10-31 22:04:52,777 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-31 22:04:52,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61584 transitions.