./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:18:31,801 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:18:31,898 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:18:31,907 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:18:31,908 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:18:31,943 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:18:31,945 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:18:31,946 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:18:31,947 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:18:31,948 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:18:31,949 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:18:31,950 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:18:31,950 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:18:31,951 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:18:31,952 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:18:31,954 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:18:31,954 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:18:31,954 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:18:31,955 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:18:31,955 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:18:31,955 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:18:31,960 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:18:31,960 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:18:31,961 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:18:31,961 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:18:31,961 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:18:31,962 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:18:31,962 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:18:31,962 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:18:31,963 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:18:31,963 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:18:31,963 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:18:31,963 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:18:31,964 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:18:31,964 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:18:31,964 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:18:31,965 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:18:31,965 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:18:31,965 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:18:31,966 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e [2024-10-31 22:18:32,250 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:18:32,285 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:18:32,288 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:18:32,290 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:18:32,291 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:18:32,292 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c Unable to find full path for "g++" [2024-10-31 22:18:34,299 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:18:34,572 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:18:34,573 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2024-10-31 22:18:34,586 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/data/faf5a20b7/ec84fcfbe6124fd2a99de846625a5a3a/FLAG7bb296a46 [2024-10-31 22:18:34,604 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/data/faf5a20b7/ec84fcfbe6124fd2a99de846625a5a3a [2024-10-31 22:18:34,606 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:18:34,608 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:18:34,609 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:18:34,610 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:18:34,616 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:18:34,617 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:18:34" (1/1) ... [2024-10-31 22:18:34,619 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c430160 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:34, skipping insertion in model container [2024-10-31 22:18:34,619 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:18:34" (1/1) ... [2024-10-31 22:18:34,670 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:18:35,057 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:35,077 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:18:35,195 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:35,223 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:18:35,223 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35 WrapperNode [2024-10-31 22:18:35,223 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:18:35,224 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:35,225 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:18:35,225 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:18:35,233 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,244 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,338 INFO L138 Inliner]: procedures = 46, calls = 59, calls flagged for inlining = 54, calls inlined = 183, statements flattened = 2778 [2024-10-31 22:18:35,339 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:35,340 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:18:35,340 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:18:35,340 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:18:35,354 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,354 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,366 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,412 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:18:35,412 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,413 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,459 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,498 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,511 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,525 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,542 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:18:35,543 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:18:35,543 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:18:35,544 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:18:35,545 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (1/1) ... [2024-10-31 22:18:35,551 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:35,564 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:35,590 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:18:35,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1abe7b8-387d-45f5-a7b5-b7f449aee6d2/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:18:35,652 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:18:35,653 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:18:35,653 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:18:35,653 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:18:35,867 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:18:35,869 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:18:38,330 INFO L? ?]: Removed 564 outVars from TransFormulas that were not future-live. [2024-10-31 22:18:38,331 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:18:38,386 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:18:38,386 INFO L316 CfgBuilder]: Removed 12 assume(true) statements. [2024-10-31 22:18:38,387 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:38 BoogieIcfgContainer [2024-10-31 22:18:38,387 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:18:38,389 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:18:38,390 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:18:38,394 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:18:38,395 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:38,395 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:18:34" (1/3) ... [2024-10-31 22:18:38,396 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@52a0d327 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:38, skipping insertion in model container [2024-10-31 22:18:38,396 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:38,397 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:35" (2/3) ... [2024-10-31 22:18:38,397 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@52a0d327 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:38, skipping insertion in model container [2024-10-31 22:18:38,397 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:38,397 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:38" (3/3) ... [2024-10-31 22:18:38,400 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2024-10-31 22:18:38,505 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:18:38,506 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:18:38,506 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:18:38,506 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:18:38,506 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:18:38,507 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:18:38,507 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:18:38,507 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:18:38,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1187 states, 1186 states have (on average 1.5050590219224282) internal successors, (1785), 1186 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:38,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1056 [2024-10-31 22:18:38,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:38,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:38,625 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:38,625 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:38,625 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:18:38,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1187 states, 1186 states have (on average 1.5050590219224282) internal successors, (1785), 1186 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:38,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1056 [2024-10-31 22:18:38,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:38,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:38,673 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:38,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:38,697 INFO L745 eck$LassoCheckResult]: Stem: 169#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1075#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 887#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1071#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 763#L658true assume !(1 == ~m_i~0);~m_st~0 := 2; 407#L658-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 786#L663-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 726#L668-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 268#L673-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 827#L678-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 633#L683-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1045#L688-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8#L693-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 103#L698-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 336#L703-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1036#L939true assume !(0 == ~M_E~0); 538#L939-2true assume !(0 == ~T1_E~0); 758#L944-1true assume !(0 == ~T2_E~0); 361#L949-1true assume !(0 == ~T3_E~0); 359#L954-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1082#L959-1true assume !(0 == ~T5_E~0); 787#L964-1true assume !(0 == ~T6_E~0); 183#L969-1true assume !(0 == ~T7_E~0); 898#L974-1true assume !(0 == ~T8_E~0); 713#L979-1true assume !(0 == ~T9_E~0); 1108#L984-1true assume !(0 == ~E_M~0); 275#L989-1true assume !(0 == ~E_1~0); 518#L994-1true assume 0 == ~E_2~0;~E_2~0 := 1; 210#L999-1true assume !(0 == ~E_3~0); 676#L1004-1true assume !(0 == ~E_4~0); 37#L1009-1true assume !(0 == ~E_5~0); 206#L1014-1true assume !(0 == ~E_6~0); 639#L1019-1true assume !(0 == ~E_7~0); 952#L1024-1true assume !(0 == ~E_8~0); 166#L1029-1true assume !(0 == ~E_9~0); 213#L1034-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 966#L460true assume 1 == ~m_pc~0; 2#L461true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 603#L471true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 743#is_master_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1040#L1167true assume !(0 != activate_threads_~tmp~1#1); 350#L1167-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 502#L479true assume 1 == ~t1_pc~0; 337#L480true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1054#L490true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 173#L1175true assume !(0 != activate_threads_~tmp___0~0#1); 393#L1175-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93#L498true assume !(1 == ~t2_pc~0); 648#L498-2true is_transmit2_triggered_~__retres1~2#1 := 0; 335#L509true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 677#L1183true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 595#L1183-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1131#L517true assume 1 == ~t3_pc~0; 911#L518true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1077#L528true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 192#L1191true assume !(0 != activate_threads_~tmp___2~0#1); 650#L1191-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 828#L536true assume !(1 == ~t4_pc~0); 1110#L536-2true is_transmit4_triggered_~__retres1~4#1 := 0; 776#L547true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 376#L1199true assume !(0 != activate_threads_~tmp___3~0#1); 1100#L1199-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 569#L555true assume 1 == ~t5_pc~0; 1176#L556true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 709#L566true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 746#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 167#L1207true assume !(0 != activate_threads_~tmp___4~0#1); 107#L1207-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56#L574true assume !(1 == ~t6_pc~0); 641#L574-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1113#L585true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 672#L1215true assume !(0 != activate_threads_~tmp___5~0#1); 1105#L1215-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 986#L593true assume 1 == ~t7_pc~0; 1152#L594true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 791#L604true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1094#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1093#L1223true assume !(0 != activate_threads_~tmp___6~0#1); 915#L1223-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 273#L612true assume !(1 == ~t8_pc~0); 1034#L612-2true is_transmit8_triggered_~__retres1~8#1 := 0; 901#L623true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 678#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 822#L1231true assume !(0 != activate_threads_~tmp___7~0#1); 450#L1231-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 506#L631true assume 1 == ~t9_pc~0; 461#L632true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52#L642true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 301#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 338#L1239true assume !(0 != activate_threads_~tmp___8~0#1); 1063#L1239-2true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 653#L1047true assume !(1 == ~M_E~0); 23#L1047-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 444#L1052-1true assume !(1 == ~T2_E~0); 15#L1057-1true assume !(1 == ~T3_E~0); 158#L1062-1true assume !(1 == ~T4_E~0); 788#L1067-1true assume !(1 == ~T5_E~0); 352#L1072-1true assume !(1 == ~T6_E~0); 621#L1077-1true assume !(1 == ~T7_E~0); 100#L1082-1true assume !(1 == ~T8_E~0); 426#L1087-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 5#L1092-1true assume !(1 == ~E_M~0); 16#L1097-1true assume !(1 == ~E_1~0); 957#L1102-1true assume !(1 == ~E_2~0); 503#L1107-1true assume !(1 == ~E_3~0); 446#L1112-1true assume !(1 == ~E_4~0); 481#L1117-1true assume !(1 == ~E_5~0); 1165#L1122-1true assume !(1 == ~E_6~0); 389#L1127-1true assume 1 == ~E_7~0;~E_7~0 := 2; 216#L1132-1true assume !(1 == ~E_8~0); 960#L1137-1true assume !(1 == ~E_9~0); 156#L1142-1true assume { :end_inline_reset_delta_events } true; 81#L1428-2true [2024-10-31 22:18:38,699 INFO L747 eck$LassoCheckResult]: Loop: 81#L1428-2true assume !false; 443#L1429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 490#L914-1true assume false; 686#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 413#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 773#L939-3true assume 0 == ~M_E~0;~M_E~0 := 1; 114#L939-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 141#L944-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 4#L949-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 730#L954-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 364#L959-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 40#L964-3true assume !(0 == ~T6_E~0); 261#L969-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 140#L974-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1068#L979-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 421#L984-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1155#L989-3true assume 0 == ~E_1~0;~E_1~0 := 1; 171#L994-3true assume 0 == ~E_2~0;~E_2~0 := 1; 987#L999-3true assume 0 == ~E_3~0;~E_3~0 := 1; 545#L1004-3true assume !(0 == ~E_4~0); 76#L1009-3true assume 0 == ~E_5~0;~E_5~0 := 1; 627#L1014-3true assume 0 == ~E_6~0;~E_6~0 := 1; 408#L1019-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1124#L1024-3true assume 0 == ~E_8~0;~E_8~0 := 1; 396#L1029-3true assume 0 == ~E_9~0;~E_9~0 := 1; 366#L1034-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 936#L460-33true assume 1 == ~m_pc~0; 390#L461-11true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 558#L471-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 701#is_master_triggered_returnLabel#12true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7#L1167-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 507#L1167-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186#L479-33true assume !(1 == ~t1_pc~0); 717#L479-35true is_transmit1_triggered_~__retres1~1#1 := 0; 168#L490-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1062#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 877#L1175-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1007#L1175-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191#L498-33true assume !(1 == ~t2_pc~0); 58#L498-35true is_transmit2_triggered_~__retres1~2#1 := 0; 322#L509-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 646#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 435#L1183-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 115#L1183-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1016#L517-33true assume !(1 == ~t3_pc~0); 1122#L517-35true is_transmit3_triggered_~__retres1~3#1 := 0; 750#L528-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 532#L1191-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 673#L1191-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241#L536-33true assume !(1 == ~t4_pc~0); 1027#L536-35true is_transmit4_triggered_~__retres1~4#1 := 0; 286#L547-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 949#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 719#L1199-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 829#L1199-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27#L555-33true assume !(1 == ~t5_pc~0); 813#L555-35true is_transmit5_triggered_~__retres1~5#1 := 0; 476#L566-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1012#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 499#L1207-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1049#L1207-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14#L574-33true assume 1 == ~t6_pc~0; 733#L575-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 857#L585-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 345#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 582#L1215-33true assume !(0 != activate_threads_~tmp___5~0#1); 331#L1215-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49#L593-33true assume 1 == ~t7_pc~0; 405#L594-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 970#L604-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 557#L1223-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 704#L1223-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1130#L612-33true assume 1 == ~t8_pc~0; 934#L613-11true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 863#L623-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 484#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 620#L1231-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 98#L1231-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1174#L631-33true assume 1 == ~t9_pc~0; 784#L632-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69#L642-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 655#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 205#L1239-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 129#L1239-35true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219#L1047-3true assume 1 == ~M_E~0;~M_E~0 := 2; 785#L1047-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1183#L1052-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 684#L1057-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1178#L1062-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 73#L1067-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1041#L1072-3true assume !(1 == ~T6_E~0); 296#L1077-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 196#L1082-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 238#L1087-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 440#L1092-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1188#L1097-3true assume 1 == ~E_1~0;~E_1~0 := 2; 388#L1102-3true assume 1 == ~E_2~0;~E_2~0 := 2; 965#L1107-3true assume 1 == ~E_3~0;~E_3~0 := 2; 738#L1112-3true assume !(1 == ~E_4~0); 193#L1117-3true assume 1 == ~E_5~0;~E_5~0 := 2; 748#L1122-3true assume 1 == ~E_6~0;~E_6~0 := 2; 220#L1127-3true assume 1 == ~E_7~0;~E_7~0 := 2; 517#L1132-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1096#L1137-3true assume 1 == ~E_9~0;~E_9~0 := 2; 493#L1142-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 131#L716-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 501#L768-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 239#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 311#L1447true assume !(0 == start_simulation_~tmp~3#1); 712#L1447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1154#L716-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 742#L768-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 38#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 209#L1402true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78#L1409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 429#stop_simulation_returnLabel#1true start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 354#L1460true assume !(0 != start_simulation_~tmp___0~1#1); 81#L1428-2true [2024-10-31 22:18:38,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:38,719 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2024-10-31 22:18:38,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:38,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494724878] [2024-10-31 22:18:38,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:38,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:38,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:39,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:39,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:39,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494724878] [2024-10-31 22:18:39,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494724878] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:39,175 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:39,175 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:39,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801859199] [2024-10-31 22:18:39,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:39,184 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:39,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:39,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1305754084, now seen corresponding path program 1 times [2024-10-31 22:18:39,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:39,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741414301] [2024-10-31 22:18:39,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:39,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:39,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:39,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:39,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:39,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741414301] [2024-10-31 22:18:39,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1741414301] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:39,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:39,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:39,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377935356] [2024-10-31 22:18:39,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:39,253 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:39,254 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:39,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:39,304 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:39,311 INFO L87 Difference]: Start difference. First operand has 1187 states, 1186 states have (on average 1.5050590219224282) internal successors, (1785), 1186 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:39,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:39,429 INFO L93 Difference]: Finished difference Result 1185 states and 1757 transitions. [2024-10-31 22:18:39,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1757 transitions. [2024-10-31 22:18:39,445 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:39,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1180 states and 1752 transitions. [2024-10-31 22:18:39,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2024-10-31 22:18:39,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2024-10-31 22:18:39,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1752 transitions. [2024-10-31 22:18:39,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:39,480 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1752 transitions. [2024-10-31 22:18:39,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1752 transitions. [2024-10-31 22:18:39,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2024-10-31 22:18:39,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4847457627118643) internal successors, (1752), 1179 states have internal predecessors, (1752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:39,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1752 transitions. [2024-10-31 22:18:39,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1752 transitions. [2024-10-31 22:18:39,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:39,613 INFO L425 stractBuchiCegarLoop]: Abstraction has 1180 states and 1752 transitions. [2024-10-31 22:18:39,614 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:18:39,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1752 transitions. [2024-10-31 22:18:39,623 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:39,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:39,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:39,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:39,627 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:39,628 INFO L745 eck$LassoCheckResult]: Stem: 2723#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3504#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3505#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3439#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3103#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3104#L663-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3415#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2891#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2892#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3342#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3343#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2395#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2396#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2599#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2993#L939 assume !(0 == ~M_E~0); 3248#L939-2 assume !(0 == ~T1_E~0); 3249#L944-1 assume !(0 == ~T2_E~0); 3031#L949-1 assume !(0 == ~T3_E~0); 3029#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3030#L959-1 assume !(0 == ~T5_E~0); 3451#L964-1 assume !(0 == ~T6_E~0); 2744#L969-1 assume !(0 == ~T7_E~0); 2745#L974-1 assume !(0 == ~T8_E~0); 3400#L979-1 assume !(0 == ~T9_E~0); 3401#L984-1 assume !(0 == ~E_M~0); 2905#L989-1 assume !(0 == ~E_1~0); 2906#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2795#L999-1 assume !(0 == ~E_3~0); 2796#L1004-1 assume !(0 == ~E_4~0); 2463#L1009-1 assume !(0 == ~E_5~0); 2464#L1014-1 assume !(0 == ~E_6~0); 2792#L1019-1 assume !(0 == ~E_7~0); 3347#L1024-1 assume !(0 == ~E_8~0); 2716#L1029-1 assume !(0 == ~E_9~0); 2717#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2801#L460 assume 1 == ~m_pc~0; 2381#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2382#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3312#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3425#L1167 assume !(0 != activate_threads_~tmp~1#1); 3014#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3015#L479 assume 1 == ~t1_pc~0; 2994#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2995#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2465#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2466#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2729#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2578#L498 assume !(1 == ~t2_pc~0); 2579#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2992#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2895#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2896#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3302#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3303#L517 assume 1 == ~t3_pc~0; 3512#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3513#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2402#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2403#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2765#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3354#L536 assume !(1 == ~t4_pc~0); 3059#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3058#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2561#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2562#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3052#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3282#L555 assume 1 == ~t5_pc~0; 3283#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3348#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3398#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2718#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2602#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2501#L574 assume !(1 == ~t6_pc~0); 2502#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3158#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2885#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2886#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3371#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3537#L593 assume 1 == ~t7_pc~0; 3538#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2737#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3454#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3554#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3516#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2900#L612 assume !(1 == ~t8_pc~0); 2901#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3330#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3374#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3375#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3160#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3161#L631 assume 1 == ~t9_pc~0; 3174#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2493#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2494#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2945#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2997#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3355#L1047 assume !(1 == ~M_E~0); 2429#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2430#L1052-1 assume !(1 == ~T2_E~0); 2412#L1057-1 assume !(1 == ~T3_E~0); 2413#L1062-1 assume !(1 == ~T4_E~0); 2702#L1067-1 assume !(1 == ~T5_E~0); 3018#L1072-1 assume !(1 == ~T6_E~0); 3019#L1077-1 assume !(1 == ~T7_E~0); 2593#L1082-1 assume !(1 == ~T8_E~0); 2594#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2391#L1092-1 assume !(1 == ~E_M~0); 2392#L1097-1 assume !(1 == ~E_1~0); 2414#L1102-1 assume !(1 == ~E_2~0); 3218#L1107-1 assume !(1 == ~E_3~0); 3156#L1112-1 assume !(1 == ~E_4~0); 3157#L1117-1 assume !(1 == ~E_5~0); 3192#L1122-1 assume !(1 == ~E_6~0); 3074#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2807#L1132-1 assume !(1 == ~E_8~0); 2808#L1137-1 assume !(1 == ~E_9~0); 2699#L1142-1 assume { :end_inline_reset_delta_events } true; 2552#L1428-2 [2024-10-31 22:18:39,629 INFO L747 eck$LassoCheckResult]: Loop: 2552#L1428-2 assume !false; 2553#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2924#L914-1 assume !false; 3152#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3153#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2400#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2401#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2923#L783 assume !(0 != eval_~tmp~0#1); 3372#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3111#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3112#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2617#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2618#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2387#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2388#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3036#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2467#L964-3 assume !(0 == ~T6_E~0); 2468#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2670#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2671#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3123#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3124#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2725#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2726#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3257#L1004-3 assume !(0 == ~E_4~0); 2544#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2545#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3105#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3106#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3084#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3037#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3038#L460-33 assume 1 == ~m_pc~0; 3075#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3076#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3272#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2393#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2394#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2753#L479-33 assume !(1 == ~t1_pc~0); 2754#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2719#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2720#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3492#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3493#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2763#L498-33 assume !(1 == ~t2_pc~0); 2507#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2508#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2975#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3146#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2619#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2620#L517-33 assume !(1 == ~t3_pc~0); 3546#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3431#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2576#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2577#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3242#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2843#L536-33 assume 1 == ~t4_pc~0; 2844#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2921#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2922#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3406#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3407#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2438#L555-33 assume 1 == ~t5_pc~0; 2439#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3184#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3185#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3214#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3215#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2404#L574-33 assume !(1 == ~t6_pc~0); 2405#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3419#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3006#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3007#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 2985#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2482#L593-33 assume 1 == ~t7_pc~0; 2483#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2949#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3442#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3270#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3271#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3393#L612-33 assume 1 == ~t8_pc~0; 3524#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3485#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3195#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3196#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2587#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2588#L631-33 assume !(1 == ~t9_pc~0); 3221#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2528#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2529#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2787#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2645#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2646#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2811#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3450#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3379#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3380#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2538#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2539#L1072-3 assume !(1 == ~T6_E~0); 2935#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2771#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2772#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2837#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3151#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3070#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3071#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3420#L1112-3 assume !(1 == ~E_4~0); 2766#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2767#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2812#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2813#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3231#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3209#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2647#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2524#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2838#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2839#L1447 assume !(0 == start_simulation_~tmp~3#1); 2955#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3399#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2678#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2462#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2546#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2547#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3022#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2552#L1428-2 [2024-10-31 22:18:39,629 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:39,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2024-10-31 22:18:39,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:39,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625976589] [2024-10-31 22:18:39,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:39,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:39,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:39,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:39,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:39,729 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625976589] [2024-10-31 22:18:39,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625976589] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:39,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:39,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:39,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593678800] [2024-10-31 22:18:39,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:39,731 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:39,731 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:39,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1780472913, now seen corresponding path program 1 times [2024-10-31 22:18:39,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:39,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312482554] [2024-10-31 22:18:39,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:39,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:39,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:39,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:39,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:39,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312482554] [2024-10-31 22:18:39,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312482554] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:39,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:39,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:39,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093992798] [2024-10-31 22:18:39,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:39,900 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:39,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:39,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:39,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:39,902 INFO L87 Difference]: Start difference. First operand 1180 states and 1752 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:39,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:39,938 INFO L93 Difference]: Finished difference Result 1180 states and 1751 transitions. [2024-10-31 22:18:39,939 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1751 transitions. [2024-10-31 22:18:39,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:39,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1751 transitions. [2024-10-31 22:18:39,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2024-10-31 22:18:39,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2024-10-31 22:18:39,962 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1751 transitions. [2024-10-31 22:18:39,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:39,967 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1751 transitions. [2024-10-31 22:18:39,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1751 transitions. [2024-10-31 22:18:39,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2024-10-31 22:18:39,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4838983050847459) internal successors, (1751), 1179 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:39,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1751 transitions. [2024-10-31 22:18:39,998 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1751 transitions. [2024-10-31 22:18:39,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:40,000 INFO L425 stractBuchiCegarLoop]: Abstraction has 1180 states and 1751 transitions. [2024-10-31 22:18:40,000 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:18:40,002 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1751 transitions. [2024-10-31 22:18:40,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:40,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:40,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:40,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:40,015 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:40,015 INFO L745 eck$LassoCheckResult]: Stem: 5090#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5091#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5871#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5872#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5806#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 5470#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5471#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5782#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5258#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5259#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5709#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5710#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4762#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4763#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4966#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5360#L939 assume !(0 == ~M_E~0); 5615#L939-2 assume !(0 == ~T1_E~0); 5616#L944-1 assume !(0 == ~T2_E~0); 5398#L949-1 assume !(0 == ~T3_E~0); 5396#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5397#L959-1 assume !(0 == ~T5_E~0); 5818#L964-1 assume !(0 == ~T6_E~0); 5111#L969-1 assume !(0 == ~T7_E~0); 5112#L974-1 assume !(0 == ~T8_E~0); 5769#L979-1 assume !(0 == ~T9_E~0); 5770#L984-1 assume !(0 == ~E_M~0); 5272#L989-1 assume !(0 == ~E_1~0); 5273#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5162#L999-1 assume !(0 == ~E_3~0); 5163#L1004-1 assume !(0 == ~E_4~0); 4830#L1009-1 assume !(0 == ~E_5~0); 4831#L1014-1 assume !(0 == ~E_6~0); 5159#L1019-1 assume !(0 == ~E_7~0); 5714#L1024-1 assume !(0 == ~E_8~0); 5083#L1029-1 assume !(0 == ~E_9~0); 5084#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5168#L460 assume 1 == ~m_pc~0; 4751#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4752#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5679#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5792#L1167 assume !(0 != activate_threads_~tmp~1#1); 5381#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5382#L479 assume 1 == ~t1_pc~0; 5361#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5362#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4834#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4835#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 5096#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4945#L498 assume !(1 == ~t2_pc~0); 4946#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5359#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5262#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5263#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5669#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5670#L517 assume 1 == ~t3_pc~0; 5879#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5880#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4769#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4770#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 5132#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5721#L536 assume !(1 == ~t4_pc~0); 5426#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5425#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4932#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 5419#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5649#L555 assume 1 == ~t5_pc~0; 5650#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5715#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5765#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5085#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 4969#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4868#L574 assume !(1 == ~t6_pc~0); 4869#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5525#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5252#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5253#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 5738#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5904#L593 assume 1 == ~t7_pc~0; 5905#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5104#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5821#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5921#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 5883#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5267#L612 assume !(1 == ~t8_pc~0); 5268#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5697#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5741#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5742#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 5527#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5528#L631 assume 1 == ~t9_pc~0; 5541#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4860#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4861#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5312#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 5364#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5722#L1047 assume !(1 == ~M_E~0); 4796#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4797#L1052-1 assume !(1 == ~T2_E~0); 4779#L1057-1 assume !(1 == ~T3_E~0); 4780#L1062-1 assume !(1 == ~T4_E~0); 5069#L1067-1 assume !(1 == ~T5_E~0); 5385#L1072-1 assume !(1 == ~T6_E~0); 5386#L1077-1 assume !(1 == ~T7_E~0); 4960#L1082-1 assume !(1 == ~T8_E~0); 4961#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4758#L1092-1 assume !(1 == ~E_M~0); 4759#L1097-1 assume !(1 == ~E_1~0); 4781#L1102-1 assume !(1 == ~E_2~0); 5585#L1107-1 assume !(1 == ~E_3~0); 5523#L1112-1 assume !(1 == ~E_4~0); 5524#L1117-1 assume !(1 == ~E_5~0); 5560#L1122-1 assume !(1 == ~E_6~0); 5441#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5174#L1132-1 assume !(1 == ~E_8~0); 5175#L1137-1 assume !(1 == ~E_9~0); 5066#L1142-1 assume { :end_inline_reset_delta_events } true; 4922#L1428-2 [2024-10-31 22:18:40,016 INFO L747 eck$LassoCheckResult]: Loop: 4922#L1428-2 assume !false; 4923#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5291#L914-1 assume !false; 5519#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5520#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4767#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4768#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5290#L783 assume !(0 != eval_~tmp~0#1); 5739#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5479#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5480#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4986#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4987#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4754#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4755#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5403#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4836#L964-3 assume !(0 == ~T6_E~0); 4837#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5037#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5038#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5490#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5491#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5092#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5093#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5624#L1004-3 assume !(0 == ~E_4~0); 4911#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4912#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5472#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5473#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5451#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5407#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5408#L460-33 assume 1 == ~m_pc~0; 5443#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5444#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5639#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4760#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4761#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5120#L479-33 assume !(1 == ~t1_pc~0); 5121#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 5086#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5087#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5859#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5860#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5125#L498-33 assume 1 == ~t2_pc~0; 5126#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4872#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5342#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5513#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4984#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4985#L517-33 assume !(1 == ~t3_pc~0); 5913#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5798#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4943#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4944#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5609#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5207#L536-33 assume 1 == ~t4_pc~0; 5208#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5288#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5289#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5773#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5774#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4805#L555-33 assume 1 == ~t5_pc~0; 4806#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5551#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5552#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5581#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5582#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4774#L574-33 assume !(1 == ~t6_pc~0); 4775#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5786#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5373#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5374#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 5352#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4852#L593-33 assume 1 == ~t7_pc~0; 4853#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5317#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5809#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5637#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5638#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5760#L612-33 assume 1 == ~t8_pc~0; 5891#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5852#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5562#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5563#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4954#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4955#L631-33 assume !(1 == ~t9_pc~0); 5588#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 4897#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4898#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5154#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5012#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5013#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5178#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5817#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5746#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5747#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4905#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4906#L1072-3 assume !(1 == ~T6_E~0); 5302#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5138#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5139#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5204#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5518#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5437#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5438#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5787#L1112-3 assume !(1 == ~E_4~0); 5133#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5134#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5179#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5180#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5598#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5576#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5017#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4891#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5205#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 5206#L1447 assume !(0 == start_simulation_~tmp~3#1); 5322#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5766#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5045#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4828#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 4829#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4913#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4914#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5389#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 4922#L1428-2 [2024-10-31 22:18:40,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:40,017 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2024-10-31 22:18:40,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:40,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478136604] [2024-10-31 22:18:40,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:40,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:40,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:40,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:40,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:40,126 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [478136604] [2024-10-31 22:18:40,127 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [478136604] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:40,127 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:40,127 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:40,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593454205] [2024-10-31 22:18:40,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:40,128 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:40,128 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:40,128 INFO L85 PathProgramCache]: Analyzing trace with hash 320478992, now seen corresponding path program 1 times [2024-10-31 22:18:40,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:40,129 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632022344] [2024-10-31 22:18:40,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:40,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:40,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:40,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:40,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:40,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632022344] [2024-10-31 22:18:40,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632022344] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:40,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:40,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:40,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563328498] [2024-10-31 22:18:40,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:40,227 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:40,228 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:40,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:40,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:40,228 INFO L87 Difference]: Start difference. First operand 1180 states and 1751 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:40,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:40,268 INFO L93 Difference]: Finished difference Result 1180 states and 1750 transitions. [2024-10-31 22:18:40,268 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1750 transitions. [2024-10-31 22:18:40,276 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:40,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1750 transitions. [2024-10-31 22:18:40,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2024-10-31 22:18:40,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2024-10-31 22:18:40,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1750 transitions. [2024-10-31 22:18:40,287 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:40,287 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1750 transitions. [2024-10-31 22:18:40,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1750 transitions. [2024-10-31 22:18:40,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2024-10-31 22:18:40,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4830508474576272) internal successors, (1750), 1179 states have internal predecessors, (1750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:40,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1750 transitions. [2024-10-31 22:18:40,311 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1750 transitions. [2024-10-31 22:18:40,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:40,313 INFO L425 stractBuchiCegarLoop]: Abstraction has 1180 states and 1750 transitions. [2024-10-31 22:18:40,314 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:18:40,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1750 transitions. [2024-10-31 22:18:40,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:40,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:40,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:40,323 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:40,323 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:40,324 INFO L745 eck$LassoCheckResult]: Stem: 7457#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8238#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8239#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8173#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 7839#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7840#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8149#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7627#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7628#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8076#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8077#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7129#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7130#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7333#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7727#L939 assume !(0 == ~M_E~0); 7982#L939-2 assume !(0 == ~T1_E~0); 7983#L944-1 assume !(0 == ~T2_E~0); 7765#L949-1 assume !(0 == ~T3_E~0); 7763#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7764#L959-1 assume !(0 == ~T5_E~0); 8185#L964-1 assume !(0 == ~T6_E~0); 7478#L969-1 assume !(0 == ~T7_E~0); 7479#L974-1 assume !(0 == ~T8_E~0); 8136#L979-1 assume !(0 == ~T9_E~0); 8137#L984-1 assume !(0 == ~E_M~0); 7641#L989-1 assume !(0 == ~E_1~0); 7642#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7529#L999-1 assume !(0 == ~E_3~0); 7530#L1004-1 assume !(0 == ~E_4~0); 7197#L1009-1 assume !(0 == ~E_5~0); 7198#L1014-1 assume !(0 == ~E_6~0); 7526#L1019-1 assume !(0 == ~E_7~0); 8081#L1024-1 assume !(0 == ~E_8~0); 7450#L1029-1 assume !(0 == ~E_9~0); 7451#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7537#L460 assume 1 == ~m_pc~0; 7118#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7119#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8046#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8160#L1167 assume !(0 != activate_threads_~tmp~1#1); 7748#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7749#L479 assume 1 == ~t1_pc~0; 7728#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7729#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7201#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7202#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 7464#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7312#L498 assume !(1 == ~t2_pc~0); 7313#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7726#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7629#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7630#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8036#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8037#L517 assume 1 == ~t3_pc~0; 8247#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8248#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7136#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7137#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 7499#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8088#L536 assume !(1 == ~t4_pc~0); 7793#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7792#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7298#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7299#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 7786#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8018#L555 assume 1 == ~t5_pc~0; 8019#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8082#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8132#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7454#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 7338#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7235#L574 assume !(1 == ~t6_pc~0); 7236#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7892#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7619#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7620#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 8105#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8271#L593 assume 1 == ~t7_pc~0; 8272#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7471#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8190#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8288#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 8250#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7634#L612 assume !(1 == ~t8_pc~0); 7635#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8064#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8110#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8111#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 7894#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7895#L631 assume 1 == ~t9_pc~0; 7908#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7227#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7228#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7679#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 7731#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8089#L1047 assume !(1 == ~M_E~0); 7165#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7166#L1052-1 assume !(1 == ~T2_E~0); 7146#L1057-1 assume !(1 == ~T3_E~0); 7147#L1062-1 assume !(1 == ~T4_E~0); 7436#L1067-1 assume !(1 == ~T5_E~0); 7752#L1072-1 assume !(1 == ~T6_E~0); 7753#L1077-1 assume !(1 == ~T7_E~0); 7327#L1082-1 assume !(1 == ~T8_E~0); 7328#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7125#L1092-1 assume !(1 == ~E_M~0); 7126#L1097-1 assume !(1 == ~E_1~0); 7148#L1102-1 assume !(1 == ~E_2~0); 7952#L1107-1 assume !(1 == ~E_3~0); 7890#L1112-1 assume !(1 == ~E_4~0); 7891#L1117-1 assume !(1 == ~E_5~0); 7927#L1122-1 assume !(1 == ~E_6~0); 7808#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7541#L1132-1 assume !(1 == ~E_8~0); 7542#L1137-1 assume !(1 == ~E_9~0); 7435#L1142-1 assume { :end_inline_reset_delta_events } true; 7289#L1428-2 [2024-10-31 22:18:40,324 INFO L747 eck$LassoCheckResult]: Loop: 7289#L1428-2 assume !false; 7290#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7657#L914-1 assume !false; 7886#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7887#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7134#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7135#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7658#L783 assume !(0 != eval_~tmp~0#1); 8106#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7847#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7353#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7354#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7121#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7122#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7770#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7203#L964-3 assume !(0 == ~T6_E~0); 7204#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7404#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7405#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7857#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7858#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7459#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7460#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7991#L1004-3 assume !(0 == ~E_4~0); 7278#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7279#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7837#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7838#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7818#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7771#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7772#L460-33 assume 1 == ~m_pc~0; 7809#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7810#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8006#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7127#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7128#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7485#L479-33 assume !(1 == ~t1_pc~0); 7486#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7452#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7453#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8226#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8227#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7495#L498-33 assume 1 == ~t2_pc~0; 7496#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7242#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7709#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7880#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7351#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7352#L517-33 assume !(1 == ~t3_pc~0); 8280#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 8165#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7310#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7311#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7976#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7577#L536-33 assume 1 == ~t4_pc~0; 7578#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7655#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7656#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8140#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8141#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7172#L555-33 assume 1 == ~t5_pc~0; 7173#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7918#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7919#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7948#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7949#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7143#L574-33 assume !(1 == ~t6_pc~0); 7144#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 8153#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7740#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7741#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 7719#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7221#L593-33 assume 1 == ~t7_pc~0; 7222#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7687#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8177#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8004#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8005#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8127#L612-33 assume 1 == ~t8_pc~0; 8258#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8219#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7929#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7930#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7323#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7324#L631-33 assume !(1 == ~t9_pc~0); 7955#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 7264#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7265#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7523#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7379#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7380#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7545#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8184#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8113#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8114#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7272#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7273#L1072-3 assume !(1 == ~T6_E~0); 7669#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7505#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7506#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7571#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7885#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7804#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7805#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8154#L1112-3 assume !(1 == ~E_4~0); 7500#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7501#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7546#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7547#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7965#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7943#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7384#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7261#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7572#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 7573#L1447 assume !(0 == start_simulation_~tmp~3#1); 7689#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8133#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7412#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7195#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 7196#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7280#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7281#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7756#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 7289#L1428-2 [2024-10-31 22:18:40,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:40,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2024-10-31 22:18:40,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:40,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800591802] [2024-10-31 22:18:40,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:40,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:40,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:40,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:40,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:40,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800591802] [2024-10-31 22:18:40,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800591802] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:40,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:40,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:40,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1056347960] [2024-10-31 22:18:40,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:40,407 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:40,408 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:40,409 INFO L85 PathProgramCache]: Analyzing trace with hash 320478992, now seen corresponding path program 2 times [2024-10-31 22:18:40,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:40,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598828102] [2024-10-31 22:18:40,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:40,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:40,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:40,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:40,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:40,507 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598828102] [2024-10-31 22:18:40,507 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [598828102] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:40,507 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:40,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:40,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310827324] [2024-10-31 22:18:40,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:40,509 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:40,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:40,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:40,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:40,511 INFO L87 Difference]: Start difference. First operand 1180 states and 1750 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:40,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:40,543 INFO L93 Difference]: Finished difference Result 1180 states and 1749 transitions. [2024-10-31 22:18:40,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1749 transitions. [2024-10-31 22:18:40,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:40,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1749 transitions. [2024-10-31 22:18:40,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2024-10-31 22:18:40,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2024-10-31 22:18:40,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1749 transitions. [2024-10-31 22:18:40,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:40,562 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1749 transitions. [2024-10-31 22:18:40,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1749 transitions. [2024-10-31 22:18:40,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2024-10-31 22:18:40,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4822033898305085) internal successors, (1749), 1179 states have internal predecessors, (1749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:40,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1749 transitions. [2024-10-31 22:18:40,589 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1749 transitions. [2024-10-31 22:18:40,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:40,590 INFO L425 stractBuchiCegarLoop]: Abstraction has 1180 states and 1749 transitions. [2024-10-31 22:18:40,592 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:18:40,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1749 transitions. [2024-10-31 22:18:40,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:40,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:40,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:40,607 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:40,607 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:40,607 INFO L745 eck$LassoCheckResult]: Stem: 9822#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 9823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10605#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10606#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10540#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 10204#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10205#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10514#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9992#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9993#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10441#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10442#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9496#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9497#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9700#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10094#L939 assume !(0 == ~M_E~0); 10349#L939-2 assume !(0 == ~T1_E~0); 10350#L944-1 assume !(0 == ~T2_E~0); 10132#L949-1 assume !(0 == ~T3_E~0); 10130#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10131#L959-1 assume !(0 == ~T5_E~0); 10552#L964-1 assume !(0 == ~T6_E~0); 9845#L969-1 assume !(0 == ~T7_E~0); 9846#L974-1 assume !(0 == ~T8_E~0); 10501#L979-1 assume !(0 == ~T9_E~0); 10502#L984-1 assume !(0 == ~E_M~0); 10006#L989-1 assume !(0 == ~E_1~0); 10007#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9896#L999-1 assume !(0 == ~E_3~0); 9897#L1004-1 assume !(0 == ~E_4~0); 9562#L1009-1 assume !(0 == ~E_5~0); 9563#L1014-1 assume !(0 == ~E_6~0); 9891#L1019-1 assume !(0 == ~E_7~0); 10448#L1024-1 assume !(0 == ~E_8~0); 9817#L1029-1 assume !(0 == ~E_9~0); 9818#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9902#L460 assume 1 == ~m_pc~0; 9482#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9483#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10413#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10526#L1167 assume !(0 != activate_threads_~tmp~1#1); 10115#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10116#L479 assume 1 == ~t1_pc~0; 10095#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10096#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9566#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9567#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 9830#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9679#L498 assume !(1 == ~t2_pc~0); 9680#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10093#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9996#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9997#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10403#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10404#L517 assume 1 == ~t3_pc~0; 10611#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10612#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9503#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9504#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 9866#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10453#L536 assume !(1 == ~t4_pc~0); 10160#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10159#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9660#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9661#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 10153#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10381#L555 assume 1 == ~t5_pc~0; 10382#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10449#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10499#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9819#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 9703#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9602#L574 assume !(1 == ~t6_pc~0); 9603#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10259#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9986#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9987#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 10470#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10638#L593 assume 1 == ~t7_pc~0; 10639#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9838#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10555#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10655#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 10617#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10001#L612 assume !(1 == ~t8_pc~0); 10002#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10431#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10475#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10476#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 10261#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10262#L631 assume 1 == ~t9_pc~0; 10275#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9594#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9595#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10046#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 10098#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10456#L1047 assume !(1 == ~M_E~0); 9530#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9531#L1052-1 assume !(1 == ~T2_E~0); 9513#L1057-1 assume !(1 == ~T3_E~0); 9514#L1062-1 assume !(1 == ~T4_E~0); 9803#L1067-1 assume !(1 == ~T5_E~0); 10119#L1072-1 assume !(1 == ~T6_E~0); 10120#L1077-1 assume !(1 == ~T7_E~0); 9694#L1082-1 assume !(1 == ~T8_E~0); 9695#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9490#L1092-1 assume !(1 == ~E_M~0); 9491#L1097-1 assume !(1 == ~E_1~0); 9515#L1102-1 assume !(1 == ~E_2~0); 10319#L1107-1 assume !(1 == ~E_3~0); 10257#L1112-1 assume !(1 == ~E_4~0); 10258#L1117-1 assume !(1 == ~E_5~0); 10293#L1122-1 assume !(1 == ~E_6~0); 10175#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9906#L1132-1 assume !(1 == ~E_8~0); 9907#L1137-1 assume !(1 == ~E_9~0); 9800#L1142-1 assume { :end_inline_reset_delta_events } true; 9653#L1428-2 [2024-10-31 22:18:40,608 INFO L747 eck$LassoCheckResult]: Loop: 9653#L1428-2 assume !false; 9654#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10025#L914-1 assume !false; 10253#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10254#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9501#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9502#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10024#L783 assume !(0 != eval_~tmp~0#1); 10473#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10212#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10213#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9718#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9719#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9488#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9489#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10136#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9568#L964-3 assume !(0 == ~T6_E~0); 9569#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9771#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9772#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10224#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10225#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9826#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9827#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10358#L1004-3 assume !(0 == ~E_4~0); 9645#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9646#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10206#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10207#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10185#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10138#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10139#L460-33 assume 1 == ~m_pc~0; 10176#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10177#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10373#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9494#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9495#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9852#L479-33 assume !(1 == ~t1_pc~0); 9853#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9820#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9821#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10593#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10594#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9864#L498-33 assume !(1 == ~t2_pc~0); 9608#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 9609#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10076#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10247#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9720#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9721#L517-33 assume !(1 == ~t3_pc~0); 10647#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 10532#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9677#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9678#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10343#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9944#L536-33 assume 1 == ~t4_pc~0; 9945#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10022#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10023#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10507#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10508#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9539#L555-33 assume 1 == ~t5_pc~0; 9540#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10285#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10286#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10315#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10316#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9510#L574-33 assume !(1 == ~t6_pc~0); 9511#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10520#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10107#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10108#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 10086#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9588#L593-33 assume 1 == ~t7_pc~0; 9589#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10054#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10544#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10371#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10372#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10495#L612-33 assume 1 == ~t8_pc~0; 10625#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10586#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10296#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10297#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9690#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9691#L631-33 assume !(1 == ~t9_pc~0); 10322#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 9631#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9632#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9890#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9746#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9747#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9912#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10551#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10480#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10481#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9639#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9640#L1072-3 assume !(1 == ~T6_E~0); 10036#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9872#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9873#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9938#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10252#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10173#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10174#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10521#L1112-3 assume !(1 == ~E_4~0); 9867#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9868#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9913#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9914#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10332#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10310#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9751#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9628#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9939#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9940#L1447 assume !(0 == start_simulation_~tmp~3#1); 10056#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10500#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9779#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9564#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 9565#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9647#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9648#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10123#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 9653#L1428-2 [2024-10-31 22:18:40,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:40,609 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2024-10-31 22:18:40,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:40,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431655778] [2024-10-31 22:18:40,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:40,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:40,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:40,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:40,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:40,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431655778] [2024-10-31 22:18:40,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431655778] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:40,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:40,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:40,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053403414] [2024-10-31 22:18:40,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:40,676 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:40,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:40,676 INFO L85 PathProgramCache]: Analyzing trace with hash 1780472913, now seen corresponding path program 2 times [2024-10-31 22:18:40,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:40,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279356899] [2024-10-31 22:18:40,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:40,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:40,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:40,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:40,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:40,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1279356899] [2024-10-31 22:18:40,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1279356899] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:40,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:40,744 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:40,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038906459] [2024-10-31 22:18:40,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:40,744 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:40,745 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:40,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:40,746 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:40,746 INFO L87 Difference]: Start difference. First operand 1180 states and 1749 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:40,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:40,776 INFO L93 Difference]: Finished difference Result 1180 states and 1748 transitions. [2024-10-31 22:18:40,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1748 transitions. [2024-10-31 22:18:40,784 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:40,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1748 transitions. [2024-10-31 22:18:40,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2024-10-31 22:18:40,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2024-10-31 22:18:40,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1748 transitions. [2024-10-31 22:18:40,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:40,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1748 transitions. [2024-10-31 22:18:40,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1748 transitions. [2024-10-31 22:18:40,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2024-10-31 22:18:40,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4813559322033898) internal successors, (1748), 1179 states have internal predecessors, (1748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:40,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1748 transitions. [2024-10-31 22:18:40,819 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1748 transitions. [2024-10-31 22:18:40,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:40,822 INFO L425 stractBuchiCegarLoop]: Abstraction has 1180 states and 1748 transitions. [2024-10-31 22:18:40,822 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:18:40,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1748 transitions. [2024-10-31 22:18:40,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:40,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:40,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:40,831 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:40,831 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:40,831 INFO L745 eck$LassoCheckResult]: Stem: 12189#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12907#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 12571#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12572#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12881#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12359#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12360#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12808#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12809#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11863#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11864#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12067#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12461#L939 assume !(0 == ~M_E~0); 12716#L939-2 assume !(0 == ~T1_E~0); 12717#L944-1 assume !(0 == ~T2_E~0); 12499#L949-1 assume !(0 == ~T3_E~0); 12497#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12498#L959-1 assume !(0 == ~T5_E~0); 12919#L964-1 assume !(0 == ~T6_E~0); 12212#L969-1 assume !(0 == ~T7_E~0); 12213#L974-1 assume !(0 == ~T8_E~0); 12868#L979-1 assume !(0 == ~T9_E~0); 12869#L984-1 assume !(0 == ~E_M~0); 12373#L989-1 assume !(0 == ~E_1~0); 12374#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12263#L999-1 assume !(0 == ~E_3~0); 12264#L1004-1 assume !(0 == ~E_4~0); 11929#L1009-1 assume !(0 == ~E_5~0); 11930#L1014-1 assume !(0 == ~E_6~0); 12258#L1019-1 assume !(0 == ~E_7~0); 12815#L1024-1 assume !(0 == ~E_8~0); 12184#L1029-1 assume !(0 == ~E_9~0); 12185#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12269#L460 assume 1 == ~m_pc~0; 11849#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11850#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12780#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12893#L1167 assume !(0 != activate_threads_~tmp~1#1); 12482#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12483#L479 assume 1 == ~t1_pc~0; 12462#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12463#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11933#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11934#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 12197#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12046#L498 assume !(1 == ~t2_pc~0); 12047#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12460#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12363#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12364#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12770#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12771#L517 assume 1 == ~t3_pc~0; 12978#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12979#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11870#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11871#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 12233#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12820#L536 assume !(1 == ~t4_pc~0); 12527#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12526#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12028#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 12520#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12748#L555 assume 1 == ~t5_pc~0; 12749#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12816#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12866#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12186#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 12070#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11969#L574 assume !(1 == ~t6_pc~0); 11970#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12626#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12353#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12354#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 12837#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13005#L593 assume 1 == ~t7_pc~0; 13006#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12205#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12922#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13022#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 12984#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12368#L612 assume !(1 == ~t8_pc~0); 12369#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12798#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12842#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12843#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 12628#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12629#L631 assume 1 == ~t9_pc~0; 12642#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11961#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11962#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12413#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 12465#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12823#L1047 assume !(1 == ~M_E~0); 11897#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11898#L1052-1 assume !(1 == ~T2_E~0); 11880#L1057-1 assume !(1 == ~T3_E~0); 11881#L1062-1 assume !(1 == ~T4_E~0); 12170#L1067-1 assume !(1 == ~T5_E~0); 12486#L1072-1 assume !(1 == ~T6_E~0); 12487#L1077-1 assume !(1 == ~T7_E~0); 12061#L1082-1 assume !(1 == ~T8_E~0); 12062#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11857#L1092-1 assume !(1 == ~E_M~0); 11858#L1097-1 assume !(1 == ~E_1~0); 11882#L1102-1 assume !(1 == ~E_2~0); 12686#L1107-1 assume !(1 == ~E_3~0); 12624#L1112-1 assume !(1 == ~E_4~0); 12625#L1117-1 assume !(1 == ~E_5~0); 12660#L1122-1 assume !(1 == ~E_6~0); 12542#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12273#L1132-1 assume !(1 == ~E_8~0); 12274#L1137-1 assume !(1 == ~E_9~0); 12167#L1142-1 assume { :end_inline_reset_delta_events } true; 12020#L1428-2 [2024-10-31 22:18:40,832 INFO L747 eck$LassoCheckResult]: Loop: 12020#L1428-2 assume !false; 12021#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12392#L914-1 assume !false; 12620#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12621#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11868#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11869#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12391#L783 assume !(0 != eval_~tmp~0#1); 12840#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12579#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12580#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12085#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12086#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11855#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11856#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12503#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11935#L964-3 assume !(0 == ~T6_E~0); 11936#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12138#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12139#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12591#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12592#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12193#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12194#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12725#L1004-3 assume !(0 == ~E_4~0); 12012#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12013#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12573#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12574#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12552#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12505#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12506#L460-33 assume !(1 == ~m_pc~0); 12545#L460-35 is_master_triggered_~__retres1~0#1 := 0; 12544#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12740#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11861#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11862#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12219#L479-33 assume !(1 == ~t1_pc~0); 12220#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12187#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12188#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12960#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12961#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12231#L498-33 assume !(1 == ~t2_pc~0); 11975#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 11976#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12443#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12614#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12087#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12088#L517-33 assume !(1 == ~t3_pc~0); 13014#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 12899#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12044#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12045#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12710#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12311#L536-33 assume 1 == ~t4_pc~0; 12312#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12389#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12390#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12874#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12875#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11906#L555-33 assume 1 == ~t5_pc~0; 11907#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12652#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12653#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12682#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12683#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11877#L574-33 assume !(1 == ~t6_pc~0); 11878#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 12887#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12474#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12475#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 12453#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11955#L593-33 assume 1 == ~t7_pc~0; 11956#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12421#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12911#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12738#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12739#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12862#L612-33 assume 1 == ~t8_pc~0; 12992#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12953#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12663#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12664#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12057#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12058#L631-33 assume !(1 == ~t9_pc~0); 12689#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 11998#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11999#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12257#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12113#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12114#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12279#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12918#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12847#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12848#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12006#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12007#L1072-3 assume !(1 == ~T6_E~0); 12403#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12239#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12240#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12305#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12619#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12540#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12541#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12888#L1112-3 assume !(1 == ~E_4~0); 12234#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12235#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12280#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12281#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12699#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12677#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12118#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11995#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12306#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12307#L1447 assume !(0 == start_simulation_~tmp~3#1); 12423#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12867#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12146#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11931#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 11932#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12014#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12015#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12490#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 12020#L1428-2 [2024-10-31 22:18:40,833 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:40,833 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2024-10-31 22:18:40,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:40,833 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442086247] [2024-10-31 22:18:40,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:40,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:40,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:40,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:40,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:40,893 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442086247] [2024-10-31 22:18:40,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442086247] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:40,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:40,896 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:40,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206282387] [2024-10-31 22:18:40,897 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:40,897 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:40,897 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:40,898 INFO L85 PathProgramCache]: Analyzing trace with hash -1397309422, now seen corresponding path program 1 times [2024-10-31 22:18:40,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:40,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822606281] [2024-10-31 22:18:40,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:40,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:40,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:40,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:40,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:40,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822606281] [2024-10-31 22:18:40,967 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822606281] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:40,967 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:40,967 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:40,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818419633] [2024-10-31 22:18:40,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:40,969 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:40,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:40,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:40,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:40,971 INFO L87 Difference]: Start difference. First operand 1180 states and 1748 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:40,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:40,998 INFO L93 Difference]: Finished difference Result 1180 states and 1747 transitions. [2024-10-31 22:18:40,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1747 transitions. [2024-10-31 22:18:41,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:41,013 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1747 transitions. [2024-10-31 22:18:41,013 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2024-10-31 22:18:41,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2024-10-31 22:18:41,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1747 transitions. [2024-10-31 22:18:41,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:41,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1747 transitions. [2024-10-31 22:18:41,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1747 transitions. [2024-10-31 22:18:41,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2024-10-31 22:18:41,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.480508474576271) internal successors, (1747), 1179 states have internal predecessors, (1747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:41,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1747 transitions. [2024-10-31 22:18:41,041 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1747 transitions. [2024-10-31 22:18:41,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:41,043 INFO L425 stractBuchiCegarLoop]: Abstraction has 1180 states and 1747 transitions. [2024-10-31 22:18:41,044 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:18:41,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1747 transitions. [2024-10-31 22:18:41,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:41,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:41,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:41,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,053 INFO L745 eck$LassoCheckResult]: Stem: 14556#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15339#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15340#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15274#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 14938#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14939#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15248#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14726#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14727#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15175#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15176#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14230#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14231#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14434#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14828#L939 assume !(0 == ~M_E~0); 15083#L939-2 assume !(0 == ~T1_E~0); 15084#L944-1 assume !(0 == ~T2_E~0); 14866#L949-1 assume !(0 == ~T3_E~0); 14864#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14865#L959-1 assume !(0 == ~T5_E~0); 15286#L964-1 assume !(0 == ~T6_E~0); 14579#L969-1 assume !(0 == ~T7_E~0); 14580#L974-1 assume !(0 == ~T8_E~0); 15235#L979-1 assume !(0 == ~T9_E~0); 15236#L984-1 assume !(0 == ~E_M~0); 14740#L989-1 assume !(0 == ~E_1~0); 14741#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14630#L999-1 assume !(0 == ~E_3~0); 14631#L1004-1 assume !(0 == ~E_4~0); 14296#L1009-1 assume !(0 == ~E_5~0); 14297#L1014-1 assume !(0 == ~E_6~0); 14625#L1019-1 assume !(0 == ~E_7~0); 15182#L1024-1 assume !(0 == ~E_8~0); 14551#L1029-1 assume !(0 == ~E_9~0); 14552#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14636#L460 assume 1 == ~m_pc~0; 14216#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14217#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15147#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15260#L1167 assume !(0 != activate_threads_~tmp~1#1); 14849#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14850#L479 assume 1 == ~t1_pc~0; 14829#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14830#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14301#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 14564#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14413#L498 assume !(1 == ~t2_pc~0); 14414#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14827#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14731#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15137#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15138#L517 assume 1 == ~t3_pc~0; 15345#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15346#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14237#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14238#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 14600#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15187#L536 assume !(1 == ~t4_pc~0); 14894#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14893#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14394#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14395#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 14887#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15115#L555 assume 1 == ~t5_pc~0; 15116#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15183#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15233#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14553#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 14437#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14336#L574 assume !(1 == ~t6_pc~0); 14337#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14993#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14720#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14721#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 15204#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15372#L593 assume 1 == ~t7_pc~0; 15373#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14572#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15289#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15389#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 15351#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14735#L612 assume !(1 == ~t8_pc~0); 14736#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15165#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15209#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15210#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 14995#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14996#L631 assume 1 == ~t9_pc~0; 15009#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14328#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14329#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14780#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 14832#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15190#L1047 assume !(1 == ~M_E~0); 14264#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14265#L1052-1 assume !(1 == ~T2_E~0); 14247#L1057-1 assume !(1 == ~T3_E~0); 14248#L1062-1 assume !(1 == ~T4_E~0); 14537#L1067-1 assume !(1 == ~T5_E~0); 14853#L1072-1 assume !(1 == ~T6_E~0); 14854#L1077-1 assume !(1 == ~T7_E~0); 14428#L1082-1 assume !(1 == ~T8_E~0); 14429#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14224#L1092-1 assume !(1 == ~E_M~0); 14225#L1097-1 assume !(1 == ~E_1~0); 14249#L1102-1 assume !(1 == ~E_2~0); 15053#L1107-1 assume !(1 == ~E_3~0); 14991#L1112-1 assume !(1 == ~E_4~0); 14992#L1117-1 assume !(1 == ~E_5~0); 15027#L1122-1 assume !(1 == ~E_6~0); 14909#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14640#L1132-1 assume !(1 == ~E_8~0); 14641#L1137-1 assume !(1 == ~E_9~0); 14534#L1142-1 assume { :end_inline_reset_delta_events } true; 14387#L1428-2 [2024-10-31 22:18:41,053 INFO L747 eck$LassoCheckResult]: Loop: 14387#L1428-2 assume !false; 14388#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14759#L914-1 assume !false; 14987#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14988#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14235#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14236#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14758#L783 assume !(0 != eval_~tmp~0#1); 15207#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14946#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14947#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14452#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14453#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14222#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14223#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14870#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14302#L964-3 assume !(0 == ~T6_E~0); 14303#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14505#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14506#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14958#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14959#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14560#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14561#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15092#L1004-3 assume !(0 == ~E_4~0); 14379#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14380#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14940#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14941#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14919#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14872#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14873#L460-33 assume !(1 == ~m_pc~0); 14912#L460-35 is_master_triggered_~__retres1~0#1 := 0; 14911#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15107#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14228#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14229#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14586#L479-33 assume !(1 == ~t1_pc~0); 14587#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 14554#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14555#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15327#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15328#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14598#L498-33 assume !(1 == ~t2_pc~0); 14342#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 14343#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14810#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14981#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14454#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14455#L517-33 assume !(1 == ~t3_pc~0); 15381#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 15266#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14411#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14412#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15077#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14678#L536-33 assume 1 == ~t4_pc~0; 14679#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14756#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14757#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15241#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15242#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14273#L555-33 assume 1 == ~t5_pc~0; 14274#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15019#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15020#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15049#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15050#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14244#L574-33 assume !(1 == ~t6_pc~0); 14245#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 15254#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14841#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14842#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 14820#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14322#L593-33 assume 1 == ~t7_pc~0; 14323#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14788#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15278#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15105#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15106#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15229#L612-33 assume !(1 == ~t8_pc~0); 15360#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 15320#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15030#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15031#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14424#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14425#L631-33 assume !(1 == ~t9_pc~0); 15056#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 14365#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14366#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14624#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14480#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14481#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14646#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15285#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15214#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15215#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14373#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14374#L1072-3 assume !(1 == ~T6_E~0); 14770#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14606#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14607#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14672#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14986#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14907#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14908#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15255#L1112-3 assume !(1 == ~E_4~0); 14601#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14602#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14647#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14648#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15066#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15044#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14485#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14362#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14673#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14674#L1447 assume !(0 == start_simulation_~tmp~3#1); 14790#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15234#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14513#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14298#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 14299#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14381#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14382#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14857#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 14387#L1428-2 [2024-10-31 22:18:41,054 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:41,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2024-10-31 22:18:41,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:41,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323044414] [2024-10-31 22:18:41,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:41,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:41,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:41,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:41,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:41,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323044414] [2024-10-31 22:18:41,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323044414] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:41,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:41,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:41,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074917909] [2024-10-31 22:18:41,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:41,108 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:41,108 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:41,108 INFO L85 PathProgramCache]: Analyzing trace with hash 2024180179, now seen corresponding path program 1 times [2024-10-31 22:18:41,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:41,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713457852] [2024-10-31 22:18:41,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:41,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:41,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:41,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:41,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:41,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713457852] [2024-10-31 22:18:41,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [713457852] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:41,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:41,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:41,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918729354] [2024-10-31 22:18:41,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:41,199 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:41,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:41,199 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:41,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:41,200 INFO L87 Difference]: Start difference. First operand 1180 states and 1747 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:41,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:41,226 INFO L93 Difference]: Finished difference Result 1180 states and 1746 transitions. [2024-10-31 22:18:41,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1746 transitions. [2024-10-31 22:18:41,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:41,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1746 transitions. [2024-10-31 22:18:41,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2024-10-31 22:18:41,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2024-10-31 22:18:41,242 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1746 transitions. [2024-10-31 22:18:41,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:41,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1746 transitions. [2024-10-31 22:18:41,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1746 transitions. [2024-10-31 22:18:41,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2024-10-31 22:18:41,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4796610169491526) internal successors, (1746), 1179 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:41,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1746 transitions. [2024-10-31 22:18:41,266 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1746 transitions. [2024-10-31 22:18:41,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:41,268 INFO L425 stractBuchiCegarLoop]: Abstraction has 1180 states and 1746 transitions. [2024-10-31 22:18:41,268 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:18:41,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1746 transitions. [2024-10-31 22:18:41,276 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:41,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:41,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:41,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,282 INFO L745 eck$LassoCheckResult]: Stem: 16923#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 16924#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17706#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17707#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17641#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 17305#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17306#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17617#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17093#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17094#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17544#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17545#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16597#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16598#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16801#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17195#L939 assume !(0 == ~M_E~0); 17450#L939-2 assume !(0 == ~T1_E~0); 17451#L944-1 assume !(0 == ~T2_E~0); 17233#L949-1 assume !(0 == ~T3_E~0); 17231#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17232#L959-1 assume !(0 == ~T5_E~0); 17653#L964-1 assume !(0 == ~T6_E~0); 16946#L969-1 assume !(0 == ~T7_E~0); 16947#L974-1 assume !(0 == ~T8_E~0); 17602#L979-1 assume !(0 == ~T9_E~0); 17603#L984-1 assume !(0 == ~E_M~0); 17107#L989-1 assume !(0 == ~E_1~0); 17108#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16997#L999-1 assume !(0 == ~E_3~0); 16998#L1004-1 assume !(0 == ~E_4~0); 16665#L1009-1 assume !(0 == ~E_5~0); 16666#L1014-1 assume !(0 == ~E_6~0); 16994#L1019-1 assume !(0 == ~E_7~0); 17549#L1024-1 assume !(0 == ~E_8~0); 16918#L1029-1 assume !(0 == ~E_9~0); 16919#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17003#L460 assume 1 == ~m_pc~0; 16583#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16584#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17514#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17627#L1167 assume !(0 != activate_threads_~tmp~1#1); 17216#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17217#L479 assume 1 == ~t1_pc~0; 17196#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17197#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16667#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16668#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 16931#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16780#L498 assume !(1 == ~t2_pc~0); 16781#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17194#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17097#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17098#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17504#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17505#L517 assume 1 == ~t3_pc~0; 17714#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17715#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16604#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16605#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 16967#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17554#L536 assume !(1 == ~t4_pc~0); 17261#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17260#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16761#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16762#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 17254#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17484#L555 assume 1 == ~t5_pc~0; 17485#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17550#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17600#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16920#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 16804#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16703#L574 assume !(1 == ~t6_pc~0); 16704#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17360#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17087#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17088#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 17571#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17739#L593 assume 1 == ~t7_pc~0; 17740#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16939#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17656#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17756#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 17718#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17102#L612 assume !(1 == ~t8_pc~0); 17103#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17532#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17576#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17577#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 17362#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17363#L631 assume 1 == ~t9_pc~0; 17376#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16695#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16696#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17147#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 17199#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17557#L1047 assume !(1 == ~M_E~0); 16631#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16632#L1052-1 assume !(1 == ~T2_E~0); 16614#L1057-1 assume !(1 == ~T3_E~0); 16615#L1062-1 assume !(1 == ~T4_E~0); 16904#L1067-1 assume !(1 == ~T5_E~0); 17220#L1072-1 assume !(1 == ~T6_E~0); 17221#L1077-1 assume !(1 == ~T7_E~0); 16795#L1082-1 assume !(1 == ~T8_E~0); 16796#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16591#L1092-1 assume !(1 == ~E_M~0); 16592#L1097-1 assume !(1 == ~E_1~0); 16616#L1102-1 assume !(1 == ~E_2~0); 17420#L1107-1 assume !(1 == ~E_3~0); 17358#L1112-1 assume !(1 == ~E_4~0); 17359#L1117-1 assume !(1 == ~E_5~0); 17394#L1122-1 assume !(1 == ~E_6~0); 17276#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17007#L1132-1 assume !(1 == ~E_8~0); 17008#L1137-1 assume !(1 == ~E_9~0); 16901#L1142-1 assume { :end_inline_reset_delta_events } true; 16754#L1428-2 [2024-10-31 22:18:41,282 INFO L747 eck$LassoCheckResult]: Loop: 16754#L1428-2 assume !false; 16755#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17126#L914-1 assume !false; 17354#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17355#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16602#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16603#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17125#L783 assume !(0 != eval_~tmp~0#1); 17574#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17313#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17314#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16819#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16820#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16589#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16590#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17237#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16669#L964-3 assume !(0 == ~T6_E~0); 16670#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16872#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16873#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17325#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17326#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16927#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16928#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17459#L1004-3 assume !(0 == ~E_4~0); 16746#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16747#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17307#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17308#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17286#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17239#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17240#L460-33 assume 1 == ~m_pc~0; 17277#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17278#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17474#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16595#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16596#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16955#L479-33 assume !(1 == ~t1_pc~0); 16956#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16921#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16922#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17694#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17695#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16965#L498-33 assume !(1 == ~t2_pc~0); 16709#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 16710#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17177#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17348#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16821#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16822#L517-33 assume !(1 == ~t3_pc~0); 17748#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 17633#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16778#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16779#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17444#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17045#L536-33 assume 1 == ~t4_pc~0; 17046#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17123#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17124#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17608#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17609#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16640#L555-33 assume 1 == ~t5_pc~0; 16641#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17386#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17387#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17416#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17417#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16611#L574-33 assume !(1 == ~t6_pc~0); 16612#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 17621#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17208#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17209#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 17187#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16689#L593-33 assume 1 == ~t7_pc~0; 16690#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17156#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17644#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17472#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17473#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17595#L612-33 assume 1 == ~t8_pc~0; 17726#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17687#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17397#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17398#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16786#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16787#L631-33 assume 1 == ~t9_pc~0; 17651#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16730#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16731#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16989#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16847#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16848#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17013#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17652#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17581#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17582#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16740#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16741#L1072-3 assume !(1 == ~T6_E~0); 17137#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16973#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16974#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17039#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17353#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17272#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17273#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17622#L1112-3 assume !(1 == ~E_4~0); 16968#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16969#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17014#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17015#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17433#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17411#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16849#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16726#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17040#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17041#L1447 assume !(0 == start_simulation_~tmp~3#1); 17157#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17601#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16880#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16663#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 16664#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16748#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16749#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 17224#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 16754#L1428-2 [2024-10-31 22:18:41,283 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:41,283 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2024-10-31 22:18:41,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:41,283 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386552026] [2024-10-31 22:18:41,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:41,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:41,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:41,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:41,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:41,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386552026] [2024-10-31 22:18:41,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386552026] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:41,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:41,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:41,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854423631] [2024-10-31 22:18:41,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:41,346 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:41,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:41,346 INFO L85 PathProgramCache]: Analyzing trace with hash -1557566000, now seen corresponding path program 1 times [2024-10-31 22:18:41,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:41,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440286333] [2024-10-31 22:18:41,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:41,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:41,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:41,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:41,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:41,419 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440286333] [2024-10-31 22:18:41,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440286333] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:41,421 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:41,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:41,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782356811] [2024-10-31 22:18:41,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:41,422 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:41,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:41,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:41,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:41,423 INFO L87 Difference]: Start difference. First operand 1180 states and 1746 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:41,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:41,449 INFO L93 Difference]: Finished difference Result 1180 states and 1745 transitions. [2024-10-31 22:18:41,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1745 transitions. [2024-10-31 22:18:41,458 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:41,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1745 transitions. [2024-10-31 22:18:41,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2024-10-31 22:18:41,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2024-10-31 22:18:41,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1745 transitions. [2024-10-31 22:18:41,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:41,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1745 transitions. [2024-10-31 22:18:41,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1745 transitions. [2024-10-31 22:18:41,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2024-10-31 22:18:41,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.478813559322034) internal successors, (1745), 1179 states have internal predecessors, (1745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:41,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1745 transitions. [2024-10-31 22:18:41,491 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1745 transitions. [2024-10-31 22:18:41,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:41,494 INFO L425 stractBuchiCegarLoop]: Abstraction has 1180 states and 1745 transitions. [2024-10-31 22:18:41,494 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:18:41,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1745 transitions. [2024-10-31 22:18:41,500 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2024-10-31 22:18:41,500 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:41,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:41,502 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,503 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,503 INFO L745 eck$LassoCheckResult]: Stem: 19292#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20073#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20074#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20008#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 19672#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19673#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19984#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19460#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19461#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19911#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19912#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18964#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18965#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19168#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19562#L939 assume !(0 == ~M_E~0); 19817#L939-2 assume !(0 == ~T1_E~0); 19818#L944-1 assume !(0 == ~T2_E~0); 19600#L949-1 assume !(0 == ~T3_E~0); 19598#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19599#L959-1 assume !(0 == ~T5_E~0); 20020#L964-1 assume !(0 == ~T6_E~0); 19313#L969-1 assume !(0 == ~T7_E~0); 19314#L974-1 assume !(0 == ~T8_E~0); 19971#L979-1 assume !(0 == ~T9_E~0); 19972#L984-1 assume !(0 == ~E_M~0); 19474#L989-1 assume !(0 == ~E_1~0); 19475#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19364#L999-1 assume !(0 == ~E_3~0); 19365#L1004-1 assume !(0 == ~E_4~0); 19032#L1009-1 assume !(0 == ~E_5~0); 19033#L1014-1 assume !(0 == ~E_6~0); 19361#L1019-1 assume !(0 == ~E_7~0); 19916#L1024-1 assume !(0 == ~E_8~0); 19285#L1029-1 assume !(0 == ~E_9~0); 19286#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19370#L460 assume 1 == ~m_pc~0; 18953#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18954#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19881#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19994#L1167 assume !(0 != activate_threads_~tmp~1#1); 19583#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19584#L479 assume 1 == ~t1_pc~0; 19563#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19564#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19035#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 19298#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19147#L498 assume !(1 == ~t2_pc~0); 19148#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19561#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19464#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19465#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19871#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19872#L517 assume 1 == ~t3_pc~0; 20081#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20082#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18971#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18972#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 19334#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19923#L536 assume !(1 == ~t4_pc~0); 19628#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19627#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19133#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19134#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 19621#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19851#L555 assume 1 == ~t5_pc~0; 19852#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19917#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19967#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19287#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 19171#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19070#L574 assume !(1 == ~t6_pc~0); 19071#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19727#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19454#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19455#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 19940#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20106#L593 assume 1 == ~t7_pc~0; 20107#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19306#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20023#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20123#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 20085#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19469#L612 assume !(1 == ~t8_pc~0); 19470#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19899#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19943#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19944#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 19729#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19730#L631 assume 1 == ~t9_pc~0; 19743#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19062#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19063#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19514#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 19566#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19924#L1047 assume !(1 == ~M_E~0); 18998#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18999#L1052-1 assume !(1 == ~T2_E~0); 18981#L1057-1 assume !(1 == ~T3_E~0); 18982#L1062-1 assume !(1 == ~T4_E~0); 19271#L1067-1 assume !(1 == ~T5_E~0); 19587#L1072-1 assume !(1 == ~T6_E~0); 19588#L1077-1 assume !(1 == ~T7_E~0); 19162#L1082-1 assume !(1 == ~T8_E~0); 19163#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18960#L1092-1 assume !(1 == ~E_M~0); 18961#L1097-1 assume !(1 == ~E_1~0); 18983#L1102-1 assume !(1 == ~E_2~0); 19787#L1107-1 assume !(1 == ~E_3~0); 19725#L1112-1 assume !(1 == ~E_4~0); 19726#L1117-1 assume !(1 == ~E_5~0); 19761#L1122-1 assume !(1 == ~E_6~0); 19643#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19376#L1132-1 assume !(1 == ~E_8~0); 19377#L1137-1 assume !(1 == ~E_9~0); 19268#L1142-1 assume { :end_inline_reset_delta_events } true; 19121#L1428-2 [2024-10-31 22:18:41,504 INFO L747 eck$LassoCheckResult]: Loop: 19121#L1428-2 assume !false; 19122#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19493#L914-1 assume !false; 19721#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19722#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 18969#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18970#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19492#L783 assume !(0 != eval_~tmp~0#1); 19941#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19682#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19186#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19187#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18956#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18957#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19605#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19036#L964-3 assume !(0 == ~T6_E~0); 19037#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19239#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19240#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19692#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19693#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19294#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19295#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19826#L1004-3 assume !(0 == ~E_4~0); 19113#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19114#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19674#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19675#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19653#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19606#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19607#L460-33 assume 1 == ~m_pc~0; 19645#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19646#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19841#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18962#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18963#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19322#L479-33 assume !(1 == ~t1_pc~0); 19323#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 19288#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19289#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20061#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20062#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19332#L498-33 assume !(1 == ~t2_pc~0); 19076#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19077#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19544#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19715#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19188#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19189#L517-33 assume !(1 == ~t3_pc~0); 20115#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 20000#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19145#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19146#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19811#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19409#L536-33 assume 1 == ~t4_pc~0; 19410#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19490#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19491#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19975#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19976#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19004#L555-33 assume 1 == ~t5_pc~0; 19005#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19753#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19754#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19783#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19784#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18976#L574-33 assume !(1 == ~t6_pc~0); 18977#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 19988#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19575#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19576#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 19554#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19054#L593-33 assume !(1 == ~t7_pc~0); 19056#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 19519#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20011#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19839#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19840#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19962#L612-33 assume 1 == ~t8_pc~0; 20093#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20054#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19764#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19765#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19156#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19157#L631-33 assume 1 == ~t9_pc~0; 20018#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19099#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19100#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19356#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19214#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19215#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19380#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20019#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19948#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19949#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19107#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19108#L1072-3 assume !(1 == ~T6_E~0); 19504#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19340#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19341#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19406#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19720#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19639#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19640#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19989#L1112-3 assume !(1 == ~E_4~0); 19335#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19336#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19381#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19382#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19800#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19778#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19216#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19093#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19407#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 19408#L1447 assume !(0 == start_simulation_~tmp~3#1); 19524#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19968#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19247#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19030#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 19031#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19115#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19116#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19591#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 19121#L1428-2 [2024-10-31 22:18:41,504 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:41,505 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2024-10-31 22:18:41,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:41,505 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131878334] [2024-10-31 22:18:41,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:41,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:41,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:41,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:41,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:41,614 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131878334] [2024-10-31 22:18:41,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2131878334] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:41,614 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:41,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:41,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301659437] [2024-10-31 22:18:41,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:41,615 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:41,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:41,616 INFO L85 PathProgramCache]: Analyzing trace with hash 636560081, now seen corresponding path program 1 times [2024-10-31 22:18:41,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:41,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823832804] [2024-10-31 22:18:41,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:41,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:41,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:41,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:41,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:41,679 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823832804] [2024-10-31 22:18:41,679 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1823832804] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:41,680 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:41,680 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:41,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017418613] [2024-10-31 22:18:41,680 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:41,680 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:41,681 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:41,681 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:41,681 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:41,681 INFO L87 Difference]: Start difference. First operand 1180 states and 1745 transitions. cyclomatic complexity: 566 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:41,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:41,857 INFO L93 Difference]: Finished difference Result 2161 states and 3183 transitions. [2024-10-31 22:18:41,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2161 states and 3183 transitions. [2024-10-31 22:18:41,870 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2024-10-31 22:18:41,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2161 states to 2161 states and 3183 transitions. [2024-10-31 22:18:41,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2161 [2024-10-31 22:18:41,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2161 [2024-10-31 22:18:41,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2161 states and 3183 transitions. [2024-10-31 22:18:41,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:41,887 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3183 transitions. [2024-10-31 22:18:41,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2161 states and 3183 transitions. [2024-10-31 22:18:41,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2161 to 2161. [2024-10-31 22:18:41,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2161 states, 2161 states have (on average 1.4729291994447016) internal successors, (3183), 2160 states have internal predecessors, (3183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:41,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2161 states to 2161 states and 3183 transitions. [2024-10-31 22:18:41,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3183 transitions. [2024-10-31 22:18:41,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:41,936 INFO L425 stractBuchiCegarLoop]: Abstraction has 2161 states and 3183 transitions. [2024-10-31 22:18:41,937 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:18:41,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2161 states and 3183 transitions. [2024-10-31 22:18:41,946 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2024-10-31 22:18:41,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:41,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:41,949 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,949 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,949 INFO L745 eck$LassoCheckResult]: Stem: 22644#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 22645#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23494#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23495#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23416#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 23036#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23037#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23387#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22819#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22820#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23300#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23301#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22315#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22316#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22519#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22921#L939 assume !(0 == ~M_E~0); 23190#L939-2 assume !(0 == ~T1_E~0); 23191#L944-1 assume !(0 == ~T2_E~0); 22959#L949-1 assume !(0 == ~T3_E~0); 22957#L954-1 assume !(0 == ~T4_E~0); 22958#L959-1 assume !(0 == ~T5_E~0); 23432#L964-1 assume !(0 == ~T6_E~0); 22665#L969-1 assume !(0 == ~T7_E~0); 22666#L974-1 assume !(0 == ~T8_E~0); 23372#L979-1 assume !(0 == ~T9_E~0); 23373#L984-1 assume !(0 == ~E_M~0); 22833#L989-1 assume !(0 == ~E_1~0); 22834#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22716#L999-1 assume !(0 == ~E_3~0); 22717#L1004-1 assume !(0 == ~E_4~0); 22383#L1009-1 assume !(0 == ~E_5~0); 22384#L1014-1 assume !(0 == ~E_6~0); 22713#L1019-1 assume !(0 == ~E_7~0); 23305#L1024-1 assume !(0 == ~E_8~0); 22637#L1029-1 assume !(0 == ~E_9~0); 22638#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22724#L460 assume 1 == ~m_pc~0; 22304#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22305#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23266#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23400#L1167 assume !(0 != activate_threads_~tmp~1#1); 22942#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22943#L479 assume 1 == ~t1_pc~0; 22922#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22923#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22387#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22388#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 22651#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22498#L498 assume !(1 == ~t2_pc~0); 22499#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22920#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22821#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22822#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23255#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23256#L517 assume 1 == ~t3_pc~0; 23506#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23507#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22322#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22323#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 22686#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23315#L536 assume !(1 == ~t4_pc~0); 22988#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22987#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22484#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22485#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 22981#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23233#L555 assume 1 == ~t5_pc~0; 23234#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23306#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23368#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22641#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 22524#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22421#L574 assume !(1 == ~t6_pc~0); 22422#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23089#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22809#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22810#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 23335#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23539#L593 assume 1 == ~t7_pc~0; 23540#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22658#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23437#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23565#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 23510#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22826#L612 assume !(1 == ~t8_pc~0); 22827#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23285#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23341#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23342#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 23091#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23092#L631 assume 1 == ~t9_pc~0; 23106#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22413#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22414#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22872#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 22925#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23317#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 22351#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22352#L1052-1 assume !(1 == ~T2_E~0); 22332#L1057-1 assume !(1 == ~T3_E~0); 22333#L1062-1 assume !(1 == ~T4_E~0); 22623#L1067-1 assume !(1 == ~T5_E~0); 22946#L1072-1 assume !(1 == ~T6_E~0); 22947#L1077-1 assume !(1 == ~T7_E~0); 22513#L1082-1 assume !(1 == ~T8_E~0); 22514#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22311#L1092-1 assume !(1 == ~E_M~0); 22312#L1097-1 assume !(1 == ~E_1~0); 22334#L1102-1 assume !(1 == ~E_2~0); 23158#L1107-1 assume !(1 == ~E_3~0); 23087#L1112-1 assume !(1 == ~E_4~0); 23088#L1117-1 assume !(1 == ~E_5~0); 23605#L1122-1 assume !(1 == ~E_6~0); 23603#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23602#L1132-1 assume !(1 == ~E_8~0); 23601#L1137-1 assume !(1 == ~E_9~0); 23600#L1142-1 assume { :end_inline_reset_delta_events } true; 23595#L1428-2 [2024-10-31 22:18:41,950 INFO L747 eck$LassoCheckResult]: Loop: 23595#L1428-2 assume !false; 23592#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23148#L914-1 assume !false; 23083#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23084#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23581#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23580#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23336#L783 assume !(0 != eval_~tmp~0#1); 23337#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23043#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23044#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22539#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22540#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22307#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22308#L954-3 assume !(0 == ~T4_E~0); 22965#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22389#L964-3 assume !(0 == ~T6_E~0); 22390#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22591#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22592#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23054#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23055#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22646#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22647#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23201#L1004-3 assume !(0 == ~E_4~0); 22464#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22465#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23034#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23035#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23015#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22966#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22967#L460-33 assume 1 == ~m_pc~0; 23005#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23006#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23220#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22313#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22314#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22672#L479-33 assume !(1 == ~t1_pc~0); 22673#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 23375#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24388#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24387#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24386#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24385#L498-33 assume !(1 == ~t2_pc~0); 24384#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 24382#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24381#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24380#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24379#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24378#L517-33 assume !(1 == ~t3_pc~0); 24376#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 24375#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24374#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24373#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24372#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24371#L536-33 assume 1 == ~t4_pc~0; 24369#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24368#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24367#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24366#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24365#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24364#L555-33 assume !(1 == ~t5_pc~0); 24362#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 24361#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24360#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24359#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24358#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24357#L574-33 assume 1 == ~t6_pc~0; 24355#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24354#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24353#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24352#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 24351#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24350#L593-33 assume 1 == ~t7_pc~0; 24348#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24347#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24346#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24345#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24344#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24343#L612-33 assume !(1 == ~t8_pc~0); 24341#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 24340#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24339#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24338#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24337#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24336#L631-33 assume 1 == ~t9_pc~0; 24334#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24333#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24332#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24331#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24330#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24329#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22732#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24328#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24327#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24326#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23578#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24325#L1072-3 assume !(1 == ~T6_E~0); 24324#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22692#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22693#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22759#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23082#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23000#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23001#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23394#L1112-3 assume !(1 == ~E_4~0); 22687#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22688#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22734#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22735#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23171#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23149#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22571#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22444#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22761#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 22762#L1447 assume !(0 == start_simulation_~tmp~3#1); 22882#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23369#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23649#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23646#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 23644#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23611#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23610#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23599#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 23595#L1428-2 [2024-10-31 22:18:41,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:41,951 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2024-10-31 22:18:41,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:41,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [883730040] [2024-10-31 22:18:41,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:41,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:41,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:42,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:42,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:42,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [883730040] [2024-10-31 22:18:42,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [883730040] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:42,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:42,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:42,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627869500] [2024-10-31 22:18:42,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:42,012 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:42,012 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:42,012 INFO L85 PathProgramCache]: Analyzing trace with hash 69234191, now seen corresponding path program 1 times [2024-10-31 22:18:42,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:42,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [512219320] [2024-10-31 22:18:42,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:42,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:42,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:42,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:42,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:42,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [512219320] [2024-10-31 22:18:42,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [512219320] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:42,065 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:42,065 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:42,065 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402876303] [2024-10-31 22:18:42,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:42,066 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:42,066 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:42,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:42,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:42,067 INFO L87 Difference]: Start difference. First operand 2161 states and 3183 transitions. cyclomatic complexity: 1024 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:42,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:42,151 INFO L93 Difference]: Finished difference Result 2161 states and 3153 transitions. [2024-10-31 22:18:42,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2161 states and 3153 transitions. [2024-10-31 22:18:42,164 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2024-10-31 22:18:42,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2161 states to 2161 states and 3153 transitions. [2024-10-31 22:18:42,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2161 [2024-10-31 22:18:42,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2161 [2024-10-31 22:18:42,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2161 states and 3153 transitions. [2024-10-31 22:18:42,180 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:42,180 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3153 transitions. [2024-10-31 22:18:42,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2161 states and 3153 transitions. [2024-10-31 22:18:42,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2161 to 2161. [2024-10-31 22:18:42,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2161 states, 2161 states have (on average 1.4590467376214715) internal successors, (3153), 2160 states have internal predecessors, (3153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:42,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2161 states to 2161 states and 3153 transitions. [2024-10-31 22:18:42,228 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3153 transitions. [2024-10-31 22:18:42,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:42,229 INFO L425 stractBuchiCegarLoop]: Abstraction has 2161 states and 3153 transitions. [2024-10-31 22:18:42,229 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:18:42,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2161 states and 3153 transitions. [2024-10-31 22:18:42,240 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2024-10-31 22:18:42,240 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:42,240 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:42,242 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:42,242 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:42,242 INFO L745 eck$LassoCheckResult]: Stem: 26973#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 26974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27732#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 27365#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27366#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27705#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27145#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27146#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27624#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27625#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26644#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26645#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26847#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27249#L939 assume !(0 == ~M_E~0); 27524#L939-2 assume !(0 == ~T1_E~0); 27525#L944-1 assume !(0 == ~T2_E~0); 27287#L949-1 assume !(0 == ~T3_E~0); 27285#L954-1 assume !(0 == ~T4_E~0); 27286#L959-1 assume !(0 == ~T5_E~0); 27746#L964-1 assume !(0 == ~T6_E~0); 26994#L969-1 assume !(0 == ~T7_E~0); 26995#L974-1 assume !(0 == ~T8_E~0); 27691#L979-1 assume !(0 == ~T9_E~0); 27692#L984-1 assume !(0 == ~E_M~0); 27159#L989-1 assume !(0 == ~E_1~0); 27160#L994-1 assume !(0 == ~E_2~0); 27046#L999-1 assume !(0 == ~E_3~0); 27047#L1004-1 assume !(0 == ~E_4~0); 26712#L1009-1 assume !(0 == ~E_5~0); 26713#L1014-1 assume !(0 == ~E_6~0); 27043#L1019-1 assume !(0 == ~E_7~0); 27629#L1024-1 assume !(0 == ~E_8~0); 26966#L1029-1 assume !(0 == ~E_9~0); 26967#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27055#L460 assume 1 == ~m_pc~0; 26633#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26634#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27590#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27718#L1167 assume !(0 != activate_threads_~tmp~1#1); 27270#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27271#L479 assume 1 == ~t1_pc~0; 27250#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27251#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26718#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26719#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 26981#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26826#L498 assume !(1 == ~t2_pc~0); 26827#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27248#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27147#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27148#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27579#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27580#L517 assume 1 == ~t3_pc~0; 27809#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27810#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26651#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26652#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 27015#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27638#L536 assume !(1 == ~t4_pc~0); 27315#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27314#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26812#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26813#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 27309#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27560#L555 assume 1 == ~t5_pc~0; 27561#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27630#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27687#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26970#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 26852#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26750#L574 assume !(1 == ~t6_pc~0); 26751#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27421#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27137#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27138#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 27657#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27839#L593 assume 1 == ~t7_pc~0; 27840#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26987#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27751#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27858#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 27813#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27152#L612 assume !(1 == ~t8_pc~0); 27153#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27610#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27663#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27664#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 27423#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27424#L631 assume 1 == ~t9_pc~0; 27437#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26742#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26743#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27199#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 27253#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27639#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 27640#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28107#L1052-1 assume !(1 == ~T2_E~0); 28106#L1057-1 assume !(1 == ~T3_E~0); 28105#L1062-1 assume !(1 == ~T4_E~0); 26951#L1067-1 assume !(1 == ~T5_E~0); 28104#L1072-1 assume !(1 == ~T6_E~0); 28103#L1077-1 assume !(1 == ~T7_E~0); 28102#L1082-1 assume !(1 == ~T8_E~0); 28101#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28100#L1092-1 assume !(1 == ~E_M~0); 28099#L1097-1 assume !(1 == ~E_1~0); 28098#L1102-1 assume !(1 == ~E_2~0); 28097#L1107-1 assume !(1 == ~E_3~0); 27419#L1112-1 assume !(1 == ~E_4~0); 27420#L1117-1 assume !(1 == ~E_5~0); 27459#L1122-1 assume !(1 == ~E_6~0); 27332#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27333#L1132-1 assume !(1 == ~E_8~0); 27886#L1137-1 assume !(1 == ~E_9~0); 26948#L1142-1 assume { :end_inline_reset_delta_events } true; 26800#L1428-2 [2024-10-31 22:18:42,243 INFO L747 eck$LassoCheckResult]: Loop: 26800#L1428-2 assume !false; 26801#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27475#L914-1 assume !false; 27476#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27614#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26649#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26650#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27658#L783 assume !(0 != eval_~tmp~0#1); 27659#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27371#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27372#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27869#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28576#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28575#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28574#L954-3 assume !(0 == ~T4_E~0); 28573#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28572#L964-3 assume !(0 == ~T6_E~0); 28571#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28570#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28569#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28568#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28567#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28566#L994-3 assume !(0 == ~E_2~0); 28565#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28564#L1004-3 assume !(0 == ~E_4~0); 28563#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28562#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28561#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28560#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28559#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28558#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28557#L460-33 assume 1 == ~m_pc~0; 28555#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28554#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28553#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28552#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28551#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28550#L479-33 assume !(1 == ~t1_pc~0); 28548#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 28547#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28546#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28545#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28544#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28543#L498-33 assume !(1 == ~t2_pc~0); 28541#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 28540#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28539#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28538#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28537#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28536#L517-33 assume !(1 == ~t3_pc~0); 28534#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 28533#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28532#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28531#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28530#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28529#L536-33 assume !(1 == ~t4_pc~0); 28528#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 28526#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28525#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28524#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28523#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28522#L555-33 assume !(1 == ~t5_pc~0); 28520#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 28519#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28518#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28517#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28516#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28515#L574-33 assume 1 == ~t6_pc~0; 28513#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28512#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28511#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28510#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 28509#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28508#L593-33 assume 1 == ~t7_pc~0; 28506#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28505#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28504#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28503#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28502#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28501#L612-33 assume !(1 == ~t8_pc~0); 28499#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 28498#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28497#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28496#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28495#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28494#L631-33 assume 1 == ~t9_pc~0; 28492#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28491#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28490#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28489#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26893#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26894#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27062#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27745#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27666#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27667#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26786#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26787#L1072-3 assume !(1 == ~T6_E~0); 27189#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27021#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27022#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27088#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27413#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27330#L1102-3 assume !(1 == ~E_2~0); 27331#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27711#L1112-3 assume !(1 == ~E_4~0); 27016#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27017#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27063#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27064#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27506#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27859#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 26898#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26775#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27089#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 27090#L1447 assume !(0 == start_simulation_~tmp~3#1); 27210#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27688#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26926#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 26711#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26794#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26795#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 27278#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 26800#L1428-2 [2024-10-31 22:18:42,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:42,244 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2024-10-31 22:18:42,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:42,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105749949] [2024-10-31 22:18:42,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:42,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:42,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:42,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:42,300 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:42,300 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105749949] [2024-10-31 22:18:42,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1105749949] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:42,301 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:42,301 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:42,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678786405] [2024-10-31 22:18:42,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:42,301 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:42,302 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:42,302 INFO L85 PathProgramCache]: Analyzing trace with hash -237143792, now seen corresponding path program 1 times [2024-10-31 22:18:42,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:42,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288786592] [2024-10-31 22:18:42,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:42,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:42,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:42,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:42,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:42,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288786592] [2024-10-31 22:18:42,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288786592] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:42,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:42,415 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:42,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906222181] [2024-10-31 22:18:42,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:42,416 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:42,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:42,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:42,417 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:42,417 INFO L87 Difference]: Start difference. First operand 2161 states and 3153 transitions. cyclomatic complexity: 994 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:42,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:42,603 INFO L93 Difference]: Finished difference Result 4147 states and 5996 transitions. [2024-10-31 22:18:42,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4147 states and 5996 transitions. [2024-10-31 22:18:42,633 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3997 [2024-10-31 22:18:42,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4147 states to 4147 states and 5996 transitions. [2024-10-31 22:18:42,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4147 [2024-10-31 22:18:42,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4147 [2024-10-31 22:18:42,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4147 states and 5996 transitions. [2024-10-31 22:18:42,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:42,668 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4147 states and 5996 transitions. [2024-10-31 22:18:42,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4147 states and 5996 transitions. [2024-10-31 22:18:42,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4147 to 4009. [2024-10-31 22:18:42,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4009 states, 4009 states have (on average 1.4477425791968073) internal successors, (5804), 4008 states have internal predecessors, (5804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:42,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4009 states to 4009 states and 5804 transitions. [2024-10-31 22:18:42,762 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4009 states and 5804 transitions. [2024-10-31 22:18:42,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:42,763 INFO L425 stractBuchiCegarLoop]: Abstraction has 4009 states and 5804 transitions. [2024-10-31 22:18:42,763 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:18:42,763 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4009 states and 5804 transitions. [2024-10-31 22:18:42,781 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3859 [2024-10-31 22:18:42,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:42,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:42,783 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:42,783 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:42,784 INFO L745 eck$LassoCheckResult]: Stem: 33286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 34134#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34135#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34052#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 33676#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33677#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34023#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33459#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33460#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33940#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33941#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32958#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32959#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33163#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33563#L939 assume !(0 == ~M_E~0); 33833#L939-2 assume !(0 == ~T1_E~0); 33834#L944-1 assume !(0 == ~T2_E~0); 33600#L949-1 assume !(0 == ~T3_E~0); 33598#L954-1 assume !(0 == ~T4_E~0); 33599#L959-1 assume !(0 == ~T5_E~0); 34067#L964-1 assume !(0 == ~T6_E~0); 33309#L969-1 assume !(0 == ~T7_E~0); 33310#L974-1 assume !(0 == ~T8_E~0); 34007#L979-1 assume !(0 == ~T9_E~0); 34008#L984-1 assume !(0 == ~E_M~0); 33473#L989-1 assume !(0 == ~E_1~0); 33474#L994-1 assume !(0 == ~E_2~0); 33358#L999-1 assume !(0 == ~E_3~0); 33359#L1004-1 assume !(0 == ~E_4~0); 33027#L1009-1 assume !(0 == ~E_5~0); 33028#L1014-1 assume !(0 == ~E_6~0); 33353#L1019-1 assume !(0 == ~E_7~0); 33945#L1024-1 assume !(0 == ~E_8~0); 33281#L1029-1 assume !(0 == ~E_9~0); 33282#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33364#L460 assume !(1 == ~m_pc~0); 34180#L460-2 is_master_triggered_~__retres1~0#1 := 0; 33905#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33906#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34036#L1167 assume !(0 != activate_threads_~tmp~1#1); 33583#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33584#L479 assume 1 == ~t1_pc~0; 33564#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33565#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33029#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33030#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 33294#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33141#L498 assume !(1 == ~t2_pc~0); 33142#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33562#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33463#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33464#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33892#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33893#L517 assume 1 == ~t3_pc~0; 34149#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34150#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32965#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32966#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 33330#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33950#L536 assume !(1 == ~t4_pc~0); 33628#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33627#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33122#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33123#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 33621#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33869#L555 assume 1 == ~t5_pc~0; 33870#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33946#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34004#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33283#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 33166#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33065#L574 assume !(1 == ~t6_pc~0); 33066#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33732#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33453#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33454#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 33971#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34189#L593 assume 1 == ~t7_pc~0; 34190#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33302#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34070#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34224#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 34153#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33468#L612 assume !(1 == ~t8_pc~0); 33469#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33925#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33976#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33977#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 33734#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33735#L631 assume 1 == ~t9_pc~0; 33750#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33057#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33058#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33514#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 33567#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33953#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 32992#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32993#L1052-1 assume !(1 == ~T2_E~0); 32975#L1057-1 assume !(1 == ~T3_E~0); 32976#L1062-1 assume !(1 == ~T4_E~0); 33267#L1067-1 assume !(1 == ~T5_E~0); 33587#L1072-1 assume !(1 == ~T6_E~0); 33588#L1077-1 assume !(1 == ~T7_E~0); 33156#L1082-1 assume !(1 == ~T8_E~0); 33157#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32952#L1092-1 assume !(1 == ~E_M~0); 32953#L1097-1 assume !(1 == ~E_1~0); 32977#L1102-1 assume !(1 == ~E_2~0); 33798#L1107-1 assume !(1 == ~E_3~0); 33730#L1112-1 assume !(1 == ~E_4~0); 33731#L1117-1 assume !(1 == ~E_5~0); 33771#L1122-1 assume !(1 == ~E_6~0); 34948#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34941#L1132-1 assume !(1 == ~E_8~0); 34934#L1137-1 assume !(1 == ~E_9~0); 34929#L1142-1 assume { :end_inline_reset_delta_events } true; 34923#L1428-2 [2024-10-31 22:18:42,784 INFO L747 eck$LassoCheckResult]: Loop: 34923#L1428-2 assume !false; 34919#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34918#L914-1 assume !false; 34917#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34915#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 34906#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 34905#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34903#L783 assume !(0 != eval_~tmp~0#1); 34902#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34900#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34897#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34898#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36800#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36799#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36798#L954-3 assume !(0 == ~T4_E~0); 36797#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36796#L964-3 assume !(0 == ~T6_E~0); 36795#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33234#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33235#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34220#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36781#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36772#L994-3 assume !(0 == ~E_2~0); 36771#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36770#L1004-3 assume !(0 == ~E_4~0); 36769#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36768#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36767#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36766#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36765#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36764#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36763#L460-33 assume !(1 == ~m_pc~0); 36762#L460-35 is_master_triggered_~__retres1~0#1 := 0; 36761#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33997#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32956#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32957#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33318#L479-33 assume !(1 == ~t1_pc~0); 33319#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 33284#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33285#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34218#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35608#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35607#L498-33 assume !(1 == ~t2_pc~0); 35444#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 35443#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35442#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35441#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35440#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35438#L517-33 assume !(1 == ~t3_pc~0); 35435#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 35433#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35374#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35368#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35334#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35328#L536-33 assume 1 == ~t4_pc~0; 35321#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35318#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35316#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35314#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35305#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35302#L555-33 assume !(1 == ~t5_pc~0); 35298#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 35295#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35293#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35291#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35289#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35287#L574-33 assume 1 == ~t6_pc~0; 35284#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35283#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35282#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35281#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 35276#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35275#L593-33 assume 1 == ~t7_pc~0; 35272#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35270#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35268#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35266#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35264#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35263#L612-33 assume !(1 == ~t8_pc~0); 35258#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 35256#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35254#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35252#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35247#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34249#L631-33 assume 1 == ~t9_pc~0; 34065#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33802#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35216#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35213#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35211#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35209#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33374#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35206#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35203#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34250#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33101#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33102#L1072-3 assume !(1 == ~T6_E~0); 35194#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35193#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35192#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35191#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35190#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35189#L1102-3 assume !(1 == ~E_2~0); 35188#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35187#L1112-3 assume !(1 == ~E_4~0); 35186#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35185#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35184#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35183#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35182#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35181#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 35176#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 35170#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 35169#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 35138#L1447 assume !(0 == start_simulation_~tmp~3#1); 35137#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34993#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 34986#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 34955#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 34947#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34940#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34933#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 34928#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 34923#L1428-2 [2024-10-31 22:18:42,785 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:42,785 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2024-10-31 22:18:42,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:42,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91943309] [2024-10-31 22:18:42,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:42,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:42,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:42,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:42,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:42,844 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91943309] [2024-10-31 22:18:42,844 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91943309] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:42,844 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:42,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:42,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631348059] [2024-10-31 22:18:42,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:42,845 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:42,846 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:42,846 INFO L85 PathProgramCache]: Analyzing trace with hash -257587696, now seen corresponding path program 1 times [2024-10-31 22:18:42,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:42,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787896455] [2024-10-31 22:18:42,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:42,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:42,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:42,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:42,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:42,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1787896455] [2024-10-31 22:18:42,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1787896455] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:42,897 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:42,897 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:42,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380336490] [2024-10-31 22:18:42,897 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:42,897 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:42,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:42,898 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:42,898 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:42,898 INFO L87 Difference]: Start difference. First operand 4009 states and 5804 transitions. cyclomatic complexity: 1799 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:43,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:43,034 INFO L93 Difference]: Finished difference Result 7541 states and 10846 transitions. [2024-10-31 22:18:43,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7541 states and 10846 transitions. [2024-10-31 22:18:43,076 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7380 [2024-10-31 22:18:43,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7541 states to 7541 states and 10846 transitions. [2024-10-31 22:18:43,109 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7541 [2024-10-31 22:18:43,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7541 [2024-10-31 22:18:43,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7541 states and 10846 transitions. [2024-10-31 22:18:43,126 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:43,126 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7541 states and 10846 transitions. [2024-10-31 22:18:43,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7541 states and 10846 transitions. [2024-10-31 22:18:43,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7541 to 7533. [2024-10-31 22:18:43,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7533 states, 7533 states have (on average 1.4387362272666933) internal successors, (10838), 7532 states have internal predecessors, (10838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:43,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7533 states to 7533 states and 10838 transitions. [2024-10-31 22:18:43,327 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7533 states and 10838 transitions. [2024-10-31 22:18:43,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:43,328 INFO L425 stractBuchiCegarLoop]: Abstraction has 7533 states and 10838 transitions. [2024-10-31 22:18:43,328 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:18:43,328 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7533 states and 10838 transitions. [2024-10-31 22:18:43,359 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7372 [2024-10-31 22:18:43,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:43,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:43,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:43,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:43,362 INFO L745 eck$LassoCheckResult]: Stem: 44843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 44844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 45679#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45680#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45600#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 45224#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45225#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45570#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45015#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45016#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45483#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45484#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44515#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44516#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44718#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45119#L939 assume !(0 == ~M_E~0); 45381#L939-2 assume !(0 == ~T1_E~0); 45382#L944-1 assume !(0 == ~T2_E~0); 45154#L949-1 assume !(0 == ~T3_E~0); 45152#L954-1 assume !(0 == ~T4_E~0); 45153#L959-1 assume !(0 == ~T5_E~0); 45617#L964-1 assume !(0 == ~T6_E~0); 44866#L969-1 assume !(0 == ~T7_E~0); 44867#L974-1 assume !(0 == ~T8_E~0); 45555#L979-1 assume !(0 == ~T9_E~0); 45556#L984-1 assume !(0 == ~E_M~0); 45029#L989-1 assume !(0 == ~E_1~0); 45030#L994-1 assume !(0 == ~E_2~0); 44918#L999-1 assume !(0 == ~E_3~0); 44919#L1004-1 assume !(0 == ~E_4~0); 44581#L1009-1 assume !(0 == ~E_5~0); 44582#L1014-1 assume !(0 == ~E_6~0); 44913#L1019-1 assume !(0 == ~E_7~0); 45490#L1024-1 assume !(0 == ~E_8~0); 44838#L1029-1 assume !(0 == ~E_9~0); 44839#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44924#L460 assume !(1 == ~m_pc~0); 45716#L460-2 is_master_triggered_~__retres1~0#1 := 0; 45453#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45454#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45583#L1167 assume !(0 != activate_threads_~tmp~1#1); 45137#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45138#L479 assume !(1 == ~t1_pc~0); 45297#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45298#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44585#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44586#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 44851#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44697#L498 assume !(1 == ~t2_pc~0); 44698#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45118#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45019#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45020#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45440#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45441#L517 assume 1 == ~t3_pc~0; 45689#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45690#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44522#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44523#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 44888#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45496#L536 assume !(1 == ~t4_pc~0); 45182#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45181#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44678#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44679#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 45175#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45416#L555 assume 1 == ~t5_pc~0; 45417#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45491#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45553#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44840#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 44721#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44621#L574 assume !(1 == ~t6_pc~0); 44622#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45279#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45009#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45010#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 45516#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45724#L593 assume 1 == ~t7_pc~0; 45725#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44859#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45620#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45755#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 45695#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45024#L612 assume !(1 == ~t8_pc~0); 45025#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 45473#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45521#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45522#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 45281#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45282#L631 assume 1 == ~t9_pc~0; 45295#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44613#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44614#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45071#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 45120#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45499#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 45500#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46914#L1052-1 assume !(1 == ~T2_E~0); 46913#L1057-1 assume !(1 == ~T3_E~0); 46912#L1062-1 assume !(1 == ~T4_E~0); 44823#L1067-1 assume !(1 == ~T5_E~0); 46911#L1072-1 assume !(1 == ~T6_E~0); 46910#L1077-1 assume !(1 == ~T7_E~0); 46909#L1082-1 assume !(1 == ~T8_E~0); 46908#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46907#L1092-1 assume !(1 == ~E_M~0); 46906#L1097-1 assume !(1 == ~E_1~0); 46905#L1102-1 assume !(1 == ~E_2~0); 46904#L1107-1 assume !(1 == ~E_3~0); 46903#L1112-1 assume !(1 == ~E_4~0); 46902#L1117-1 assume !(1 == ~E_5~0); 46901#L1122-1 assume !(1 == ~E_6~0); 46900#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46899#L1132-1 assume !(1 == ~E_8~0); 46898#L1137-1 assume !(1 == ~E_9~0); 44819#L1142-1 assume { :end_inline_reset_delta_events } true; 44820#L1428-2 [2024-10-31 22:18:43,363 INFO L747 eck$LassoCheckResult]: Loop: 44820#L1428-2 assume !false; 46606#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46602#L914-1 assume !false; 46598#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 46580#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46570#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 46568#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46564#L783 assume !(0 != eval_~tmp~0#1); 46562#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46560#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46557#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46558#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47877#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47876#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47875#L954-3 assume !(0 == ~T4_E~0); 47874#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47873#L964-3 assume !(0 == ~T6_E~0); 47872#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47871#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47870#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47869#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47868#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47867#L994-3 assume !(0 == ~E_2~0); 47866#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47865#L1004-3 assume !(0 == ~E_4~0); 47864#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47863#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47862#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47861#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47860#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47859#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47858#L460-33 assume !(1 == ~m_pc~0); 47857#L460-35 is_master_triggered_~__retres1~0#1 := 0; 47856#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47855#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47854#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47853#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47852#L479-33 assume !(1 == ~t1_pc~0); 47851#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 47850#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47849#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47848#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47847#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46475#L498-33 assume !(1 == ~t2_pc~0); 46343#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 46332#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46320#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46311#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46310#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46309#L517-33 assume !(1 == ~t3_pc~0); 46307#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 46306#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46305#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46304#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46303#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46302#L536-33 assume 1 == ~t4_pc~0; 46300#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46299#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46298#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46297#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46296#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46295#L555-33 assume !(1 == ~t5_pc~0); 46293#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 46292#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46291#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46290#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46289#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46286#L574-33 assume 1 == ~t6_pc~0; 46281#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46282#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47814#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46270#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 46267#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46264#L593-33 assume 1 == ~t7_pc~0; 46260#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46257#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46254#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46250#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46247#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46245#L612-33 assume !(1 == ~t8_pc~0); 46242#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 46240#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46237#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46233#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46230#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46228#L631-33 assume 1 == ~t9_pc~0; 46225#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46223#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46220#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46216#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46213#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46211#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46209#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46206#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46207#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47780#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46199#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47776#L1072-3 assume !(1 == ~T6_E~0); 47774#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47772#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47770#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47768#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47765#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47763#L1102-3 assume !(1 == ~E_2~0); 47761#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47759#L1112-3 assume !(1 == ~E_4~0); 47757#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47755#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47752#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47750#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47748#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47746#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 46144#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46139#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 45828#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 45829#L1447 assume !(0 == start_simulation_~tmp~3#1); 47536#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 46890#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46883#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 46880#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 46878#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46876#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46874#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 46872#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 44820#L1428-2 [2024-10-31 22:18:43,364 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:43,364 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2024-10-31 22:18:43,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:43,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697419201] [2024-10-31 22:18:43,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:43,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:43,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:43,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:43,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:43,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697419201] [2024-10-31 22:18:43,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697419201] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:43,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:43,459 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:43,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428655173] [2024-10-31 22:18:43,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:43,460 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:43,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:43,461 INFO L85 PathProgramCache]: Analyzing trace with hash -257587696, now seen corresponding path program 2 times [2024-10-31 22:18:43,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:43,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806572041] [2024-10-31 22:18:43,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:43,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:43,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:43,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:43,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:43,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806572041] [2024-10-31 22:18:43,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806572041] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:43,513 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:43,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:43,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1608810098] [2024-10-31 22:18:43,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:43,514 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:43,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:43,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:18:43,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:18:43,515 INFO L87 Difference]: Start difference. First operand 7533 states and 10838 transitions. cyclomatic complexity: 3313 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:43,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:43,807 INFO L93 Difference]: Finished difference Result 7545 states and 10769 transitions. [2024-10-31 22:18:43,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7545 states and 10769 transitions. [2024-10-31 22:18:43,847 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7384 [2024-10-31 22:18:43,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7545 states to 7545 states and 10769 transitions. [2024-10-31 22:18:43,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7545 [2024-10-31 22:18:43,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7545 [2024-10-31 22:18:43,880 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7545 states and 10769 transitions. [2024-10-31 22:18:43,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:43,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7545 states and 10769 transitions. [2024-10-31 22:18:43,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7545 states and 10769 transitions. [2024-10-31 22:18:44,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7545 to 7545. [2024-10-31 22:18:44,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7545 states, 7545 states have (on average 1.4273028495692512) internal successors, (10769), 7544 states have internal predecessors, (10769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:44,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7545 states to 7545 states and 10769 transitions. [2024-10-31 22:18:44,102 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7545 states and 10769 transitions. [2024-10-31 22:18:44,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:18:44,103 INFO L425 stractBuchiCegarLoop]: Abstraction has 7545 states and 10769 transitions. [2024-10-31 22:18:44,103 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:18:44,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7545 states and 10769 transitions. [2024-10-31 22:18:44,133 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7384 [2024-10-31 22:18:44,133 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:44,133 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:44,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:44,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:44,135 INFO L745 eck$LassoCheckResult]: Stem: 59932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 59933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 60762#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60763#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60685#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 60318#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60319#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60657#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60105#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60106#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60577#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60578#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59602#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59603#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59805#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60208#L939 assume !(0 == ~M_E~0); 60479#L939-2 assume !(0 == ~T1_E~0); 60480#L944-1 assume !(0 == ~T2_E~0); 60243#L949-1 assume !(0 == ~T3_E~0); 60241#L954-1 assume !(0 == ~T4_E~0); 60242#L959-1 assume !(0 == ~T5_E~0); 60699#L964-1 assume !(0 == ~T6_E~0); 59955#L969-1 assume !(0 == ~T7_E~0); 59956#L974-1 assume !(0 == ~T8_E~0); 60642#L979-1 assume !(0 == ~T9_E~0); 60643#L984-1 assume !(0 == ~E_M~0); 60119#L989-1 assume !(0 == ~E_1~0); 60120#L994-1 assume !(0 == ~E_2~0); 60006#L999-1 assume !(0 == ~E_3~0); 60007#L1004-1 assume !(0 == ~E_4~0); 59668#L1009-1 assume !(0 == ~E_5~0); 59669#L1014-1 assume !(0 == ~E_6~0); 60001#L1019-1 assume !(0 == ~E_7~0); 60585#L1024-1 assume !(0 == ~E_8~0); 59927#L1029-1 assume !(0 == ~E_9~0); 59928#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60012#L460 assume !(1 == ~m_pc~0); 60797#L460-2 is_master_triggered_~__retres1~0#1 := 0; 60548#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60549#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60671#L1167 assume !(0 != activate_threads_~tmp~1#1); 60226#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60227#L479 assume !(1 == ~t1_pc~0); 60395#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60396#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59672#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59673#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 59940#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59784#L498 assume !(1 == ~t2_pc~0); 59785#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 60207#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60109#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60110#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 60536#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60537#L517 assume 1 == ~t3_pc~0; 60772#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60773#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59609#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59610#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 59976#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60590#L536 assume !(1 == ~t4_pc~0); 60274#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 60273#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59765#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59766#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 60265#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60515#L555 assume 1 == ~t5_pc~0; 60516#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60586#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59929#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 59808#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59708#L574 assume !(1 == ~t6_pc~0); 59709#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 60376#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60099#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60100#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 60609#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60805#L593 assume 1 == ~t7_pc~0; 60806#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59948#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60702#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60838#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 60778#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60114#L612 assume !(1 == ~t8_pc~0); 60115#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 60567#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60614#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60615#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 60378#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60379#L631 assume 1 == ~t9_pc~0; 60393#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59700#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59701#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60160#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 60209#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60593#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 60594#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62000#L1052-1 assume !(1 == ~T2_E~0); 61999#L1057-1 assume !(1 == ~T3_E~0); 61998#L1062-1 assume !(1 == ~T4_E~0); 59912#L1067-1 assume !(1 == ~T5_E~0); 61997#L1072-1 assume !(1 == ~T6_E~0); 61996#L1077-1 assume !(1 == ~T7_E~0); 61995#L1082-1 assume !(1 == ~T8_E~0); 61994#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61993#L1092-1 assume !(1 == ~E_M~0); 61992#L1097-1 assume !(1 == ~E_1~0); 61991#L1102-1 assume !(1 == ~E_2~0); 61990#L1107-1 assume !(1 == ~E_3~0); 61989#L1112-1 assume !(1 == ~E_4~0); 61988#L1117-1 assume !(1 == ~E_5~0); 61987#L1122-1 assume !(1 == ~E_6~0); 61986#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 61985#L1132-1 assume !(1 == ~E_8~0); 61984#L1137-1 assume !(1 == ~E_9~0); 59908#L1142-1 assume { :end_inline_reset_delta_events } true; 59909#L1428-2 [2024-10-31 22:18:44,136 INFO L747 eck$LassoCheckResult]: Loop: 59909#L1428-2 assume !false; 61692#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61688#L914-1 assume !false; 61684#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 61666#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 61656#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 61654#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 61650#L783 assume !(0 != eval_~tmp~0#1); 61648#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61646#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61643#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 61644#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62961#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62960#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62959#L954-3 assume !(0 == ~T4_E~0); 62958#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62957#L964-3 assume !(0 == ~T6_E~0); 62956#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62955#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62954#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62953#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62952#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62951#L994-3 assume !(0 == ~E_2~0); 62950#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62949#L1004-3 assume !(0 == ~E_4~0); 62948#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62947#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62946#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62945#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62944#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62943#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62942#L460-33 assume !(1 == ~m_pc~0); 62941#L460-35 is_master_triggered_~__retres1~0#1 := 0; 62940#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62939#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 62938#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62937#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62936#L479-33 assume !(1 == ~t1_pc~0); 62935#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 62934#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62933#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62932#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62931#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61541#L498-33 assume !(1 == ~t2_pc~0); 61406#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 61392#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61380#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61371#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 61370#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61369#L517-33 assume !(1 == ~t3_pc~0); 61367#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 61366#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61365#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61364#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61363#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61362#L536-33 assume 1 == ~t4_pc~0; 61360#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61359#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61358#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61357#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61356#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61355#L555-33 assume !(1 == ~t5_pc~0); 61353#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 61352#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61351#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61350#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 61349#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61348#L574-33 assume 1 == ~t6_pc~0; 61344#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61345#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62898#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61336#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 61334#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61332#L593-33 assume 1 == ~t7_pc~0; 61329#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61327#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61325#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61323#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 61320#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61318#L612-33 assume !(1 == ~t8_pc~0); 61315#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 61313#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61311#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61309#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61306#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61304#L631-33 assume 1 == ~t9_pc~0; 61301#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61299#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61297#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61295#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61292#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61290#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61288#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61285#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61286#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62864#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61281#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62860#L1072-3 assume !(1 == ~T6_E~0); 62858#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62856#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62854#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62852#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62849#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62847#L1102-3 assume !(1 == ~E_2~0); 62845#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62843#L1112-3 assume !(1 == ~E_4~0); 62841#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62839#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62836#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 62834#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62832#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 62830#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 61227#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 61222#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 60896#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 60897#L1447 assume !(0 == start_simulation_~tmp~3#1); 62620#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 61976#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 61969#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 61966#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 61964#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61962#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61960#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 61958#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 59909#L1428-2 [2024-10-31 22:18:44,137 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:44,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2024-10-31 22:18:44,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:44,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109926468] [2024-10-31 22:18:44,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:44,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:44,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:44,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:44,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:44,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109926468] [2024-10-31 22:18:44,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109926468] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:44,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:44,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:44,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59169171] [2024-10-31 22:18:44,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:44,220 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:44,220 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:44,221 INFO L85 PathProgramCache]: Analyzing trace with hash -230522094, now seen corresponding path program 1 times [2024-10-31 22:18:44,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:44,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998300532] [2024-10-31 22:18:44,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:44,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:44,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:44,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:44,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:44,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998300532] [2024-10-31 22:18:44,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [998300532] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:44,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:44,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:44,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144992085] [2024-10-31 22:18:44,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:44,291 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:44,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:44,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:44,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:44,293 INFO L87 Difference]: Start difference. First operand 7545 states and 10769 transitions. cyclomatic complexity: 3232 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:44,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:44,453 INFO L93 Difference]: Finished difference Result 14284 states and 20274 transitions. [2024-10-31 22:18:44,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14284 states and 20274 transitions. [2024-10-31 22:18:44,619 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14100 [2024-10-31 22:18:44,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14284 states to 14284 states and 20274 transitions. [2024-10-31 22:18:44,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14284 [2024-10-31 22:18:44,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14284 [2024-10-31 22:18:44,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14284 states and 20274 transitions. [2024-10-31 22:18:44,692 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:44,692 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14284 states and 20274 transitions. [2024-10-31 22:18:44,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14284 states and 20274 transitions. [2024-10-31 22:18:44,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14284 to 14268. [2024-10-31 22:18:44,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14268 states, 14268 states have (on average 1.41982057751612) internal successors, (20258), 14267 states have internal predecessors, (20258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:45,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14268 states to 14268 states and 20258 transitions. [2024-10-31 22:18:45,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14268 states and 20258 transitions. [2024-10-31 22:18:45,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:45,040 INFO L425 stractBuchiCegarLoop]: Abstraction has 14268 states and 20258 transitions. [2024-10-31 22:18:45,040 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:18:45,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14268 states and 20258 transitions. [2024-10-31 22:18:45,099 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14084 [2024-10-31 22:18:45,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:45,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:45,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:45,101 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:45,102 INFO L745 eck$LassoCheckResult]: Stem: 81768#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 81769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 82626#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82627#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82540#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 82155#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82156#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82508#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81942#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81943#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82420#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82421#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81438#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81439#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81641#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82045#L939 assume !(0 == ~M_E~0); 82316#L939-2 assume !(0 == ~T1_E~0); 82317#L944-1 assume !(0 == ~T2_E~0); 82082#L949-1 assume !(0 == ~T3_E~0); 82080#L954-1 assume !(0 == ~T4_E~0); 82081#L959-1 assume !(0 == ~T5_E~0); 82557#L964-1 assume !(0 == ~T6_E~0); 81793#L969-1 assume !(0 == ~T7_E~0); 81794#L974-1 assume !(0 == ~T8_E~0); 82494#L979-1 assume !(0 == ~T9_E~0); 82495#L984-1 assume !(0 == ~E_M~0); 81956#L989-1 assume !(0 == ~E_1~0); 81957#L994-1 assume !(0 == ~E_2~0); 81843#L999-1 assume !(0 == ~E_3~0); 81844#L1004-1 assume !(0 == ~E_4~0); 81504#L1009-1 assume !(0 == ~E_5~0); 81505#L1014-1 assume !(0 == ~E_6~0); 81838#L1019-1 assume !(0 == ~E_7~0); 82429#L1024-1 assume !(0 == ~E_8~0); 81763#L1029-1 assume !(0 == ~E_9~0); 81764#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81849#L460 assume !(1 == ~m_pc~0); 82673#L460-2 is_master_triggered_~__retres1~0#1 := 0; 82388#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82389#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82525#L1167 assume !(0 != activate_threads_~tmp~1#1); 82065#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82066#L479 assume !(1 == ~t1_pc~0); 82231#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82232#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81508#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81509#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 81776#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81619#L498 assume !(1 == ~t2_pc~0); 81620#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 82044#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81946#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81947#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 82376#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82377#L517 assume !(1 == ~t3_pc~0); 82718#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82719#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81445#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81446#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 81815#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82434#L536 assume !(1 == ~t4_pc~0); 82110#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 82109#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81601#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 82102#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82348#L555 assume 1 == ~t5_pc~0; 82349#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82430#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82492#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81765#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 81646#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81544#L574 assume !(1 == ~t6_pc~0); 81545#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 82212#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81935#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81936#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 82455#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82681#L593 assume 1 == ~t7_pc~0; 82682#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81784#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82560#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82723#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 82644#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81951#L612 assume !(1 == ~t8_pc~0); 81952#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82409#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82460#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82461#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 82215#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82216#L631 assume 1 == ~t9_pc~0; 82229#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81536#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81537#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81996#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 82046#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82437#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 82438#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85818#L1052-1 assume !(1 == ~T2_E~0); 85816#L1057-1 assume !(1 == ~T3_E~0); 85813#L1062-1 assume !(1 == ~T4_E~0); 81748#L1067-1 assume !(1 == ~T5_E~0); 85810#L1072-1 assume !(1 == ~T6_E~0); 85808#L1077-1 assume !(1 == ~T7_E~0); 85806#L1082-1 assume !(1 == ~T8_E~0); 85804#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 85801#L1092-1 assume !(1 == ~E_M~0); 85799#L1097-1 assume !(1 == ~E_1~0); 85797#L1102-1 assume !(1 == ~E_2~0); 85795#L1107-1 assume !(1 == ~E_3~0); 85793#L1112-1 assume !(1 == ~E_4~0); 85791#L1117-1 assume !(1 == ~E_5~0); 85788#L1122-1 assume !(1 == ~E_6~0); 82126#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 82127#L1132-1 assume !(1 == ~E_8~0); 82672#L1137-1 assume !(1 == ~E_9~0); 81744#L1142-1 assume { :end_inline_reset_delta_events } true; 81745#L1428-2 [2024-10-31 22:18:45,102 INFO L747 eck$LassoCheckResult]: Loop: 81745#L1428-2 assume !false; 90751#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 90745#L914-1 assume !false; 90740#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 90599#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 90582#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 90576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 90569#L783 assume !(0 != eval_~tmp~0#1); 90570#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 92750#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 92747#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 92745#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 92743#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 92741#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 92739#L954-3 assume !(0 == ~T4_E~0); 92737#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 92734#L964-3 assume !(0 == ~T6_E~0); 92731#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 92729#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 92727#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 92725#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 92722#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 92705#L994-3 assume !(0 == ~E_2~0); 92704#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 92702#L1004-3 assume !(0 == ~E_4~0); 92700#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 92697#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 92695#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 92693#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 92685#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 92682#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92680#L460-33 assume !(1 == ~m_pc~0); 92678#L460-35 is_master_triggered_~__retres1~0#1 := 0; 92676#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92674#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 92666#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 92664#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92662#L479-33 assume !(1 == ~t1_pc~0); 92660#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 92657#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92654#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 92653#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 92650#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92648#L498-33 assume !(1 == ~t2_pc~0); 92645#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 92637#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92595#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92593#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 92588#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92587#L517-33 assume !(1 == ~t3_pc~0); 92586#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 92585#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92584#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 92583#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 92582#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92581#L536-33 assume 1 == ~t4_pc~0; 92579#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 92578#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92577#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 92576#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82580#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81478#L555-33 assume 1 == ~t5_pc~0; 81479#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82246#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82247#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82277#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82278#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81449#L574-33 assume 1 == ~t6_pc~0; 81451#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82516#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82055#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82056#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 82037#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81527#L593-33 assume !(1 == ~t7_pc~0); 81529#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 82003#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82544#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82337#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 82338#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82488#L612-33 assume !(1 == ~t8_pc~0); 82661#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 82604#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82257#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82258#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 81630#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81631#L631-33 assume 1 == ~t9_pc~0; 82555#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81571#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81572#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81837#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 81691#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81692#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 81860#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82556#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82468#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82469#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81579#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81580#L1072-3 assume !(1 == ~T6_E~0); 81986#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81821#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 81822#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81887#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 82206#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 82124#L1102-3 assume !(1 == ~E_2~0); 82125#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82520#L1112-3 assume !(1 == ~E_4~0); 81816#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81817#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81861#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81862#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 82295#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 82271#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 81696#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 81568#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 81888#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 81889#L1447 assume !(0 == start_simulation_~tmp~3#1); 82006#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 91010#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 90831#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 90827#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 90825#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 90821#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 90792#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 90770#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 81745#L1428-2 [2024-10-31 22:18:45,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:45,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2024-10-31 22:18:45,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:45,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459255125] [2024-10-31 22:18:45,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:45,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:45,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:45,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:45,189 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:45,189 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459255125] [2024-10-31 22:18:45,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1459255125] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:45,189 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:45,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:45,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1584172492] [2024-10-31 22:18:45,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:45,190 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:45,191 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:45,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1386675346, now seen corresponding path program 1 times [2024-10-31 22:18:45,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:45,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882102922] [2024-10-31 22:18:45,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:45,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:45,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:45,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:45,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:45,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882102922] [2024-10-31 22:18:45,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882102922] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:45,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:45,264 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:45,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180778647] [2024-10-31 22:18:45,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:45,264 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:45,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:45,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:45,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:45,265 INFO L87 Difference]: Start difference. First operand 14268 states and 20258 transitions. cyclomatic complexity: 6006 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:45,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:45,541 INFO L93 Difference]: Finished difference Result 27103 states and 38299 transitions. [2024-10-31 22:18:45,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27103 states and 38299 transitions. [2024-10-31 22:18:45,859 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26848 [2024-10-31 22:18:45,935 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27103 states to 27103 states and 38299 transitions. [2024-10-31 22:18:45,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27103 [2024-10-31 22:18:45,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27103 [2024-10-31 22:18:45,962 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27103 states and 38299 transitions. [2024-10-31 22:18:45,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:45,985 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27103 states and 38299 transitions. [2024-10-31 22:18:46,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27103 states and 38299 transitions. [2024-10-31 22:18:46,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27103 to 27071. [2024-10-31 22:18:46,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27071 states, 27071 states have (on average 1.4135791067932475) internal successors, (38267), 27070 states have internal predecessors, (38267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:46,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27071 states to 27071 states and 38267 transitions. [2024-10-31 22:18:46,495 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27071 states and 38267 transitions. [2024-10-31 22:18:46,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:46,498 INFO L425 stractBuchiCegarLoop]: Abstraction has 27071 states and 38267 transitions. [2024-10-31 22:18:46,499 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 22:18:46,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27071 states and 38267 transitions. [2024-10-31 22:18:46,684 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26816 [2024-10-31 22:18:46,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:46,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:46,691 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:46,691 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:46,691 INFO L745 eck$LassoCheckResult]: Stem: 123142#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 123143#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 123982#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 123983#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 123894#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 123525#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 123526#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 123865#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 123317#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123318#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 123780#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123781#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122816#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 122817#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 123019#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 123421#L939 assume !(0 == ~M_E~0); 123680#L939-2 assume !(0 == ~T1_E~0); 123681#L944-1 assume !(0 == ~T2_E~0); 123455#L949-1 assume !(0 == ~T3_E~0); 123453#L954-1 assume !(0 == ~T4_E~0); 123454#L959-1 assume !(0 == ~T5_E~0); 123911#L964-1 assume !(0 == ~T6_E~0); 123165#L969-1 assume !(0 == ~T7_E~0); 123166#L974-1 assume !(0 == ~T8_E~0); 123847#L979-1 assume !(0 == ~T9_E~0); 123848#L984-1 assume !(0 == ~E_M~0); 123331#L989-1 assume !(0 == ~E_1~0); 123332#L994-1 assume !(0 == ~E_2~0); 123215#L999-1 assume !(0 == ~E_3~0); 123216#L1004-1 assume !(0 == ~E_4~0); 122881#L1009-1 assume !(0 == ~E_5~0); 122882#L1014-1 assume !(0 == ~E_6~0); 123210#L1019-1 assume !(0 == ~E_7~0); 123788#L1024-1 assume !(0 == ~E_8~0); 123137#L1029-1 assume !(0 == ~E_9~0); 123138#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123221#L460 assume !(1 == ~m_pc~0); 124030#L460-2 is_master_triggered_~__retres1~0#1 := 0; 123751#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123752#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 123879#L1167 assume !(0 != activate_threads_~tmp~1#1); 123438#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123439#L479 assume !(1 == ~t1_pc~0); 123599#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123600#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122885#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 122886#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 123150#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122998#L498 assume !(1 == ~t2_pc~0); 122999#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 123420#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123321#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123322#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 123740#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123741#L517 assume !(1 == ~t3_pc~0); 124060#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 124061#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122823#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 122824#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 123185#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123793#L536 assume !(1 == ~t4_pc~0); 123482#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 123481#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122979#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122980#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 123475#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123714#L555 assume !(1 == ~t5_pc~0); 123715#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 123789#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123845#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123139#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 123022#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122922#L574 assume !(1 == ~t6_pc~0); 122923#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 123581#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123311#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123312#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 123813#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124036#L593 assume 1 == ~t7_pc~0; 124037#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 123158#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123914#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124063#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 124002#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 123326#L612 assume !(1 == ~t8_pc~0); 123327#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 123770#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 123818#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 123819#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 123583#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123584#L631 assume 1 == ~t9_pc~0; 123597#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 122913#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 122914#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 123373#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 123422#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123796#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 122850#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 122851#L1052-1 assume !(1 == ~T2_E~0); 122833#L1057-1 assume !(1 == ~T3_E~0); 122834#L1062-1 assume !(1 == ~T4_E~0); 123123#L1067-1 assume !(1 == ~T5_E~0); 123442#L1072-1 assume !(1 == ~T6_E~0); 123443#L1077-1 assume !(1 == ~T7_E~0); 123013#L1082-1 assume !(1 == ~T8_E~0); 123014#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 122810#L1092-1 assume !(1 == ~E_M~0); 122811#L1097-1 assume !(1 == ~E_1~0); 122835#L1102-1 assume !(1 == ~E_2~0); 123650#L1107-1 assume !(1 == ~E_3~0); 123579#L1112-1 assume !(1 == ~E_4~0); 123580#L1117-1 assume !(1 == ~E_5~0); 123623#L1122-1 assume !(1 == ~E_6~0); 123497#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 123226#L1132-1 assume !(1 == ~E_8~0); 123227#L1137-1 assume !(1 == ~E_9~0); 123119#L1142-1 assume { :end_inline_reset_delta_events } true; 123120#L1428-2 [2024-10-31 22:18:46,692 INFO L747 eck$LassoCheckResult]: Loop: 123120#L1428-2 assume !false; 145505#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 145503#L914-1 assume !false; 145501#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 145493#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 145483#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 145481#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 145478#L783 assume !(0 != eval_~tmp~0#1); 145479#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146872#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146868#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 146863#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 146859#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 146855#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 146850#L954-3 assume !(0 == ~T4_E~0); 146845#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 146841#L964-3 assume !(0 == ~T6_E~0); 146836#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 146832#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 146828#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 146824#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 146819#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 146815#L994-3 assume !(0 == ~E_2~0); 146810#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 146806#L1004-3 assume !(0 == ~E_4~0); 146802#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 146797#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 146792#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 146788#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 146784#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 146780#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 146776#L460-33 assume !(1 == ~m_pc~0); 146769#L460-35 is_master_triggered_~__retres1~0#1 := 0; 146765#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 146762#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 146759#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146756#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 146752#L479-33 assume !(1 == ~t1_pc~0); 146747#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 146743#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 146739#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 146735#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 146731#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 146727#L498-33 assume !(1 == ~t2_pc~0); 146720#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 146716#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 146712#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 146708#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 146705#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 146704#L517-33 assume !(1 == ~t3_pc~0); 146703#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 146702#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 146700#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 146687#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 146683#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 146679#L536-33 assume 1 == ~t4_pc~0; 146674#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 146670#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 146666#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 146662#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 146659#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 146656#L555-33 assume !(1 == ~t5_pc~0); 146652#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 146648#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 146645#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 146641#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 146636#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 146632#L574-33 assume 1 == ~t6_pc~0; 146627#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 146622#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 146618#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 146614#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 146610#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 146606#L593-33 assume 1 == ~t7_pc~0; 146600#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 146596#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 146591#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 146587#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 146583#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 146578#L612-33 assume 1 == ~t8_pc~0; 146574#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 146569#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 146565#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 146561#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 146557#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 146553#L631-33 assume 1 == ~t9_pc~0; 146548#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 146543#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 146538#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 146534#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 146531#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 146527#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 140936#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 146520#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 146515#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 146511#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 140927#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 146503#L1072-3 assume !(1 == ~T6_E~0); 146499#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 146495#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 146490#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 146486#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 146481#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 146476#L1102-3 assume !(1 == ~E_2~0); 146472#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 146468#L1112-3 assume !(1 == ~E_4~0); 146463#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 146458#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 146454#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 146449#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 146445#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 146439#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 146088#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 146067#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 146057#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 146047#L1447 assume !(0 == start_simulation_~tmp~3#1); 146040#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 145728#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 145720#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 145718#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 145716#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 145714#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 145712#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 145710#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 123120#L1428-2 [2024-10-31 22:18:46,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:46,692 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2024-10-31 22:18:46,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:46,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542324971] [2024-10-31 22:18:46,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:46,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:46,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:46,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:46,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:46,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542324971] [2024-10-31 22:18:46,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542324971] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:46,781 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:46,781 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:46,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079459554] [2024-10-31 22:18:46,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:46,782 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:46,782 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:46,782 INFO L85 PathProgramCache]: Analyzing trace with hash 642955601, now seen corresponding path program 1 times [2024-10-31 22:18:46,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:46,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367952407] [2024-10-31 22:18:46,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:46,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:46,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:46,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:46,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:46,842 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [367952407] [2024-10-31 22:18:46,842 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [367952407] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:46,842 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:46,843 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:46,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032244983] [2024-10-31 22:18:46,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:46,843 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:46,844 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:46,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:46,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:46,845 INFO L87 Difference]: Start difference. First operand 27071 states and 38267 transitions. cyclomatic complexity: 11228 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:47,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:47,580 INFO L93 Difference]: Finished difference Result 63666 states and 89420 transitions. [2024-10-31 22:18:47,580 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63666 states and 89420 transitions. [2024-10-31 22:18:48,042 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 63140 [2024-10-31 22:18:48,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63666 states to 63666 states and 89420 transitions. [2024-10-31 22:18:48,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63666 [2024-10-31 22:18:48,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63666 [2024-10-31 22:18:48,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63666 states and 89420 transitions. [2024-10-31 22:18:48,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:48,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63666 states and 89420 transitions. [2024-10-31 22:18:48,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63666 states and 89420 transitions. [2024-10-31 22:18:49,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63666 to 51390. [2024-10-31 22:18:49,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51390 states, 51390 states have (on average 1.4080560420315236) internal successors, (72360), 51389 states have internal predecessors, (72360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:49,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51390 states to 51390 states and 72360 transitions. [2024-10-31 22:18:49,452 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51390 states and 72360 transitions. [2024-10-31 22:18:49,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:49,454 INFO L425 stractBuchiCegarLoop]: Abstraction has 51390 states and 72360 transitions. [2024-10-31 22:18:49,454 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-31 22:18:49,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51390 states and 72360 transitions. [2024-10-31 22:18:49,800 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 51024 [2024-10-31 22:18:49,800 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:49,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:49,803 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:49,803 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:49,803 INFO L745 eck$LassoCheckResult]: Stem: 213894#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 213895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 214787#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 214788#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 214688#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 214289#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 214290#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 214659#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 214068#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 214069#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 214572#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 214573#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 213562#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 213563#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 213767#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 214175#L939 assume !(0 == ~M_E~0); 214454#L939-2 assume !(0 == ~T1_E~0); 214455#L944-1 assume !(0 == ~T2_E~0); 214212#L949-1 assume !(0 == ~T3_E~0); 214210#L954-1 assume !(0 == ~T4_E~0); 214211#L959-1 assume !(0 == ~T5_E~0); 214706#L964-1 assume !(0 == ~T6_E~0); 213919#L969-1 assume !(0 == ~T7_E~0); 213920#L974-1 assume !(0 == ~T8_E~0); 214642#L979-1 assume !(0 == ~T9_E~0); 214643#L984-1 assume !(0 == ~E_M~0); 214082#L989-1 assume !(0 == ~E_1~0); 214083#L994-1 assume !(0 == ~E_2~0); 213968#L999-1 assume !(0 == ~E_3~0); 213969#L1004-1 assume !(0 == ~E_4~0); 213629#L1009-1 assume !(0 == ~E_5~0); 213630#L1014-1 assume !(0 == ~E_6~0); 213962#L1019-1 assume !(0 == ~E_7~0); 214580#L1024-1 assume !(0 == ~E_8~0); 213889#L1029-1 assume !(0 == ~E_9~0); 213890#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213975#L460 assume !(1 == ~m_pc~0); 214845#L460-2 is_master_triggered_~__retres1~0#1 := 0; 214537#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 214538#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 214672#L1167 assume !(0 != activate_threads_~tmp~1#1); 214195#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 214196#L479 assume !(1 == ~t1_pc~0); 214369#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 214370#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 213633#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 213634#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 213902#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213746#L498 assume !(1 == ~t2_pc~0); 213747#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 214174#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214072#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 214073#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 214525#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214526#L517 assume !(1 == ~t3_pc~0); 214888#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 214889#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 213569#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 213570#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 213939#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214589#L536 assume !(1 == ~t4_pc~0); 214240#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 214239#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 213727#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 213728#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 214232#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 214496#L555 assume !(1 == ~t5_pc~0); 214497#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 214581#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 214639#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 213891#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 213772#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 213669#L574 assume !(1 == ~t6_pc~0); 213670#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 214350#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 214061#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 214062#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 214607#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 214853#L593 assume !(1 == ~t7_pc~0); 213909#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 213910#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 214711#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 214894#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 214801#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 214077#L612 assume !(1 == ~t8_pc~0); 214078#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 214558#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 214612#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 214613#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 214352#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 214353#L631 assume 1 == ~t9_pc~0; 214367#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 213661#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 213662#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 214123#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 214176#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 214592#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 214593#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 214345#L1052-1 assume !(1 == ~T2_E~0); 214346#L1057-1 assume !(1 == ~T3_E~0); 213874#L1062-1 assume !(1 == ~T4_E~0); 213875#L1067-1 assume !(1 == ~T5_E~0); 214199#L1072-1 assume !(1 == ~T6_E~0); 214200#L1077-1 assume !(1 == ~T7_E~0); 213761#L1082-1 assume !(1 == ~T8_E~0); 213762#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 213556#L1092-1 assume !(1 == ~E_M~0); 213557#L1097-1 assume !(1 == ~E_1~0); 214838#L1102-1 assume !(1 == ~E_2~0); 214839#L1107-1 assume !(1 == ~E_3~0); 214348#L1112-1 assume !(1 == ~E_4~0); 214349#L1117-1 assume !(1 == ~E_5~0); 214912#L1122-1 assume !(1 == ~E_6~0); 214913#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 213980#L1132-1 assume !(1 == ~E_8~0); 213981#L1137-1 assume !(1 == ~E_9~0); 213870#L1142-1 assume { :end_inline_reset_delta_events } true; 213871#L1428-2 [2024-10-31 22:18:49,803 INFO L747 eck$LassoCheckResult]: Loop: 213871#L1428-2 assume !false; 259652#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 259651#L914-1 assume !false; 259650#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 259648#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 259639#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 259489#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 259479#L783 assume !(0 != eval_~tmp~0#1); 259480#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 260363#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 260361#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 260359#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 260357#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 260355#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 260353#L954-3 assume !(0 == ~T4_E~0); 260351#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 260349#L964-3 assume !(0 == ~T6_E~0); 260347#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 260345#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 260343#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 260341#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 260339#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 260337#L994-3 assume !(0 == ~E_2~0); 260335#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 260333#L1004-3 assume !(0 == ~E_4~0); 260331#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 260329#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 260327#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 260325#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 260323#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 260321#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 260319#L460-33 assume !(1 == ~m_pc~0); 260317#L460-35 is_master_triggered_~__retres1~0#1 := 0; 260315#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 260313#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 260311#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 260309#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 260307#L479-33 assume !(1 == ~t1_pc~0); 260305#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 260303#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260301#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 260299#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 260297#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 260294#L498-33 assume !(1 == ~t2_pc~0); 260291#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 260289#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 260287#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 260285#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 260283#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 260281#L517-33 assume !(1 == ~t3_pc~0); 260279#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 260277#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 260275#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 260273#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 260271#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 260269#L536-33 assume !(1 == ~t4_pc~0); 260266#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 260263#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 260261#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 260259#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 260257#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 260255#L555-33 assume !(1 == ~t5_pc~0); 260253#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 260251#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 260249#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 260247#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 260245#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 260243#L574-33 assume !(1 == ~t6_pc~0); 260240#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 260237#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 260235#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 260233#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 260231#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 260229#L593-33 assume !(1 == ~t7_pc~0); 237905#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 260227#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 260225#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 260223#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 260221#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 260219#L612-33 assume !(1 == ~t8_pc~0); 260215#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 260213#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 260211#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 260209#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 260207#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 260205#L631-33 assume !(1 == ~t9_pc~0); 260202#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 260199#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 260197#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 260195#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 260193#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260192#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 260189#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 260187#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 260185#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 260184#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 260181#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 260170#L1072-3 assume !(1 == ~T6_E~0); 260168#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 260166#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 260163#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 260162#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 260160#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 260158#L1102-3 assume !(1 == ~E_2~0); 260156#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 260154#L1112-3 assume !(1 == ~E_4~0); 260152#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 260150#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 260148#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 260146#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 260144#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 260142#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 260128#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 260121#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 260119#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 260000#L1447 assume !(0 == start_simulation_~tmp~3#1); 259998#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 259984#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 259977#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 259976#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 259975#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 259971#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 259969#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 259967#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 213871#L1428-2 [2024-10-31 22:18:49,804 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:49,805 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2024-10-31 22:18:49,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:49,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893365682] [2024-10-31 22:18:49,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:49,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:49,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:49,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:49,887 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:49,887 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893365682] [2024-10-31 22:18:49,887 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [893365682] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:49,887 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:49,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:49,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509803138] [2024-10-31 22:18:49,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:49,888 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:49,888 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:49,888 INFO L85 PathProgramCache]: Analyzing trace with hash -1910395498, now seen corresponding path program 1 times [2024-10-31 22:18:49,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:49,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960118412] [2024-10-31 22:18:49,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:49,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:49,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:49,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:49,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:49,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960118412] [2024-10-31 22:18:49,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1960118412] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:49,978 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:49,979 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:49,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [37174702] [2024-10-31 22:18:49,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:49,979 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:49,980 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:49,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:49,980 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:49,980 INFO L87 Difference]: Start difference. First operand 51390 states and 72360 transitions. cyclomatic complexity: 21002 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:50,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:50,750 INFO L93 Difference]: Finished difference Result 97613 states and 136917 transitions. [2024-10-31 22:18:50,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97613 states and 136917 transitions. [2024-10-31 22:18:51,309 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 96896 [2024-10-31 22:18:51,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97613 states to 97613 states and 136917 transitions. [2024-10-31 22:18:51,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97613 [2024-10-31 22:18:51,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97613 [2024-10-31 22:18:51,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97613 states and 136917 transitions. [2024-10-31 22:18:51,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:51,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97613 states and 136917 transitions. [2024-10-31 22:18:51,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97613 states and 136917 transitions. [2024-10-31 22:18:52,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97613 to 97485. [2024-10-31 22:18:52,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97485 states, 97485 states have (on average 1.4031799764066266) internal successors, (136789), 97484 states have internal predecessors, (136789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:53,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97485 states to 97485 states and 136789 transitions. [2024-10-31 22:18:53,640 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97485 states and 136789 transitions. [2024-10-31 22:18:53,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:53,640 INFO L425 stractBuchiCegarLoop]: Abstraction has 97485 states and 136789 transitions. [2024-10-31 22:18:53,641 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-31 22:18:53,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97485 states and 136789 transitions. [2024-10-31 22:18:53,817 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 96768 [2024-10-31 22:18:53,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:53,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:53,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:53,820 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:53,820 INFO L745 eck$LassoCheckResult]: Stem: 362902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 362903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 363847#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 363848#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 363733#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 363316#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 363317#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 363700#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 363087#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 363088#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 363604#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 363605#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 362574#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 362575#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 362775#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 363198#L939 assume !(0 == ~M_E~0); 363488#L939-2 assume !(0 == ~T1_E~0); 363489#L944-1 assume !(0 == ~T2_E~0); 363238#L949-1 assume !(0 == ~T3_E~0); 363234#L954-1 assume !(0 == ~T4_E~0); 363235#L959-1 assume !(0 == ~T5_E~0); 363757#L964-1 assume !(0 == ~T6_E~0); 362927#L969-1 assume !(0 == ~T7_E~0); 362928#L974-1 assume !(0 == ~T8_E~0); 363681#L979-1 assume !(0 == ~T9_E~0); 363682#L984-1 assume !(0 == ~E_M~0); 363101#L989-1 assume !(0 == ~E_1~0); 363102#L994-1 assume !(0 == ~E_2~0); 362979#L999-1 assume !(0 == ~E_3~0); 362980#L1004-1 assume !(0 == ~E_4~0); 362639#L1009-1 assume !(0 == ~E_5~0); 362640#L1014-1 assume !(0 == ~E_6~0); 362974#L1019-1 assume !(0 == ~E_7~0); 363612#L1024-1 assume !(0 == ~E_8~0); 362897#L1029-1 assume !(0 == ~E_9~0); 362898#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 362986#L460 assume !(1 == ~m_pc~0); 363897#L460-2 is_master_triggered_~__retres1~0#1 := 0; 363571#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 363572#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 363713#L1167 assume !(0 != activate_threads_~tmp~1#1); 363219#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 363220#L479 assume !(1 == ~t1_pc~0); 363395#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 363396#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362643#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 362644#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 362910#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 362754#L498 assume !(1 == ~t2_pc~0); 362755#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 363197#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 363091#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 363092#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 363561#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 363562#L517 assume !(1 == ~t3_pc~0); 363952#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 363953#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 362581#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 362582#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 362948#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 363618#L536 assume !(1 == ~t4_pc~0); 363269#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 363268#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 362736#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 362737#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 363260#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 363530#L555 assume !(1 == ~t5_pc~0); 363531#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 363613#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 363679#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 362899#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 362780#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 362678#L574 assume !(1 == ~t6_pc~0); 362679#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 363376#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363078#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 363079#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 363640#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 363908#L593 assume !(1 == ~t7_pc~0); 362918#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 362919#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 363760#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 363959#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 363863#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 363096#L612 assume !(1 == ~t8_pc~0); 363097#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 363592#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 363645#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 363646#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 363378#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 363379#L631 assume !(1 == ~t9_pc~0); 363451#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 362670#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 362671#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 363144#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 363199#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363623#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 363624#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 394196#L1052-1 assume !(1 == ~T2_E~0); 394195#L1057-1 assume !(1 == ~T3_E~0); 394194#L1062-1 assume !(1 == ~T4_E~0); 362882#L1067-1 assume !(1 == ~T5_E~0); 394193#L1072-1 assume !(1 == ~T6_E~0); 394192#L1077-1 assume !(1 == ~T7_E~0); 394191#L1082-1 assume !(1 == ~T8_E~0); 394190#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 394189#L1092-1 assume !(1 == ~E_M~0); 394188#L1097-1 assume !(1 == ~E_1~0); 394185#L1102-1 assume !(1 == ~E_2~0); 394183#L1107-1 assume !(1 == ~E_3~0); 394181#L1112-1 assume !(1 == ~E_4~0); 394179#L1117-1 assume !(1 == ~E_5~0); 394177#L1122-1 assume !(1 == ~E_6~0); 394175#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 394173#L1132-1 assume !(1 == ~E_8~0); 394171#L1137-1 assume !(1 == ~E_9~0); 394169#L1142-1 assume { :end_inline_reset_delta_events } true; 394166#L1428-2 [2024-10-31 22:18:53,820 INFO L747 eck$LassoCheckResult]: Loop: 394166#L1428-2 assume !false; 394069#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 394067#L914-1 assume !false; 394065#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 394060#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 394050#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 394048#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 394045#L783 assume !(0 != eval_~tmp~0#1); 394046#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 403505#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 403502#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 403500#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 403498#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 403496#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 403494#L954-3 assume !(0 == ~T4_E~0); 403492#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 403489#L964-3 assume !(0 == ~T6_E~0); 403487#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 403485#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 403483#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 403481#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 403479#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 403476#L994-3 assume !(0 == ~E_2~0); 403474#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 403472#L1004-3 assume !(0 == ~E_4~0); 403470#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 403468#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 403466#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 403463#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 403461#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 403459#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 403457#L460-33 assume !(1 == ~m_pc~0); 402995#L460-35 is_master_triggered_~__retres1~0#1 := 0; 402714#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 394421#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 394420#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 394419#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394408#L479-33 assume !(1 == ~t1_pc~0); 394406#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 394404#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 394401#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 394400#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 394398#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 394396#L498-33 assume !(1 == ~t2_pc~0); 394393#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 394391#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 394389#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 394387#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 394385#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 394383#L517-33 assume !(1 == ~t3_pc~0); 394381#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 394379#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 394377#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 394375#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 394372#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 394370#L536-33 assume !(1 == ~t4_pc~0); 394368#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 394365#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 394363#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 394361#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 394359#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 394357#L555-33 assume !(1 == ~t5_pc~0); 394355#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 394353#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 394351#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 394349#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 394347#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 394344#L574-33 assume !(1 == ~t6_pc~0); 394342#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 394339#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 394337#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 394335#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 394333#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 394331#L593-33 assume !(1 == ~t7_pc~0); 386821#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 394328#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 394326#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 394324#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 394322#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 394319#L612-33 assume !(1 == ~t8_pc~0); 394316#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 394314#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 394312#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 394310#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 394308#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 394307#L631-33 assume !(1 == ~t9_pc~0); 394305#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 394303#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 394301#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 394299#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 394297#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 394294#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 394290#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 394288#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 394286#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 394284#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 394280#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 394278#L1072-3 assume !(1 == ~T6_E~0); 394276#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 394274#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 394272#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 394270#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 394268#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 394266#L1102-3 assume !(1 == ~E_2~0); 394264#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 394262#L1112-3 assume !(1 == ~E_4~0); 394260#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 394258#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 394256#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 394254#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 394252#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 394250#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 394238#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 394231#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 394229#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 394225#L1447 assume !(0 == start_simulation_~tmp~3#1); 394224#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 394219#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 394213#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 394212#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 394211#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 394209#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 394207#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 394168#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 394166#L1428-2 [2024-10-31 22:18:53,821 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:53,821 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2024-10-31 22:18:53,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:53,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946285009] [2024-10-31 22:18:53,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:53,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:53,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:53,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:53,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:53,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1946285009] [2024-10-31 22:18:53,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1946285009] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:53,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:53,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:53,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1682188770] [2024-10-31 22:18:53,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:53,905 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:53,905 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:53,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1910395498, now seen corresponding path program 2 times [2024-10-31 22:18:53,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:53,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119181036] [2024-10-31 22:18:53,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:53,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:53,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:53,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:53,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:53,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119181036] [2024-10-31 22:18:53,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119181036] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:53,978 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:53,979 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:53,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170308497] [2024-10-31 22:18:53,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:53,979 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:53,979 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:53,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:53,980 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:53,980 INFO L87 Difference]: Start difference. First operand 97485 states and 136789 transitions. cyclomatic complexity: 39368 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:54,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:54,894 INFO L93 Difference]: Finished difference Result 144585 states and 203180 transitions. [2024-10-31 22:18:54,895 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144585 states and 203180 transitions. [2024-10-31 22:18:55,331 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 143584 [2024-10-31 22:18:56,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144585 states to 144585 states and 203180 transitions. [2024-10-31 22:18:56,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144585 [2024-10-31 22:18:56,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144585 [2024-10-31 22:18:56,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144585 states and 203180 transitions. [2024-10-31 22:18:56,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:56,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144585 states and 203180 transitions. [2024-10-31 22:18:56,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144585 states and 203180 transitions. [2024-10-31 22:18:57,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144585 to 98745. [2024-10-31 22:18:57,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98745 states, 98745 states have (on average 1.4088612081624385) internal successors, (139118), 98744 states have internal predecessors, (139118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:57,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98745 states to 98745 states and 139118 transitions. [2024-10-31 22:18:57,803 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98745 states and 139118 transitions. [2024-10-31 22:18:57,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:57,805 INFO L425 stractBuchiCegarLoop]: Abstraction has 98745 states and 139118 transitions. [2024-10-31 22:18:57,805 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-31 22:18:57,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98745 states and 139118 transitions. [2024-10-31 22:18:58,046 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98048 [2024-10-31 22:18:58,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:58,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:58,051 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:58,051 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:58,052 INFO L745 eck$LassoCheckResult]: Stem: 604980#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 604981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 605866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 605867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 605777#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 605382#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 605383#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 605745#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 605158#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 605159#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 605654#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 605655#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 604653#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 604654#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 604855#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 605267#L939 assume !(0 == ~M_E~0); 605539#L939-2 assume !(0 == ~T1_E~0); 605540#L944-1 assume !(0 == ~T2_E~0); 605305#L949-1 assume !(0 == ~T3_E~0); 605303#L954-1 assume !(0 == ~T4_E~0); 605304#L959-1 assume !(0 == ~T5_E~0); 605797#L964-1 assume !(0 == ~T6_E~0); 605002#L969-1 assume !(0 == ~T7_E~0); 605003#L974-1 assume !(0 == ~T8_E~0); 605728#L979-1 assume !(0 == ~T9_E~0); 605729#L984-1 assume !(0 == ~E_M~0); 605173#L989-1 assume !(0 == ~E_1~0); 605174#L994-1 assume !(0 == ~E_2~0); 605054#L999-1 assume !(0 == ~E_3~0); 605055#L1004-1 assume !(0 == ~E_4~0); 604720#L1009-1 assume !(0 == ~E_5~0); 604721#L1014-1 assume !(0 == ~E_6~0); 605051#L1019-1 assume !(0 == ~E_7~0); 605660#L1024-1 assume !(0 == ~E_8~0); 604973#L1029-1 assume !(0 == ~E_9~0); 604974#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 605064#L460 assume !(1 == ~m_pc~0); 605903#L460-2 is_master_triggered_~__retres1~0#1 := 0; 605617#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 605618#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 605758#L1167 assume !(0 != activate_threads_~tmp~1#1); 605288#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 605289#L479 assume !(1 == ~t1_pc~0); 605457#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 605458#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 604726#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 604727#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 604989#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 604834#L498 assume !(1 == ~t2_pc~0); 604835#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 605266#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 605160#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 605161#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 605605#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 605606#L517 assume !(1 == ~t3_pc~0); 605953#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 605954#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 604660#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 604661#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 605022#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 605670#L536 assume !(1 == ~t4_pc~0); 605333#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 605332#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 604820#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 604821#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 605327#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 605581#L555 assume !(1 == ~t5_pc~0); 605582#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 605661#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 605723#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 604977#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 604860#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 604758#L574 assume !(1 == ~t6_pc~0); 604759#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 605440#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 605150#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 605151#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 605690#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 605913#L593 assume !(1 == ~t7_pc~0); 604994#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 604995#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 605802#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 605958#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 605881#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 605166#L612 assume !(1 == ~t8_pc~0); 605167#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 605639#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 605695#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 605696#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 605442#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 605443#L631 assume !(1 == ~t9_pc~0); 605509#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 604749#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 604750#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 605214#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 605268#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 605671#L1047 assume !(1 == ~M_E~0); 604689#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 604690#L1052-1 assume !(1 == ~T2_E~0); 604670#L1057-1 assume !(1 == ~T3_E~0); 604671#L1062-1 assume !(1 == ~T4_E~0); 604959#L1067-1 assume !(1 == ~T5_E~0); 605292#L1072-1 assume !(1 == ~T6_E~0); 605293#L1077-1 assume !(1 == ~T7_E~0); 604849#L1082-1 assume !(1 == ~T8_E~0); 604850#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 604649#L1092-1 assume !(1 == ~E_M~0); 604650#L1097-1 assume !(1 == ~E_1~0); 604672#L1102-1 assume !(1 == ~E_2~0); 605505#L1107-1 assume !(1 == ~E_3~0); 605438#L1112-1 assume !(1 == ~E_4~0); 605439#L1117-1 assume !(1 == ~E_5~0); 605479#L1122-1 assume !(1 == ~E_6~0); 605348#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 605067#L1132-1 assume !(1 == ~E_8~0); 605068#L1137-1 assume !(1 == ~E_9~0); 604957#L1142-1 assume { :end_inline_reset_delta_events } true; 604958#L1428-2 [2024-10-31 22:18:58,052 INFO L747 eck$LassoCheckResult]: Loop: 604958#L1428-2 assume !false; 642501#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 642377#L914-1 assume !false; 642497#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 642491#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 642481#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 642479#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 642476#L783 assume !(0 != eval_~tmp~0#1); 642477#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 651171#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 651154#L939-3 assume !(0 == ~M_E~0); 651150#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 651145#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 651140#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 651135#L954-3 assume !(0 == ~T4_E~0); 651130#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 651125#L964-3 assume !(0 == ~T6_E~0); 651120#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 651113#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 651109#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 651104#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 651100#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 651096#L994-3 assume !(0 == ~E_2~0); 651091#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 651087#L1004-3 assume !(0 == ~E_4~0); 651082#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 651078#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 651073#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 651068#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 651063#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 651057#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 651052#L460-33 assume !(1 == ~m_pc~0); 651046#L460-35 is_master_triggered_~__retres1~0#1 := 0; 651041#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 651036#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 651031#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 651024#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 651019#L479-33 assume !(1 == ~t1_pc~0); 651013#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 651008#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 651003#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 650998#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 650992#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 650987#L498-33 assume !(1 == ~t2_pc~0); 650981#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 650977#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 650973#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 650968#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 650962#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 650956#L517-33 assume !(1 == ~t3_pc~0); 650950#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 650945#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 650940#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 650935#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 650928#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 650922#L536-33 assume !(1 == ~t4_pc~0); 650917#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 650910#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 650904#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 650897#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 650890#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 650883#L555-33 assume !(1 == ~t5_pc~0); 650876#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 650870#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 650863#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 650857#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 650849#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 650844#L574-33 assume !(1 == ~t6_pc~0); 650767#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 650763#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 650761#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 650759#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 650757#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 650755#L593-33 assume !(1 == ~t7_pc~0); 647625#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 650752#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 650749#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 650747#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 650745#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 650743#L612-33 assume 1 == ~t8_pc~0; 650741#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 650738#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 650737#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 650734#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 650732#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 650730#L631-33 assume !(1 == ~t9_pc~0); 650728#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 650726#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 650724#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 650722#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 650720#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 650718#L1047-3 assume !(1 == ~M_E~0); 618483#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 650715#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 650713#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 650710#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 650708#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 650706#L1072-3 assume !(1 == ~T6_E~0); 650704#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 650702#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 650700#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 650697#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 650695#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 650693#L1102-3 assume !(1 == ~E_2~0); 650691#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 650689#L1112-3 assume !(1 == ~E_4~0); 650687#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 650686#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 650656#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 650649#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 650642#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 650635#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 641554#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 641548#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 641535#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 618464#L1447 assume !(0 == start_simulation_~tmp~3#1); 618465#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 642522#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 642515#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 642513#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 642511#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 642509#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 642507#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 642505#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 604958#L1428-2 [2024-10-31 22:18:58,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:58,053 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2024-10-31 22:18:58,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:58,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586155085] [2024-10-31 22:18:58,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:58,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:58,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:58,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:58,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:58,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1586155085] [2024-10-31 22:18:58,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1586155085] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:58,173 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:58,173 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:58,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953372580] [2024-10-31 22:18:58,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:58,174 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:58,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:58,176 INFO L85 PathProgramCache]: Analyzing trace with hash 892581909, now seen corresponding path program 1 times [2024-10-31 22:18:58,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:58,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371502832] [2024-10-31 22:18:58,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:58,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:58,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:58,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:58,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:58,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371502832] [2024-10-31 22:18:58,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1371502832] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:58,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:58,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:58,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19237116] [2024-10-31 22:18:58,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:58,271 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:58,271 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:58,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:58,272 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:58,272 INFO L87 Difference]: Start difference. First operand 98745 states and 139118 transitions. cyclomatic complexity: 40405 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:59,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:59,389 INFO L93 Difference]: Finished difference Result 98745 states and 138732 transitions. [2024-10-31 22:18:59,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98745 states and 138732 transitions. [2024-10-31 22:18:59,782 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98048 [2024-10-31 22:18:59,961 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98745 states to 98745 states and 138732 transitions. [2024-10-31 22:18:59,961 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98745 [2024-10-31 22:19:00,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98745 [2024-10-31 22:19:00,015 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98745 states and 138732 transitions. [2024-10-31 22:19:00,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:19:00,071 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98745 states and 138732 transitions. [2024-10-31 22:19:00,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98745 states and 138732 transitions.