./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:07:03,256 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:07:03,389 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:07:03,399 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:07:03,400 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:07:03,439 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:07:03,439 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:07:03,440 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:07:03,441 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:07:03,441 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:07:03,442 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:07:03,442 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:07:03,443 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:07:03,443 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:07:03,444 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:07:03,444 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:07:03,444 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:07:03,445 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:07:03,445 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:07:03,446 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:07:03,446 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:07:03,447 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:07:03,447 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:07:03,448 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:07:03,448 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:07:03,448 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:07:03,449 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:07:03,449 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:07:03,449 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:07:03,450 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:07:03,450 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:07:03,450 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:07:03,451 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:07:03,451 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:07:03,451 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:07:03,452 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:07:03,452 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:07:03,452 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:07:03,453 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:07:03,453 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2024-10-31 22:07:03,828 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:07:03,865 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:07:03,868 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:07:03,870 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:07:03,871 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:07:03,872 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/transmitter.02.cil.c Unable to find full path for "g++" [2024-10-31 22:07:05,902 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:07:06,116 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:07:06,116 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/sv-benchmarks/c/systemc/transmitter.02.cil.c [2024-10-31 22:07:06,128 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/data/f919e20d6/a33cd657d43c403e9a15815f81dcaa67/FLAG0706a1a4c [2024-10-31 22:07:06,478 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/data/f919e20d6/a33cd657d43c403e9a15815f81dcaa67 [2024-10-31 22:07:06,480 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:07:06,482 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:07:06,483 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:07:06,483 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:07:06,489 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:07:06,490 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,491 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1ae0aa10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06, skipping insertion in model container [2024-10-31 22:07:06,491 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,521 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:07:06,750 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:07:06,765 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:07:06,802 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:07:06,820 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:07:06,820 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06 WrapperNode [2024-10-31 22:07:06,820 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:07:06,821 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:07:06,821 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:07:06,821 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:07:06,827 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,834 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,874 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 45, statements flattened = 536 [2024-10-31 22:07:06,875 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:07:06,875 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:07:06,876 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:07:06,876 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:07:06,887 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,887 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,890 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,905 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:07:06,905 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,905 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,919 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,928 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,934 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,936 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,944 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:07:06,949 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:07:06,949 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:07:06,949 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:07:06,950 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (1/1) ... [2024-10-31 22:07:06,957 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:06,969 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:06,981 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:06,984 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:07:07,009 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:07:07,009 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:07:07,009 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:07:07,009 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:07:07,087 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:07:07,089 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:07:07,862 INFO L? ?]: Removed 90 outVars from TransFormulas that were not future-live. [2024-10-31 22:07:07,862 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:07:07,884 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:07:07,885 INFO L316 CfgBuilder]: Removed 6 assume(true) statements. [2024-10-31 22:07:07,885 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:07:07 BoogieIcfgContainer [2024-10-31 22:07:07,886 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:07:07,887 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:07:07,887 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:07:07,891 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:07:07,892 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:07:07,892 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:07:06" (1/3) ... [2024-10-31 22:07:07,893 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@30da9bde and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:07:07, skipping insertion in model container [2024-10-31 22:07:07,893 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:07:07,894 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:07:06" (2/3) ... [2024-10-31 22:07:07,894 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@30da9bde and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:07:07, skipping insertion in model container [2024-10-31 22:07:07,894 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:07:07,894 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:07:07" (3/3) ... [2024-10-31 22:07:07,896 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2024-10-31 22:07:07,960 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:07:07,960 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:07:07,960 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:07:07,960 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:07:07,961 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:07:07,961 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:07:07,962 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:07:07,962 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:07:07,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:08,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2024-10-31 22:07:08,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:08,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:08,012 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:08,012 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:08,012 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:07:08,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:08,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2024-10-31 22:07:08,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:08,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:08,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:08,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:08,038 INFO L745 eck$LassoCheckResult]: Stem: 147#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 158#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 205#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 182#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 60#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 42#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 162#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33#L334true assume !(0 == ~M_E~0); 169#L334-2true assume !(0 == ~T1_E~0); 113#L339-1true assume !(0 == ~T2_E~0); 108#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 143#L349-1true assume !(0 == ~E_2~0); 41#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117#L156true assume !(1 == ~m_pc~0); 154#L156-2true is_master_triggered_~__retres1~0#1 := 0; 136#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128#is_master_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 78#L405true assume !(0 != activate_threads_~tmp~1#1); 63#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126#L175true assume 1 == ~t1_pc~0; 161#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 115#L413true assume !(0 != activate_threads_~tmp___0~0#1); 185#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187#L194true assume !(1 == ~t2_pc~0); 203#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 70#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27#L421true assume !(0 != activate_threads_~tmp___1~0#1); 85#L421-2true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12#L367true assume !(1 == ~M_E~0); 186#L367-2true assume !(1 == ~T1_E~0); 130#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 132#L377-1true assume !(1 == ~E_1~0); 25#L382-1true assume !(1 == ~E_2~0); 80#L387-1true assume { :end_inline_reset_delta_events } true; 107#L528-2true [2024-10-31 22:07:08,040 INFO L747 eck$LassoCheckResult]: Loop: 107#L528-2true assume !false; 88#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17#L309-1true assume false; 82#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 207#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 159#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 116#L339-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 183#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 76#L349-3true assume !(0 == ~E_2~0); 32#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101#L156-9true assume !(1 == ~m_pc~0); 4#L156-11true is_master_triggered_~__retres1~0#1 := 0; 57#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135#is_master_triggered_returnLabel#4true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 118#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192#L175-9true assume !(1 == ~t1_pc~0); 141#L175-11true is_transmit1_triggered_~__retres1~1#1 := 0; 14#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201#is_transmit1_triggered_returnLabel#4true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 153#L413-9true assume !(0 != activate_threads_~tmp___0~0#1); 146#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190#L194-9true assume !(1 == ~t2_pc~0); 28#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 196#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5#is_transmit2_triggered_returnLabel#4true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 110#L421-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144#L421-11true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 7#L367-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 34#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 18#L377-3true assume !(1 == ~E_1~0); 30#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 111#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 145#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 180#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 188#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 152#L547true assume !(0 == start_simulation_~tmp~3#1); 166#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 149#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 52#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 40#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 20#L560true assume !(0 != start_simulation_~tmp___0~1#1); 107#L528-2true [2024-10-31 22:07:08,047 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:08,047 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2024-10-31 22:07:08,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:08,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91062255] [2024-10-31 22:07:08,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:08,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:08,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:08,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:08,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:08,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91062255] [2024-10-31 22:07:08,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91062255] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:08,299 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:08,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:08,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958349361] [2024-10-31 22:07:08,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:08,306 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:07:08,307 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:08,307 INFO L85 PathProgramCache]: Analyzing trace with hash -294698413, now seen corresponding path program 1 times [2024-10-31 22:07:08,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:08,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416286428] [2024-10-31 22:07:08,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:08,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:08,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:08,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:08,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:08,353 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416286428] [2024-10-31 22:07:08,353 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416286428] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:08,353 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:08,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:07:08,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288041979] [2024-10-31 22:07:08,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:08,355 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:08,360 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:08,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:08,393 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:08,395 INFO L87 Difference]: Start difference. First operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:08,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:08,445 INFO L93 Difference]: Finished difference Result 207 states and 302 transitions. [2024-10-31 22:07:08,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207 states and 302 transitions. [2024-10-31 22:07:08,452 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-10-31 22:07:08,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207 states to 201 states and 296 transitions. [2024-10-31 22:07:08,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2024-10-31 22:07:08,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2024-10-31 22:07:08,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 296 transitions. [2024-10-31 22:07:08,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:08,462 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2024-10-31 22:07:08,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 296 transitions. [2024-10-31 22:07:08,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2024-10-31 22:07:08,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.472636815920398) internal successors, (296), 200 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:08,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 296 transitions. [2024-10-31 22:07:08,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2024-10-31 22:07:08,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:08,517 INFO L425 stractBuchiCegarLoop]: Abstraction has 201 states and 296 transitions. [2024-10-31 22:07:08,517 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:07:08,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 296 transitions. [2024-10-31 22:07:08,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-10-31 22:07:08,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:08,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:08,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:08,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:08,527 INFO L745 eck$LassoCheckResult]: Stem: 608#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 617#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 616#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 530#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 505#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 506#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 489#L334 assume !(0 == ~M_E~0); 490#L334-2 assume !(0 == ~T1_E~0); 585#L339-1 assume !(0 == ~T2_E~0); 579#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 580#L349-1 assume !(0 == ~E_2~0); 503#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 504#L156 assume !(1 == ~m_pc~0); 436#L156-2 is_master_triggered_~__retres1~0#1 := 0; 435#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 597#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 552#L405 assume !(0 != activate_threads_~tmp~1#1); 534#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 535#L175 assume 1 == ~t1_pc~0; 594#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 536#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 500#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 501#L413 assume !(0 != activate_threads_~tmp___0~0#1); 587#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 624#L194 assume !(1 == ~t2_pc~0); 578#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 546#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 478#L421 assume !(0 != activate_threads_~tmp___1~0#1); 479#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448#L367 assume !(1 == ~M_E~0); 449#L367-2 assume !(1 == ~T1_E~0); 598#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 599#L377-1 assume !(1 == ~E_1~0); 475#L382-1 assume !(1 == ~E_2~0); 476#L387-1 assume { :end_inline_reset_delta_events } true; 465#L528-2 [2024-10-31 22:07:08,527 INFO L747 eck$LassoCheckResult]: Loop: 465#L528-2 assume !false; 559#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 458#L309-1 assume !false; 459#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 439#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 440#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 447#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 425#L276 assume !(0 != eval_~tmp~0#1); 427#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 584#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 618#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 588#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 589#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 551#L349-3 assume !(0 == ~E_2~0); 487#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488#L156-9 assume 1 == ~m_pc~0; 573#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 431#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 527#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 590#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 466#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 467#L175-9 assume 1 == ~t1_pc~0; 512#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 452#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 606#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607#L194-9 assume !(1 == ~t2_pc~0); 480#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 481#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 432#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 433#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 582#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 523#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 437#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 438#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 460#L377-3 assume !(1 == ~E_1~0); 461#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 484#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 583#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 492#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 613#L547 assume !(0 == start_simulation_~tmp~3#1); 600#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 610#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 521#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 495#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 496#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 502#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 517#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 464#L560 assume !(0 != start_simulation_~tmp___0~1#1); 465#L528-2 [2024-10-31 22:07:08,528 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:08,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2024-10-31 22:07:08,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:08,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244907607] [2024-10-31 22:07:08,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:08,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:08,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:08,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:08,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:08,608 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244907607] [2024-10-31 22:07:08,608 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1244907607] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:08,608 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:08,609 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:08,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220529515] [2024-10-31 22:07:08,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:08,610 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:07:08,610 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:08,610 INFO L85 PathProgramCache]: Analyzing trace with hash -724130786, now seen corresponding path program 1 times [2024-10-31 22:07:08,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:08,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075300760] [2024-10-31 22:07:08,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:08,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:08,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:08,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:08,702 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:08,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075300760] [2024-10-31 22:07:08,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075300760] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:08,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:08,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:08,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163021849] [2024-10-31 22:07:08,703 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:08,704 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:08,704 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:08,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:08,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:08,706 INFO L87 Difference]: Start difference. First operand 201 states and 296 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:08,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:08,731 INFO L93 Difference]: Finished difference Result 201 states and 295 transitions. [2024-10-31 22:07:08,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201 states and 295 transitions. [2024-10-31 22:07:08,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-10-31 22:07:08,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201 states to 201 states and 295 transitions. [2024-10-31 22:07:08,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2024-10-31 22:07:08,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2024-10-31 22:07:08,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 295 transitions. [2024-10-31 22:07:08,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:08,741 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2024-10-31 22:07:08,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 295 transitions. [2024-10-31 22:07:08,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2024-10-31 22:07:08,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.4676616915422886) internal successors, (295), 200 states have internal predecessors, (295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:08,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 295 transitions. [2024-10-31 22:07:08,757 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2024-10-31 22:07:08,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:08,758 INFO L425 stractBuchiCegarLoop]: Abstraction has 201 states and 295 transitions. [2024-10-31 22:07:08,758 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:07:08,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 295 transitions. [2024-10-31 22:07:08,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-10-31 22:07:08,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:08,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:08,762 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:08,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:08,762 INFO L745 eck$LassoCheckResult]: Stem: 1017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1025#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 939#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 914#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 915#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 898#L334 assume !(0 == ~M_E~0); 899#L334-2 assume !(0 == ~T1_E~0); 994#L339-1 assume !(0 == ~T2_E~0); 988#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 989#L349-1 assume !(0 == ~E_2~0); 912#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 913#L156 assume !(1 == ~m_pc~0); 845#L156-2 is_master_triggered_~__retres1~0#1 := 0; 844#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 961#L405 assume !(0 != activate_threads_~tmp~1#1); 943#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 944#L175 assume 1 == ~t1_pc~0; 1003#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 945#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 909#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 910#L413 assume !(0 != activate_threads_~tmp___0~0#1); 996#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1033#L194 assume !(1 == ~t2_pc~0); 987#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 955#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 887#L421 assume !(0 != activate_threads_~tmp___1~0#1); 888#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 857#L367 assume !(1 == ~M_E~0); 858#L367-2 assume !(1 == ~T1_E~0); 1007#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1008#L377-1 assume !(1 == ~E_1~0); 884#L382-1 assume !(1 == ~E_2~0); 885#L387-1 assume { :end_inline_reset_delta_events } true; 874#L528-2 [2024-10-31 22:07:08,763 INFO L747 eck$LassoCheckResult]: Loop: 874#L528-2 assume !false; 968#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 867#L309-1 assume !false; 868#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 848#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 849#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 856#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 834#L276 assume !(0 != eval_~tmp~0#1); 836#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 964#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 993#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1027#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 997#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 998#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 960#L349-3 assume !(0 == ~E_2~0); 896#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 897#L156-9 assume 1 == ~m_pc~0; 982#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 840#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 936#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 999#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 875#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 876#L175-9 assume 1 == ~t1_pc~0; 921#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 861#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 862#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1023#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1015#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1016#L194-9 assume 1 == ~t2_pc~0; 963#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 890#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 841#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 842#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 991#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 932#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 846#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 847#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 869#L377-3 assume !(1 == ~E_1~0); 870#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 893#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 992#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 901#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1032#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1022#L547 assume !(0 == start_simulation_~tmp~3#1); 1009#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1019#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 930#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 905#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 911#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 926#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 873#L560 assume !(0 != start_simulation_~tmp___0~1#1); 874#L528-2 [2024-10-31 22:07:08,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:08,764 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2024-10-31 22:07:08,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:08,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208097806] [2024-10-31 22:07:08,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:08,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:08,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:08,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:08,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:08,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208097806] [2024-10-31 22:07:08,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1208097806] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:08,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:08,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:08,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50492037] [2024-10-31 22:07:08,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:08,880 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:07:08,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:08,880 INFO L85 PathProgramCache]: Analyzing trace with hash 866264191, now seen corresponding path program 1 times [2024-10-31 22:07:08,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:08,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800416654] [2024-10-31 22:07:08,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:08,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:08,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:08,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:08,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:08,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800416654] [2024-10-31 22:07:08,967 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800416654] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:08,967 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:08,967 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:08,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708840816] [2024-10-31 22:07:08,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:08,968 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:08,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:08,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:07:08,969 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:07:08,969 INFO L87 Difference]: Start difference. First operand 201 states and 295 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:09,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:09,230 INFO L93 Difference]: Finished difference Result 342 states and 498 transitions. [2024-10-31 22:07:09,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 498 transitions. [2024-10-31 22:07:09,243 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2024-10-31 22:07:09,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 498 transitions. [2024-10-31 22:07:09,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2024-10-31 22:07:09,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2024-10-31 22:07:09,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 498 transitions. [2024-10-31 22:07:09,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:09,253 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 498 transitions. [2024-10-31 22:07:09,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 498 transitions. [2024-10-31 22:07:09,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 340. [2024-10-31 22:07:09,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 340 states, 340 states have (on average 1.4588235294117646) internal successors, (496), 339 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:09,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 496 transitions. [2024-10-31 22:07:09,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 340 states and 496 transitions. [2024-10-31 22:07:09,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:07:09,271 INFO L425 stractBuchiCegarLoop]: Abstraction has 340 states and 496 transitions. [2024-10-31 22:07:09,272 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:07:09,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 340 states and 496 transitions. [2024-10-31 22:07:09,274 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2024-10-31 22:07:09,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:09,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:09,275 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:09,276 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:09,276 INFO L745 eck$LassoCheckResult]: Stem: 1591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1602#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1599#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1600#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1501#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1472#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1473#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1454#L334 assume !(0 == ~M_E~0); 1455#L334-2 assume !(0 == ~T1_E~0); 1561#L339-1 assume !(0 == ~T2_E~0); 1554#L344-1 assume !(0 == ~E_1~0); 1555#L349-1 assume !(0 == ~E_2~0); 1470#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1471#L156 assume !(1 == ~m_pc~0); 1398#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1397#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1578#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1525#L405 assume !(0 != activate_threads_~tmp~1#1); 1505#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1506#L175 assume 1 == ~t1_pc~0; 1575#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1507#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1467#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1563#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1612#L194 assume !(1 == ~t2_pc~0); 1552#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1517#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1442#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1443#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1411#L367 assume !(1 == ~M_E~0); 1412#L367-2 assume !(1 == ~T1_E~0); 1579#L372-1 assume !(1 == ~T2_E~0); 1580#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1439#L382-1 assume !(1 == ~E_2~0); 1440#L387-1 assume { :end_inline_reset_delta_events } true; 1429#L528-2 [2024-10-31 22:07:09,276 INFO L747 eck$LassoCheckResult]: Loop: 1429#L528-2 assume !false; 1553#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1421#L309-1 assume !false; 1422#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1401#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1402#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1409#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1410#L276 assume !(0 != eval_~tmp~0#1); 1528#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1529#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1619#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1603#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1604#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1620#L344-3 assume !(0 == ~E_1~0); 1695#L349-3 assume !(0 == ~E_2~0); 1694#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1693#L156-9 assume !(1 == ~m_pc~0); 1691#L156-11 is_master_triggered_~__retres1~0#1 := 0; 1690#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1689#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1688#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1687#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1686#L175-9 assume 1 == ~t1_pc~0; 1481#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1415#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1416#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1598#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1589#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1590#L194-9 assume 1 == ~t2_pc~0; 1613#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1680#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1679#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1678#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1677#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1676#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1675#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1674#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L377-3 assume !(1 == ~E_1~0); 1425#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1673#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1672#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1669#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1668#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1666#L547 assume !(0 == start_simulation_~tmp~3#1); 1664#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1593#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1595#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1462#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1486#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1487#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1428#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1429#L528-2 [2024-10-31 22:07:09,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:09,277 INFO L85 PathProgramCache]: Analyzing trace with hash -1288865440, now seen corresponding path program 1 times [2024-10-31 22:07:09,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:09,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520858950] [2024-10-31 22:07:09,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:09,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:09,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:09,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:09,340 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:09,340 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520858950] [2024-10-31 22:07:09,340 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520858950] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:09,341 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:09,341 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:07:09,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983705218] [2024-10-31 22:07:09,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:09,342 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:07:09,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:09,342 INFO L85 PathProgramCache]: Analyzing trace with hash 1551047712, now seen corresponding path program 1 times [2024-10-31 22:07:09,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:09,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617401961] [2024-10-31 22:07:09,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:09,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:09,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:09,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:09,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:09,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617401961] [2024-10-31 22:07:09,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617401961] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:09,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:09,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:09,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [194492423] [2024-10-31 22:07:09,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:09,399 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:09,399 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:09,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:09,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:09,400 INFO L87 Difference]: Start difference. First operand 340 states and 496 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:09,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:09,456 INFO L93 Difference]: Finished difference Result 582 states and 842 transitions. [2024-10-31 22:07:09,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 582 states and 842 transitions. [2024-10-31 22:07:09,461 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 535 [2024-10-31 22:07:09,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 582 states to 582 states and 842 transitions. [2024-10-31 22:07:09,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 582 [2024-10-31 22:07:09,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 582 [2024-10-31 22:07:09,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 582 states and 842 transitions. [2024-10-31 22:07:09,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:09,469 INFO L218 hiAutomatonCegarLoop]: Abstraction has 582 states and 842 transitions. [2024-10-31 22:07:09,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states and 842 transitions. [2024-10-31 22:07:09,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 578. [2024-10-31 22:07:09,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 578 states, 578 states have (on average 1.4498269896193772) internal successors, (838), 577 states have internal predecessors, (838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:09,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 578 states to 578 states and 838 transitions. [2024-10-31 22:07:09,502 INFO L240 hiAutomatonCegarLoop]: Abstraction has 578 states and 838 transitions. [2024-10-31 22:07:09,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:09,504 INFO L425 stractBuchiCegarLoop]: Abstraction has 578 states and 838 transitions. [2024-10-31 22:07:09,504 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:07:09,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 578 states and 838 transitions. [2024-10-31 22:07:09,507 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2024-10-31 22:07:09,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:09,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:09,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:09,509 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:09,509 INFO L745 eck$LassoCheckResult]: Stem: 2518#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2531#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2526#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2527#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2428#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2400#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2401#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2382#L334 assume !(0 == ~M_E~0); 2383#L334-2 assume !(0 == ~T1_E~0); 2490#L339-1 assume !(0 == ~T2_E~0); 2483#L344-1 assume !(0 == ~E_1~0); 2484#L349-1 assume !(0 == ~E_2~0); 2398#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2399#L156 assume !(1 == ~m_pc~0); 2329#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2328#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2501#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2453#L405 assume !(0 != activate_threads_~tmp~1#1); 2436#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2437#L175 assume !(1 == ~t1_pc~0); 2441#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2438#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2394#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2395#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2492#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2545#L194 assume !(1 == ~t2_pc~0); 2482#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2448#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2449#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2370#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2371#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2339#L367 assume !(1 == ~M_E~0); 2340#L367-2 assume !(1 == ~T1_E~0); 2502#L372-1 assume !(1 == ~T2_E~0); 2503#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2506#L382-1 assume !(1 == ~E_2~0); 2825#L387-1 assume { :end_inline_reset_delta_events } true; 2823#L528-2 [2024-10-31 22:07:09,510 INFO L747 eck$LassoCheckResult]: Loop: 2823#L528-2 assume !false; 2785#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2783#L309-1 assume !false; 2782#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2780#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2778#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2777#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2316#L276 assume !(0 != eval_~tmp~0#1); 2318#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2456#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2775#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2774#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2772#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2773#L344-3 assume !(0 == ~E_1~0); 2893#L349-3 assume !(0 == ~E_2~0); 2892#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2891#L156-9 assume !(1 == ~m_pc~0); 2889#L156-11 is_master_triggered_~__retres1~0#1 := 0; 2888#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2887#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2886#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2885#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2884#L175-9 assume !(1 == ~t1_pc~0); 2883#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2882#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2881#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2880#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 2879#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2878#L194-9 assume 1 == ~t2_pc~0; 2876#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2875#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2874#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2873#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2872#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2871#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2870#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2869#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2384#L377-3 assume !(1 == ~E_1~0); 2353#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2868#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2514#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2386#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2639#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2640#L547 assume !(0 == start_simulation_~tmp~3#1); 2835#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2834#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2831#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2830#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2829#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2828#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2827#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2826#L560 assume !(0 != start_simulation_~tmp___0~1#1); 2823#L528-2 [2024-10-31 22:07:09,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:09,510 INFO L85 PathProgramCache]: Analyzing trace with hash -148513729, now seen corresponding path program 1 times [2024-10-31 22:07:09,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:09,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629907474] [2024-10-31 22:07:09,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:09,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:09,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:09,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:09,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:09,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [629907474] [2024-10-31 22:07:09,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [629907474] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:09,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:09,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:09,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918853666] [2024-10-31 22:07:09,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:09,607 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:07:09,610 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:09,611 INFO L85 PathProgramCache]: Analyzing trace with hash 1493903487, now seen corresponding path program 1 times [2024-10-31 22:07:09,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:09,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269824642] [2024-10-31 22:07:09,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:09,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:09,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:09,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:09,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:09,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1269824642] [2024-10-31 22:07:09,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1269824642] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:09,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:09,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:07:09,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305218250] [2024-10-31 22:07:09,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:09,714 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:09,714 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:09,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:07:09,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:07:09,715 INFO L87 Difference]: Start difference. First operand 578 states and 838 transitions. cyclomatic complexity: 264 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:09,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:09,820 INFO L93 Difference]: Finished difference Result 592 states and 834 transitions. [2024-10-31 22:07:09,821 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 592 states and 834 transitions. [2024-10-31 22:07:09,825 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 544 [2024-10-31 22:07:09,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 592 states to 592 states and 834 transitions. [2024-10-31 22:07:09,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 592 [2024-10-31 22:07:09,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 592 [2024-10-31 22:07:09,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 592 states and 834 transitions. [2024-10-31 22:07:09,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:09,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 592 states and 834 transitions. [2024-10-31 22:07:09,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states and 834 transitions. [2024-10-31 22:07:09,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 575. [2024-10-31 22:07:09,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 575 states, 575 states have (on average 1.413913043478261) internal successors, (813), 574 states have internal predecessors, (813), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:09,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 575 states to 575 states and 813 transitions. [2024-10-31 22:07:09,845 INFO L240 hiAutomatonCegarLoop]: Abstraction has 575 states and 813 transitions. [2024-10-31 22:07:09,845 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:07:09,846 INFO L425 stractBuchiCegarLoop]: Abstraction has 575 states and 813 transitions. [2024-10-31 22:07:09,846 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:07:09,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 575 states and 813 transitions. [2024-10-31 22:07:09,849 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2024-10-31 22:07:09,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:09,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:09,851 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:09,851 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:09,851 INFO L745 eck$LassoCheckResult]: Stem: 3706#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3719#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3715#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3716#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 3610#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3579#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3580#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3563#L334 assume !(0 == ~M_E~0); 3564#L334-2 assume !(0 == ~T1_E~0); 3673#L339-1 assume !(0 == ~T2_E~0); 3666#L344-1 assume !(0 == ~E_1~0); 3667#L349-1 assume !(0 == ~E_2~0); 3577#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3578#L156 assume !(1 == ~m_pc~0); 3511#L156-2 is_master_triggered_~__retres1~0#1 := 0; 3510#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3687#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3633#L405 assume !(0 != activate_threads_~tmp~1#1); 3617#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3618#L175 assume !(1 == ~t1_pc~0); 3622#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3619#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3574#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3575#L413 assume !(0 != activate_threads_~tmp___0~0#1); 3677#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3735#L194 assume !(1 == ~t2_pc~0); 3665#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3627#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3628#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3551#L421 assume !(0 != activate_threads_~tmp___1~0#1); 3552#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3522#L367 assume !(1 == ~M_E~0); 3523#L367-2 assume !(1 == ~T1_E~0); 3688#L372-1 assume !(1 == ~T2_E~0); 3689#L377-1 assume !(1 == ~E_1~0); 3548#L382-1 assume !(1 == ~E_2~0); 3549#L387-1 assume { :end_inline_reset_delta_events } true; 3635#L528-2 [2024-10-31 22:07:09,851 INFO L747 eck$LassoCheckResult]: Loop: 3635#L528-2 assume !false; 3819#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3813#L309-1 assume !false; 3792#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3793#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3684#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3519#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3498#L276 assume !(0 != eval_~tmp~0#1); 3500#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3804#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3802#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3799#L339-3 assume !(0 == ~T2_E~0); 3800#L344-3 assume !(0 == ~E_1~0); 3790#L349-3 assume !(0 == ~E_2~0); 3791#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3959#L156-9 assume !(1 == ~m_pc~0); 3957#L156-11 is_master_triggered_~__retres1~0#1 := 0; 3605#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3606#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3678#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3679#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3739#L175-9 assume !(1 == ~t1_pc~0); 3740#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 3955#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3949#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3946#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 3942#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3939#L194-9 assume 1 == ~t2_pc~0; 3934#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3930#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3926#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3922#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3917#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3912#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3908#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3904#L372-3 assume !(1 == ~T2_E~0); 3899#L377-3 assume !(1 == ~E_1~0); 3895#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3891#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3887#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3881#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3877#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 3872#L547 assume !(0 == start_simulation_~tmp~3#1); 3866#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3863#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3857#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3852#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 3841#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3837#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3835#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3833#L560 assume !(0 != start_simulation_~tmp___0~1#1); 3635#L528-2 [2024-10-31 22:07:09,852 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:09,852 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2024-10-31 22:07:09,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:09,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899846075] [2024-10-31 22:07:09,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:09,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:09,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:09,863 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:09,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:09,901 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:09,901 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:09,902 INFO L85 PathProgramCache]: Analyzing trace with hash -898972165, now seen corresponding path program 1 times [2024-10-31 22:07:09,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:09,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737341704] [2024-10-31 22:07:09,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:09,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:09,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:09,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:09,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:09,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737341704] [2024-10-31 22:07:09,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1737341704] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:09,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:09,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:07:10,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857434983] [2024-10-31 22:07:10,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:10,000 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:10,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:10,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:07:10,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:07:10,001 INFO L87 Difference]: Start difference. First operand 575 states and 813 transitions. cyclomatic complexity: 242 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:10,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:10,073 INFO L93 Difference]: Finished difference Result 603 states and 841 transitions. [2024-10-31 22:07:10,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 603 states and 841 transitions. [2024-10-31 22:07:10,077 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 559 [2024-10-31 22:07:10,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 603 states to 603 states and 841 transitions. [2024-10-31 22:07:10,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 603 [2024-10-31 22:07:10,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 603 [2024-10-31 22:07:10,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 603 states and 841 transitions. [2024-10-31 22:07:10,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:10,084 INFO L218 hiAutomatonCegarLoop]: Abstraction has 603 states and 841 transitions. [2024-10-31 22:07:10,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 603 states and 841 transitions. [2024-10-31 22:07:10,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 603 to 587. [2024-10-31 22:07:10,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 587 states, 587 states have (on average 1.405451448040886) internal successors, (825), 586 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:10,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 825 transitions. [2024-10-31 22:07:10,098 INFO L240 hiAutomatonCegarLoop]: Abstraction has 587 states and 825 transitions. [2024-10-31 22:07:10,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:07:10,099 INFO L425 stractBuchiCegarLoop]: Abstraction has 587 states and 825 transitions. [2024-10-31 22:07:10,100 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:07:10,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 587 states and 825 transitions. [2024-10-31 22:07:10,103 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 543 [2024-10-31 22:07:10,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:10,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:10,104 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:10,108 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:10,109 INFO L745 eck$LassoCheckResult]: Stem: 4885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4901#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4895#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4896#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 4790#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4764#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4765#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4747#L334 assume !(0 == ~M_E~0); 4748#L334-2 assume !(0 == ~T1_E~0); 4855#L339-1 assume !(0 == ~T2_E~0); 4848#L344-1 assume !(0 == ~E_1~0); 4849#L349-1 assume !(0 == ~E_2~0); 4762#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4763#L156 assume !(1 == ~m_pc~0); 4694#L156-2 is_master_triggered_~__retres1~0#1 := 0; 4693#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4867#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4815#L405 assume !(0 != activate_threads_~tmp~1#1); 4796#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4797#L175 assume !(1 == ~t1_pc~0); 4804#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4798#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4759#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4760#L413 assume !(0 != activate_threads_~tmp___0~0#1); 4857#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4913#L194 assume !(1 == ~t2_pc~0); 4847#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4808#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4809#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4735#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4736#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4705#L367 assume !(1 == ~M_E~0); 4706#L367-2 assume !(1 == ~T1_E~0); 4868#L372-1 assume !(1 == ~T2_E~0); 4869#L377-1 assume !(1 == ~E_1~0); 4732#L382-1 assume !(1 == ~E_2~0); 4733#L387-1 assume { :end_inline_reset_delta_events } true; 4818#L528-2 [2024-10-31 22:07:10,109 INFO L747 eck$LassoCheckResult]: Loop: 4818#L528-2 assume !false; 5014#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5008#L309-1 assume !false; 5006#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5004#L244 assume !(0 == ~m_st~0); 5002#L248 assume !(0 == ~t1_st~0); 5000#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 4997#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4995#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4993#L276 assume !(0 != eval_~tmp~0#1); 4991#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4989#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4987#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4985#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4982#L339-3 assume !(0 == ~T2_E~0); 4983#L344-3 assume !(0 == ~E_1~0); 5229#L349-3 assume !(0 == ~E_2~0); 4972#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4973#L156-9 assume !(1 == ~m_pc~0); 4965#L156-11 is_master_triggered_~__retres1~0#1 := 0; 4786#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4787#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4860#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4723#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4724#L175-9 assume !(1 == ~t1_pc~0); 4876#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4877#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5222#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5221#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 4881#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4882#L194-9 assume !(1 == ~t2_pc~0); 4737#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 4738#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4690#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4691#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4851#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4782#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4695#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4696#L372-3 assume !(1 == ~T2_E~0); 4749#L377-3 assume !(1 == ~E_1~0); 4741#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4742#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4879#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4751#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4911#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4891#L547 assume !(0 == start_simulation_~tmp~3#1); 4870#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4905#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5252#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5032#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 5027#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5026#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5024#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5022#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4818#L528-2 [2024-10-31 22:07:10,109 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:10,110 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2024-10-31 22:07:10,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:10,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760715070] [2024-10-31 22:07:10,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:10,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:10,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:10,126 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:10,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:10,144 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:10,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:10,145 INFO L85 PathProgramCache]: Analyzing trace with hash -975167437, now seen corresponding path program 1 times [2024-10-31 22:07:10,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:10,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [898358989] [2024-10-31 22:07:10,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:10,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:10,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:10,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:10,259 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:10,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [898358989] [2024-10-31 22:07:10,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [898358989] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:10,260 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:10,260 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:07:10,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889642171] [2024-10-31 22:07:10,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:10,261 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:10,261 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:10,261 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:07:10,261 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:07:10,262 INFO L87 Difference]: Start difference. First operand 587 states and 825 transitions. cyclomatic complexity: 242 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:10,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:10,383 INFO L93 Difference]: Finished difference Result 626 states and 864 transitions. [2024-10-31 22:07:10,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 864 transitions. [2024-10-31 22:07:10,387 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 579 [2024-10-31 22:07:10,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 864 transitions. [2024-10-31 22:07:10,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2024-10-31 22:07:10,391 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2024-10-31 22:07:10,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 864 transitions. [2024-10-31 22:07:10,393 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:10,393 INFO L218 hiAutomatonCegarLoop]: Abstraction has 626 states and 864 transitions. [2024-10-31 22:07:10,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 864 transitions. [2024-10-31 22:07:10,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2024-10-31 22:07:10,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.3801916932907348) internal successors, (864), 625 states have internal predecessors, (864), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:10,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 864 transitions. [2024-10-31 22:07:10,406 INFO L240 hiAutomatonCegarLoop]: Abstraction has 626 states and 864 transitions. [2024-10-31 22:07:10,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:07:10,408 INFO L425 stractBuchiCegarLoop]: Abstraction has 626 states and 864 transitions. [2024-10-31 22:07:10,409 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:07:10,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 864 transitions. [2024-10-31 22:07:10,412 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 579 [2024-10-31 22:07:10,412 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:10,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:10,413 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:10,413 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:10,414 INFO L745 eck$LassoCheckResult]: Stem: 6107#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6121#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6116#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6117#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 6013#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5984#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5985#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5968#L334 assume !(0 == ~M_E~0); 5969#L334-2 assume !(0 == ~T1_E~0); 6078#L339-1 assume !(0 == ~T2_E~0); 6072#L344-1 assume !(0 == ~E_1~0); 6073#L349-1 assume !(0 == ~E_2~0); 5982#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5983#L156 assume !(1 == ~m_pc~0); 5915#L156-2 is_master_triggered_~__retres1~0#1 := 0; 6100#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6093#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6039#L405 assume !(0 != activate_threads_~tmp~1#1); 6017#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6018#L175 assume !(1 == ~t1_pc~0); 6025#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6019#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5980#L413 assume !(0 != activate_threads_~tmp___0~0#1); 6080#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6135#L194 assume !(1 == ~t2_pc~0); 6071#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6029#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6030#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5957#L421 assume !(0 != activate_threads_~tmp___1~0#1); 5958#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5927#L367 assume !(1 == ~M_E~0); 5928#L367-2 assume !(1 == ~T1_E~0); 6094#L372-1 assume !(1 == ~T2_E~0); 6095#L377-1 assume !(1 == ~E_1~0); 5954#L382-1 assume !(1 == ~E_2~0); 5955#L387-1 assume { :end_inline_reset_delta_events } true; 6041#L528-2 [2024-10-31 22:07:10,414 INFO L747 eck$LassoCheckResult]: Loop: 6041#L528-2 assume !false; 6293#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6287#L309-1 assume !false; 6285#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6283#L244 assume !(0 == ~m_st~0); 6281#L248 assume !(0 == ~t1_st~0); 6278#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 6276#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6274#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6272#L276 assume !(0 != eval_~tmp~0#1); 6270#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6268#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6266#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6264#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6262#L339-3 assume !(0 == ~T2_E~0); 6260#L344-3 assume !(0 == ~E_1~0); 6258#L349-3 assume !(0 == ~E_2~0); 6256#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6254#L156-9 assume 1 == ~m_pc~0; 6251#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6247#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6243#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6239#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6236#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6234#L175-9 assume !(1 == ~t1_pc~0); 6232#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 6230#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6228#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6226#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 6224#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6222#L194-9 assume 1 == ~t2_pc~0; 6219#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6216#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6214#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6212#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6210#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6208#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6206#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6204#L372-3 assume !(1 == ~T2_E~0); 6199#L377-3 assume !(1 == ~E_1~0); 6200#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6194#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6195#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6342#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6339#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 6113#L547 assume !(0 == start_simulation_~tmp~3#1); 6114#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6365#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6361#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6359#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 6348#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6343#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6332#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6329#L560 assume !(0 != start_simulation_~tmp___0~1#1); 6041#L528-2 [2024-10-31 22:07:10,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:10,415 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2024-10-31 22:07:10,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:10,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893180398] [2024-10-31 22:07:10,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:10,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:10,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:10,424 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:10,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:10,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:10,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:10,439 INFO L85 PathProgramCache]: Analyzing trace with hash -1914923147, now seen corresponding path program 1 times [2024-10-31 22:07:10,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:10,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549435207] [2024-10-31 22:07:10,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:10,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:10,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:10,457 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:10,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:10,472 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:10,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:10,473 INFO L85 PathProgramCache]: Analyzing trace with hash 1578773301, now seen corresponding path program 1 times [2024-10-31 22:07:10,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:10,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796686589] [2024-10-31 22:07:10,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:10,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:10,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:10,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:10,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:10,526 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796686589] [2024-10-31 22:07:10,526 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796686589] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:10,526 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:10,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:10,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031302011] [2024-10-31 22:07:10,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:11,192 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:07:11,193 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:07:11,193 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:07:11,193 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:07:11,193 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-10-31 22:07:11,193 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:11,193 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:07:11,194 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:07:11,194 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration8_Loop [2024-10-31 22:07:11,194 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:07:11,194 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:07:11,213 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,248 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,254 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,257 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,271 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,274 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,290 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,297 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,300 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,306 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,309 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,315 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,321 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,331 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,335 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,342 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,344 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,348 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,351 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,354 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,360 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,365 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,368 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,372 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,378 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,384 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,389 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,392 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,395 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:11,749 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:07:11,749 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-10-31 22:07:11,752 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:11,752 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:11,754 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:11,756 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-10-31 22:07:11,758 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:11,758 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:11,780 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:11,780 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:11,797 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-10-31 22:07:11,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:11,797 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:11,799 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:11,800 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-10-31 22:07:11,801 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:11,801 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:11,814 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:11,814 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret13#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret13#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:11,833 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-10-31 22:07:11,834 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:11,834 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:11,837 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:11,846 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-10-31 22:07:11,848 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:11,848 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:11,866 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:11,866 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:11,882 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:11,882 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:11,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:11,884 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:11,885 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-10-31 22:07:11,886 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:11,886 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:11,904 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:11,904 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_master_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:11,917 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:11,917 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:11,918 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:11,919 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:11,920 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-10-31 22:07:11,921 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:11,921 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:11,938 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:11,939 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:11,955 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:11,955 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:11,955 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:11,956 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:11,957 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-10-31 22:07:11,958 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:11,958 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:11,975 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:11,975 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:11,989 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:11,990 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:11,990 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:11,991 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:11,992 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-10-31 22:07:11,993 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:11,993 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:12,008 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:12,009 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:12,021 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:12,022 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,022 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,023 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,024 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-10-31 22:07:12,025 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:12,025 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:12,040 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:12,041 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:12,052 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:12,053 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,053 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,054 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,056 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-10-31 22:07:12,057 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:12,057 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:12,083 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:12,084 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:12,102 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-10-31 22:07:12,103 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,103 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,105 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,106 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-10-31 22:07:12,108 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:12,108 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:12,127 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:12,127 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:12,145 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-10-31 22:07:12,145 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,146 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,148 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,150 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-10-31 22:07:12,150 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:12,151 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:12,167 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:12,167 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret8#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret8#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:12,185 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-10-31 22:07:12,186 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,186 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,188 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,189 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-10-31 22:07:12,191 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:12,191 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:12,216 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-10-31 22:07:12,216 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_1~0=-1} Honda state: {~E_1~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-10-31 22:07:12,234 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-10-31 22:07:12,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,235 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,237 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,240 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-10-31 22:07:12,241 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-10-31 22:07:12,241 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:12,281 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-10-31 22:07:12,281 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,281 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,282 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,283 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-10-31 22:07:12,285 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-10-31 22:07:12,285 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-10-31 22:07:12,331 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-10-31 22:07:12,334 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:12,334 INFO L204 LassoAnalysis]: Preferences: [2024-10-31 22:07:12,334 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-10-31 22:07:12,334 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-10-31 22:07:12,334 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-10-31 22:07:12,334 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-10-31 22:07:12,334 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,334 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-10-31 22:07:12,334 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-10-31 22:07:12,334 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration8_Loop [2024-10-31 22:07:12,335 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-10-31 22:07:12,335 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-10-31 22:07:12,337 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,346 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,349 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,352 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,354 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,357 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,360 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,362 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,365 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,368 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,372 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,379 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,386 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,402 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,404 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,407 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,419 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,422 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,434 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,436 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,439 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,441 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,448 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,455 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,457 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,460 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,462 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,471 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,473 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,482 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,484 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,487 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,490 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-10-31 22:07:12,806 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-10-31 22:07:12,811 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-10-31 22:07:12,812 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,812 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,814 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,815 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-10-31 22:07:12,818 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:12,833 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:12,833 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:12,834 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:12,834 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:12,834 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:12,836 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:12,837 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:12,840 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:12,858 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-10-31 22:07:12,858 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,859 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,861 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,864 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-10-31 22:07:12,865 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:12,879 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:12,879 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:12,879 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:12,879 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:12,879 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:12,880 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:12,880 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:12,882 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:12,900 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-10-31 22:07:12,900 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,900 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,902 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,903 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-10-31 22:07:12,904 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:12,919 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:12,920 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:12,920 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:12,920 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:12,920 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:12,921 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:12,921 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:12,923 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:12,941 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-10-31 22:07:12,942 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,942 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,944 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,946 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-10-31 22:07:12,947 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:12,961 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:12,961 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:12,961 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:12,962 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:12,962 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:12,962 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:12,963 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:12,965 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:12,984 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-10-31 22:07:12,984 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:12,984 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:12,987 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:12,988 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-10-31 22:07:12,990 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,004 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,004 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,005 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,005 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:13,005 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,006 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:13,006 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,008 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:13,025 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-10-31 22:07:13,026 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,026 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,028 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,029 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-10-31 22:07:13,031 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,045 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,045 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,046 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,046 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:13,046 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,046 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:13,047 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,048 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:13,066 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-10-31 22:07:13,067 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,067 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,069 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,071 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-10-31 22:07:13,072 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,089 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,089 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,089 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,089 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:13,089 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,090 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:13,090 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,096 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:13,117 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:13,121 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,122 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,124 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,125 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-10-31 22:07:13,126 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,144 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,144 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,144 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,145 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:13,145 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,146 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:13,146 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,151 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:13,173 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:13,174 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,174 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,176 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,179 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-10-31 22:07:13,180 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,198 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,198 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,198 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,199 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:13,199 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,200 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:13,200 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,203 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:13,224 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:13,225 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,225 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,227 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,229 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-10-31 22:07:13,231 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,249 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,249 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,249 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,249 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-31 22:07:13,250 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,251 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-31 22:07:13,251 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,256 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:13,278 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:13,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,279 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,281 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,284 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-10-31 22:07:13,285 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,305 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,305 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,305 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,305 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:13,305 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,306 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:13,306 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,311 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:13,332 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:13,333 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,333 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,337 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,340 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-10-31 22:07:13,342 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,358 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,358 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,359 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,359 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-31 22:07:13,359 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,360 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-31 22:07:13,360 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,365 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:13,385 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-10-31 22:07:13,386 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,386 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,388 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,390 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-10-31 22:07:13,391 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,408 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,408 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,408 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,409 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-10-31 22:07:13,409 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,411 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-10-31 22:07:13,411 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,416 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-10-31 22:07:13,437 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:13,438 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,438 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,440 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,471 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-10-31 22:07:13,472 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-10-31 22:07:13,490 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-10-31 22:07:13,490 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-10-31 22:07:13,490 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-10-31 22:07:13,490 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-10-31 22:07:13,490 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-10-31 22:07:13,492 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-10-31 22:07:13,492 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-10-31 22:07:13,496 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-10-31 22:07:13,507 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-10-31 22:07:13,508 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-10-31 22:07:13,510 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:07:13,510 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:07:13,531 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:07:13,534 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-10-31 22:07:13,534 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-10-31 22:07:13,534 INFO L474 LassoAnalysis]: Proved termination. [2024-10-31 22:07:13,535 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2024-10-31 22:07:13,535 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-10-31 22:07:13,553 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2024-10-31 22:07:13,556 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-10-31 22:07:13,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:13,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:13,642 INFO L255 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-10-31 22:07:13,645 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:07:13,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:13,778 INFO L255 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-10-31 22:07:13,781 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-10-31 22:07:14,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:14,042 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-10-31 22:07:14,043 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 626 states and 864 transitions. cyclomatic complexity: 242 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:14,215 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 626 states and 864 transitions. cyclomatic complexity: 242. Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 1566 states and 2181 transitions. Complement of second has 5 states. [2024-10-31 22:07:14,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-10-31 22:07:14,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:14,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 246 transitions. [2024-10-31 22:07:14,220 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 246 transitions. Stem has 38 letters. Loop has 54 letters. [2024-10-31 22:07:14,222 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:07:14,223 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 246 transitions. Stem has 92 letters. Loop has 54 letters. [2024-10-31 22:07:14,223 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:07:14,224 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 246 transitions. Stem has 38 letters. Loop has 108 letters. [2024-10-31 22:07:14,226 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-10-31 22:07:14,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2181 transitions. [2024-10-31 22:07:14,239 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1036 [2024-10-31 22:07:14,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2181 transitions. [2024-10-31 22:07:14,248 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1088 [2024-10-31 22:07:14,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1097 [2024-10-31 22:07:14,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2181 transitions. [2024-10-31 22:07:14,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:07:14,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2181 transitions. [2024-10-31 22:07:14,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2181 transitions. [2024-10-31 22:07:14,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1557. [2024-10-31 22:07:14,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1557 states, 1557 states have (on average 1.3924213230571612) internal successors, (2168), 1556 states have internal predecessors, (2168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:14,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1557 states to 1557 states and 2168 transitions. [2024-10-31 22:07:14,288 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1557 states and 2168 transitions. [2024-10-31 22:07:14,290 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:14,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:14,290 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:14,294 INFO L87 Difference]: Start difference. First operand 1557 states and 2168 transitions. Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:14,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:14,399 INFO L93 Difference]: Finished difference Result 2628 states and 3563 transitions. [2024-10-31 22:07:14,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2628 states and 3563 transitions. [2024-10-31 22:07:14,422 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1780 [2024-10-31 22:07:14,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2628 states to 2628 states and 3563 transitions. [2024-10-31 22:07:14,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1840 [2024-10-31 22:07:14,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1840 [2024-10-31 22:07:14,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2628 states and 3563 transitions. [2024-10-31 22:07:14,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:07:14,445 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2628 states and 3563 transitions. [2024-10-31 22:07:14,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2628 states and 3563 transitions. [2024-10-31 22:07:14,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2628 to 2523. [2024-10-31 22:07:14,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2523 states, 2523 states have (on average 1.3586999603646452) internal successors, (3428), 2522 states have internal predecessors, (3428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:14,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2523 states to 2523 states and 3428 transitions. [2024-10-31 22:07:14,508 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2523 states and 3428 transitions. [2024-10-31 22:07:14,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:14,510 INFO L425 stractBuchiCegarLoop]: Abstraction has 2523 states and 3428 transitions. [2024-10-31 22:07:14,511 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:07:14,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2523 states and 3428 transitions. [2024-10-31 22:07:14,525 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1710 [2024-10-31 22:07:14,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:14,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:14,527 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:14,527 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:14,527 INFO L745 eck$LassoCheckResult]: Stem: 12931#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12932#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12954#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12949#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12950#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 12763#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12712#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12713#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12686#L334 assume !(0 == ~M_E~0); 12687#L334-2 assume !(0 == ~T1_E~0); 12873#L339-1 assume !(0 == ~T2_E~0); 12863#L344-1 assume !(0 == ~E_1~0); 12864#L349-1 assume !(0 == ~E_2~0); 12710#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12711#L156 assume !(1 == ~m_pc~0); 12600#L156-2 is_master_triggered_~__retres1~0#1 := 0; 12948#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13009#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12803#L405 assume !(0 != activate_threads_~tmp~1#1); 12779#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12780#L175 assume !(1 == ~t1_pc~0); 12784#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12781#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12706#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12707#L413 assume !(0 != activate_threads_~tmp___0~0#1); 12880#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12985#L194 assume !(1 == ~t2_pc~0); 12861#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12791#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12792#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12668#L421 assume !(0 != activate_threads_~tmp___1~0#1); 12669#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12616#L367 assume !(1 == ~M_E~0); 12617#L367-2 assume !(1 == ~T1_E~0); 12907#L372-1 assume !(1 == ~T2_E~0); 12908#L377-1 assume !(1 == ~E_1~0); 12663#L382-1 assume !(1 == ~E_2~0); 12664#L387-1 assume { :end_inline_reset_delta_events } true; 12808#L528-2 assume !false; 13302#L529 [2024-10-31 22:07:14,528 INFO L747 eck$LassoCheckResult]: Loop: 13302#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14418#L309-1 assume !false; 14419#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14406#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14404#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14402#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14398#L276 assume 0 != eval_~tmp~0#1; 14393#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 14381#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 14388#L47 assume !(0 == ~m_pc~0); 14401#L50 assume 1 == ~m_pc~0; 14397#$Ultimate##124 assume !false; 14392#L67 ~m_pc~0 := 1;~m_st~0 := 2; 14386#master_returnLabel#1 assume { :end_inline_master } true; 14379#L284-2 havoc eval_~tmp_ndt_1~0#1; 14372#L281-1 assume !(0 == ~t1_st~0); 14373#L295-1 assume !(0 == ~t2_st~0); 14422#L309-1 assume !false; 14415#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14416#L244 assume !(0 == ~m_st~0); 14648#L248 assume !(0 == ~t1_st~0); 14646#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 14647#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14530#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14531#L276 assume !(0 != eval_~tmp~0#1); 12811#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12812#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14969#L334-3 assume !(0 == ~M_E~0); 12955#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12876#L339-3 assume !(0 == ~T2_E~0); 12877#L344-3 assume !(0 == ~E_1~0); 12801#L349-3 assume !(0 == ~E_2~0); 12682#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12683#L156-9 assume 1 == ~m_pc~0; 12848#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14966#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14964#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14965#L405-9 assume !(0 != activate_threads_~tmp~1#1); 12882#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14996#L175-9 assume !(1 == ~t1_pc~0); 14995#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 14994#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14993#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14992#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 14991#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14990#L194-9 assume 1 == ~t2_pc~0; 14988#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14986#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14984#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14982#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14980#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14978#L367-3 assume !(1 == ~M_E~0); 14976#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14975#L372-3 assume !(1 == ~T2_E~0); 14974#L377-3 assume !(1 == ~E_1~0); 14973#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14972#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14971#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14739#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14736#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 14733#L547 assume !(0 == start_simulation_~tmp~3#1); 14731#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14691#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14688#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14685#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 14682#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14678#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14673#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 14670#L560 assume !(0 != start_simulation_~tmp___0~1#1); 14666#L528-2 assume !false; 13302#L529 [2024-10-31 22:07:14,528 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:14,528 INFO L85 PathProgramCache]: Analyzing trace with hash -308898552, now seen corresponding path program 1 times [2024-10-31 22:07:14,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:14,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241984491] [2024-10-31 22:07:14,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:14,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:14,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:14,543 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:14,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:14,558 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:14,562 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:14,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1365140293, now seen corresponding path program 1 times [2024-10-31 22:07:14,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:14,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929868458] [2024-10-31 22:07:14,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:14,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:14,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:14,635 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-10-31 22:07:14,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:14,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929868458] [2024-10-31 22:07:14,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [929868458] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:14,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:14,636 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:14,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396655663] [2024-10-31 22:07:14,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:14,636 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:14,637 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:14,637 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:14,637 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:14,638 INFO L87 Difference]: Start difference. First operand 2523 states and 3428 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:14,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:14,729 INFO L93 Difference]: Finished difference Result 3814 states and 5080 transitions. [2024-10-31 22:07:14,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3814 states and 5080 transitions. [2024-10-31 22:07:14,763 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 2339 [2024-10-31 22:07:14,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3814 states to 3626 states and 4832 transitions. [2024-10-31 22:07:14,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2453 [2024-10-31 22:07:14,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2453 [2024-10-31 22:07:14,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3626 states and 4832 transitions. [2024-10-31 22:07:14,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-10-31 22:07:14,869 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3626 states and 4832 transitions. [2024-10-31 22:07:14,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3626 states and 4832 transitions. [2024-10-31 22:07:14,916 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2024-10-31 22:07:14,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3626 to 3506. [2024-10-31 22:07:14,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3506 states, 3506 states have (on average 1.3331431831146605) internal successors, (4674), 3505 states have internal predecessors, (4674), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:14,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3506 states to 3506 states and 4674 transitions. [2024-10-31 22:07:14,979 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3506 states and 4674 transitions. [2024-10-31 22:07:14,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:14,980 INFO L425 stractBuchiCegarLoop]: Abstraction has 3506 states and 4674 transitions. [2024-10-31 22:07:14,980 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:07:14,981 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3506 states and 4674 transitions. [2024-10-31 22:07:14,999 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 2222 [2024-10-31 22:07:14,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:14,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:15,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,001 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,001 INFO L745 eck$LassoCheckResult]: Stem: 19291#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 19292#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 19312#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19309#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19310#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 19108#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19058#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19059#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19028#L334 assume 0 == ~M_E~0;~M_E~0 := 1; 19029#L334-2 assume !(0 == ~T1_E~0); 19222#L339-1 assume !(0 == ~T2_E~0); 19223#L344-1 assume !(0 == ~E_1~0); 19379#L349-1 assume !(0 == ~E_2~0); 19056#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19057#L156 assume !(1 == ~m_pc~0); 19232#L156-2 is_master_triggered_~__retres1~0#1 := 0; 19308#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19375#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 19151#L405 assume !(0 != activate_threads_~tmp~1#1); 19123#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19124#L175 assume !(1 == ~t1_pc~0); 19129#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19125#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19126#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19366#L413 assume !(0 != activate_threads_~tmp___0~0#1); 19337#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19338#L194 assume !(1 == ~t2_pc~0); 19364#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19363#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19361#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19360#L421 assume !(0 != activate_threads_~tmp___1~0#1); 19359#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18959#L367 assume 1 == ~M_E~0;~M_E~0 := 2; 18960#L367-2 assume !(1 == ~T1_E~0); 19262#L372-1 assume !(1 == ~T2_E~0); 19263#L377-1 assume !(1 == ~E_1~0); 19005#L382-1 assume !(1 == ~E_2~0); 19006#L387-1 assume { :end_inline_reset_delta_events } true; 19156#L528-2 assume !false; 19171#L529 [2024-10-31 22:07:15,001 INFO L747 eck$LassoCheckResult]: Loop: 19171#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19172#L309-1 assume !false; 22306#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22304#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22231#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22301#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22300#L276 assume 0 != eval_~tmp~0#1; 19311#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 19109#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 19045#L47 assume !(0 == ~m_pc~0); 19047#L50 assume 1 == ~m_pc~0; 19342#$Ultimate##124 assume !false; 21902#L67 ~m_pc~0 := 1;~m_st~0 := 2; 21899#master_returnLabel#1 assume { :end_inline_master } true; 21896#L284-2 havoc eval_~tmp_ndt_1~0#1; 21892#L281-1 assume !(0 == ~t1_st~0); 21893#L295-1 assume !(0 == ~t2_st~0); 22238#L309-1 assume !false; 22235#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22230#L244 assume !(0 == ~m_st~0); 22225#L248 assume !(0 == ~t1_st~0); 22218#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 22213#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22208#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22202#L276 assume !(0 != eval_~tmp~0#1); 19159#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19220#L334-3 assume !(0 == ~M_E~0); 19313#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19227#L339-3 assume !(0 == ~T2_E~0); 19228#L344-3 assume !(0 == ~E_1~0); 22264#L349-3 assume !(0 == ~E_2~0); 22262#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22260#L156-9 assume !(1 == ~m_pc~0); 22249#L156-11 is_master_triggered_~__retres1~0#1 := 0; 22248#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22247#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 19233#L405-9 assume !(0 != activate_threads_~tmp~1#1); 19234#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22233#L175-9 assume !(1 == ~t1_pc~0); 22228#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 22223#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22216#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 22211#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 22206#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22200#L194-9 assume 1 == ~t2_pc~0; 22196#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22191#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22188#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22185#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22182#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22179#L367-3 assume !(1 == ~M_E~0); 22174#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22175#L372-3 assume !(1 == ~T2_E~0); 18975#L377-3 assume !(1 == ~E_1~0); 18976#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19020#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22032#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22033#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 19340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 19302#L547 assume !(0 == start_simulation_~tmp~3#1); 19303#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 19293#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 19090#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 19041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 19042#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19053#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19081#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 18983#L560 assume !(0 != start_simulation_~tmp___0~1#1); 18984#L528-2 assume !false; 19171#L529 [2024-10-31 22:07:15,002 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,002 INFO L85 PathProgramCache]: Analyzing trace with hash 1509461508, now seen corresponding path program 1 times [2024-10-31 22:07:15,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,003 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786454684] [2024-10-31 22:07:15,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:15,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:15,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:15,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1786454684] [2024-10-31 22:07:15,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1786454684] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:15,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:15,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:07:15,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429354733] [2024-10-31 22:07:15,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:15,056 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:07:15,056 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1804567034, now seen corresponding path program 1 times [2024-10-31 22:07:15,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775329700] [2024-10-31 22:07:15,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:15,104 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:15,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:15,105 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775329700] [2024-10-31 22:07:15,105 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1775329700] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:15,105 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:15,105 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:15,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154149843] [2024-10-31 22:07:15,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:15,106 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:15,106 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:15,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:15,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:15,107 INFO L87 Difference]: Start difference. First operand 3506 states and 4674 transitions. cyclomatic complexity: 1182 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:15,152 INFO L93 Difference]: Finished difference Result 2160 states and 2841 transitions. [2024-10-31 22:07:15,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2160 states and 2841 transitions. [2024-10-31 22:07:15,163 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1478 [2024-10-31 22:07:15,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2160 states to 1535 states and 2021 transitions. [2024-10-31 22:07:15,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1535 [2024-10-31 22:07:15,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1535 [2024-10-31 22:07:15,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1535 states and 2021 transitions. [2024-10-31 22:07:15,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:15,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1535 states and 2021 transitions. [2024-10-31 22:07:15,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1535 states and 2021 transitions. [2024-10-31 22:07:15,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1535 to 909. [2024-10-31 22:07:15,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.3124312431243124) internal successors, (1193), 908 states have internal predecessors, (1193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1193 transitions. [2024-10-31 22:07:15,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 909 states and 1193 transitions. [2024-10-31 22:07:15,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:15,201 INFO L425 stractBuchiCegarLoop]: Abstraction has 909 states and 1193 transitions. [2024-10-31 22:07:15,201 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:07:15,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1193 transitions. [2024-10-31 22:07:15,205 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 861 [2024-10-31 22:07:15,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:15,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:15,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,207 INFO L745 eck$LassoCheckResult]: Stem: 24799#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 24800#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24811#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24809#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24810#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 24698#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24672#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24673#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24656#L334 assume !(0 == ~M_E~0); 24657#L334-2 assume !(0 == ~T1_E~0); 24765#L339-1 assume !(0 == ~T2_E~0); 24758#L344-1 assume !(0 == ~E_1~0); 24759#L349-1 assume !(0 == ~E_2~0); 24670#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24671#L156 assume !(1 == ~m_pc~0); 24607#L156-2 is_master_triggered_~__retres1~0#1 := 0; 24789#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24780#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 24724#L405 assume !(0 != activate_threads_~tmp~1#1); 24705#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24706#L175 assume !(1 == ~t1_pc~0); 24710#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24707#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24667#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24668#L413 assume !(0 != activate_threads_~tmp___0~0#1); 24770#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24830#L194 assume !(1 == ~t2_pc~0); 24757#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24716#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24645#L421 assume !(0 != activate_threads_~tmp___1~0#1); 24646#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24617#L367 assume !(1 == ~M_E~0); 24618#L367-2 assume !(1 == ~T1_E~0); 24781#L372-1 assume !(1 == ~T2_E~0); 24782#L377-1 assume !(1 == ~E_1~0); 24642#L382-1 assume !(1 == ~E_2~0); 24643#L387-1 assume { :end_inline_reset_delta_events } true; 24727#L528-2 [2024-10-31 22:07:15,207 INFO L747 eck$LassoCheckResult]: Loop: 24727#L528-2 assume !false; 25183#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25181#L309-1 assume !false; 25180#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 25179#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 24922#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25178#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25177#L276 assume 0 != eval_~tmp~0#1; 24858#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 24859#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 24852#L47 assume !(0 == ~m_pc~0); 24853#L50 assume 1 == ~m_pc~0; 24854#$Ultimate##124 assume !false; 24973#L67 ~m_pc~0 := 1;~m_st~0 := 2; 24971#master_returnLabel#1 assume { :end_inline_master } true; 24964#L284-2 havoc eval_~tmp_ndt_1~0#1; 24961#L281-1 assume !(0 == ~t1_st~0); 24933#L295-1 assume !(0 == ~t2_st~0); 24926#L309-1 assume !false; 24924#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24921#L244 assume !(0 == ~m_st~0); 24918#L248 assume !(0 == ~t1_st~0); 24915#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 24912#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24910#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24907#L276 assume !(0 != eval_~tmp~0#1); 24904#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24902#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24900#L334-3 assume !(0 == ~M_E~0); 24898#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24895#L339-3 assume !(0 == ~T2_E~0); 24896#L344-3 assume !(0 == ~E_1~0); 25176#L349-3 assume !(0 == ~E_2~0); 25175#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25174#L156-9 assume !(1 == ~m_pc~0); 25172#L156-11 is_master_triggered_~__retres1~0#1 := 0; 25171#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24786#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 24771#L405-9 assume !(0 != activate_threads_~tmp~1#1); 24633#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24634#L175-9 assume !(1 == ~t1_pc~0); 24833#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 25468#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25168#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 25165#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 25133#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25130#L194-9 assume 1 == ~t2_pc~0; 25126#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25124#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25121#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25117#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25112#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25109#L367-3 assume !(1 == ~M_E~0); 25105#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25097#L372-3 assume !(1 == ~T2_E~0); 25091#L377-3 assume !(1 == ~E_1~0); 25088#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25085#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 25081#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 25082#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25166#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 25077#L547 assume !(0 == start_simulation_~tmp~3#1); 25079#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 25200#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 25028#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25199#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 25198#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25197#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25196#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 25195#L560 assume !(0 != start_simulation_~tmp___0~1#1); 24727#L528-2 [2024-10-31 22:07:15,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,208 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 4 times [2024-10-31 22:07:15,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247904606] [2024-10-31 22:07:15,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,216 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:15,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,226 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:15,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,227 INFO L85 PathProgramCache]: Analyzing trace with hash 1131871900, now seen corresponding path program 2 times [2024-10-31 22:07:15,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,227 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517888191] [2024-10-31 22:07:15,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:15,273 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:15,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:15,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [517888191] [2024-10-31 22:07:15,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [517888191] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:15,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:15,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:15,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423245028] [2024-10-31 22:07:15,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:15,275 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:15,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:15,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:15,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:15,276 INFO L87 Difference]: Start difference. First operand 909 states and 1193 transitions. cyclomatic complexity: 288 Second operand has 3 states, 3 states have (on average 23.333333333333332) internal successors, (70), 3 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:15,319 INFO L93 Difference]: Finished difference Result 1019 states and 1320 transitions. [2024-10-31 22:07:15,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1019 states and 1320 transitions. [2024-10-31 22:07:15,325 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 849 [2024-10-31 22:07:15,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1019 states to 1019 states and 1320 transitions. [2024-10-31 22:07:15,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1019 [2024-10-31 22:07:15,331 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1019 [2024-10-31 22:07:15,331 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1019 states and 1320 transitions. [2024-10-31 22:07:15,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:15,333 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1019 states and 1320 transitions. [2024-10-31 22:07:15,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1019 states and 1320 transitions. [2024-10-31 22:07:15,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1019 to 976. [2024-10-31 22:07:15,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 976 states, 976 states have (on average 1.298155737704918) internal successors, (1267), 975 states have internal predecessors, (1267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 976 states to 976 states and 1267 transitions. [2024-10-31 22:07:15,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 976 states and 1267 transitions. [2024-10-31 22:07:15,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:15,358 INFO L425 stractBuchiCegarLoop]: Abstraction has 976 states and 1267 transitions. [2024-10-31 22:07:15,358 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:07:15,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 976 states and 1267 transitions. [2024-10-31 22:07:15,364 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 849 [2024-10-31 22:07:15,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:15,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:15,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,365 INFO L745 eck$LassoCheckResult]: Stem: 26736#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 26737#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 26749#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26747#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26748#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 26630#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26604#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26605#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26588#L334 assume !(0 == ~M_E~0); 26589#L334-2 assume !(0 == ~T1_E~0); 26700#L339-1 assume !(0 == ~T2_E~0); 26694#L344-1 assume !(0 == ~E_1~0); 26695#L349-1 assume !(0 == ~E_2~0); 26602#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26603#L156 assume 1 == ~m_pc~0; 26538#L157 assume !(1 == ~M_E~0); 26539#L156-2 is_master_triggered_~__retres1~0#1 := 0; 26746#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26872#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 26657#L405 assume !(0 != activate_threads_~tmp~1#1); 26635#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26636#L175 assume !(1 == ~t1_pc~0); 26713#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26863#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26599#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26600#L413 assume !(0 != activate_threads_~tmp___0~0#1); 26702#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26763#L194 assume !(1 == ~t2_pc~0); 26691#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26692#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26851#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26849#L421 assume !(0 != activate_threads_~tmp___1~0#1); 26668#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26669#L367 assume !(1 == ~M_E~0); 26762#L367-2 assume !(1 == ~T1_E~0); 26718#L372-1 assume !(1 == ~T2_E~0); 26719#L377-1 assume !(1 == ~E_1~0); 26721#L382-1 assume !(1 == ~E_2~0); 26660#L387-1 assume { :end_inline_reset_delta_events } true; 26661#L528-2 [2024-10-31 22:07:15,366 INFO L747 eck$LassoCheckResult]: Loop: 26661#L528-2 assume !false; 27043#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27037#L309-1 assume !false; 27032#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27028#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 26918#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 27016#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27011#L276 assume 0 != eval_~tmp~0#1; 27006#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 26969#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 26994#L47 assume !(0 == ~m_pc~0); 26989#L50 assume 1 == ~m_pc~0; 26776#$Ultimate##124 assume !false; 26981#L67 ~m_pc~0 := 1;~m_st~0 := 2; 26976#master_returnLabel#1 assume { :end_inline_master } true; 26968#L284-2 havoc eval_~tmp_ndt_1~0#1; 26941#L281-1 assume !(0 == ~t1_st~0); 26929#L295-1 assume !(0 == ~t2_st~0); 26922#L309-1 assume !false; 26920#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26917#L244 assume !(0 == ~m_st~0); 26914#L248 assume !(0 == ~t1_st~0); 26911#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 26908#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26906#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26903#L276 assume !(0 != eval_~tmp~0#1); 26900#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26898#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26896#L334-3 assume !(0 == ~M_E~0); 26894#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26892#L339-3 assume !(0 == ~T2_E~0); 26888#L344-3 assume !(0 == ~E_1~0); 26889#L349-3 assume !(0 == ~E_2~0); 26884#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26885#L156-9 assume 1 == ~m_pc~0; 26880#L157-3 assume !(1 == ~M_E~0); 26881#L156-11 is_master_triggered_~__retres1~0#1 := 0; 26877#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26724#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 26706#L405-9 assume !(0 != activate_threads_~tmp~1#1); 26565#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26566#L175-9 assume !(1 == ~t1_pc~0); 27107#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 27103#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27098#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 27093#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 27088#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27084#L194-9 assume !(1 == ~t2_pc~0); 27072#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 27069#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27061#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27049#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27041#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27036#L367-3 assume !(1 == ~M_E~0); 27031#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27027#L372-3 assume !(1 == ~T2_E~0); 27021#L377-3 assume !(1 == ~E_1~0); 27015#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27010#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27004#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 27005#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 27116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 27110#L547 assume !(0 == start_simulation_~tmp~3#1); 27105#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27100#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 26956#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 27090#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 27086#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27080#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27063#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 27052#L560 assume !(0 != start_simulation_~tmp___0~1#1); 26661#L528-2 [2024-10-31 22:07:15,366 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,367 INFO L85 PathProgramCache]: Analyzing trace with hash -1839445214, now seen corresponding path program 1 times [2024-10-31 22:07:15,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762279682] [2024-10-31 22:07:15,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:15,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:15,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:15,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762279682] [2024-10-31 22:07:15,402 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762279682] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:15,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:15,403 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:07:15,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974817004] [2024-10-31 22:07:15,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:15,403 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:07:15,403 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,404 INFO L85 PathProgramCache]: Analyzing trace with hash -1918612552, now seen corresponding path program 1 times [2024-10-31 22:07:15,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379038117] [2024-10-31 22:07:15,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:15,449 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-10-31 22:07:15,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:15,450 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [379038117] [2024-10-31 22:07:15,450 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [379038117] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:15,450 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:15,450 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:15,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029371066] [2024-10-31 22:07:15,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:15,451 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:07:15,452 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:15,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:15,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:15,453 INFO L87 Difference]: Start difference. First operand 976 states and 1267 transitions. cyclomatic complexity: 297 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:15,489 INFO L93 Difference]: Finished difference Result 558 states and 722 transitions. [2024-10-31 22:07:15,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 558 states and 722 transitions. [2024-10-31 22:07:15,492 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 458 [2024-10-31 22:07:15,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 558 states to 558 states and 722 transitions. [2024-10-31 22:07:15,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 558 [2024-10-31 22:07:15,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 558 [2024-10-31 22:07:15,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 558 states and 722 transitions. [2024-10-31 22:07:15,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:15,498 INFO L218 hiAutomatonCegarLoop]: Abstraction has 558 states and 722 transitions. [2024-10-31 22:07:15,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 558 states and 722 transitions. [2024-10-31 22:07:15,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 558 to 554. [2024-10-31 22:07:15,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 554 states, 554 states have (on average 1.296028880866426) internal successors, (718), 553 states have internal predecessors, (718), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 554 states to 554 states and 718 transitions. [2024-10-31 22:07:15,510 INFO L240 hiAutomatonCegarLoop]: Abstraction has 554 states and 718 transitions. [2024-10-31 22:07:15,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:15,511 INFO L425 stractBuchiCegarLoop]: Abstraction has 554 states and 718 transitions. [2024-10-31 22:07:15,512 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:07:15,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 554 states and 718 transitions. [2024-10-31 22:07:15,514 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 458 [2024-10-31 22:07:15,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:15,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:15,515 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,515 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,515 INFO L745 eck$LassoCheckResult]: Stem: 28263#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 28264#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28277#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28273#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28274#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 28164#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28139#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28140#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28124#L334 assume !(0 == ~M_E~0); 28125#L334-2 assume !(0 == ~T1_E~0); 28232#L339-1 assume !(0 == ~T2_E~0); 28225#L344-1 assume !(0 == ~E_1~0); 28226#L349-1 assume !(0 == ~E_2~0); 28137#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28138#L156 assume !(1 == ~m_pc~0); 28237#L156-2 is_master_triggered_~__retres1~0#1 := 0; 28254#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28247#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 28189#L405 assume !(0 != activate_threads_~tmp~1#1); 28171#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28172#L175 assume !(1 == ~t1_pc~0); 28176#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28173#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28134#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28135#L413 assume !(0 != activate_threads_~tmp___0~0#1); 28236#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28292#L194 assume !(1 == ~t2_pc~0); 28223#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28181#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28182#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28113#L421 assume !(0 != activate_threads_~tmp___1~0#1); 28114#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28088#L367 assume !(1 == ~M_E~0); 28089#L367-2 assume !(1 == ~T1_E~0); 28248#L372-1 assume !(1 == ~T2_E~0); 28249#L377-1 assume !(1 == ~E_1~0); 28110#L382-1 assume !(1 == ~E_2~0); 28111#L387-1 assume { :end_inline_reset_delta_events } true; 28192#L528-2 assume !false; 28410#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28407#L309-1 [2024-10-31 22:07:15,516 INFO L747 eck$LassoCheckResult]: Loop: 28407#L309-1 assume !false; 28405#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 28403#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 28401#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 28399#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28397#L276 assume 0 != eval_~tmp~0#1; 28395#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 28392#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 28393#L284-2 havoc eval_~tmp_ndt_1~0#1; 28416#L281-1 assume !(0 == ~t1_st~0); 28411#L295-1 assume !(0 == ~t2_st~0); 28407#L309-1 [2024-10-31 22:07:15,516 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,516 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 1 times [2024-10-31 22:07:15,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501843454] [2024-10-31 22:07:15,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,526 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:15,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,537 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:15,538 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,538 INFO L85 PathProgramCache]: Analyzing trace with hash 993947407, now seen corresponding path program 1 times [2024-10-31 22:07:15,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888924649] [2024-10-31 22:07:15,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,546 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:15,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:15,550 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,551 INFO L85 PathProgramCache]: Analyzing trace with hash 1252886829, now seen corresponding path program 1 times [2024-10-31 22:07:15,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60253563] [2024-10-31 22:07:15,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:15,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:15,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:15,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60253563] [2024-10-31 22:07:15,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60253563] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:15,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:15,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:15,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685146225] [2024-10-31 22:07:15,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:15,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:15,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:15,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:15,745 INFO L87 Difference]: Start difference. First operand 554 states and 718 transitions. cyclomatic complexity: 168 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:15,803 INFO L93 Difference]: Finished difference Result 984 states and 1261 transitions. [2024-10-31 22:07:15,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 984 states and 1261 transitions. [2024-10-31 22:07:15,809 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 709 [2024-10-31 22:07:15,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 984 states to 984 states and 1261 transitions. [2024-10-31 22:07:15,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 984 [2024-10-31 22:07:15,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 984 [2024-10-31 22:07:15,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 984 states and 1261 transitions. [2024-10-31 22:07:15,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:15,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 984 states and 1261 transitions. [2024-10-31 22:07:15,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 984 states and 1261 transitions. [2024-10-31 22:07:15,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 984 to 951. [2024-10-31 22:07:15,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 951 states, 951 states have (on average 1.2818086225026288) internal successors, (1219), 950 states have internal predecessors, (1219), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 951 states to 951 states and 1219 transitions. [2024-10-31 22:07:15,840 INFO L240 hiAutomatonCegarLoop]: Abstraction has 951 states and 1219 transitions. [2024-10-31 22:07:15,840 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:15,841 INFO L425 stractBuchiCegarLoop]: Abstraction has 951 states and 1219 transitions. [2024-10-31 22:07:15,841 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:07:15,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 951 states and 1219 transitions. [2024-10-31 22:07:15,846 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 676 [2024-10-31 22:07:15,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:15,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:15,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,847 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,847 INFO L745 eck$LassoCheckResult]: Stem: 29807#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 29808#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 29821#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29817#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29818#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 29710#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 29685#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29686#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29670#L334 assume !(0 == ~M_E~0); 29671#L334-2 assume !(0 == ~T1_E~0); 29777#L339-1 assume !(0 == ~T2_E~0); 29771#L344-1 assume !(0 == ~E_1~0); 29772#L349-1 assume !(0 == ~E_2~0); 29683#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29684#L156 assume !(1 == ~m_pc~0); 29783#L156-2 is_master_triggered_~__retres1~0#1 := 0; 29799#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29792#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 29737#L405 assume !(0 != activate_threads_~tmp~1#1); 29720#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29721#L175 assume !(1 == ~t1_pc~0); 29724#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29716#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29680#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 29681#L413 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29779#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30172#L194 assume !(1 == ~t2_pc~0); 30170#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29728#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29729#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29659#L421 assume !(0 != activate_threads_~tmp___1~0#1); 29660#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29632#L367 assume !(1 == ~M_E~0); 29633#L367-2 assume !(1 == ~T1_E~0); 30158#L372-1 assume !(1 == ~T2_E~0); 30156#L377-1 assume !(1 == ~E_1~0); 30154#L382-1 assume !(1 == ~E_2~0); 30152#L387-1 assume { :end_inline_reset_delta_events } true; 30149#L528-2 assume !false; 30142#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30139#L309-1 [2024-10-31 22:07:15,847 INFO L747 eck$LassoCheckResult]: Loop: 30139#L309-1 assume !false; 30137#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 29988#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 29985#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 29986#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30082#L276 assume 0 != eval_~tmp~0#1; 30081#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 29975#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 29976#L284-2 havoc eval_~tmp_ndt_1~0#1; 30072#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 30003#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 30000#L298-2 havoc eval_~tmp_ndt_2~0#1; 30001#L295-1 assume !(0 == ~t2_st~0); 30139#L309-1 [2024-10-31 22:07:15,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,848 INFO L85 PathProgramCache]: Analyzing trace with hash -808857497, now seen corresponding path program 1 times [2024-10-31 22:07:15,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305953712] [2024-10-31 22:07:15,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:15,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:15,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:15,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305953712] [2024-10-31 22:07:15,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305953712] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:15,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:15,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:07:15,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916078751] [2024-10-31 22:07:15,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:15,872 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:07:15,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,872 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 1 times [2024-10-31 22:07:15,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978387801] [2024-10-31 22:07:15,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,877 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:15,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,880 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:15,935 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:15,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:15,935 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:15,936 INFO L87 Difference]: Start difference. First operand 951 states and 1219 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:15,945 INFO L93 Difference]: Finished difference Result 617 states and 788 transitions. [2024-10-31 22:07:15,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 617 states and 788 transitions. [2024-10-31 22:07:15,949 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 496 [2024-10-31 22:07:15,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 617 states to 617 states and 788 transitions. [2024-10-31 22:07:15,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 617 [2024-10-31 22:07:15,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 617 [2024-10-31 22:07:15,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 617 states and 788 transitions. [2024-10-31 22:07:15,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:15,955 INFO L218 hiAutomatonCegarLoop]: Abstraction has 617 states and 788 transitions. [2024-10-31 22:07:15,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 617 states and 788 transitions. [2024-10-31 22:07:15,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 617 to 617. [2024-10-31 22:07:15,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 617 states, 617 states have (on average 1.2771474878444085) internal successors, (788), 616 states have internal predecessors, (788), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:15,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 617 states to 617 states and 788 transitions. [2024-10-31 22:07:15,968 INFO L240 hiAutomatonCegarLoop]: Abstraction has 617 states and 788 transitions. [2024-10-31 22:07:15,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:15,969 INFO L425 stractBuchiCegarLoop]: Abstraction has 617 states and 788 transitions. [2024-10-31 22:07:15,969 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:07:15,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 617 states and 788 transitions. [2024-10-31 22:07:15,971 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 496 [2024-10-31 22:07:15,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:15,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:15,972 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,972 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:15,973 INFO L745 eck$LassoCheckResult]: Stem: 31386#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 31387#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 31396#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31394#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31395#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 31287#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31261#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31262#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31246#L334 assume !(0 == ~M_E~0); 31247#L334-2 assume !(0 == ~T1_E~0); 31353#L339-1 assume !(0 == ~T2_E~0); 31346#L344-1 assume !(0 == ~E_1~0); 31347#L349-1 assume !(0 == ~E_2~0); 31259#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31260#L156 assume !(1 == ~m_pc~0); 31358#L156-2 is_master_triggered_~__retres1~0#1 := 0; 31376#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31367#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 31313#L405 assume !(0 != activate_threads_~tmp~1#1); 31294#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31295#L175 assume !(1 == ~t1_pc~0); 31299#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31296#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31256#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 31257#L413 assume !(0 != activate_threads_~tmp___0~0#1); 31357#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31413#L194 assume !(1 == ~t2_pc~0); 31345#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31305#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31306#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31235#L421 assume !(0 != activate_threads_~tmp___1~0#1); 31236#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31209#L367 assume !(1 == ~M_E~0); 31210#L367-2 assume !(1 == ~T1_E~0); 31368#L372-1 assume !(1 == ~T2_E~0); 31369#L377-1 assume !(1 == ~E_1~0); 31232#L382-1 assume !(1 == ~E_2~0); 31233#L387-1 assume { :end_inline_reset_delta_events } true; 31316#L528-2 assume !false; 31325#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31326#L309-1 [2024-10-31 22:07:15,973 INFO L747 eck$LassoCheckResult]: Loop: 31326#L309-1 assume !false; 31692#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31691#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31690#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31689#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31686#L276 assume 0 != eval_~tmp~0#1; 31683#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 31678#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 31679#L284-2 havoc eval_~tmp_ndt_1~0#1; 31701#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31700#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 31697#L298-2 havoc eval_~tmp_ndt_2~0#1; 31695#L295-1 assume !(0 == ~t2_st~0); 31326#L309-1 [2024-10-31 22:07:15,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,974 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 2 times [2024-10-31 22:07:15,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056023492] [2024-10-31 22:07:15,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,982 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:15,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,991 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:15,991 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:15,992 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 2 times [2024-10-31 22:07:15,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:15,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677050338] [2024-10-31 22:07:15,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:15,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:15,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,996 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:15,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:15,999 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:16,000 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:16,000 INFO L85 PathProgramCache]: Analyzing trace with hash 1430117784, now seen corresponding path program 1 times [2024-10-31 22:07:16,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:16,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872909207] [2024-10-31 22:07:16,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:16,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:16,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:07:16,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:07:16,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:07:16,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872909207] [2024-10-31 22:07:16,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1872909207] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:07:16,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:07:16,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:07:16,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575313216] [2024-10-31 22:07:16,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:07:16,093 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:07:16,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:07:16,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:07:16,094 INFO L87 Difference]: Start difference. First operand 617 states and 788 transitions. cyclomatic complexity: 175 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:16,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:07:16,174 INFO L93 Difference]: Finished difference Result 1098 states and 1390 transitions. [2024-10-31 22:07:16,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1098 states and 1390 transitions. [2024-10-31 22:07:16,179 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-10-31 22:07:16,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1098 states to 1098 states and 1390 transitions. [2024-10-31 22:07:16,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1098 [2024-10-31 22:07:16,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1098 [2024-10-31 22:07:16,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1098 states and 1390 transitions. [2024-10-31 22:07:16,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:07:16,201 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1098 states and 1390 transitions. [2024-10-31 22:07:16,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1098 states and 1390 transitions. [2024-10-31 22:07:16,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1098 to 1098. [2024-10-31 22:07:16,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1098 states, 1098 states have (on average 1.2659380692167577) internal successors, (1390), 1097 states have internal predecessors, (1390), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:07:16,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1098 states to 1098 states and 1390 transitions. [2024-10-31 22:07:16,233 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1098 states and 1390 transitions. [2024-10-31 22:07:16,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:07:16,234 INFO L425 stractBuchiCegarLoop]: Abstraction has 1098 states and 1390 transitions. [2024-10-31 22:07:16,234 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 22:07:16,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1098 states and 1390 transitions. [2024-10-31 22:07:16,241 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-10-31 22:07:16,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:07:16,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:07:16,244 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:16,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:07:16,245 INFO L745 eck$LassoCheckResult]: Stem: 33107#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 33108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 33121#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33118#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33119#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 33010#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32983#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32984#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32968#L334 assume !(0 == ~M_E~0); 32969#L334-2 assume !(0 == ~T1_E~0); 33077#L339-1 assume !(0 == ~T2_E~0); 33070#L344-1 assume !(0 == ~E_1~0); 33071#L349-1 assume !(0 == ~E_2~0); 32981#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32982#L156 assume !(1 == ~m_pc~0); 33083#L156-2 is_master_triggered_~__retres1~0#1 := 0; 33098#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33092#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 33036#L405 assume !(0 != activate_threads_~tmp~1#1); 33015#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33016#L175 assume !(1 == ~t1_pc~0); 33024#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33017#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32978#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 32979#L413 assume !(0 != activate_threads_~tmp___0~0#1); 33080#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33137#L194 assume !(1 == ~t2_pc~0); 33069#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33028#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33029#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32957#L421 assume !(0 != activate_threads_~tmp___1~0#1); 32958#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32930#L367 assume !(1 == ~M_E~0); 32931#L367-2 assume !(1 == ~T1_E~0); 33093#L372-1 assume !(1 == ~T2_E~0); 33094#L377-1 assume !(1 == ~E_1~0); 32954#L382-1 assume !(1 == ~E_2~0); 32955#L387-1 assume { :end_inline_reset_delta_events } true; 33039#L528-2 assume !false; 33819#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33815#L309-1 [2024-10-31 22:07:16,245 INFO L747 eck$LassoCheckResult]: Loop: 33815#L309-1 assume !false; 33814#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 32924#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 32925#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 32929#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32914#L276 assume 0 != eval_~tmp~0#1; 32915#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 33745#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 33101#L284-2 havoc eval_~tmp_ndt_1~0#1; 33053#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 33054#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 33110#L298-2 havoc eval_~tmp_ndt_2~0#1; 33801#L295-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 33779#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 33799#L312-2 havoc eval_~tmp_ndt_3~0#1; 33815#L309-1 [2024-10-31 22:07:16,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:16,245 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 3 times [2024-10-31 22:07:16,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:16,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302014023] [2024-10-31 22:07:16,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:16,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:16,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:16,262 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:16,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:16,274 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:16,278 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:16,278 INFO L85 PathProgramCache]: Analyzing trace with hash -851208175, now seen corresponding path program 1 times [2024-10-31 22:07:16,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:16,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577026659] [2024-10-31 22:07:16,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:16,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:16,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:16,286 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:16,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:16,293 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:16,293 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:07:16,293 INFO L85 PathProgramCache]: Analyzing trace with hash -46370001, now seen corresponding path program 1 times [2024-10-31 22:07:16,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:07:16,294 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288338705] [2024-10-31 22:07:16,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:07:16,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:07:16,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:16,306 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:16,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:16,315 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:07:17,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:17,021 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:07:17,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:07:17,129 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 31.10 10:07:17 BoogieIcfgContainer [2024-10-31 22:07:17,129 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-10-31 22:07:17,129 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-10-31 22:07:17,130 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-10-31 22:07:17,130 INFO L274 PluginConnector]: Witness Printer initialized [2024-10-31 22:07:17,130 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:07:07" (3/4) ... [2024-10-31 22:07:17,137 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-10-31 22:07:17,230 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/witness.graphml [2024-10-31 22:07:17,231 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-10-31 22:07:17,231 INFO L158 Benchmark]: Toolchain (without parser) took 10749.50ms. Allocated memory was 138.4MB in the beginning and 224.4MB in the end (delta: 86.0MB). Free memory was 100.1MB in the beginning and 140.9MB in the end (delta: -40.8MB). Peak memory consumption was 46.2MB. Max. memory is 16.1GB. [2024-10-31 22:07:17,232 INFO L158 Benchmark]: CDTParser took 0.34ms. Allocated memory is still 138.4MB. Free memory is still 108.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-10-31 22:07:17,232 INFO L158 Benchmark]: CACSL2BoogieTranslator took 337.43ms. Allocated memory is still 138.4MB. Free memory was 99.6MB in the beginning and 84.5MB in the end (delta: 15.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-10-31 22:07:17,232 INFO L158 Benchmark]: Boogie Procedure Inliner took 53.63ms. Allocated memory is still 138.4MB. Free memory was 84.5MB in the beginning and 81.7MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-10-31 22:07:17,233 INFO L158 Benchmark]: Boogie Preprocessor took 73.13ms. Allocated memory is still 138.4MB. Free memory was 81.7MB in the beginning and 78.2MB in the end (delta: 3.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-10-31 22:07:17,233 INFO L158 Benchmark]: RCFGBuilder took 936.68ms. Allocated memory was 138.4MB in the beginning and 186.6MB in the end (delta: 48.2MB). Free memory was 78.2MB in the beginning and 154.8MB in the end (delta: -76.6MB). Peak memory consumption was 40.6MB. Max. memory is 16.1GB. [2024-10-31 22:07:17,234 INFO L158 Benchmark]: BuchiAutomizer took 9242.27ms. Allocated memory was 186.6MB in the beginning and 224.4MB in the end (delta: 37.7MB). Free memory was 154.8MB in the beginning and 146.1MB in the end (delta: 8.7MB). Peak memory consumption was 47.5MB. Max. memory is 16.1GB. [2024-10-31 22:07:17,234 INFO L158 Benchmark]: Witness Printer took 101.34ms. Allocated memory is still 224.4MB. Free memory was 146.1MB in the beginning and 140.9MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-10-31 22:07:17,236 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.34ms. Allocated memory is still 138.4MB. Free memory is still 108.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 337.43ms. Allocated memory is still 138.4MB. Free memory was 99.6MB in the beginning and 84.5MB in the end (delta: 15.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 53.63ms. Allocated memory is still 138.4MB. Free memory was 84.5MB in the beginning and 81.7MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 73.13ms. Allocated memory is still 138.4MB. Free memory was 81.7MB in the beginning and 78.2MB in the end (delta: 3.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 936.68ms. Allocated memory was 138.4MB in the beginning and 186.6MB in the end (delta: 48.2MB). Free memory was 78.2MB in the beginning and 154.8MB in the end (delta: -76.6MB). Peak memory consumption was 40.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 9242.27ms. Allocated memory was 186.6MB in the beginning and 224.4MB in the end (delta: 37.7MB). Free memory was 154.8MB in the beginning and 146.1MB in the end (delta: 8.7MB). Peak memory consumption was 47.5MB. Max. memory is 16.1GB. * Witness Printer took 101.34ms. Allocated memory is still 224.4MB. Free memory was 146.1MB in the beginning and 140.9MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (15 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * M_E) + 1) and consists of 3 locations. 15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1098 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 9.1s and 16 iterations. TraceHistogramMax:2. Analysis of lassos took 6.1s. Construction of modules took 0.6s. Büchi inclusion checks took 2.0s. Highest rank in rank-based complementation 3. Minimization of det autom 13. Minimization of nondet autom 3. Automata minimization 0.5s AutomataMinimizationTime, 16 MinimizatonAttempts, 979 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3764 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3763 mSDsluCounter, 8683 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3838 mSDsCounter, 137 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 377 IncrementalHoareTripleChecker+Invalid, 514 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 137 mSolverCounterUnsat, 4845 mSDtfsCounter, 377 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT1 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital64 mio100 ax100 hnf100 lsp15 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 31ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 12 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.3s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-10-31 22:07:17,269 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_993ff74e-4066-4e50-bec9-88356d28472e/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)