./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.08.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.08.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 22:18:24,293 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 22:18:24,389 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 22:18:24,395 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 22:18:24,397 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 22:18:24,431 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 22:18:24,432 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 22:18:24,433 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 22:18:24,433 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 22:18:24,434 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 22:18:24,439 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 22:18:24,439 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 22:18:24,440 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 22:18:24,440 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 22:18:24,441 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 22:18:24,441 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 22:18:24,441 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 22:18:24,442 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 22:18:24,445 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 22:18:24,445 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 22:18:24,446 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 22:18:24,446 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 22:18:24,447 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 22:18:24,447 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 22:18:24,447 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 22:18:24,447 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 22:18:24,448 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 22:18:24,452 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 22:18:24,452 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 22:18:24,453 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 22:18:24,453 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 22:18:24,453 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 22:18:24,453 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 22:18:24,454 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 22:18:24,454 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 22:18:24,454 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 22:18:24,455 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 22:18:24,455 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 22:18:24,455 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 22:18:24,456 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 [2024-10-31 22:18:24,756 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 22:18:24,785 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 22:18:24,788 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 22:18:24,791 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 22:18:24,791 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 22:18:24,793 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/transmitter.08.cil.c Unable to find full path for "g++" [2024-10-31 22:18:26,810 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 22:18:27,086 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 22:18:27,087 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/sv-benchmarks/c/systemc/transmitter.08.cil.c [2024-10-31 22:18:27,117 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/data/372be3224/d07311f358d2446c95c6abdf45b8c629/FLAG4ccfd521a [2024-10-31 22:18:27,414 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/data/372be3224/d07311f358d2446c95c6abdf45b8c629 [2024-10-31 22:18:27,417 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 22:18:27,419 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 22:18:27,421 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 22:18:27,421 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 22:18:27,428 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 22:18:27,429 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:18:27" (1/1) ... [2024-10-31 22:18:27,430 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@d0bb150 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:27, skipping insertion in model container [2024-10-31 22:18:27,430 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 10:18:27" (1/1) ... [2024-10-31 22:18:27,491 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 22:18:27,904 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:27,927 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 22:18:28,016 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 22:18:28,045 INFO L204 MainTranslator]: Completed translation [2024-10-31 22:18:28,046 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28 WrapperNode [2024-10-31 22:18:28,046 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 22:18:28,047 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:28,048 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 22:18:28,048 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 22:18:28,060 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,075 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,182 INFO L138 Inliner]: procedures = 44, calls = 55, calls flagged for inlining = 50, calls inlined = 147, statements flattened = 2216 [2024-10-31 22:18:28,183 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 22:18:28,183 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 22:18:28,184 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 22:18:28,184 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 22:18:28,197 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,198 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,207 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,253 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 22:18:28,254 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,254 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,303 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,334 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,338 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,345 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,354 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 22:18:28,355 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 22:18:28,355 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 22:18:28,355 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 22:18:28,356 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (1/1) ... [2024-10-31 22:18:28,362 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 22:18:28,380 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 22:18:28,401 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 22:18:28,411 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cca5858c-bd2e-485f-a60e-a3983f5075e3/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 22:18:28,445 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 22:18:28,446 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 22:18:28,446 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 22:18:28,446 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 22:18:28,600 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 22:18:28,602 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 22:18:30,757 INFO L? ?]: Removed 438 outVars from TransFormulas that were not future-live. [2024-10-31 22:18:30,757 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 22:18:30,805 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 22:18:30,806 INFO L316 CfgBuilder]: Removed 12 assume(true) statements. [2024-10-31 22:18:30,806 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:30 BoogieIcfgContainer [2024-10-31 22:18:30,806 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 22:18:30,812 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 22:18:30,812 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 22:18:30,818 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 22:18:30,819 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:30,820 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 10:18:27" (1/3) ... [2024-10-31 22:18:30,821 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64b3ceda and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:30, skipping insertion in model container [2024-10-31 22:18:30,821 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:30,821 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 10:18:28" (2/3) ... [2024-10-31 22:18:30,822 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64b3ceda and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 10:18:30, skipping insertion in model container [2024-10-31 22:18:30,822 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 22:18:30,822 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 10:18:30" (3/3) ... [2024-10-31 22:18:30,823 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.08.cil.c [2024-10-31 22:18:30,919 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 22:18:30,919 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 22:18:30,919 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 22:18:30,919 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 22:18:30,920 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 22:18:30,920 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 22:18:30,921 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 22:18:30,921 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 22:18:30,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:31,013 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2024-10-31 22:18:31,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:31,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:31,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:31,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:31,032 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 22:18:31,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:31,048 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2024-10-31 22:18:31,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:31,049 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:31,055 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:31,056 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:31,067 INFO L745 eck$LassoCheckResult]: Stem: 126#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 859#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 683#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 855#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 685#L581true assume !(1 == ~m_i~0);~m_st~0 := 2; 193#L581-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 827#L586-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 676#L591-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 652#L596-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 239#L601-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 686#L606-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 413#L611-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 771#L616-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 295#L621-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 713#L838true assume !(0 == ~M_E~0); 422#L838-2true assume !(0 == ~T1_E~0); 25#L843-1true assume !(0 == ~T2_E~0); 83#L848-1true assume !(0 == ~T3_E~0); 435#L853-1true assume !(0 == ~T4_E~0); 287#L858-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 2#L863-1true assume !(0 == ~T6_E~0); 764#L868-1true assume !(0 == ~T7_E~0); 884#L873-1true assume !(0 == ~T8_E~0); 758#L878-1true assume !(0 == ~E_1~0); 722#L883-1true assume !(0 == ~E_2~0); 797#L888-1true assume !(0 == ~E_3~0); 390#L893-1true assume !(0 == ~E_4~0); 798#L898-1true assume 0 == ~E_5~0;~E_5~0 := 1; 928#L903-1true assume !(0 == ~E_6~0); 719#L908-1true assume !(0 == ~E_7~0); 506#L913-1true assume !(0 == ~E_8~0); 30#L918-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 525#L402true assume !(1 == ~m_pc~0); 271#L402-2true is_master_triggered_~__retres1~0#1 := 0; 96#L413true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 575#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 243#L1035true assume !(0 != activate_threads_~tmp~1#1); 279#L1035-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 710#L421true assume 1 == ~t1_pc~0; 826#L422true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 900#L432true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315#L1043true assume !(0 != activate_threads_~tmp___0~0#1); 787#L1043-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912#L440true assume 1 == ~t2_pc~0; 18#L441true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 101#L451true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 833#L1051true assume !(0 != activate_threads_~tmp___1~0#1); 527#L1051-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213#L459true assume !(1 == ~t3_pc~0); 702#L459-2true is_transmit3_triggered_~__retres1~3#1 := 0; 782#L470true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 93#L1059true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 934#L1059-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98#L478true assume 1 == ~t4_pc~0; 394#L479true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 674#L489true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198#L1067true assume !(0 != activate_threads_~tmp___3~0#1); 50#L1067-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 432#L497true assume !(1 == ~t5_pc~0); 361#L497-2true is_transmit5_triggered_~__retres1~5#1 := 0; 458#L508true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 577#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 788#L1075true assume !(0 != activate_threads_~tmp___4~0#1); 696#L1075-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 891#L516true assume 1 == ~t6_pc~0; 892#L517true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 412#L527true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123#L1083true assume !(0 != activate_threads_~tmp___5~0#1); 472#L1083-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406#L535true assume !(1 == ~t7_pc~0); 802#L535-2true is_transmit7_triggered_~__retres1~7#1 := 0; 470#L546true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 870#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 500#L1091true assume !(0 != activate_threads_~tmp___6~0#1); 493#L1091-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 687#L554true assume 1 == ~t8_pc~0; 438#L555true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 828#L565true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 518#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171#L1099true assume !(0 != activate_threads_~tmp___7~0#1); 501#L1099-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7#L931true assume !(1 == ~M_E~0); 743#L931-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 824#L936-1true assume !(1 == ~T2_E~0); 909#L941-1true assume !(1 == ~T3_E~0); 280#L946-1true assume !(1 == ~T4_E~0); 707#L951-1true assume !(1 == ~T5_E~0); 131#L956-1true assume !(1 == ~T6_E~0); 893#L961-1true assume !(1 == ~T7_E~0); 391#L966-1true assume !(1 == ~T8_E~0); 495#L971-1true assume 1 == ~E_1~0;~E_1~0 := 2; 845#L976-1true assume !(1 == ~E_2~0); 463#L981-1true assume !(1 == ~E_3~0); 283#L986-1true assume !(1 == ~E_4~0); 146#L991-1true assume !(1 == ~E_5~0); 874#L996-1true assume !(1 == ~E_6~0); 776#L1001-1true assume !(1 == ~E_7~0); 431#L1006-1true assume !(1 == ~E_8~0); 708#L1011-1true assume { :end_inline_reset_delta_events } true; 36#L1272-2true [2024-10-31 22:18:31,073 INFO L747 eck$LassoCheckResult]: Loop: 36#L1272-2true assume !false; 427#L1273true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 837#L813-1true assume false; 524#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 316#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 657#L838-3true assume 0 == ~M_E~0;~M_E~0 := 1; 478#L838-5true assume !(0 == ~T1_E~0); 808#L843-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 350#L848-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 392#L853-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 585#L858-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 452#L863-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 442#L868-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 461#L873-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 160#L878-3true assume !(0 == ~E_1~0); 19#L883-3true assume 0 == ~E_2~0;~E_2~0 := 1; 671#L888-3true assume 0 == ~E_3~0;~E_3~0 := 1; 20#L893-3true assume 0 == ~E_4~0;~E_4~0 := 1; 298#L898-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L903-3true assume 0 == ~E_6~0;~E_6~0 := 1; 796#L908-3true assume 0 == ~E_7~0;~E_7~0 := 1; 303#L913-3true assume 0 == ~E_8~0;~E_8~0 := 1; 38#L918-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 902#L402-27true assume 1 == ~m_pc~0; 14#L403-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 850#L413-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471#is_master_triggered_returnLabel#10true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 748#L1035-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 640#L1035-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 673#L421-27true assume 1 == ~t1_pc~0; 504#L422-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 832#L432-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 374#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 777#L1043-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 898#L1043-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 407#L440-27true assume 1 == ~t2_pc~0; 880#L441-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 940#L451-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 446#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 330#L1051-27true assume !(0 != activate_threads_~tmp___1~0#1); 420#L1051-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148#L459-27true assume !(1 == ~t3_pc~0); 662#L459-29true is_transmit3_triggered_~__retres1~3#1 := 0; 847#L470-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 405#L1059-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 762#L1059-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 895#L478-27true assume !(1 == ~t4_pc~0); 141#L478-29true is_transmit4_triggered_~__retres1~4#1 := 0; 414#L489-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 555#L1067-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 763#L1067-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607#L497-27true assume 1 == ~t5_pc~0; 840#L498-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 166#L508-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134#L1075-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 678#L1075-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 300#L516-27true assume !(1 == ~t6_pc~0); 418#L516-29true is_transmit6_triggered_~__retres1~6#1 := 0; 203#L527-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 424#L1083-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 774#L1083-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254#L535-27true assume !(1 == ~t7_pc~0); 534#L535-29true is_transmit7_triggered_~__retres1~7#1 := 0; 937#L546-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842#L1091-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 225#L1091-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 786#L554-27true assume !(1 == ~t8_pc~0); 26#L554-29true is_transmit8_triggered_~__retres1~8#1 := 0; 100#L565-9true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 550#is_transmit8_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 335#L1099-27true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 158#L1099-29true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 529#L931-3true assume 1 == ~M_E~0;~M_E~0 := 2; 91#L931-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 223#L936-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 311#L941-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 531#L946-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 168#L951-3true assume !(1 == ~T5_E~0); 513#L956-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 371#L961-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 232#L966-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 726#L971-3true assume 1 == ~E_1~0;~E_1~0 := 2; 411#L976-3true assume 1 == ~E_2~0;~E_2~0 := 2; 35#L981-3true assume 1 == ~E_3~0;~E_3~0 := 2; 159#L986-3true assume 1 == ~E_4~0;~E_4~0 := 2; 29#L991-3true assume !(1 == ~E_5~0); 482#L996-3true assume 1 == ~E_6~0;~E_6~0 := 2; 611#L1001-3true assume 1 == ~E_7~0;~E_7~0 := 2; 215#L1006-3true assume 1 == ~E_8~0;~E_8~0 := 2; 516#L1011-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48#L634-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 314#L681-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 183#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 792#L1291true assume !(0 == start_simulation_~tmp~3#1); 759#L1291-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 293#L634-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4#L681-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 730#L1246true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267#L1253true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 329#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 556#L1304true assume !(0 != start_simulation_~tmp___0~1#1); 36#L1272-2true [2024-10-31 22:18:31,085 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:31,086 INFO L85 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2024-10-31 22:18:31,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:31,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217963769] [2024-10-31 22:18:31,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:31,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:31,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:31,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:31,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:31,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217963769] [2024-10-31 22:18:31,521 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217963769] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:31,522 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:31,522 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:31,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752438943] [2024-10-31 22:18:31,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:31,530 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:31,532 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:31,533 INFO L85 PathProgramCache]: Analyzing trace with hash -651940443, now seen corresponding path program 1 times [2024-10-31 22:18:31,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:31,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245676142] [2024-10-31 22:18:31,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:31,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:31,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:31,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:31,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:31,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245676142] [2024-10-31 22:18:31,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245676142] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:31,626 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:31,626 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:31,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889640701] [2024-10-31 22:18:31,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:31,630 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:31,631 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:31,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:31,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:31,676 INFO L87 Difference]: Start difference. First operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:31,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:31,777 INFO L93 Difference]: Finished difference Result 939 states and 1394 transitions. [2024-10-31 22:18:31,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 939 states and 1394 transitions. [2024-10-31 22:18:31,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:31,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 939 states to 933 states and 1388 transitions. [2024-10-31 22:18:31,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-31 22:18:31,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-31 22:18:31,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1388 transitions. [2024-10-31 22:18:31,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:31,805 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2024-10-31 22:18:31,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1388 transitions. [2024-10-31 22:18:31,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-31 22:18:31,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.487674169346195) internal successors, (1388), 932 states have internal predecessors, (1388), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:31,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1388 transitions. [2024-10-31 22:18:31,897 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2024-10-31 22:18:31,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:31,903 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1388 transitions. [2024-10-31 22:18:31,904 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 22:18:31,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1388 transitions. [2024-10-31 22:18:31,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:31,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:31,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:31,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:31,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:31,917 INFO L745 eck$LassoCheckResult]: Stem: 2139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2766#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2767#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2768#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2258#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2259#L586-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2764#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2760#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2330#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2331#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2565#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2566#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2414#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2415#L838 assume !(0 == ~M_E~0); 2573#L838-2 assume !(0 == ~T1_E~0); 1938#L843-1 assume !(0 == ~T2_E~0); 1939#L848-1 assume !(0 == ~T3_E~0); 2059#L853-1 assume !(0 == ~T4_E~0); 2401#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1889#L863-1 assume !(0 == ~T6_E~0); 1890#L868-1 assume !(0 == ~T7_E~0); 2796#L873-1 assume !(0 == ~T8_E~0); 2794#L878-1 assume !(0 == ~E_1~0); 2785#L883-1 assume !(0 == ~E_2~0); 2786#L888-1 assume !(0 == ~E_3~0); 2534#L893-1 assume !(0 == ~E_4~0); 2535#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2806#L903-1 assume !(0 == ~E_6~0); 2783#L908-1 assume !(0 == ~E_7~0); 2664#L913-1 assume !(0 == ~E_8~0); 1950#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1951#L402 assume !(1 == ~m_pc~0); 2162#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2083#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2084#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2336#L1035 assume !(0 != activate_threads_~tmp~1#1); 2337#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2389#L421 assume 1 == ~t1_pc~0; 2779#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2797#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1953#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1954#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2443#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2804#L440 assume 1 == ~t2_pc~0; 1922#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1923#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2093#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2284#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2679#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2287#L459 assume !(1 == ~t3_pc~0); 2288#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2777#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1911#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1912#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2078#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2087#L478 assume 1 == ~t4_pc~0; 2088#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2539#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2032#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1992#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1993#L497 assume !(1 == ~t5_pc~0); 2042#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2043#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2610#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2716#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2773#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2774#L516 assume 1 == ~t6_pc~0; 2820#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2564#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2267#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2133#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2134#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2553#L535 assume !(1 == ~t7_pc~0); 2554#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2624#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2656#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2646#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2647#L554 assume 1 == ~t8_pc~0; 2589#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1914#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2672#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2221#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2222#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1900#L931 assume !(1 == ~M_E~0); 1901#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2792#L936-1 assume !(1 == ~T2_E~0); 2811#L941-1 assume !(1 == ~T3_E~0); 2390#L946-1 assume !(1 == ~T4_E~0); 2391#L951-1 assume !(1 == ~T5_E~0); 2148#L956-1 assume !(1 == ~T6_E~0); 2149#L961-1 assume !(1 == ~T7_E~0); 2536#L966-1 assume !(1 == ~T8_E~0); 2537#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2649#L976-1 assume !(1 == ~E_2~0); 2614#L981-1 assume !(1 == ~E_3~0); 2394#L986-1 assume !(1 == ~E_4~0); 2175#L991-1 assume !(1 == ~E_5~0); 2176#L996-1 assume !(1 == ~E_6~0); 2801#L1001-1 assume !(1 == ~E_7~0); 2584#L1006-1 assume !(1 == ~E_8~0); 2585#L1011-1 assume { :end_inline_reset_delta_events } true; 1961#L1272-2 [2024-10-31 22:18:31,918 INFO L747 eck$LassoCheckResult]: Loop: 1961#L1272-2 assume !false; 1962#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2198#L813-1 assume !false; 2734#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2735#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1964#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2303#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2304#L696 assume !(0 != eval_~tmp~0#1); 2677#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2444#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2445#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2633#L838-5 assume !(0 == ~T1_E~0); 2634#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2487#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2488#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2538#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2603#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2593#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2594#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2202#L878-3 assume !(0 == ~E_1~0); 1925#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1926#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1927#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1928#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2420#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2736#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2428#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1966#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1967#L402-27 assume 1 == ~m_pc~0; 1915#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1916#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2626#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2627#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2753#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2754#L421-27 assume !(1 == ~t1_pc~0); 2192#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2193#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2512#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2513#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2802#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2556#L440-27 assume !(1 == ~t2_pc~0); 2557#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2731#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2598#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2463#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 2464#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2178#L459-27 assume 1 == ~t3_pc~0; 2179#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2619#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2440#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2441#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2552#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2795#L478-27 assume !(1 == ~t4_pc~0); 2167#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2168#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2351#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2352#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2701#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2737#L497-27 assume 1 == ~t5_pc~0; 2738#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2211#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2212#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2154#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2155#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2422#L516-27 assume !(1 == ~t6_pc~0); 2423#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2275#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2276#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2575#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2576#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2355#L535-27 assume 1 == ~t7_pc~0; 2356#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2685#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2235#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2236#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2306#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2307#L554-27 assume !(1 == ~t8_pc~0); 1940#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1941#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2092#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2472#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2199#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2200#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2074#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2075#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2305#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2439#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2215#L951-3 assume !(1 == ~T5_E~0); 2216#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2510#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2315#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2316#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2563#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1959#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1960#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1948#L991-3 assume !(1 == ~E_5~0); 1949#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2639#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2292#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2293#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1987#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1988#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2241#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2242#L1291 assume !(0 == start_simulation_~tmp~3#1); 2507#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2410#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1893#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1894#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1952#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2376#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2377#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2462#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1961#L1272-2 [2024-10-31 22:18:31,919 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:31,919 INFO L85 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2024-10-31 22:18:31,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:31,919 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251315450] [2024-10-31 22:18:31,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:31,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:31,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:32,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:32,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:32,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [251315450] [2024-10-31 22:18:32,049 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [251315450] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:32,049 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:32,049 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:32,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387222215] [2024-10-31 22:18:32,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:32,050 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:32,051 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:32,051 INFO L85 PathProgramCache]: Analyzing trace with hash 56067214, now seen corresponding path program 1 times [2024-10-31 22:18:32,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:32,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278077029] [2024-10-31 22:18:32,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:32,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:32,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:32,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:32,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:32,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278077029] [2024-10-31 22:18:32,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278077029] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:32,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:32,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:32,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191048535] [2024-10-31 22:18:32,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:32,240 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:32,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:32,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:32,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:32,241 INFO L87 Difference]: Start difference. First operand 933 states and 1388 transitions. cyclomatic complexity: 456 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:32,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:32,272 INFO L93 Difference]: Finished difference Result 933 states and 1387 transitions. [2024-10-31 22:18:32,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1387 transitions. [2024-10-31 22:18:32,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:32,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1387 transitions. [2024-10-31 22:18:32,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-31 22:18:32,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-31 22:18:32,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1387 transitions. [2024-10-31 22:18:32,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:32,329 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2024-10-31 22:18:32,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1387 transitions. [2024-10-31 22:18:32,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-31 22:18:32,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4866023579849947) internal successors, (1387), 932 states have internal predecessors, (1387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:32,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1387 transitions. [2024-10-31 22:18:32,361 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2024-10-31 22:18:32,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:32,363 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1387 transitions. [2024-10-31 22:18:32,363 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 22:18:32,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1387 transitions. [2024-10-31 22:18:32,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:32,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:32,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:32,374 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:32,375 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:32,376 INFO L745 eck$LassoCheckResult]: Stem: 4012#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4013#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4641#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4131#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4132#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4637#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4633#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4203#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4204#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4438#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4439#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4287#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4288#L838 assume !(0 == ~M_E~0); 4446#L838-2 assume !(0 == ~T1_E~0); 3811#L843-1 assume !(0 == ~T2_E~0); 3812#L848-1 assume !(0 == ~T3_E~0); 3932#L853-1 assume !(0 == ~T4_E~0); 4274#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3762#L863-1 assume !(0 == ~T6_E~0); 3763#L868-1 assume !(0 == ~T7_E~0); 4669#L873-1 assume !(0 == ~T8_E~0); 4667#L878-1 assume !(0 == ~E_1~0); 4658#L883-1 assume !(0 == ~E_2~0); 4659#L888-1 assume !(0 == ~E_3~0); 4407#L893-1 assume !(0 == ~E_4~0); 4408#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4679#L903-1 assume !(0 == ~E_6~0); 4656#L908-1 assume !(0 == ~E_7~0); 4537#L913-1 assume !(0 == ~E_8~0); 3823#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3824#L402 assume !(1 == ~m_pc~0); 4035#L402-2 is_master_triggered_~__retres1~0#1 := 0; 3956#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3957#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4209#L1035 assume !(0 != activate_threads_~tmp~1#1); 4210#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4262#L421 assume 1 == ~t1_pc~0; 4652#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4670#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3827#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4316#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4677#L440 assume 1 == ~t2_pc~0; 3795#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3796#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3966#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4157#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4552#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4160#L459 assume !(1 == ~t3_pc~0); 4161#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3784#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3785#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3951#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3960#L478 assume 1 == ~t4_pc~0; 3961#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4412#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3904#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3905#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 3865#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3866#L497 assume !(1 == ~t5_pc~0); 3915#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3916#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4483#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4589#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4646#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4647#L516 assume 1 == ~t6_pc~0; 4693#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4437#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4006#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 4007#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4426#L535 assume !(1 == ~t7_pc~0); 4427#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4497#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4498#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4529#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4519#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4520#L554 assume 1 == ~t8_pc~0; 4462#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3787#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4545#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4094#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4095#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3773#L931 assume !(1 == ~M_E~0); 3774#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4665#L936-1 assume !(1 == ~T2_E~0); 4684#L941-1 assume !(1 == ~T3_E~0); 4263#L946-1 assume !(1 == ~T4_E~0); 4264#L951-1 assume !(1 == ~T5_E~0); 4021#L956-1 assume !(1 == ~T6_E~0); 4022#L961-1 assume !(1 == ~T7_E~0); 4409#L966-1 assume !(1 == ~T8_E~0); 4410#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4522#L976-1 assume !(1 == ~E_2~0); 4487#L981-1 assume !(1 == ~E_3~0); 4267#L986-1 assume !(1 == ~E_4~0); 4048#L991-1 assume !(1 == ~E_5~0); 4049#L996-1 assume !(1 == ~E_6~0); 4674#L1001-1 assume !(1 == ~E_7~0); 4457#L1006-1 assume !(1 == ~E_8~0); 4458#L1011-1 assume { :end_inline_reset_delta_events } true; 3834#L1272-2 [2024-10-31 22:18:32,381 INFO L747 eck$LassoCheckResult]: Loop: 3834#L1272-2 assume !false; 3835#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4071#L813-1 assume !false; 4607#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4608#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3837#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4176#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4177#L696 assume !(0 != eval_~tmp~0#1); 4550#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4318#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4506#L838-5 assume !(0 == ~T1_E~0); 4507#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4360#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4361#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4411#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4476#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4466#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4467#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4075#L878-3 assume !(0 == ~E_1~0); 3798#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3799#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3800#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3801#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4293#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4609#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4301#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3839#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3840#L402-27 assume 1 == ~m_pc~0; 3788#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3789#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4499#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4500#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4626#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4627#L421-27 assume !(1 == ~t1_pc~0); 4065#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4066#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4386#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4675#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4429#L440-27 assume !(1 == ~t2_pc~0); 4430#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 4604#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4471#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4336#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 4337#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4051#L459-27 assume 1 == ~t3_pc~0; 4052#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4492#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4313#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4314#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4425#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4668#L478-27 assume !(1 == ~t4_pc~0); 4040#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4041#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4224#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4225#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4574#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4610#L497-27 assume 1 == ~t5_pc~0; 4611#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4084#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4085#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4027#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4028#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4295#L516-27 assume !(1 == ~t6_pc~0); 4296#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 4148#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4149#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4448#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4449#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4228#L535-27 assume 1 == ~t7_pc~0; 4229#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4558#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4108#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4109#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4179#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4180#L554-27 assume !(1 == ~t8_pc~0); 3813#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 3814#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3965#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4345#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4072#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4073#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3947#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3948#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4178#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4312#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4088#L951-3 assume !(1 == ~T5_E~0); 4089#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4383#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4188#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4189#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4436#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3832#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3833#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3821#L991-3 assume !(1 == ~E_5~0); 3822#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4512#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4165#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4166#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3860#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3861#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4115#L1291 assume !(0 == start_simulation_~tmp~3#1); 4380#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4283#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3766#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3825#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4249#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4250#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4335#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 3834#L1272-2 [2024-10-31 22:18:32,382 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:32,382 INFO L85 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2024-10-31 22:18:32,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:32,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642091237] [2024-10-31 22:18:32,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:32,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:32,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:32,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:32,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:32,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642091237] [2024-10-31 22:18:32,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642091237] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:32,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:32,500 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:32,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [837031693] [2024-10-31 22:18:32,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:32,501 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:32,501 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:32,501 INFO L85 PathProgramCache]: Analyzing trace with hash 56067214, now seen corresponding path program 2 times [2024-10-31 22:18:32,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:32,502 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620850141] [2024-10-31 22:18:32,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:32,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:32,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:32,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:32,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:32,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620850141] [2024-10-31 22:18:32,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [620850141] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:32,625 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:32,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:32,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282553874] [2024-10-31 22:18:32,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:32,626 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:32,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:32,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:32,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:32,628 INFO L87 Difference]: Start difference. First operand 933 states and 1387 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:32,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:32,657 INFO L93 Difference]: Finished difference Result 933 states and 1386 transitions. [2024-10-31 22:18:32,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1386 transitions. [2024-10-31 22:18:32,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:32,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1386 transitions. [2024-10-31 22:18:32,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-31 22:18:32,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-31 22:18:32,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1386 transitions. [2024-10-31 22:18:32,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:32,677 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2024-10-31 22:18:32,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1386 transitions. [2024-10-31 22:18:32,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-31 22:18:32,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4855305466237942) internal successors, (1386), 932 states have internal predecessors, (1386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:32,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1386 transitions. [2024-10-31 22:18:32,699 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2024-10-31 22:18:32,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:32,701 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1386 transitions. [2024-10-31 22:18:32,702 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 22:18:32,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1386 transitions. [2024-10-31 22:18:32,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:32,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:32,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:32,714 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:32,714 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:32,715 INFO L745 eck$LassoCheckResult]: Stem: 5885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6514#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 6004#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6005#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6510#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6506#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6076#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6077#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6311#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6312#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6160#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6161#L838 assume !(0 == ~M_E~0); 6319#L838-2 assume !(0 == ~T1_E~0); 5684#L843-1 assume !(0 == ~T2_E~0); 5685#L848-1 assume !(0 == ~T3_E~0); 5805#L853-1 assume !(0 == ~T4_E~0); 6147#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5635#L863-1 assume !(0 == ~T6_E~0); 5636#L868-1 assume !(0 == ~T7_E~0); 6542#L873-1 assume !(0 == ~T8_E~0); 6540#L878-1 assume !(0 == ~E_1~0); 6531#L883-1 assume !(0 == ~E_2~0); 6532#L888-1 assume !(0 == ~E_3~0); 6280#L893-1 assume !(0 == ~E_4~0); 6281#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6552#L903-1 assume !(0 == ~E_6~0); 6529#L908-1 assume !(0 == ~E_7~0); 6410#L913-1 assume !(0 == ~E_8~0); 5696#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5697#L402 assume !(1 == ~m_pc~0); 5908#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5829#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5830#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6082#L1035 assume !(0 != activate_threads_~tmp~1#1); 6083#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6135#L421 assume 1 == ~t1_pc~0; 6525#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6543#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5700#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6189#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6550#L440 assume 1 == ~t2_pc~0; 5668#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5669#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5839#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6030#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6425#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6033#L459 assume !(1 == ~t3_pc~0); 6034#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6523#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5657#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5658#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5824#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5833#L478 assume 1 == ~t4_pc~0; 5834#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6285#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5778#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5738#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5739#L497 assume !(1 == ~t5_pc~0); 5788#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5789#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6356#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6462#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6519#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6520#L516 assume 1 == ~t6_pc~0; 6566#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6310#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6013#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5879#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5880#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6299#L535 assume !(1 == ~t7_pc~0); 6300#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6370#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6371#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6402#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6392#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6393#L554 assume 1 == ~t8_pc~0; 6335#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5660#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6418#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5967#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5968#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5646#L931 assume !(1 == ~M_E~0); 5647#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6538#L936-1 assume !(1 == ~T2_E~0); 6557#L941-1 assume !(1 == ~T3_E~0); 6136#L946-1 assume !(1 == ~T4_E~0); 6137#L951-1 assume !(1 == ~T5_E~0); 5894#L956-1 assume !(1 == ~T6_E~0); 5895#L961-1 assume !(1 == ~T7_E~0); 6282#L966-1 assume !(1 == ~T8_E~0); 6283#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6395#L976-1 assume !(1 == ~E_2~0); 6360#L981-1 assume !(1 == ~E_3~0); 6140#L986-1 assume !(1 == ~E_4~0); 5921#L991-1 assume !(1 == ~E_5~0); 5922#L996-1 assume !(1 == ~E_6~0); 6547#L1001-1 assume !(1 == ~E_7~0); 6330#L1006-1 assume !(1 == ~E_8~0); 6331#L1011-1 assume { :end_inline_reset_delta_events } true; 5707#L1272-2 [2024-10-31 22:18:32,716 INFO L747 eck$LassoCheckResult]: Loop: 5707#L1272-2 assume !false; 5708#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5944#L813-1 assume !false; 6480#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6481#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5710#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6049#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6050#L696 assume !(0 != eval_~tmp~0#1); 6423#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6190#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6191#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6379#L838-5 assume !(0 == ~T1_E~0); 6380#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6233#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6234#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6284#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6349#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6339#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6340#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5948#L878-3 assume !(0 == ~E_1~0); 5671#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5672#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5673#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5674#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6166#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6482#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6174#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5712#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5713#L402-27 assume 1 == ~m_pc~0; 5661#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5662#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6372#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6373#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6499#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6500#L421-27 assume !(1 == ~t1_pc~0); 5938#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5939#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6258#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6259#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6548#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6302#L440-27 assume 1 == ~t2_pc~0; 6304#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6477#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6344#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6209#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 6210#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5924#L459-27 assume 1 == ~t3_pc~0; 5925#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6365#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6186#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6187#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6298#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6541#L478-27 assume 1 == ~t4_pc~0; 6560#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5914#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6097#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6098#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6447#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6483#L497-27 assume 1 == ~t5_pc~0; 6484#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5957#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5958#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5900#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5901#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6168#L516-27 assume !(1 == ~t6_pc~0); 6169#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 6021#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6022#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6321#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6322#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6101#L535-27 assume 1 == ~t7_pc~0; 6102#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6431#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5981#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5982#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6052#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6053#L554-27 assume !(1 == ~t8_pc~0); 5686#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 5687#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5838#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6218#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5945#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5946#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5820#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5821#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6051#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6185#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5961#L951-3 assume !(1 == ~T5_E~0); 5962#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6256#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6061#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6062#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6309#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5705#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5706#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5694#L991-3 assume !(1 == ~E_5~0); 5695#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6385#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6038#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6039#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5733#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5734#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5987#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5988#L1291 assume !(0 == start_simulation_~tmp~3#1); 6253#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6156#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5639#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5698#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6122#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6123#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6208#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 5707#L1272-2 [2024-10-31 22:18:32,717 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:32,718 INFO L85 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2024-10-31 22:18:32,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:32,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009125090] [2024-10-31 22:18:32,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:32,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:32,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:32,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:32,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:32,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009125090] [2024-10-31 22:18:32,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1009125090] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:32,785 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:32,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:32,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319230310] [2024-10-31 22:18:32,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:32,786 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:32,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:32,787 INFO L85 PathProgramCache]: Analyzing trace with hash -1847000368, now seen corresponding path program 1 times [2024-10-31 22:18:32,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:32,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238737058] [2024-10-31 22:18:32,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:32,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:32,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:32,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:32,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:32,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [238737058] [2024-10-31 22:18:32,864 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [238737058] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:32,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:32,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:32,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76319877] [2024-10-31 22:18:32,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:32,866 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:32,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:32,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:32,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:32,867 INFO L87 Difference]: Start difference. First operand 933 states and 1386 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:32,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:32,893 INFO L93 Difference]: Finished difference Result 933 states and 1385 transitions. [2024-10-31 22:18:32,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1385 transitions. [2024-10-31 22:18:32,903 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:32,907 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1385 transitions. [2024-10-31 22:18:32,907 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-31 22:18:32,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-31 22:18:32,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1385 transitions. [2024-10-31 22:18:32,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:32,910 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2024-10-31 22:18:32,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1385 transitions. [2024-10-31 22:18:32,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-31 22:18:32,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4844587352625938) internal successors, (1385), 932 states have internal predecessors, (1385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:32,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1385 transitions. [2024-10-31 22:18:32,930 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2024-10-31 22:18:32,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:32,931 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1385 transitions. [2024-10-31 22:18:32,931 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 22:18:32,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1385 transitions. [2024-10-31 22:18:32,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:32,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:32,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:32,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:32,945 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:32,946 INFO L745 eck$LassoCheckResult]: Stem: 7758#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 7759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8387#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 7877#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7878#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8383#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8379#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7949#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7950#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8184#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8185#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8033#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8034#L838 assume !(0 == ~M_E~0); 8192#L838-2 assume !(0 == ~T1_E~0); 7557#L843-1 assume !(0 == ~T2_E~0); 7558#L848-1 assume !(0 == ~T3_E~0); 7678#L853-1 assume !(0 == ~T4_E~0); 8020#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7508#L863-1 assume !(0 == ~T6_E~0); 7509#L868-1 assume !(0 == ~T7_E~0); 8415#L873-1 assume !(0 == ~T8_E~0); 8413#L878-1 assume !(0 == ~E_1~0); 8404#L883-1 assume !(0 == ~E_2~0); 8405#L888-1 assume !(0 == ~E_3~0); 8153#L893-1 assume !(0 == ~E_4~0); 8154#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8425#L903-1 assume !(0 == ~E_6~0); 8402#L908-1 assume !(0 == ~E_7~0); 8283#L913-1 assume !(0 == ~E_8~0); 7569#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7570#L402 assume !(1 == ~m_pc~0); 7781#L402-2 is_master_triggered_~__retres1~0#1 := 0; 7702#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7703#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7955#L1035 assume !(0 != activate_threads_~tmp~1#1); 7956#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8008#L421 assume 1 == ~t1_pc~0; 8398#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8416#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7573#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 8062#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8423#L440 assume 1 == ~t2_pc~0; 7541#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7542#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7712#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7903#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 8298#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7906#L459 assume !(1 == ~t3_pc~0); 7907#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8396#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7530#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7531#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7697#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7706#L478 assume 1 == ~t4_pc~0; 7707#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8158#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7651#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 7611#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7612#L497 assume !(1 == ~t5_pc~0); 7661#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7662#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8229#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8335#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 8392#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8393#L516 assume 1 == ~t6_pc~0; 8439#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8183#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7886#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7752#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 7753#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8172#L535 assume !(1 == ~t7_pc~0); 8173#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8243#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8244#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8275#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 8265#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8266#L554 assume 1 == ~t8_pc~0; 8208#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7533#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8291#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7840#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 7841#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7519#L931 assume !(1 == ~M_E~0); 7520#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8411#L936-1 assume !(1 == ~T2_E~0); 8430#L941-1 assume !(1 == ~T3_E~0); 8009#L946-1 assume !(1 == ~T4_E~0); 8010#L951-1 assume !(1 == ~T5_E~0); 7767#L956-1 assume !(1 == ~T6_E~0); 7768#L961-1 assume !(1 == ~T7_E~0); 8155#L966-1 assume !(1 == ~T8_E~0); 8156#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8268#L976-1 assume !(1 == ~E_2~0); 8233#L981-1 assume !(1 == ~E_3~0); 8013#L986-1 assume !(1 == ~E_4~0); 7794#L991-1 assume !(1 == ~E_5~0); 7795#L996-1 assume !(1 == ~E_6~0); 8420#L1001-1 assume !(1 == ~E_7~0); 8203#L1006-1 assume !(1 == ~E_8~0); 8204#L1011-1 assume { :end_inline_reset_delta_events } true; 7580#L1272-2 [2024-10-31 22:18:32,946 INFO L747 eck$LassoCheckResult]: Loop: 7580#L1272-2 assume !false; 7581#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7817#L813-1 assume !false; 8353#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8354#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7583#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7922#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7923#L696 assume !(0 != eval_~tmp~0#1); 8296#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8064#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8252#L838-5 assume !(0 == ~T1_E~0); 8253#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8106#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8107#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8157#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8222#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8212#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8213#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7821#L878-3 assume !(0 == ~E_1~0); 7544#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7545#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7546#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7547#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8039#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8355#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8047#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7585#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7586#L402-27 assume !(1 == ~m_pc~0); 7536#L402-29 is_master_triggered_~__retres1~0#1 := 0; 7535#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8245#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8246#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8372#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8373#L421-27 assume !(1 == ~t1_pc~0); 7811#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7812#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8131#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8132#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8421#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8175#L440-27 assume !(1 == ~t2_pc~0); 8176#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 8350#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8217#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8082#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 8083#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7797#L459-27 assume 1 == ~t3_pc~0; 7798#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8238#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8059#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8060#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8171#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8414#L478-27 assume 1 == ~t4_pc~0; 8433#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7787#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7970#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7971#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8320#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8356#L497-27 assume 1 == ~t5_pc~0; 8357#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7830#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7831#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7773#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7774#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8041#L516-27 assume !(1 == ~t6_pc~0); 8042#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 7894#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7895#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8194#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8195#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7974#L535-27 assume 1 == ~t7_pc~0; 7975#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8304#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7854#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7855#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7925#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7926#L554-27 assume 1 == ~t8_pc~0; 8128#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7560#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7711#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8091#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7818#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7819#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7693#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7694#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7924#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8058#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7834#L951-3 assume !(1 == ~T5_E~0); 7835#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8129#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7934#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7935#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8182#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7578#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7579#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7567#L991-3 assume !(1 == ~E_5~0); 7568#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8258#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7911#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7912#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7606#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7607#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7861#L1291 assume !(0 == start_simulation_~tmp~3#1); 8126#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8029#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7512#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7513#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 7571#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7995#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7996#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8081#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 7580#L1272-2 [2024-10-31 22:18:32,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:32,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2024-10-31 22:18:32,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:32,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356022366] [2024-10-31 22:18:32,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:32,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:32,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [356022366] [2024-10-31 22:18:33,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [356022366] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,037 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,037 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:33,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259319271] [2024-10-31 22:18:33,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,037 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:33,038 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:33,038 INFO L85 PathProgramCache]: Analyzing trace with hash -1022505361, now seen corresponding path program 1 times [2024-10-31 22:18:33,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:33,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982426978] [2024-10-31 22:18:33,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:33,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:33,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982426978] [2024-10-31 22:18:33,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1982426978] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:33,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342811229] [2024-10-31 22:18:33,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,102 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:33,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:33,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:33,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:33,103 INFO L87 Difference]: Start difference. First operand 933 states and 1385 transitions. cyclomatic complexity: 453 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:33,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:33,129 INFO L93 Difference]: Finished difference Result 933 states and 1384 transitions. [2024-10-31 22:18:33,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1384 transitions. [2024-10-31 22:18:33,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:33,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1384 transitions. [2024-10-31 22:18:33,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-31 22:18:33,142 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-31 22:18:33,142 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1384 transitions. [2024-10-31 22:18:33,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:33,144 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2024-10-31 22:18:33,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1384 transitions. [2024-10-31 22:18:33,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-31 22:18:33,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4833869239013933) internal successors, (1384), 932 states have internal predecessors, (1384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:33,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1384 transitions. [2024-10-31 22:18:33,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2024-10-31 22:18:33,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:33,164 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1384 transitions. [2024-10-31 22:18:33,164 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 22:18:33,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1384 transitions. [2024-10-31 22:18:33,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:33,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:33,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:33,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:33,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:33,176 INFO L745 eck$LassoCheckResult]: Stem: 9631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10258#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10259#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10260#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9750#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9751#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10256#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10252#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9822#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9823#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10057#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10058#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9906#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9907#L838 assume !(0 == ~M_E~0); 10065#L838-2 assume !(0 == ~T1_E~0); 9430#L843-1 assume !(0 == ~T2_E~0); 9431#L848-1 assume !(0 == ~T3_E~0); 9551#L853-1 assume !(0 == ~T4_E~0); 9893#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9381#L863-1 assume !(0 == ~T6_E~0); 9382#L868-1 assume !(0 == ~T7_E~0); 10288#L873-1 assume !(0 == ~T8_E~0); 10286#L878-1 assume !(0 == ~E_1~0); 10277#L883-1 assume !(0 == ~E_2~0); 10278#L888-1 assume !(0 == ~E_3~0); 10026#L893-1 assume !(0 == ~E_4~0); 10027#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10298#L903-1 assume !(0 == ~E_6~0); 10275#L908-1 assume !(0 == ~E_7~0); 10156#L913-1 assume !(0 == ~E_8~0); 9442#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9443#L402 assume !(1 == ~m_pc~0); 9654#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9575#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9576#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9828#L1035 assume !(0 != activate_threads_~tmp~1#1); 9829#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9881#L421 assume 1 == ~t1_pc~0; 10271#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10289#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9445#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9446#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9935#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10296#L440 assume 1 == ~t2_pc~0; 9414#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9415#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9585#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9776#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 10171#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9779#L459 assume !(1 == ~t3_pc~0); 9780#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10269#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9404#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9570#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9579#L478 assume 1 == ~t4_pc~0; 9580#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10031#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9523#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9524#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9484#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9485#L497 assume !(1 == ~t5_pc~0); 9534#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9535#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10102#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10208#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 10265#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10266#L516 assume 1 == ~t6_pc~0; 10312#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10056#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9759#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9625#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9626#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10045#L535 assume !(1 == ~t7_pc~0); 10046#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10116#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10148#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 10138#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10139#L554 assume 1 == ~t8_pc~0; 10081#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9406#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10164#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9713#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9714#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9392#L931 assume !(1 == ~M_E~0); 9393#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10284#L936-1 assume !(1 == ~T2_E~0); 10303#L941-1 assume !(1 == ~T3_E~0); 9882#L946-1 assume !(1 == ~T4_E~0); 9883#L951-1 assume !(1 == ~T5_E~0); 9640#L956-1 assume !(1 == ~T6_E~0); 9641#L961-1 assume !(1 == ~T7_E~0); 10028#L966-1 assume !(1 == ~T8_E~0); 10029#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10141#L976-1 assume !(1 == ~E_2~0); 10106#L981-1 assume !(1 == ~E_3~0); 9886#L986-1 assume !(1 == ~E_4~0); 9667#L991-1 assume !(1 == ~E_5~0); 9668#L996-1 assume !(1 == ~E_6~0); 10293#L1001-1 assume !(1 == ~E_7~0); 10076#L1006-1 assume !(1 == ~E_8~0); 10077#L1011-1 assume { :end_inline_reset_delta_events } true; 9453#L1272-2 [2024-10-31 22:18:33,177 INFO L747 eck$LassoCheckResult]: Loop: 9453#L1272-2 assume !false; 9454#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9690#L813-1 assume !false; 10226#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10227#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9456#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9795#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9796#L696 assume !(0 != eval_~tmp~0#1); 10169#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9936#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9937#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10125#L838-5 assume !(0 == ~T1_E~0); 10126#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9979#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9980#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10030#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10095#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10085#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10086#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9694#L878-3 assume !(0 == ~E_1~0); 9417#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9418#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9419#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9420#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9912#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10228#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9920#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9458#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9459#L402-27 assume !(1 == ~m_pc~0); 9409#L402-29 is_master_triggered_~__retres1~0#1 := 0; 9408#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10118#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10119#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10245#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10246#L421-27 assume !(1 == ~t1_pc~0); 9684#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 9685#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10004#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10005#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10294#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10048#L440-27 assume !(1 == ~t2_pc~0); 10049#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 10223#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10090#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9955#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 9956#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9670#L459-27 assume 1 == ~t3_pc~0; 9671#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10111#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9932#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9933#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10044#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10287#L478-27 assume 1 == ~t4_pc~0; 10306#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9660#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9843#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9844#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10193#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10229#L497-27 assume 1 == ~t5_pc~0; 10230#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9703#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9704#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9646#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9647#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9914#L516-27 assume !(1 == ~t6_pc~0); 9915#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9767#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9768#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10067#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10068#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9847#L535-27 assume 1 == ~t7_pc~0; 9848#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10177#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9727#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9728#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9798#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9799#L554-27 assume 1 == ~t8_pc~0; 10001#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9433#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9584#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9964#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9691#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9692#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9566#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9567#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9797#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9931#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9707#L951-3 assume !(1 == ~T5_E~0); 9708#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10002#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9807#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9808#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10055#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9451#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9452#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9440#L991-3 assume !(1 == ~E_5~0); 9441#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10131#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9784#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9785#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9479#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9480#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9733#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9734#L1291 assume !(0 == start_simulation_~tmp~3#1); 9999#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9902#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9385#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9386#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 9444#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9868#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9869#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9954#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 9453#L1272-2 [2024-10-31 22:18:33,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:33,178 INFO L85 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2024-10-31 22:18:33,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:33,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102240110] [2024-10-31 22:18:33,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:33,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:33,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102240110] [2024-10-31 22:18:33,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102240110] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:33,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337400538] [2024-10-31 22:18:33,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,235 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:33,235 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:33,235 INFO L85 PathProgramCache]: Analyzing trace with hash -1022505361, now seen corresponding path program 2 times [2024-10-31 22:18:33,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:33,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113364678] [2024-10-31 22:18:33,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:33,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:33,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,308 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113364678] [2024-10-31 22:18:33,309 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113364678] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,309 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,309 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:33,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096575613] [2024-10-31 22:18:33,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,310 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:33,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:33,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:33,312 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:33,312 INFO L87 Difference]: Start difference. First operand 933 states and 1384 transitions. cyclomatic complexity: 452 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:33,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:33,338 INFO L93 Difference]: Finished difference Result 933 states and 1383 transitions. [2024-10-31 22:18:33,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1383 transitions. [2024-10-31 22:18:33,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:33,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1383 transitions. [2024-10-31 22:18:33,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-31 22:18:33,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-31 22:18:33,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1383 transitions. [2024-10-31 22:18:33,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:33,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2024-10-31 22:18:33,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1383 transitions. [2024-10-31 22:18:33,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-31 22:18:33,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.482315112540193) internal successors, (1383), 932 states have internal predecessors, (1383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:33,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1383 transitions. [2024-10-31 22:18:33,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2024-10-31 22:18:33,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:33,373 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1383 transitions. [2024-10-31 22:18:33,374 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 22:18:33,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1383 transitions. [2024-10-31 22:18:33,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:33,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:33,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:33,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:33,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:33,383 INFO L745 eck$LassoCheckResult]: Stem: 11504#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 11505#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12133#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 11623#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11624#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12129#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12125#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11695#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11696#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11930#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11931#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11779#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11780#L838 assume !(0 == ~M_E~0); 11938#L838-2 assume !(0 == ~T1_E~0); 11303#L843-1 assume !(0 == ~T2_E~0); 11304#L848-1 assume !(0 == ~T3_E~0); 11424#L853-1 assume !(0 == ~T4_E~0); 11766#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11254#L863-1 assume !(0 == ~T6_E~0); 11255#L868-1 assume !(0 == ~T7_E~0); 12161#L873-1 assume !(0 == ~T8_E~0); 12159#L878-1 assume !(0 == ~E_1~0); 12150#L883-1 assume !(0 == ~E_2~0); 12151#L888-1 assume !(0 == ~E_3~0); 11899#L893-1 assume !(0 == ~E_4~0); 11900#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12171#L903-1 assume !(0 == ~E_6~0); 12148#L908-1 assume !(0 == ~E_7~0); 12029#L913-1 assume !(0 == ~E_8~0); 11315#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11316#L402 assume !(1 == ~m_pc~0); 11527#L402-2 is_master_triggered_~__retres1~0#1 := 0; 11448#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11449#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11701#L1035 assume !(0 != activate_threads_~tmp~1#1); 11702#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11754#L421 assume 1 == ~t1_pc~0; 12144#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12162#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11318#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11319#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12169#L440 assume 1 == ~t2_pc~0; 11287#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11288#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11458#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11649#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 12044#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11652#L459 assume !(1 == ~t3_pc~0); 11653#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12142#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11276#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11277#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11443#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11452#L478 assume 1 == ~t4_pc~0; 11453#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11904#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11397#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 11357#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11358#L497 assume !(1 == ~t5_pc~0); 11407#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11408#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11975#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12081#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 12138#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12139#L516 assume 1 == ~t6_pc~0; 12185#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11929#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11632#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11498#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 11499#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11918#L535 assume !(1 == ~t7_pc~0); 11919#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11989#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11990#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12021#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 12011#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12012#L554 assume 1 == ~t8_pc~0; 11954#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11279#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12037#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11586#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 11587#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11265#L931 assume !(1 == ~M_E~0); 11266#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12157#L936-1 assume !(1 == ~T2_E~0); 12176#L941-1 assume !(1 == ~T3_E~0); 11755#L946-1 assume !(1 == ~T4_E~0); 11756#L951-1 assume !(1 == ~T5_E~0); 11513#L956-1 assume !(1 == ~T6_E~0); 11514#L961-1 assume !(1 == ~T7_E~0); 11901#L966-1 assume !(1 == ~T8_E~0); 11902#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12014#L976-1 assume !(1 == ~E_2~0); 11979#L981-1 assume !(1 == ~E_3~0); 11759#L986-1 assume !(1 == ~E_4~0); 11540#L991-1 assume !(1 == ~E_5~0); 11541#L996-1 assume !(1 == ~E_6~0); 12166#L1001-1 assume !(1 == ~E_7~0); 11949#L1006-1 assume !(1 == ~E_8~0); 11950#L1011-1 assume { :end_inline_reset_delta_events } true; 11326#L1272-2 [2024-10-31 22:18:33,383 INFO L747 eck$LassoCheckResult]: Loop: 11326#L1272-2 assume !false; 11327#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11563#L813-1 assume !false; 12099#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12100#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11329#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11668#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11669#L696 assume !(0 != eval_~tmp~0#1); 12042#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11809#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11810#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11998#L838-5 assume !(0 == ~T1_E~0); 11999#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11852#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11853#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11903#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11968#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11958#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11959#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11567#L878-3 assume !(0 == ~E_1~0); 11290#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11291#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11292#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11293#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11785#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12101#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11793#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11331#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11332#L402-27 assume 1 == ~m_pc~0; 11280#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11281#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11991#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11992#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12118#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12119#L421-27 assume !(1 == ~t1_pc~0); 11557#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 11558#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11877#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11878#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12167#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11921#L440-27 assume !(1 == ~t2_pc~0); 11922#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 12096#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11963#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11828#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 11829#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11543#L459-27 assume 1 == ~t3_pc~0; 11544#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11984#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11805#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11806#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11917#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12160#L478-27 assume 1 == ~t4_pc~0; 12179#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11533#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11716#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11717#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12066#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12102#L497-27 assume 1 == ~t5_pc~0; 12103#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11576#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11577#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11519#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11520#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11787#L516-27 assume !(1 == ~t6_pc~0); 11788#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 11640#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11641#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11940#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11941#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11720#L535-27 assume 1 == ~t7_pc~0; 11721#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12050#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11600#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11601#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11671#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11672#L554-27 assume 1 == ~t8_pc~0; 11874#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11306#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11457#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11837#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11564#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11565#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11439#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11440#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11670#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11804#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11580#L951-3 assume !(1 == ~T5_E~0); 11581#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11875#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11680#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11681#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11928#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11324#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11325#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11313#L991-3 assume !(1 == ~E_5~0); 11314#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12004#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11657#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11658#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11352#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11353#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11606#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11607#L1291 assume !(0 == start_simulation_~tmp~3#1); 11872#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11775#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11258#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11259#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11317#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11741#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11742#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 11827#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 11326#L1272-2 [2024-10-31 22:18:33,384 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:33,384 INFO L85 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2024-10-31 22:18:33,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:33,385 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801630788] [2024-10-31 22:18:33,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:33,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:33,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,431 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801630788] [2024-10-31 22:18:33,431 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801630788] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,431 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:33,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099286123] [2024-10-31 22:18:33,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,432 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:33,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:33,433 INFO L85 PathProgramCache]: Analyzing trace with hash -567599280, now seen corresponding path program 1 times [2024-10-31 22:18:33,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:33,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51179166] [2024-10-31 22:18:33,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:33,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:33,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51179166] [2024-10-31 22:18:33,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51179166] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,500 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,500 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:33,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785590979] [2024-10-31 22:18:33,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,500 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:33,501 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:33,501 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:33,501 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:33,502 INFO L87 Difference]: Start difference. First operand 933 states and 1383 transitions. cyclomatic complexity: 451 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:33,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:33,523 INFO L93 Difference]: Finished difference Result 933 states and 1382 transitions. [2024-10-31 22:18:33,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1382 transitions. [2024-10-31 22:18:33,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:33,536 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1382 transitions. [2024-10-31 22:18:33,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-31 22:18:33,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-31 22:18:33,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1382 transitions. [2024-10-31 22:18:33,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:33,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2024-10-31 22:18:33,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1382 transitions. [2024-10-31 22:18:33,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-31 22:18:33,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4812433011789925) internal successors, (1382), 932 states have internal predecessors, (1382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:33,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1382 transitions. [2024-10-31 22:18:33,562 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2024-10-31 22:18:33,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:33,564 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1382 transitions. [2024-10-31 22:18:33,565 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 22:18:33,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1382 transitions. [2024-10-31 22:18:33,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:33,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:33,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:33,573 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:33,573 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:33,573 INFO L745 eck$LassoCheckResult]: Stem: 13377#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14004#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14005#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14006#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 13496#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13497#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14002#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13998#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13568#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13569#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13803#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13804#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13652#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13653#L838 assume !(0 == ~M_E~0); 13812#L838-2 assume !(0 == ~T1_E~0); 13176#L843-1 assume !(0 == ~T2_E~0); 13177#L848-1 assume !(0 == ~T3_E~0); 13297#L853-1 assume !(0 == ~T4_E~0); 13641#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13129#L863-1 assume !(0 == ~T6_E~0); 13130#L868-1 assume !(0 == ~T7_E~0); 14034#L873-1 assume !(0 == ~T8_E~0); 14032#L878-1 assume !(0 == ~E_1~0); 14023#L883-1 assume !(0 == ~E_2~0); 14024#L888-1 assume !(0 == ~E_3~0); 13775#L893-1 assume !(0 == ~E_4~0); 13776#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 14044#L903-1 assume !(0 == ~E_6~0); 14021#L908-1 assume !(0 == ~E_7~0); 13903#L913-1 assume !(0 == ~E_8~0); 13189#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13190#L402 assume !(1 == ~m_pc~0); 13404#L402-2 is_master_triggered_~__retres1~0#1 := 0; 13321#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13322#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13574#L1035 assume !(0 != activate_threads_~tmp~1#1); 13575#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13629#L421 assume 1 == ~t1_pc~0; 14017#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14038#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13191#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13192#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 13683#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14042#L440 assume 1 == ~t2_pc~0; 13160#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13161#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13522#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 13917#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13529#L459 assume !(1 == ~t3_pc~0); 13530#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14015#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13149#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13150#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13316#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13325#L478 assume 1 == ~t4_pc~0; 13326#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13777#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13270#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 13232#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13233#L497 assume !(1 == ~t5_pc~0); 13280#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13281#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13954#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 14011#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14012#L516 assume 1 == ~t6_pc~0; 14058#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13802#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13505#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13371#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 13372#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13791#L535 assume !(1 == ~t7_pc~0); 13792#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13862#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13863#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13894#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 13885#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13886#L554 assume 1 == ~t8_pc~0; 13827#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13152#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13911#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13462#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 13463#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13138#L931 assume !(1 == ~M_E~0); 13139#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14030#L936-1 assume !(1 == ~T2_E~0); 14049#L941-1 assume !(1 == ~T3_E~0); 13627#L946-1 assume !(1 == ~T4_E~0); 13628#L951-1 assume !(1 == ~T5_E~0); 13386#L956-1 assume !(1 == ~T6_E~0); 13387#L961-1 assume !(1 == ~T7_E~0); 13772#L966-1 assume !(1 == ~T8_E~0); 13773#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13887#L976-1 assume !(1 == ~E_2~0); 13852#L981-1 assume !(1 == ~E_3~0); 13632#L986-1 assume !(1 == ~E_4~0); 13413#L991-1 assume !(1 == ~E_5~0); 13414#L996-1 assume !(1 == ~E_6~0); 14039#L1001-1 assume !(1 == ~E_7~0); 13822#L1006-1 assume !(1 == ~E_8~0); 13823#L1011-1 assume { :end_inline_reset_delta_events } true; 13199#L1272-2 [2024-10-31 22:18:33,574 INFO L747 eck$LassoCheckResult]: Loop: 13199#L1272-2 assume !false; 13200#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13436#L813-1 assume !false; 13972#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13973#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13202#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13541#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13542#L696 assume !(0 != eval_~tmp~0#1); 13915#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13682#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13871#L838-5 assume !(0 == ~T1_E~0); 13872#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13725#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13726#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13774#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13841#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13832#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13440#L878-3 assume !(0 == ~E_1~0); 13163#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13164#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13165#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13166#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13658#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13974#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13666#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13204#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13205#L402-27 assume 1 == ~m_pc~0; 13153#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13154#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13864#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13865#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13991#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13992#L421-27 assume !(1 == ~t1_pc~0); 13430#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 13431#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13750#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13751#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14040#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13794#L440-27 assume !(1 == ~t2_pc~0); 13795#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 13968#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13836#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13701#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 13702#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13416#L459-27 assume 1 == ~t3_pc~0; 13417#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13857#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13678#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13679#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13790#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14033#L478-27 assume 1 == ~t4_pc~0; 14052#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13406#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13589#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13590#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13939#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13975#L497-27 assume 1 == ~t5_pc~0; 13976#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13449#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13450#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13392#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13393#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13660#L516-27 assume !(1 == ~t6_pc~0); 13661#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 13513#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13514#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13813#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13814#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13593#L535-27 assume 1 == ~t7_pc~0; 13594#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13923#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13473#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13474#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13544#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13545#L554-27 assume 1 == ~t8_pc~0; 13747#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13179#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13330#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13710#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13437#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13438#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13312#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13313#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13543#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13677#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13453#L951-3 assume !(1 == ~T5_E~0); 13454#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13748#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13553#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13554#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13801#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13197#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13198#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13186#L991-3 assume !(1 == ~E_5~0); 13187#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13877#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13527#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13528#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13225#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13226#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13479#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 13480#L1291 assume !(0 == start_simulation_~tmp~3#1); 13745#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13648#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13131#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13188#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13614#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13615#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 13700#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 13199#L1272-2 [2024-10-31 22:18:33,575 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:33,575 INFO L85 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2024-10-31 22:18:33,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:33,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400524315] [2024-10-31 22:18:33,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:33,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:33,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,677 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400524315] [2024-10-31 22:18:33,677 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400524315] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:33,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1617379580] [2024-10-31 22:18:33,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,679 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:33,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:33,679 INFO L85 PathProgramCache]: Analyzing trace with hash -567599280, now seen corresponding path program 2 times [2024-10-31 22:18:33,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:33,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496077651] [2024-10-31 22:18:33,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:33,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:33,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [496077651] [2024-10-31 22:18:33,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [496077651] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,742 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,742 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:33,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627914400] [2024-10-31 22:18:33,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,743 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:33,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:33,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:33,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:33,744 INFO L87 Difference]: Start difference. First operand 933 states and 1382 transitions. cyclomatic complexity: 450 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:33,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:33,767 INFO L93 Difference]: Finished difference Result 933 states and 1381 transitions. [2024-10-31 22:18:33,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1381 transitions. [2024-10-31 22:18:33,773 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:33,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1381 transitions. [2024-10-31 22:18:33,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-31 22:18:33,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-31 22:18:33,780 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1381 transitions. [2024-10-31 22:18:33,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:33,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2024-10-31 22:18:33,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1381 transitions. [2024-10-31 22:18:33,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-31 22:18:33,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.480171489817792) internal successors, (1381), 932 states have internal predecessors, (1381), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:33,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1381 transitions. [2024-10-31 22:18:33,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2024-10-31 22:18:33,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:33,800 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1381 transitions. [2024-10-31 22:18:33,801 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 22:18:33,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1381 transitions. [2024-10-31 22:18:33,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:33,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:33,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:33,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:33,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:33,810 INFO L745 eck$LassoCheckResult]: Stem: 15250#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 15251#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15879#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 15369#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15370#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15875#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15871#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15441#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15442#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15676#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15677#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15525#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15526#L838 assume !(0 == ~M_E~0); 15685#L838-2 assume !(0 == ~T1_E~0); 15049#L843-1 assume !(0 == ~T2_E~0); 15050#L848-1 assume !(0 == ~T3_E~0); 15170#L853-1 assume !(0 == ~T4_E~0); 15514#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15002#L863-1 assume !(0 == ~T6_E~0); 15003#L868-1 assume !(0 == ~T7_E~0); 15907#L873-1 assume !(0 == ~T8_E~0); 15905#L878-1 assume !(0 == ~E_1~0); 15896#L883-1 assume !(0 == ~E_2~0); 15897#L888-1 assume !(0 == ~E_3~0); 15645#L893-1 assume !(0 == ~E_4~0); 15646#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 15917#L903-1 assume !(0 == ~E_6~0); 15894#L908-1 assume !(0 == ~E_7~0); 15776#L913-1 assume !(0 == ~E_8~0); 15062#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15063#L402 assume !(1 == ~m_pc~0); 15277#L402-2 is_master_triggered_~__retres1~0#1 := 0; 15194#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15195#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15447#L1035 assume !(0 != activate_threads_~tmp~1#1); 15448#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15500#L421 assume 1 == ~t1_pc~0; 15890#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15911#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15064#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15065#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 15554#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15915#L440 assume 1 == ~t2_pc~0; 15033#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15034#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15204#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15395#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 15790#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15402#L459 assume !(1 == ~t3_pc~0); 15403#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15888#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15023#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15189#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15198#L478 assume 1 == ~t4_pc~0; 15199#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15650#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15142#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15143#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 15105#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15106#L497 assume !(1 == ~t5_pc~0); 15153#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15154#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15721#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15827#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 15884#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15885#L516 assume 1 == ~t6_pc~0; 15931#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15675#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15378#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15244#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 15245#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15664#L535 assume !(1 == ~t7_pc~0); 15665#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15735#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15736#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15767#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 15758#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15759#L554 assume 1 == ~t8_pc~0; 15700#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15025#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15783#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15335#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 15336#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15011#L931 assume !(1 == ~M_E~0); 15012#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15903#L936-1 assume !(1 == ~T2_E~0); 15922#L941-1 assume !(1 == ~T3_E~0); 15501#L946-1 assume !(1 == ~T4_E~0); 15502#L951-1 assume !(1 == ~T5_E~0); 15259#L956-1 assume !(1 == ~T6_E~0); 15260#L961-1 assume !(1 == ~T7_E~0); 15647#L966-1 assume !(1 == ~T8_E~0); 15648#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15761#L976-1 assume !(1 == ~E_2~0); 15725#L981-1 assume !(1 == ~E_3~0); 15505#L986-1 assume !(1 == ~E_4~0); 15286#L991-1 assume !(1 == ~E_5~0); 15287#L996-1 assume !(1 == ~E_6~0); 15912#L1001-1 assume !(1 == ~E_7~0); 15695#L1006-1 assume !(1 == ~E_8~0); 15696#L1011-1 assume { :end_inline_reset_delta_events } true; 15072#L1272-2 [2024-10-31 22:18:33,811 INFO L747 eck$LassoCheckResult]: Loop: 15072#L1272-2 assume !false; 15073#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15311#L813-1 assume !false; 15845#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15846#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15075#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15414#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15415#L696 assume !(0 != eval_~tmp~0#1); 15788#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15556#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15744#L838-5 assume !(0 == ~T1_E~0); 15745#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15599#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15600#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15649#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15714#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15705#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15706#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15315#L878-3 assume !(0 == ~E_1~0); 15038#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15039#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15036#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15037#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15531#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15847#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15539#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15077#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15078#L402-27 assume 1 == ~m_pc~0; 15026#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15027#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15737#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15738#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15864#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15865#L421-27 assume !(1 == ~t1_pc~0); 15303#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 15304#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15623#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15624#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15913#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15667#L440-27 assume !(1 == ~t2_pc~0); 15668#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15841#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15709#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15574#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 15575#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15289#L459-27 assume 1 == ~t3_pc~0; 15290#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15730#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15552#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15663#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15906#L478-27 assume 1 == ~t4_pc~0; 15925#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15279#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15462#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15463#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15812#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15848#L497-27 assume !(1 == ~t5_pc~0); 15456#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15322#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15323#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15265#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15266#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15532#L516-27 assume !(1 == ~t6_pc~0); 15533#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 15383#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15384#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15686#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15687#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15466#L535-27 assume 1 == ~t7_pc~0; 15467#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15796#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15346#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15347#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15417#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15418#L554-27 assume 1 == ~t8_pc~0; 15620#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15052#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15203#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15580#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15308#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15309#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15185#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15186#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15416#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15550#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15326#L951-3 assume !(1 == ~T5_E~0); 15327#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15621#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15426#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15427#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15674#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15070#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15071#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15059#L991-3 assume !(1 == ~E_5~0); 15060#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15750#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15400#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15401#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15098#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15099#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15349#L1291 assume !(0 == start_simulation_~tmp~3#1); 15618#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15521#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15004#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15005#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15061#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15487#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15488#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15573#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 15072#L1272-2 [2024-10-31 22:18:33,812 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:33,812 INFO L85 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2024-10-31 22:18:33,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:33,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738226981] [2024-10-31 22:18:33,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:33,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:33,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738226981] [2024-10-31 22:18:33,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738226981] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:33,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799040485] [2024-10-31 22:18:33,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,887 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:33,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:33,888 INFO L85 PathProgramCache]: Analyzing trace with hash -464798033, now seen corresponding path program 1 times [2024-10-31 22:18:33,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:33,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625885252] [2024-10-31 22:18:33,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:33,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:33,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:33,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:33,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:33,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625885252] [2024-10-31 22:18:33,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625885252] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:33,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:33,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:33,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011199869] [2024-10-31 22:18:33,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:33,948 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:33,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:33,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:33,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:33,949 INFO L87 Difference]: Start difference. First operand 933 states and 1381 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:33,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:33,986 INFO L93 Difference]: Finished difference Result 933 states and 1376 transitions. [2024-10-31 22:18:33,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1376 transitions. [2024-10-31 22:18:34,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:34,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1376 transitions. [2024-10-31 22:18:34,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-10-31 22:18:34,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-10-31 22:18:34,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1376 transitions. [2024-10-31 22:18:34,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:34,014 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2024-10-31 22:18:34,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1376 transitions. [2024-10-31 22:18:34,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-10-31 22:18:34,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.47481243301179) internal successors, (1376), 932 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:34,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1376 transitions. [2024-10-31 22:18:34,033 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2024-10-31 22:18:34,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:34,035 INFO L425 stractBuchiCegarLoop]: Abstraction has 933 states and 1376 transitions. [2024-10-31 22:18:34,036 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 22:18:34,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1376 transitions. [2024-10-31 22:18:34,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-10-31 22:18:34,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:34,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:34,043 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:34,043 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:34,044 INFO L745 eck$LassoCheckResult]: Stem: 17123#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 17124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17750#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17751#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17752#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 17242#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17243#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17748#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17744#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17314#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17315#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17549#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17550#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 17398#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17399#L838 assume !(0 == ~M_E~0); 17558#L838-2 assume !(0 == ~T1_E~0); 16922#L843-1 assume !(0 == ~T2_E~0); 16923#L848-1 assume !(0 == ~T3_E~0); 17043#L853-1 assume !(0 == ~T4_E~0); 17387#L858-1 assume !(0 == ~T5_E~0); 16873#L863-1 assume !(0 == ~T6_E~0); 16874#L868-1 assume !(0 == ~T7_E~0); 17780#L873-1 assume !(0 == ~T8_E~0); 17778#L878-1 assume !(0 == ~E_1~0); 17769#L883-1 assume !(0 == ~E_2~0); 17770#L888-1 assume !(0 == ~E_3~0); 17518#L893-1 assume !(0 == ~E_4~0); 17519#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17790#L903-1 assume !(0 == ~E_6~0); 17767#L908-1 assume !(0 == ~E_7~0); 17648#L913-1 assume !(0 == ~E_8~0); 16935#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16936#L402 assume !(1 == ~m_pc~0); 17148#L402-2 is_master_triggered_~__retres1~0#1 := 0; 17067#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17068#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17320#L1035 assume !(0 != activate_threads_~tmp~1#1); 17321#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17373#L421 assume 1 == ~t1_pc~0; 17763#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17784#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16937#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16938#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 17427#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17788#L440 assume 1 == ~t2_pc~0; 16906#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16907#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17268#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 17663#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17275#L459 assume !(1 == ~t3_pc~0); 17276#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17761#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16895#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16896#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17062#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17071#L478 assume 1 == ~t4_pc~0; 17072#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17523#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17015#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17016#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 16978#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16979#L497 assume !(1 == ~t5_pc~0); 17026#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17027#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17594#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17700#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 17757#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17758#L516 assume 1 == ~t6_pc~0; 17804#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17548#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17251#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17117#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 17118#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17537#L535 assume !(1 == ~t7_pc~0); 17538#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17608#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17609#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17640#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 17630#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17631#L554 assume 1 == ~t8_pc~0; 17573#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16898#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17656#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17208#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 17209#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16884#L931 assume !(1 == ~M_E~0); 16885#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17776#L936-1 assume !(1 == ~T2_E~0); 17795#L941-1 assume !(1 == ~T3_E~0); 17374#L946-1 assume !(1 == ~T4_E~0); 17375#L951-1 assume !(1 == ~T5_E~0); 17132#L956-1 assume !(1 == ~T6_E~0); 17133#L961-1 assume !(1 == ~T7_E~0); 17520#L966-1 assume !(1 == ~T8_E~0); 17521#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17633#L976-1 assume !(1 == ~E_2~0); 17598#L981-1 assume !(1 == ~E_3~0); 17378#L986-1 assume !(1 == ~E_4~0); 17159#L991-1 assume !(1 == ~E_5~0); 17160#L996-1 assume !(1 == ~E_6~0); 17785#L1001-1 assume !(1 == ~E_7~0); 17568#L1006-1 assume !(1 == ~E_8~0); 17569#L1011-1 assume { :end_inline_reset_delta_events } true; 16945#L1272-2 [2024-10-31 22:18:34,044 INFO L747 eck$LassoCheckResult]: Loop: 16945#L1272-2 assume !false; 16946#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17184#L813-1 assume !false; 17718#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17719#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16948#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17287#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17288#L696 assume !(0 != eval_~tmp~0#1); 17661#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17429#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17617#L838-5 assume !(0 == ~T1_E~0); 17618#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17471#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17472#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17522#L858-3 assume !(0 == ~T5_E~0); 17587#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17578#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17579#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17188#L878-3 assume !(0 == ~E_1~0); 16909#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16910#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16911#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16912#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17404#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17722#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17412#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16950#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16951#L402-27 assume 1 == ~m_pc~0; 16899#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16900#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17610#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17611#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17737#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17738#L421-27 assume !(1 == ~t1_pc~0); 17176#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 17177#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17496#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17497#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17786#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17540#L440-27 assume !(1 == ~t2_pc~0); 17541#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 17714#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17582#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17447#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 17448#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17162#L459-27 assume 1 == ~t3_pc~0; 17163#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17603#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17424#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17425#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17536#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17779#L478-27 assume 1 == ~t4_pc~0; 17798#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17335#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17336#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17685#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17720#L497-27 assume 1 == ~t5_pc~0; 17721#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17195#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17196#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17138#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17139#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17405#L516-27 assume !(1 == ~t6_pc~0); 17406#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 17252#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17253#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17559#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17560#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17339#L535-27 assume 1 == ~t7_pc~0; 17340#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17667#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17219#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17220#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17290#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17291#L554-27 assume 1 == ~t8_pc~0; 17493#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16925#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17076#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17453#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17181#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17182#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17058#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17059#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17289#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17423#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17199#L951-3 assume !(1 == ~T5_E~0); 17200#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17494#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17299#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17300#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17547#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16943#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16944#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16932#L991-3 assume !(1 == ~E_5~0); 16933#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17623#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17273#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17274#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16971#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16972#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17221#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 17222#L1291 assume !(0 == start_simulation_~tmp~3#1); 17491#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17392#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16877#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 16934#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17359#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17360#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 17446#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 16945#L1272-2 [2024-10-31 22:18:34,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:34,045 INFO L85 PathProgramCache]: Analyzing trace with hash 623392352, now seen corresponding path program 1 times [2024-10-31 22:18:34,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:34,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610489035] [2024-10-31 22:18:34,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:34,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:34,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:34,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:34,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:34,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610489035] [2024-10-31 22:18:34,151 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610489035] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:34,151 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:34,151 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:34,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045903208] [2024-10-31 22:18:34,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:34,152 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:34,153 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:34,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1033471826, now seen corresponding path program 1 times [2024-10-31 22:18:34,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:34,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107692339] [2024-10-31 22:18:34,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:34,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:34,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:34,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:34,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:34,213 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107692339] [2024-10-31 22:18:34,213 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107692339] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:34,213 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:34,213 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:34,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201447921] [2024-10-31 22:18:34,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:34,214 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:34,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:34,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:34,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:34,215 INFO L87 Difference]: Start difference. First operand 933 states and 1376 transitions. cyclomatic complexity: 444 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:34,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:34,486 INFO L93 Difference]: Finished difference Result 1704 states and 2511 transitions. [2024-10-31 22:18:34,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1704 states and 2511 transitions. [2024-10-31 22:18:34,499 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2024-10-31 22:18:34,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1704 states to 1704 states and 2511 transitions. [2024-10-31 22:18:34,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1704 [2024-10-31 22:18:34,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1704 [2024-10-31 22:18:34,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1704 states and 2511 transitions. [2024-10-31 22:18:34,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:34,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1704 states and 2511 transitions. [2024-10-31 22:18:34,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1704 states and 2511 transitions. [2024-10-31 22:18:34,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1704 to 1703. [2024-10-31 22:18:34,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1703 states, 1703 states have (on average 1.473869641808573) internal successors, (2510), 1702 states have internal predecessors, (2510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:34,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1703 states to 1703 states and 2510 transitions. [2024-10-31 22:18:34,545 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2024-10-31 22:18:34,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:34,546 INFO L425 stractBuchiCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2024-10-31 22:18:34,546 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 22:18:34,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1703 states and 2510 transitions. [2024-10-31 22:18:34,554 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2024-10-31 22:18:34,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:34,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:34,556 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:34,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:34,556 INFO L745 eck$LassoCheckResult]: Stem: 19770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 19771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20417#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20418#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20419#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 19889#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19890#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20415#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20409#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19963#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19964#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20207#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20208#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 20048#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20049#L838 assume !(0 == ~M_E~0); 20215#L838-2 assume !(0 == ~T1_E~0); 19569#L843-1 assume !(0 == ~T2_E~0); 19570#L848-1 assume !(0 == ~T3_E~0); 19690#L853-1 assume !(0 == ~T4_E~0); 20035#L858-1 assume !(0 == ~T5_E~0); 19520#L863-1 assume !(0 == ~T6_E~0); 19521#L868-1 assume !(0 == ~T7_E~0); 20452#L873-1 assume !(0 == ~T8_E~0); 20450#L878-1 assume !(0 == ~E_1~0); 20438#L883-1 assume !(0 == ~E_2~0); 20439#L888-1 assume !(0 == ~E_3~0); 20175#L893-1 assume !(0 == ~E_4~0); 20176#L898-1 assume !(0 == ~E_5~0); 20464#L903-1 assume !(0 == ~E_6~0); 20436#L908-1 assume !(0 == ~E_7~0); 20306#L913-1 assume !(0 == ~E_8~0); 19581#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19582#L402 assume !(1 == ~m_pc~0); 19793#L402-2 is_master_triggered_~__retres1~0#1 := 0; 19714#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19715#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19969#L1035 assume !(0 != activate_threads_~tmp~1#1); 19970#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20023#L421 assume 1 == ~t1_pc~0; 20432#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20453#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19584#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19585#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 20079#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20462#L440 assume 1 == ~t2_pc~0; 19553#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19554#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19915#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 20325#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19918#L459 assume !(1 == ~t3_pc~0); 19919#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20428#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19542#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19543#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19709#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19718#L478 assume 1 == ~t4_pc~0; 19719#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20180#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19662#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19663#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 19623#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19624#L497 assume !(1 == ~t5_pc~0); 19673#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19674#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20252#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20363#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 20424#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20425#L516 assume 1 == ~t6_pc~0; 20486#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20206#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19898#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19764#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 19765#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20195#L535 assume !(1 == ~t7_pc~0); 20196#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20266#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20298#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 20288#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20289#L554 assume 1 == ~t8_pc~0; 20231#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19545#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19852#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 19853#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19531#L931 assume !(1 == ~M_E~0); 19532#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20447#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20473#L941-1 assume !(1 == ~T3_E~0); 20024#L946-1 assume !(1 == ~T4_E~0); 20025#L951-1 assume !(1 == ~T5_E~0); 19779#L956-1 assume !(1 == ~T6_E~0); 19780#L961-1 assume !(1 == ~T7_E~0); 20177#L966-1 assume !(1 == ~T8_E~0); 20178#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20291#L976-1 assume !(1 == ~E_2~0); 20256#L981-1 assume !(1 == ~E_3~0); 20028#L986-1 assume !(1 == ~E_4~0); 19806#L991-1 assume !(1 == ~E_5~0); 19807#L996-1 assume !(1 == ~E_6~0); 20457#L1001-1 assume !(1 == ~E_7~0); 20226#L1006-1 assume !(1 == ~E_8~0); 20227#L1011-1 assume { :end_inline_reset_delta_events } true; 20505#L1272-2 [2024-10-31 22:18:34,557 INFO L747 eck$LassoCheckResult]: Loop: 20505#L1272-2 assume !false; 20501#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20476#L813-1 assume !false; 20477#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20499#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20172#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19934#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19935#L696 assume !(0 != eval_~tmp~0#1); 20322#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20323#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20412#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20413#L838-5 assume !(0 == ~T1_E~0); 20489#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20123#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20124#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20179#L858-3 assume !(0 == ~T5_E~0); 20245#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20235#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20236#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19833#L878-3 assume !(0 == ~E_1~0); 19556#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19557#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19558#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19559#L898-3 assume !(0 == ~E_5~0); 20054#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20383#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20063#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19597#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19598#L402-27 assume 1 == ~m_pc~0; 19546#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19547#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20268#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20269#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20402#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20403#L421-27 assume 1 == ~t1_pc~0; 20304#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19824#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20151#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20152#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20458#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20198#L440-27 assume !(1 == ~t2_pc~0); 20199#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 20378#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20240#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20099#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 20100#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19809#L459-27 assume 1 == ~t3_pc~0; 19810#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20261#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20075#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20076#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20194#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20451#L478-27 assume !(1 == ~t4_pc~0); 19798#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 19799#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19984#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19985#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20347#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20384#L497-27 assume 1 == ~t5_pc~0; 20385#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19842#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19843#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19785#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19786#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20056#L516-27 assume !(1 == ~t6_pc~0); 20057#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 19906#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19907#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20217#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20218#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19988#L535-27 assume 1 == ~t7_pc~0; 19989#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20331#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19866#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19867#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19938#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19939#L554-27 assume !(1 == ~t8_pc~0); 19571#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 19572#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19723#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20108#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19830#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19831#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19705#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19706#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19937#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20074#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19846#L951-3 assume !(1 == ~T5_E~0); 19847#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20149#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19948#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19949#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20205#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19590#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19591#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19579#L991-3 assume !(1 == ~E_5~0); 19580#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20281#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19923#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19924#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19618#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19619#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20078#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 20537#L1291 assume !(0 == start_simulation_~tmp~3#1); 20535#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20534#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20524#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20523#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 20442#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20009#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20010#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20098#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 20505#L1272-2 [2024-10-31 22:18:34,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:34,558 INFO L85 PathProgramCache]: Analyzing trace with hash 1671526308, now seen corresponding path program 1 times [2024-10-31 22:18:34,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:34,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531906401] [2024-10-31 22:18:34,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:34,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:34,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:34,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:34,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:34,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [531906401] [2024-10-31 22:18:34,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [531906401] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:34,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:34,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:34,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1833727468] [2024-10-31 22:18:34,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:34,611 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:34,611 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:34,612 INFO L85 PathProgramCache]: Analyzing trace with hash -2131409869, now seen corresponding path program 1 times [2024-10-31 22:18:34,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:34,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551323000] [2024-10-31 22:18:34,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:34,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:34,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:34,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:34,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:34,666 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [551323000] [2024-10-31 22:18:34,666 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [551323000] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:34,666 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:34,666 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:34,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873063482] [2024-10-31 22:18:34,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:34,667 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:34,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:34,667 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:34,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:34,668 INFO L87 Difference]: Start difference. First operand 1703 states and 2510 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:34,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:34,785 INFO L93 Difference]: Finished difference Result 3128 states and 4579 transitions. [2024-10-31 22:18:34,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3128 states and 4579 transitions. [2024-10-31 22:18:34,806 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2997 [2024-10-31 22:18:34,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3128 states to 3128 states and 4579 transitions. [2024-10-31 22:18:34,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3128 [2024-10-31 22:18:34,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3128 [2024-10-31 22:18:34,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3128 states and 4579 transitions. [2024-10-31 22:18:34,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:34,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3128 states and 4579 transitions. [2024-10-31 22:18:34,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3128 states and 4579 transitions. [2024-10-31 22:18:34,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3128 to 3124. [2024-10-31 22:18:34,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3124 states, 3124 states have (on average 1.4644686299615877) internal successors, (4575), 3123 states have internal predecessors, (4575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:34,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3124 states to 3124 states and 4575 transitions. [2024-10-31 22:18:34,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3124 states and 4575 transitions. [2024-10-31 22:18:34,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:34,906 INFO L425 stractBuchiCegarLoop]: Abstraction has 3124 states and 4575 transitions. [2024-10-31 22:18:34,906 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 22:18:34,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3124 states and 4575 transitions. [2024-10-31 22:18:34,922 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2993 [2024-10-31 22:18:34,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:34,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:34,924 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:34,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:34,925 INFO L745 eck$LassoCheckResult]: Stem: 24613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 24614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25349#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25350#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25351#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 24735#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24736#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25341#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25335#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24819#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24820#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25079#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25080#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24911#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24912#L838 assume !(0 == ~M_E~0); 25087#L838-2 assume !(0 == ~T1_E~0); 24407#L843-1 assume !(0 == ~T2_E~0); 24408#L848-1 assume !(0 == ~T3_E~0); 24530#L853-1 assume !(0 == ~T4_E~0); 24898#L858-1 assume !(0 == ~T5_E~0); 24358#L863-1 assume !(0 == ~T6_E~0); 24359#L868-1 assume !(0 == ~T7_E~0); 25407#L873-1 assume !(0 == ~T8_E~0); 25404#L878-1 assume !(0 == ~E_1~0); 25379#L883-1 assume !(0 == ~E_2~0); 25380#L888-1 assume !(0 == ~E_3~0); 25047#L893-1 assume !(0 == ~E_4~0); 25048#L898-1 assume !(0 == ~E_5~0); 25422#L903-1 assume !(0 == ~E_6~0); 25375#L908-1 assume !(0 == ~E_7~0); 25197#L913-1 assume !(0 == ~E_8~0); 24420#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24421#L402 assume !(1 == ~m_pc~0); 24636#L402-2 is_master_triggered_~__retres1~0#1 := 0; 24554#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24555#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24826#L1035 assume !(0 != activate_threads_~tmp~1#1); 24827#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24885#L421 assume !(1 == ~t1_pc~0); 25371#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25408#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24424#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24425#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 24941#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25419#L440 assume 1 == ~t2_pc~0; 24391#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24392#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24564#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24762#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 25215#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24765#L459 assume !(1 == ~t3_pc~0); 24766#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25362#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24380#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24381#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24549#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24558#L478 assume 1 == ~t4_pc~0; 24559#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25052#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24502#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24503#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 24462#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24463#L497 assume !(1 == ~t5_pc~0); 24513#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24514#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25131#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25265#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 25357#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25358#L516 assume 1 == ~t6_pc~0; 25454#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25078#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24745#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24607#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 24608#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25067#L535 assume !(1 == ~t7_pc~0); 25068#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25146#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25147#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25186#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 25174#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25175#L554 assume 1 == ~t8_pc~0; 25105#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24383#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25207#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24695#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 24696#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24369#L931 assume !(1 == ~M_E~0); 24370#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25397#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25430#L941-1 assume !(1 == ~T3_E~0); 24886#L946-1 assume !(1 == ~T4_E~0); 24887#L951-1 assume !(1 == ~T5_E~0); 24622#L956-1 assume !(1 == ~T6_E~0); 24623#L961-1 assume !(1 == ~T7_E~0); 25049#L966-1 assume !(1 == ~T8_E~0); 25050#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 25178#L976-1 assume !(1 == ~E_2~0); 25135#L981-1 assume !(1 == ~E_3~0); 25136#L986-1 assume !(1 == ~E_4~0); 24649#L991-1 assume !(1 == ~E_5~0); 24650#L996-1 assume !(1 == ~E_6~0); 25412#L1001-1 assume !(1 == ~E_7~0); 25413#L1006-1 assume !(1 == ~E_8~0); 25369#L1011-1 assume { :end_inline_reset_delta_events } true; 25243#L1272-2 [2024-10-31 22:18:34,925 INFO L747 eck$LassoCheckResult]: Loop: 25243#L1272-2 assume !false; 25093#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24670#L813-1 assume !false; 25433#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26690#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25044#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24783#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24784#L696 assume !(0 != eval_~tmp~0#1); 26680#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26679#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26678#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26677#L838-5 assume !(0 == ~T1_E~0); 26674#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26675#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27404#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27403#L858-3 assume !(0 == ~T5_E~0); 27402#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27401#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27400#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27399#L878-3 assume !(0 == ~E_1~0); 27398#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27397#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27396#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27395#L898-3 assume !(0 == ~E_5~0); 27394#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27393#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27392#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27391#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27390#L402-27 assume 1 == ~m_pc~0; 27388#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27387#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27386#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27385#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27384#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27383#L421-27 assume !(1 == ~t1_pc~0); 27382#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 27381#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27380#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27379#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27378#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27377#L440-27 assume !(1 == ~t2_pc~0); 27376#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 27374#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27373#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27372#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 27371#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27370#L459-27 assume 1 == ~t3_pc~0; 27368#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27367#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27366#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27365#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27364#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27363#L478-27 assume 1 == ~t4_pc~0; 27361#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27360#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27359#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27358#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27357#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27356#L497-27 assume 1 == ~t5_pc~0; 27354#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27353#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27352#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27351#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27350#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27349#L516-27 assume !(1 == ~t6_pc~0); 27347#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 27346#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27345#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27344#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27343#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27342#L535-27 assume 1 == ~t7_pc~0; 27340#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27339#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27338#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27337#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27336#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27335#L554-27 assume !(1 == ~t8_pc~0); 27333#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 27332#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27331#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27330#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27329#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27328#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27327#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27326#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24787#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27325#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27324#L951-3 assume !(1 == ~T5_E~0); 27323#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27322#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27321#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27320#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27319#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27318#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27317#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27316#L991-3 assume !(1 == ~E_5~0); 26009#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27315#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27314#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27313#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 27311#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 27303#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 27302#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 27300#L1291 assume !(0 == start_simulation_~tmp~3#1); 27298#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24907#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 24482#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24422#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 24423#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24867#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24868#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25242#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 25243#L1272-2 [2024-10-31 22:18:34,926 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:34,926 INFO L85 PathProgramCache]: Analyzing trace with hash 493551747, now seen corresponding path program 1 times [2024-10-31 22:18:34,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:34,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389797578] [2024-10-31 22:18:34,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:34,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:34,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:34,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:34,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:34,988 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389797578] [2024-10-31 22:18:34,988 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1389797578] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:34,989 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:34,989 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:34,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786131951] [2024-10-31 22:18:34,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:34,989 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:34,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:34,990 INFO L85 PathProgramCache]: Analyzing trace with hash -1502078349, now seen corresponding path program 1 times [2024-10-31 22:18:34,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:34,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336551094] [2024-10-31 22:18:34,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:34,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:35,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:35,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:35,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:35,039 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336551094] [2024-10-31 22:18:35,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1336551094] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:35,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:35,040 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:35,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719063128] [2024-10-31 22:18:35,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:35,040 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:35,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:35,041 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:35,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:35,041 INFO L87 Difference]: Start difference. First operand 3124 states and 4575 transitions. cyclomatic complexity: 1455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:35,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:35,245 INFO L93 Difference]: Finished difference Result 5826 states and 8485 transitions. [2024-10-31 22:18:35,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5826 states and 8485 transitions. [2024-10-31 22:18:35,291 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5684 [2024-10-31 22:18:35,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5826 states to 5826 states and 8485 transitions. [2024-10-31 22:18:35,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5826 [2024-10-31 22:18:35,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5826 [2024-10-31 22:18:35,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5826 states and 8485 transitions. [2024-10-31 22:18:35,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:35,354 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5826 states and 8485 transitions. [2024-10-31 22:18:35,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5826 states and 8485 transitions. [2024-10-31 22:18:35,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5826 to 5818. [2024-10-31 22:18:35,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5818 states, 5818 states have (on average 1.4570299071845996) internal successors, (8477), 5817 states have internal predecessors, (8477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:35,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5818 states to 5818 states and 8477 transitions. [2024-10-31 22:18:35,506 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5818 states and 8477 transitions. [2024-10-31 22:18:35,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:35,508 INFO L425 stractBuchiCegarLoop]: Abstraction has 5818 states and 8477 transitions. [2024-10-31 22:18:35,508 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 22:18:35,508 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5818 states and 8477 transitions. [2024-10-31 22:18:35,542 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5676 [2024-10-31 22:18:35,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:35,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:35,544 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:35,545 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:35,545 INFO L745 eck$LassoCheckResult]: Stem: 33564#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 33565#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 34233#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34234#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34235#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 33682#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33683#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34231#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34225#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33758#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33759#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33999#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34000#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33843#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33844#L838 assume !(0 == ~M_E~0); 34007#L838-2 assume !(0 == ~T1_E~0); 33363#L843-1 assume !(0 == ~T2_E~0); 33364#L848-1 assume !(0 == ~T3_E~0); 33482#L853-1 assume !(0 == ~T4_E~0); 33830#L858-1 assume !(0 == ~T5_E~0); 33315#L863-1 assume !(0 == ~T6_E~0); 33316#L868-1 assume !(0 == ~T7_E~0); 34277#L873-1 assume !(0 == ~T8_E~0); 34274#L878-1 assume !(0 == ~E_1~0); 34256#L883-1 assume !(0 == ~E_2~0); 34257#L888-1 assume !(0 == ~E_3~0); 33968#L893-1 assume !(0 == ~E_4~0); 33969#L898-1 assume !(0 == ~E_5~0); 34293#L903-1 assume !(0 == ~E_6~0); 34254#L908-1 assume !(0 == ~E_7~0); 34109#L913-1 assume !(0 == ~E_8~0); 33375#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33376#L402 assume !(1 == ~m_pc~0); 33589#L402-2 is_master_triggered_~__retres1~0#1 := 0; 33507#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33508#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33764#L1035 assume !(0 != activate_threads_~tmp~1#1); 33765#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33818#L421 assume !(1 == ~t1_pc~0); 34251#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34278#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33378#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33379#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 33872#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34290#L440 assume !(1 == ~t2_pc~0); 34326#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33517#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33708#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 34126#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33711#L459 assume !(1 == ~t3_pc~0); 33712#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34246#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33337#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33338#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33501#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33511#L478 assume 1 == ~t4_pc~0; 33512#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33973#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33454#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33455#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 33416#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33417#L497 assume !(1 == ~t5_pc~0); 33465#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33466#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34049#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34170#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 34241#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34242#L516 assume 1 == ~t6_pc~0; 34320#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33998#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33692#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33558#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 33559#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33988#L535 assume !(1 == ~t7_pc~0); 33989#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34063#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34064#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34100#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 34090#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34091#L554 assume 1 == ~t8_pc~0; 34024#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33340#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34118#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33644#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 33645#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33326#L931 assume !(1 == ~M_E~0); 33327#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34268#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34301#L941-1 assume !(1 == ~T3_E~0); 33819#L946-1 assume !(1 == ~T4_E~0); 33820#L951-1 assume !(1 == ~T5_E~0); 33573#L956-1 assume !(1 == ~T6_E~0); 33574#L961-1 assume !(1 == ~T7_E~0); 33970#L966-1 assume !(1 == ~T8_E~0); 33971#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 34093#L976-1 assume !(1 == ~E_2~0); 34053#L981-1 assume !(1 == ~E_3~0); 33823#L986-1 assume !(1 == ~E_4~0); 33600#L991-1 assume !(1 == ~E_5~0); 33601#L996-1 assume !(1 == ~E_6~0); 34285#L1001-1 assume !(1 == ~E_7~0); 34018#L1006-1 assume !(1 == ~E_8~0); 34019#L1011-1 assume { :end_inline_reset_delta_events } true; 34249#L1272-2 [2024-10-31 22:18:35,546 INFO L747 eck$LassoCheckResult]: Loop: 34249#L1272-2 assume !false; 38515#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38514#L813-1 assume !false; 34192#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 34193#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 33389#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 33727#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33728#L696 assume !(0 != eval_~tmp~0#1); 34203#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36825#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36826#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37071#L838-5 assume !(0 == ~T1_E~0); 34296#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33918#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33919#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33972#L858-3 assume !(0 == ~T5_E~0); 34041#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34029#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34030#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33625#L878-3 assume !(0 == ~E_1~0); 33350#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33351#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33352#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33353#L898-3 assume !(0 == ~E_5~0); 33849#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34194#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33857#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33391#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33392#L402-27 assume 1 == ~m_pc~0; 33341#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33342#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34065#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34066#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34217#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34218#L421-27 assume !(1 == ~t1_pc~0); 33615#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 33616#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33945#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33946#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34286#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33991#L440-27 assume !(1 == ~t2_pc~0); 33992#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 34189#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34036#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33894#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 33895#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33603#L459-27 assume 1 == ~t3_pc~0; 33604#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34058#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33869#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33870#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33987#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34276#L478-27 assume 1 == ~t4_pc~0; 34306#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33593#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33779#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33780#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34154#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34195#L497-27 assume 1 == ~t5_pc~0; 34196#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33635#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33636#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33579#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33580#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33851#L516-27 assume !(1 == ~t6_pc~0); 33852#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 33699#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33700#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34009#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34010#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33783#L535-27 assume 1 == ~t7_pc~0; 33784#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34132#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33660#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33661#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33731#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33732#L554-27 assume !(1 == ~t8_pc~0); 33365#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 33366#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33516#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33903#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33622#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33623#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33497#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33498#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33729#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33868#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33638#L951-3 assume !(1 == ~T5_E~0); 33639#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33942#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33743#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33744#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33997#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33384#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33385#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33373#L991-3 assume !(1 == ~E_5~0); 33374#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34079#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33716#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33717#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 33411#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 33412#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 33666#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 33667#L1291 assume !(0 == start_simulation_~tmp~3#1); 34291#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38631#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38621#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38620#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 38619#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38616#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38614#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 38612#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 34249#L1272-2 [2024-10-31 22:18:35,546 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:35,547 INFO L85 PathProgramCache]: Analyzing trace with hash -1412932446, now seen corresponding path program 1 times [2024-10-31 22:18:35,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:35,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925022281] [2024-10-31 22:18:35,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:35,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:35,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:35,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:35,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:35,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925022281] [2024-10-31 22:18:35,639 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925022281] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:35,639 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:35,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:35,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758039235] [2024-10-31 22:18:35,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:35,640 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:35,640 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:35,641 INFO L85 PathProgramCache]: Analyzing trace with hash -1502078349, now seen corresponding path program 2 times [2024-10-31 22:18:35,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:35,641 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612439997] [2024-10-31 22:18:35,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:35,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:35,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:35,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:35,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:35,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612439997] [2024-10-31 22:18:35,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612439997] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:35,691 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:35,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:35,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989594286] [2024-10-31 22:18:35,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:35,692 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:35,692 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:35,693 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:18:35,693 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:18:35,693 INFO L87 Difference]: Start difference. First operand 5818 states and 8477 transitions. cyclomatic complexity: 2667 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:36,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:36,012 INFO L93 Difference]: Finished difference Result 6025 states and 8684 transitions. [2024-10-31 22:18:36,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6025 states and 8684 transitions. [2024-10-31 22:18:36,047 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5880 [2024-10-31 22:18:36,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6025 states to 6025 states and 8684 transitions. [2024-10-31 22:18:36,092 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6025 [2024-10-31 22:18:36,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6025 [2024-10-31 22:18:36,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6025 states and 8684 transitions. [2024-10-31 22:18:36,106 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:36,106 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2024-10-31 22:18:36,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6025 states and 8684 transitions. [2024-10-31 22:18:36,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6025 to 6025. [2024-10-31 22:18:36,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6025 states, 6025 states have (on average 1.4413278008298755) internal successors, (8684), 6024 states have internal predecessors, (8684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:36,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6025 states to 6025 states and 8684 transitions. [2024-10-31 22:18:36,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2024-10-31 22:18:36,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:18:36,294 INFO L425 stractBuchiCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2024-10-31 22:18:36,294 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 22:18:36,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6025 states and 8684 transitions. [2024-10-31 22:18:36,320 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5880 [2024-10-31 22:18:36,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:36,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:36,322 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:36,322 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:36,323 INFO L745 eck$LassoCheckResult]: Stem: 45414#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 45415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 46114#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46115#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46117#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 45532#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45533#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46109#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46096#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45614#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45615#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45861#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45862#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45700#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45701#L838 assume !(0 == ~M_E~0); 45871#L838-2 assume !(0 == ~T1_E~0); 45213#L843-1 assume !(0 == ~T2_E~0); 45214#L848-1 assume !(0 == ~T3_E~0); 45333#L853-1 assume !(0 == ~T4_E~0); 45689#L858-1 assume !(0 == ~T5_E~0); 45169#L863-1 assume !(0 == ~T6_E~0); 45170#L868-1 assume !(0 == ~T7_E~0); 46164#L873-1 assume !(0 == ~T8_E~0); 46157#L878-1 assume !(0 == ~E_1~0); 46142#L883-1 assume !(0 == ~E_2~0); 46143#L888-1 assume !(0 == ~E_3~0); 45830#L893-1 assume !(0 == ~E_4~0); 45831#L898-1 assume !(0 == ~E_5~0); 46183#L903-1 assume !(0 == ~E_6~0); 46139#L908-1 assume !(0 == ~E_7~0); 45971#L913-1 assume !(0 == ~E_8~0); 45227#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45228#L402 assume !(1 == ~m_pc~0); 45441#L402-2 is_master_triggered_~__retres1~0#1 := 0; 45358#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45359#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45621#L1035 assume !(0 != activate_threads_~tmp~1#1); 45622#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45674#L421 assume !(1 == ~t1_pc~0); 46135#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46168#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45229#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45230#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 45731#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46178#L440 assume !(1 == ~t2_pc~0); 46226#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45368#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45369#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45560#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 45994#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45567#L459 assume !(1 == ~t3_pc~0); 45568#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46131#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45189#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45190#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 45352#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45362#L478 assume 1 == ~t4_pc~0; 45363#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45834#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45305#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45306#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 45269#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45270#L497 assume !(1 == ~t5_pc~0); 45316#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45317#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45910#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46041#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 46126#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46127#L516 assume 1 == ~t6_pc~0; 46216#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45860#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45542#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45408#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 45409#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45849#L535 assume !(1 == ~t7_pc~0); 45850#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45924#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45925#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45963#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 45954#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45955#L554 assume 1 == ~t8_pc~0; 45887#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45192#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45982#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45499#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 45500#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45178#L931 assume !(1 == ~M_E~0); 45179#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46151#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46192#L941-1 assume !(1 == ~T3_E~0); 45675#L946-1 assume !(1 == ~T4_E~0); 45676#L951-1 assume !(1 == ~T5_E~0); 45423#L956-1 assume !(1 == ~T6_E~0); 45424#L961-1 assume !(1 == ~T7_E~0); 45832#L966-1 assume !(1 == ~T8_E~0); 45833#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 45956#L976-1 assume !(1 == ~E_2~0); 45914#L981-1 assume !(1 == ~E_3~0); 45679#L986-1 assume !(1 == ~E_4~0); 45680#L991-1 assume !(1 == ~E_5~0); 45451#L996-1 assume !(1 == ~E_6~0); 46172#L1001-1 assume !(1 == ~E_7~0); 46173#L1006-1 assume !(1 == ~E_8~0); 48306#L1011-1 assume { :end_inline_reset_delta_events } true; 48302#L1272-2 [2024-10-31 22:18:36,323 INFO L747 eck$LassoCheckResult]: Loop: 48302#L1272-2 assume !false; 48300#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47962#L813-1 assume !false; 47963#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 47949#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 47942#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 45580#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45581#L696 assume !(0 != eval_~tmp~0#1); 46073#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50316#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50314#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50312#L838-5 assume !(0 == ~T1_E~0); 50295#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50294#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50292#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50290#L858-3 assume !(0 == ~T5_E~0); 50288#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50279#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50277#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50276#L878-3 assume !(0 == ~E_1~0); 50274#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50273#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50255#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50254#L898-3 assume !(0 == ~E_5~0); 50253#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50252#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50251#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50250#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50248#L402-27 assume 1 == ~m_pc~0; 50245#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50244#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45926#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45927#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46091#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46092#L421-27 assume !(1 == ~t1_pc~0); 46108#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 50054#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50053#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49755#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49746#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45852#L440-27 assume !(1 == ~t2_pc~0); 45853#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 50249#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50247#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49823#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 49820#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49819#L459-27 assume !(1 == ~t3_pc~0); 49817#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 49815#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49813#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49812#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 49810#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49809#L478-27 assume !(1 == ~t4_pc~0); 49808#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 49806#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49798#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49797#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49796#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49794#L497-27 assume 1 == ~t5_pc~0; 49792#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49791#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49790#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49789#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49788#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49787#L516-27 assume !(1 == ~t6_pc~0); 49785#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 49784#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49783#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49782#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49781#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49779#L535-27 assume 1 == ~t7_pc~0; 49776#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49775#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49774#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49773#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49771#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49769#L554-27 assume !(1 == ~t8_pc~0); 49766#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 49764#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49762#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49760#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49758#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49756#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49607#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49593#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48670#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48666#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48662#L951-3 assume !(1 == ~T5_E~0); 48656#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48650#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48646#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48642#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48638#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48634#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48630#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48624#L991-3 assume !(1 == ~E_5~0); 48621#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48618#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48378#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48377#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48340#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 48331#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 48329#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 48327#L1291 assume !(0 == start_simulation_~tmp~3#1); 48325#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48324#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 48315#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 48314#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 48313#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48312#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48311#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 48305#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 48302#L1272-2 [2024-10-31 22:18:36,324 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:36,324 INFO L85 PathProgramCache]: Analyzing trace with hash -1894012704, now seen corresponding path program 1 times [2024-10-31 22:18:36,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:36,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643374197] [2024-10-31 22:18:36,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:36,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:36,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:36,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:36,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:36,383 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643374197] [2024-10-31 22:18:36,383 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643374197] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:36,383 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:36,383 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:36,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [754354522] [2024-10-31 22:18:36,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:36,384 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:36,384 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:36,384 INFO L85 PathProgramCache]: Analyzing trace with hash 387702447, now seen corresponding path program 1 times [2024-10-31 22:18:36,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:36,384 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752337176] [2024-10-31 22:18:36,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:36,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:36,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:36,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:36,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:36,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752337176] [2024-10-31 22:18:36,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752337176] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:36,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:36,434 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:36,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925848469] [2024-10-31 22:18:36,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:36,435 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:36,435 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:36,435 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:36,435 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:36,436 INFO L87 Difference]: Start difference. First operand 6025 states and 8684 transitions. cyclomatic complexity: 2667 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:36,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:36,591 INFO L93 Difference]: Finished difference Result 11580 states and 16593 transitions. [2024-10-31 22:18:36,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11580 states and 16593 transitions. [2024-10-31 22:18:36,664 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11404 [2024-10-31 22:18:36,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11580 states to 11580 states and 16593 transitions. [2024-10-31 22:18:36,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11580 [2024-10-31 22:18:36,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11580 [2024-10-31 22:18:36,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11580 states and 16593 transitions. [2024-10-31 22:18:36,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:36,743 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11580 states and 16593 transitions. [2024-10-31 22:18:36,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11580 states and 16593 transitions. [2024-10-31 22:18:37,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11580 to 11564. [2024-10-31 22:18:37,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11564 states, 11564 states have (on average 1.4335005188516083) internal successors, (16577), 11563 states have internal predecessors, (16577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:37,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11564 states to 11564 states and 16577 transitions. [2024-10-31 22:18:37,123 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11564 states and 16577 transitions. [2024-10-31 22:18:37,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:37,124 INFO L425 stractBuchiCegarLoop]: Abstraction has 11564 states and 16577 transitions. [2024-10-31 22:18:37,124 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 22:18:37,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11564 states and 16577 transitions. [2024-10-31 22:18:37,174 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11388 [2024-10-31 22:18:37,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:37,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:37,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:37,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:37,177 INFO L745 eck$LassoCheckResult]: Stem: 63027#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 63028#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 63721#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63722#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63724#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 63147#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63148#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63715#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63706#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63223#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63224#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63469#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63470#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63310#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63311#L838 assume !(0 == ~M_E~0); 63479#L838-2 assume !(0 == ~T1_E~0); 62827#L843-1 assume !(0 == ~T2_E~0); 62828#L848-1 assume !(0 == ~T3_E~0); 62946#L853-1 assume !(0 == ~T4_E~0); 63297#L858-1 assume !(0 == ~T5_E~0); 62779#L863-1 assume !(0 == ~T6_E~0); 62780#L868-1 assume !(0 == ~T7_E~0); 63778#L873-1 assume !(0 == ~T8_E~0); 63773#L878-1 assume !(0 == ~E_1~0); 63751#L883-1 assume !(0 == ~E_2~0); 63752#L888-1 assume !(0 == ~E_3~0); 63438#L893-1 assume !(0 == ~E_4~0); 63439#L898-1 assume !(0 == ~E_5~0); 63797#L903-1 assume !(0 == ~E_6~0); 63749#L908-1 assume !(0 == ~E_7~0); 63576#L913-1 assume !(0 == ~E_8~0); 62839#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62840#L402 assume !(1 == ~m_pc~0); 63051#L402-2 is_master_triggered_~__retres1~0#1 := 0; 62972#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62973#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63230#L1035 assume !(0 != activate_threads_~tmp~1#1); 63231#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63285#L421 assume !(1 == ~t1_pc~0); 63742#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63779#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62842#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 62843#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 63341#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63791#L440 assume !(1 == ~t2_pc~0); 63833#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62981#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63174#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 63599#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63177#L459 assume !(1 == ~t3_pc~0); 63178#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63739#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62801#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62802#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 62967#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62976#L478 assume !(1 == ~t4_pc~0); 62977#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63655#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62918#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62919#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 62880#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62881#L497 assume !(1 == ~t5_pc~0); 62929#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62930#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63518#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63650#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 63732#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63733#L516 assume 1 == ~t6_pc~0; 63826#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63468#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63157#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63021#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 63022#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63457#L535 assume !(1 == ~t7_pc~0); 63458#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 63532#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63533#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63567#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 63557#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63558#L554 assume 1 == ~t8_pc~0; 63495#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62804#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63587#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63109#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 63110#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62790#L931 assume !(1 == ~M_E~0); 62791#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63764#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63807#L941-1 assume !(1 == ~T3_E~0); 69830#L946-1 assume !(1 == ~T4_E~0); 69829#L951-1 assume !(1 == ~T5_E~0); 69828#L956-1 assume !(1 == ~T6_E~0); 69827#L961-1 assume !(1 == ~T7_E~0); 69826#L966-1 assume !(1 == ~T8_E~0); 69825#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 69824#L976-1 assume !(1 == ~E_2~0); 69823#L981-1 assume !(1 == ~E_3~0); 69822#L986-1 assume !(1 == ~E_4~0); 69821#L991-1 assume !(1 == ~E_5~0); 63065#L996-1 assume !(1 == ~E_6~0); 69820#L1001-1 assume !(1 == ~E_7~0); 69819#L1006-1 assume !(1 == ~E_8~0); 69818#L1011-1 assume { :end_inline_reset_delta_events } true; 69816#L1272-2 [2024-10-31 22:18:37,177 INFO L747 eck$LassoCheckResult]: Loop: 69816#L1272-2 assume !false; 69511#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69510#L813-1 assume !false; 69509#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 69470#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 69461#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 69460#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69458#L696 assume !(0 != eval_~tmp~0#1); 69459#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70229#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70228#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 70227#L838-5 assume !(0 == ~T1_E~0); 70226#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70225#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70224#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70223#L858-3 assume !(0 == ~T5_E~0); 70222#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 70221#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 70219#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70218#L878-3 assume !(0 == ~E_1~0); 70217#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70216#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70215#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70214#L898-3 assume !(0 == ~E_5~0); 70212#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70211#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70210#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 70209#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70208#L402-27 assume !(1 == ~m_pc~0); 70207#L402-29 is_master_triggered_~__retres1~0#1 := 0; 70204#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70202#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 70200#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70198#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70196#L421-27 assume !(1 == ~t1_pc~0); 70194#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 70192#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70190#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70188#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70186#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70184#L440-27 assume !(1 == ~t2_pc~0); 70182#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 70180#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70178#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 70176#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 70174#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70172#L459-27 assume !(1 == ~t3_pc~0); 70168#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 70166#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70164#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70161#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 70158#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70156#L478-27 assume !(1 == ~t4_pc~0); 70154#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 70152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70150#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 70148#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70146#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70144#L497-27 assume 1 == ~t5_pc~0; 70141#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 70139#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70137#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70135#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70133#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70131#L516-27 assume 1 == ~t6_pc~0; 70129#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 70126#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70122#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70120#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70118#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70116#L535-27 assume !(1 == ~t7_pc~0); 70113#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 70110#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70108#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70106#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70104#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70102#L554-27 assume !(1 == ~t8_pc~0); 70099#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 70097#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70095#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70092#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70090#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70088#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70086#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70084#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70047#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70080#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70078#L951-3 assume !(1 == ~T5_E~0); 70076#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70074#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70072#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70070#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70067#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70065#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70063#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70061#L991-3 assume !(1 == ~E_5~0); 70033#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70058#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70055#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70053#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 69860#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 69851#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 69849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 69847#L1291 assume !(0 == start_simulation_~tmp~3#1); 69845#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 69844#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 69835#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 69834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 69833#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69832#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69831#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 69817#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 69816#L1272-2 [2024-10-31 22:18:37,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:37,178 INFO L85 PathProgramCache]: Analyzing trace with hash -461177985, now seen corresponding path program 1 times [2024-10-31 22:18:37,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:37,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617165354] [2024-10-31 22:18:37,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:37,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:37,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:37,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:37,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:37,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617165354] [2024-10-31 22:18:37,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1617165354] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:37,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:37,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:37,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594314905] [2024-10-31 22:18:37,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:37,336 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:37,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:37,337 INFO L85 PathProgramCache]: Analyzing trace with hash 639414542, now seen corresponding path program 1 times [2024-10-31 22:18:37,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:37,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983703544] [2024-10-31 22:18:37,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:37,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:37,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:37,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:37,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:37,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983703544] [2024-10-31 22:18:37,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983703544] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:37,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:37,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:37,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355400860] [2024-10-31 22:18:37,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:37,388 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:37,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:37,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:37,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:37,389 INFO L87 Difference]: Start difference. First operand 11564 states and 16577 transitions. cyclomatic complexity: 5029 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:37,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:37,592 INFO L93 Difference]: Finished difference Result 21803 states and 31130 transitions. [2024-10-31 22:18:37,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21803 states and 31130 transitions. [2024-10-31 22:18:37,814 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21548 [2024-10-31 22:18:37,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21803 states to 21803 states and 31130 transitions. [2024-10-31 22:18:37,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21803 [2024-10-31 22:18:37,951 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21803 [2024-10-31 22:18:37,951 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21803 states and 31130 transitions. [2024-10-31 22:18:37,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:37,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21803 states and 31130 transitions. [2024-10-31 22:18:38,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21803 states and 31130 transitions. [2024-10-31 22:18:38,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21803 to 21771. [2024-10-31 22:18:38,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21771 states, 21771 states have (on average 1.4284139451564006) internal successors, (31098), 21770 states have internal predecessors, (31098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:38,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21771 states to 21771 states and 31098 transitions. [2024-10-31 22:18:38,490 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21771 states and 31098 transitions. [2024-10-31 22:18:38,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:38,492 INFO L425 stractBuchiCegarLoop]: Abstraction has 21771 states and 31098 transitions. [2024-10-31 22:18:38,493 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 22:18:38,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21771 states and 31098 transitions. [2024-10-31 22:18:38,619 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21516 [2024-10-31 22:18:38,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:38,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:38,621 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:38,621 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:38,621 INFO L745 eck$LassoCheckResult]: Stem: 96402#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 96403#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 97108#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97109#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 97111#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 96523#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96524#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97100#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97092#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96599#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96600#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96851#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96852#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96686#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96687#L838 assume !(0 == ~M_E~0); 96861#L838-2 assume !(0 == ~T1_E~0); 96199#L843-1 assume !(0 == ~T2_E~0); 96200#L848-1 assume !(0 == ~T3_E~0); 96320#L853-1 assume !(0 == ~T4_E~0); 96673#L858-1 assume !(0 == ~T5_E~0); 96153#L863-1 assume !(0 == ~T6_E~0); 96154#L868-1 assume !(0 == ~T7_E~0); 97164#L873-1 assume !(0 == ~T8_E~0); 97157#L878-1 assume !(0 == ~E_1~0); 97140#L883-1 assume !(0 == ~E_2~0); 97141#L888-1 assume !(0 == ~E_3~0); 96817#L893-1 assume !(0 == ~E_4~0); 96818#L898-1 assume !(0 == ~E_5~0); 97180#L903-1 assume !(0 == ~E_6~0); 97137#L908-1 assume !(0 == ~E_7~0); 96960#L913-1 assume !(0 == ~E_8~0); 96211#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96212#L402 assume !(1 == ~m_pc~0); 96426#L402-2 is_master_triggered_~__retres1~0#1 := 0; 96347#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96348#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96606#L1035 assume !(0 != activate_threads_~tmp~1#1); 96607#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96661#L421 assume !(1 == ~t1_pc~0); 97132#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97165#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96214#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 96215#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 96718#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97175#L440 assume !(1 == ~t2_pc~0); 97227#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96356#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96357#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96551#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 96979#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96554#L459 assume !(1 == ~t3_pc~0); 96555#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97127#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 96176#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 96341#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96351#L478 assume !(1 == ~t4_pc~0); 96352#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 97040#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96291#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96292#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 96252#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96253#L497 assume !(1 == ~t5_pc~0); 96302#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 96303#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96901#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 97034#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 97121#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97122#L516 assume !(1 == ~t6_pc~0); 97053#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 96850#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96533#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96396#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 96397#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96837#L535 assume !(1 == ~t7_pc~0); 96838#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 96916#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96917#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96952#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 96942#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96943#L554 assume 1 == ~t8_pc~0; 96878#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 96178#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96970#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96485#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 96486#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96164#L931 assume !(1 == ~M_E~0); 96165#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97151#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97188#L941-1 assume !(1 == ~T3_E~0); 96662#L946-1 assume !(1 == ~T4_E~0); 96663#L951-1 assume !(1 == ~T5_E~0); 96412#L956-1 assume !(1 == ~T6_E~0); 96413#L961-1 assume !(1 == ~T7_E~0); 96819#L966-1 assume !(1 == ~T8_E~0); 96820#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 96945#L976-1 assume !(1 == ~E_2~0); 97197#L981-1 assume !(1 == ~E_3~0); 96666#L986-1 assume !(1 == ~E_4~0); 96440#L991-1 assume !(1 == ~E_5~0); 96441#L996-1 assume !(1 == ~E_6~0); 97170#L1001-1 assume !(1 == ~E_7~0); 96873#L1006-1 assume !(1 == ~E_8~0); 96874#L1011-1 assume { :end_inline_reset_delta_events } true; 99819#L1272-2 [2024-10-31 22:18:38,622 INFO L747 eck$LassoCheckResult]: Loop: 99819#L1272-2 assume !false; 99813#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99810#L813-1 assume !false; 99808#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 99692#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 99679#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 99675#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 99670#L696 assume !(0 != eval_~tmp~0#1); 99671#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100209#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100207#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 100205#L838-5 assume !(0 == ~T1_E~0); 100202#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 100200#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100198#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100196#L858-3 assume !(0 == ~T5_E~0); 100194#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 100192#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 100190#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 100188#L878-3 assume !(0 == ~E_1~0); 100186#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 100183#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100181#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 100179#L898-3 assume !(0 == ~E_5~0); 100177#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 100175#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 100173#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 100171#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100169#L402-27 assume !(1 == ~m_pc~0); 100167#L402-29 is_master_triggered_~__retres1~0#1 := 0; 100164#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100162#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100160#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 100157#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100155#L421-27 assume !(1 == ~t1_pc~0); 100153#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 100151#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100149#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100147#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100144#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100142#L440-27 assume !(1 == ~t2_pc~0); 100140#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 100138#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100136#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100134#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 100132#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100128#L459-27 assume !(1 == ~t3_pc~0); 100124#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 100122#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100120#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100118#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 100115#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100113#L478-27 assume !(1 == ~t4_pc~0); 100111#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 100109#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100107#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 100105#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 100101#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100099#L497-27 assume !(1 == ~t5_pc~0); 100097#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 100094#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100093#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 100092#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100091#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100090#L516-27 assume !(1 == ~t6_pc~0); 100089#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 100088#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100087#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100086#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100085#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100084#L535-27 assume 1 == ~t7_pc~0; 100081#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 100079#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100077#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100075#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 100072#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100070#L554-27 assume !(1 == ~t8_pc~0); 100067#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 100065#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100063#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100061#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 100059#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100057#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 100055#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100053#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100025#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100050#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100047#L951-3 assume !(1 == ~T5_E~0); 100045#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100043#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100041#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 100039#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100037#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100034#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 100032#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99997#L991-3 assume !(1 == ~E_5~0); 99995#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 99993#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 99990#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 99988#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 99982#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 99973#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 99971#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 99968#L1291 assume !(0 == start_simulation_~tmp~3#1); 99965#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 99858#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 99848#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 99846#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 99843#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 99841#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 99839#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 99827#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 99819#L1272-2 [2024-10-31 22:18:38,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:38,623 INFO L85 PathProgramCache]: Analyzing trace with hash 2068972702, now seen corresponding path program 1 times [2024-10-31 22:18:38,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:38,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757110745] [2024-10-31 22:18:38,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:38,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:38,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:38,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:38,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:38,711 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757110745] [2024-10-31 22:18:38,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757110745] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:38,712 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:38,712 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:38,712 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601115244] [2024-10-31 22:18:38,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:38,713 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:38,713 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:38,713 INFO L85 PathProgramCache]: Analyzing trace with hash 35597613, now seen corresponding path program 1 times [2024-10-31 22:18:38,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:38,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111036453] [2024-10-31 22:18:38,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:38,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:38,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:38,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:38,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:38,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111036453] [2024-10-31 22:18:38,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111036453] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:38,914 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:38,915 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:38,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1117036935] [2024-10-31 22:18:38,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:38,915 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:38,916 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:38,916 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:38,916 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:38,916 INFO L87 Difference]: Start difference. First operand 21771 states and 31098 transitions. cyclomatic complexity: 9359 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:39,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:39,302 INFO L93 Difference]: Finished difference Result 43134 states and 61227 transitions. [2024-10-31 22:18:39,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43134 states and 61227 transitions. [2024-10-31 22:18:39,559 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42688 [2024-10-31 22:18:39,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43134 states to 43134 states and 61227 transitions. [2024-10-31 22:18:39,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43134 [2024-10-31 22:18:39,771 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43134 [2024-10-31 22:18:39,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43134 states and 61227 transitions. [2024-10-31 22:18:40,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:40,046 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43134 states and 61227 transitions. [2024-10-31 22:18:40,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43134 states and 61227 transitions. [2024-10-31 22:18:40,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43134 to 43006. [2024-10-31 22:18:40,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43006 states, 43006 states have (on average 1.4199646560944985) internal successors, (61067), 43005 states have internal predecessors, (61067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:41,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43006 states to 43006 states and 61067 transitions. [2024-10-31 22:18:41,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43006 states and 61067 transitions. [2024-10-31 22:18:41,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:41,078 INFO L425 stractBuchiCegarLoop]: Abstraction has 43006 states and 61067 transitions. [2024-10-31 22:18:41,078 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-31 22:18:41,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43006 states and 61067 transitions. [2024-10-31 22:18:41,357 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-10-31 22:18:41,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:41,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:41,359 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:41,360 INFO L745 eck$LassoCheckResult]: Stem: 161312#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 161313#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 162045#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 162046#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 162048#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 161431#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 161432#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 162037#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 162030#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 161510#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 161511#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 161768#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 161769#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 161598#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 161599#L838 assume !(0 == ~M_E~0); 161778#L838-2 assume !(0 == ~T1_E~0); 161113#L843-1 assume !(0 == ~T2_E~0); 161114#L848-1 assume !(0 == ~T3_E~0); 161232#L853-1 assume !(0 == ~T4_E~0); 161586#L858-1 assume !(0 == ~T5_E~0); 161069#L863-1 assume !(0 == ~T6_E~0); 161070#L868-1 assume !(0 == ~T7_E~0); 162115#L873-1 assume !(0 == ~T8_E~0); 162109#L878-1 assume !(0 == ~E_1~0); 162087#L883-1 assume !(0 == ~E_2~0); 162088#L888-1 assume !(0 == ~E_3~0); 161736#L893-1 assume !(0 == ~E_4~0); 161737#L898-1 assume !(0 == ~E_5~0); 162127#L903-1 assume !(0 == ~E_6~0); 162084#L908-1 assume !(0 == ~E_7~0); 161884#L913-1 assume !(0 == ~E_8~0); 161126#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 161127#L402 assume !(1 == ~m_pc~0); 161340#L402-2 is_master_triggered_~__retres1~0#1 := 0; 161256#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161257#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 161517#L1035 assume !(0 != activate_threads_~tmp~1#1); 161518#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161572#L421 assume !(1 == ~t1_pc~0); 162072#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 162118#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 161128#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 161129#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 161629#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162124#L440 assume !(1 == ~t2_pc~0); 162181#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 161265#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 161266#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 161458#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 161907#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161467#L459 assume !(1 == ~t3_pc~0); 161468#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 162068#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161089#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 161090#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 161251#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161260#L478 assume !(1 == ~t4_pc~0); 161261#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 161959#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 161204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 161205#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 161168#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 161169#L497 assume !(1 == ~t5_pc~0); 161215#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 161216#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 161819#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 161954#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 162059#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 162060#L516 assume !(1 == ~t6_pc~0); 161974#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 161767#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 161441#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 161306#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 161307#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 161755#L535 assume !(1 == ~t7_pc~0); 161756#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 161834#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 161835#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 161874#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 161864#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 161865#L554 assume !(1 == ~t8_pc~0); 161091#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 161092#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 161899#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 161395#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 161396#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 161078#L931 assume !(1 == ~M_E~0); 161079#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 162102#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 162142#L941-1 assume !(1 == ~T3_E~0); 161573#L946-1 assume !(1 == ~T4_E~0); 161574#L951-1 assume !(1 == ~T5_E~0); 161322#L956-1 assume !(1 == ~T6_E~0); 161323#L961-1 assume !(1 == ~T7_E~0); 161738#L966-1 assume !(1 == ~T8_E~0); 161739#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 161867#L976-1 assume !(1 == ~E_2~0); 161824#L981-1 assume !(1 == ~E_3~0); 161577#L986-1 assume !(1 == ~E_4~0); 161349#L991-1 assume !(1 == ~E_5~0); 161350#L996-1 assume !(1 == ~E_6~0); 162120#L1001-1 assume !(1 == ~E_7~0); 161787#L1006-1 assume !(1 == ~E_8~0); 161788#L1011-1 assume { :end_inline_reset_delta_events } true; 162070#L1272-2 [2024-10-31 22:18:41,361 INFO L747 eck$LassoCheckResult]: Loop: 162070#L1272-2 assume !false; 180999#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 180995#L813-1 assume !false; 180992#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 180840#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 180823#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 180816#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 180809#L696 assume !(0 != eval_~tmp~0#1); 180810#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 181483#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 181481#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 181479#L838-5 assume !(0 == ~T1_E~0); 181477#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 181475#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 181473#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 181470#L858-3 assume !(0 == ~T5_E~0); 181468#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 181466#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 181464#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 181462#L878-3 assume !(0 == ~E_1~0); 181460#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 181458#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 181456#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 181454#L898-3 assume !(0 == ~E_5~0); 181452#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 181450#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 181446#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 181444#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 181442#L402-27 assume 1 == ~m_pc~0; 181438#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 181437#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 181436#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 181434#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 181431#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 181429#L421-27 assume !(1 == ~t1_pc~0); 181427#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 181425#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 181423#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 181421#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 181419#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 181417#L440-27 assume !(1 == ~t2_pc~0); 181415#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 181413#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 181411#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 181409#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 181407#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 181405#L459-27 assume 1 == ~t3_pc~0; 181402#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 181399#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 181396#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 181393#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 181390#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 181387#L478-27 assume !(1 == ~t4_pc~0); 181384#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 181381#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 181379#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 181377#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 181375#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 181372#L497-27 assume 1 == ~t5_pc~0; 181368#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 181365#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181362#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 181359#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 181355#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 181352#L516-27 assume !(1 == ~t6_pc~0); 181349#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 181346#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 181343#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 181340#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 181337#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 181334#L535-27 assume 1 == ~t7_pc~0; 181330#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 181327#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 181324#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 181321#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 181317#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 181314#L554-27 assume !(1 == ~t8_pc~0); 181311#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 181307#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 181304#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 181301#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 181298#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 181294#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 181289#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 181285#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 172318#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 181278#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 181274#L951-3 assume !(1 == ~T5_E~0); 181270#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 181267#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 181263#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 181259#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 181255#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 181251#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 181247#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 181243#L991-3 assume !(1 == ~E_5~0); 172294#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 181234#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 181229#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 181225#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 181159#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 181147#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 181140#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 181133#L1291 assume !(0 == start_simulation_~tmp~3#1); 181129#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 181060#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 181045#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 181040#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 181034#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 181028#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 181020#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 181011#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 162070#L1272-2 [2024-10-31 22:18:41,361 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:41,361 INFO L85 PathProgramCache]: Analyzing trace with hash 478577725, now seen corresponding path program 1 times [2024-10-31 22:18:41,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:41,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918956615] [2024-10-31 22:18:41,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:41,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:41,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:41,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:41,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:41,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [918956615] [2024-10-31 22:18:41,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [918956615] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:41,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:41,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:41,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717360965] [2024-10-31 22:18:41,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:41,427 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:41,428 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:41,428 INFO L85 PathProgramCache]: Analyzing trace with hash 886404754, now seen corresponding path program 1 times [2024-10-31 22:18:41,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:41,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253403209] [2024-10-31 22:18:41,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:41,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:41,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:41,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:41,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:41,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253403209] [2024-10-31 22:18:41,477 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253403209] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:41,477 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:41,477 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:41,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419668381] [2024-10-31 22:18:41,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:41,478 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:41,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:41,478 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:41,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:41,479 INFO L87 Difference]: Start difference. First operand 43006 states and 61067 transitions. cyclomatic complexity: 18125 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:41,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:41,887 INFO L93 Difference]: Finished difference Result 43006 states and 60873 transitions. [2024-10-31 22:18:41,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43006 states and 60873 transitions. [2024-10-31 22:18:42,142 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-10-31 22:18:42,327 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43006 states to 43006 states and 60873 transitions. [2024-10-31 22:18:42,328 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43006 [2024-10-31 22:18:42,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43006 [2024-10-31 22:18:42,383 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43006 states and 60873 transitions. [2024-10-31 22:18:42,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:42,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2024-10-31 22:18:42,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43006 states and 60873 transitions. [2024-10-31 22:18:43,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43006 to 43006. [2024-10-31 22:18:43,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43006 states, 43006 states have (on average 1.415453657629168) internal successors, (60873), 43005 states have internal predecessors, (60873), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:43,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43006 states to 43006 states and 60873 transitions. [2024-10-31 22:18:43,393 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2024-10-31 22:18:43,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:43,394 INFO L425 stractBuchiCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2024-10-31 22:18:43,394 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-31 22:18:43,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43006 states and 60873 transitions. [2024-10-31 22:18:43,552 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-10-31 22:18:43,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:43,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:43,554 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:43,554 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:43,555 INFO L745 eck$LassoCheckResult]: Stem: 247332#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 247333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 248050#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 248051#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 248053#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 247450#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 247451#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 248044#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 248030#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 247526#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 247527#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 247776#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 247777#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 247613#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 247614#L838 assume !(0 == ~M_E~0); 247785#L838-2 assume !(0 == ~T1_E~0); 247132#L843-1 assume !(0 == ~T2_E~0); 247133#L848-1 assume !(0 == ~T3_E~0); 247252#L853-1 assume !(0 == ~T4_E~0); 247600#L858-1 assume !(0 == ~T5_E~0); 247086#L863-1 assume !(0 == ~T6_E~0); 247087#L868-1 assume !(0 == ~T7_E~0); 248101#L873-1 assume !(0 == ~T8_E~0); 248099#L878-1 assume !(0 == ~E_1~0); 248080#L883-1 assume !(0 == ~E_2~0); 248081#L888-1 assume !(0 == ~E_3~0); 247745#L893-1 assume !(0 == ~E_4~0); 247746#L898-1 assume !(0 == ~E_5~0); 248117#L903-1 assume !(0 == ~E_6~0); 248078#L908-1 assume !(0 == ~E_7~0); 247890#L913-1 assume !(0 == ~E_8~0); 247144#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247145#L402 assume !(1 == ~m_pc~0); 247357#L402-2 is_master_triggered_~__retres1~0#1 := 0; 247276#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247277#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 247533#L1035 assume !(0 != activate_threads_~tmp~1#1); 247534#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247588#L421 assume !(1 == ~t1_pc~0); 248072#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 248102#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247148#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 247149#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 247641#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 248114#L440 assume !(1 == ~t2_pc~0); 248161#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 247286#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 247476#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 247907#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247479#L459 assume !(1 == ~t3_pc~0); 247480#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 248069#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247108#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 247109#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 247271#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247280#L478 assume !(1 == ~t4_pc~0); 247281#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 247966#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247224#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 247225#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 247186#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247187#L497 assume !(1 == ~t5_pc~0); 247235#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 247236#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247830#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 247962#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 248063#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 248064#L516 assume !(1 == ~t6_pc~0); 247981#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 247775#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247460#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247326#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 247327#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 247764#L535 assume !(1 == ~t7_pc~0); 247765#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 247845#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 247846#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247881#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 247871#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 247872#L554 assume !(1 == ~t8_pc~0); 247110#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 247111#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 247898#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 247413#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 247414#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247097#L931 assume !(1 == ~M_E~0); 247098#L931-2 assume !(1 == ~T1_E~0); 248092#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 248126#L941-1 assume !(1 == ~T3_E~0); 247589#L946-1 assume !(1 == ~T4_E~0); 247590#L951-1 assume !(1 == ~T5_E~0); 247342#L956-1 assume !(1 == ~T6_E~0); 247343#L961-1 assume !(1 == ~T7_E~0); 247747#L966-1 assume !(1 == ~T8_E~0); 247748#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 247874#L976-1 assume !(1 == ~E_2~0); 247835#L981-1 assume !(1 == ~E_3~0); 247593#L986-1 assume !(1 == ~E_4~0); 247371#L991-1 assume !(1 == ~E_5~0); 247372#L996-1 assume !(1 == ~E_6~0); 248108#L1001-1 assume !(1 == ~E_7~0); 247797#L1006-1 assume !(1 == ~E_8~0); 247798#L1011-1 assume { :end_inline_reset_delta_events } true; 248070#L1272-2 [2024-10-31 22:18:43,555 INFO L747 eck$LassoCheckResult]: Loop: 248070#L1272-2 assume !false; 262501#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 262499#L813-1 assume !false; 262497#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 262491#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 262481#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 262479#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 262476#L696 assume !(0 != eval_~tmp~0#1); 262477#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 262975#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 262974#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 262973#L838-5 assume !(0 == ~T1_E~0); 262972#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 262971#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 262970#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 262969#L858-3 assume !(0 == ~T5_E~0); 262968#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 262967#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 262966#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 262965#L878-3 assume !(0 == ~E_1~0); 262964#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 262963#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 262962#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 262961#L898-3 assume !(0 == ~E_5~0); 262960#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 262958#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 262957#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 262956#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 262955#L402-27 assume 1 == ~m_pc~0; 262953#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 262951#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 262950#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 262949#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 262948#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 262947#L421-27 assume !(1 == ~t1_pc~0); 262945#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 262942#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 262940#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 262938#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 262936#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 262934#L440-27 assume !(1 == ~t2_pc~0); 262932#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 262930#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 262928#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 262926#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 262924#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 262922#L459-27 assume !(1 == ~t3_pc~0); 262918#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 262916#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 262914#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 262912#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 262909#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 262907#L478-27 assume !(1 == ~t4_pc~0); 262903#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 262901#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 262899#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 262897#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 262894#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 262892#L497-27 assume 1 == ~t5_pc~0; 262889#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 262887#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 262885#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 262883#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 262881#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 262879#L516-27 assume !(1 == ~t6_pc~0); 262877#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 262874#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 262872#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 262870#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 262868#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 262866#L535-27 assume !(1 == ~t7_pc~0); 262864#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 262861#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 262859#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 262857#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 262855#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 262853#L554-27 assume !(1 == ~t8_pc~0); 262851#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 262848#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 262846#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 262844#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 262842#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 262840#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 262838#L931-5 assume !(1 == ~T1_E~0); 262836#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 257553#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 262833#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 262831#L951-3 assume !(1 == ~T5_E~0); 262829#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 262827#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 262825#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 262823#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 262822#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 262820#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 262818#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 262816#L991-3 assume !(1 == ~E_5~0); 257529#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 262813#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 262811#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 262809#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 262804#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 262795#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 262793#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 262791#L1291 assume !(0 == start_simulation_~tmp~3#1); 262789#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 262784#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 262774#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 262772#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 262770#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 262768#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 262766#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 262764#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 248070#L1272-2 [2024-10-31 22:18:43,556 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:43,556 INFO L85 PathProgramCache]: Analyzing trace with hash -1109770177, now seen corresponding path program 1 times [2024-10-31 22:18:43,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:43,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666600850] [2024-10-31 22:18:43,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:43,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:43,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:43,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:43,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:43,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666600850] [2024-10-31 22:18:43,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666600850] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:43,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:43,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 22:18:43,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154838019] [2024-10-31 22:18:43,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:43,628 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:43,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:43,628 INFO L85 PathProgramCache]: Analyzing trace with hash -381608560, now seen corresponding path program 1 times [2024-10-31 22:18:43,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:43,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136879845] [2024-10-31 22:18:43,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:43,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:43,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:43,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:43,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:43,672 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [136879845] [2024-10-31 22:18:43,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [136879845] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:43,673 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:43,673 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:43,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181126474] [2024-10-31 22:18:43,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:43,674 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:43,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:43,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:43,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:43,675 INFO L87 Difference]: Start difference. First operand 43006 states and 60873 transitions. cyclomatic complexity: 17931 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:43,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:44,000 INFO L93 Difference]: Finished difference Result 42995 states and 60691 transitions. [2024-10-31 22:18:44,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42995 states and 60691 transitions. [2024-10-31 22:18:44,197 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-10-31 22:18:44,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42995 states to 42995 states and 60691 transitions. [2024-10-31 22:18:44,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42995 [2024-10-31 22:18:44,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42995 [2024-10-31 22:18:44,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42995 states and 60691 transitions. [2024-10-31 22:18:44,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:44,638 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42995 states and 60691 transitions. [2024-10-31 22:18:44,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42995 states and 60691 transitions. [2024-10-31 22:18:45,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42995 to 22079. [2024-10-31 22:18:45,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.4100276280628652) internal successors, (31132), 22078 states have internal predecessors, (31132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:45,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 31132 transitions. [2024-10-31 22:18:45,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 31132 transitions. [2024-10-31 22:18:45,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:45,153 INFO L425 stractBuchiCegarLoop]: Abstraction has 22079 states and 31132 transitions. [2024-10-31 22:18:45,153 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-31 22:18:45,154 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 31132 transitions. [2024-10-31 22:18:45,242 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2024-10-31 22:18:45,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:45,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:45,244 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:45,245 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:45,245 INFO L745 eck$LassoCheckResult]: Stem: 333343#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 333344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 334049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 334050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 334052#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 333460#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 333461#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 334042#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 334034#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 333537#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 333538#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 333788#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 333789#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 333623#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 333624#L838 assume !(0 == ~M_E~0); 333798#L838-2 assume !(0 == ~T1_E~0); 333142#L843-1 assume !(0 == ~T2_E~0); 333143#L848-1 assume !(0 == ~T3_E~0); 333261#L853-1 assume !(0 == ~T4_E~0); 333610#L858-1 assume !(0 == ~T5_E~0); 333094#L863-1 assume !(0 == ~T6_E~0); 333095#L868-1 assume !(0 == ~T7_E~0); 334097#L873-1 assume !(0 == ~T8_E~0); 334094#L878-1 assume !(0 == ~E_1~0); 334075#L883-1 assume !(0 == ~E_2~0); 334076#L888-1 assume !(0 == ~E_3~0); 333755#L893-1 assume !(0 == ~E_4~0); 333756#L898-1 assume !(0 == ~E_5~0); 334116#L903-1 assume !(0 == ~E_6~0); 334073#L908-1 assume !(0 == ~E_7~0); 333902#L913-1 assume !(0 == ~E_8~0); 333155#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 333156#L402 assume !(1 == ~m_pc~0); 333369#L402-2 is_master_triggered_~__retres1~0#1 := 0; 333288#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 333289#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 333544#L1035 assume !(0 != activate_threads_~tmp~1#1); 333545#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 333597#L421 assume !(1 == ~t1_pc~0); 334068#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 334098#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 333157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 333158#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 333656#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 334111#L440 assume !(1 == ~t2_pc~0); 334159#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 333298#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 333299#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 333487#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 333921#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 333493#L459 assume !(1 == ~t3_pc~0); 333494#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 334065#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 333116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 333117#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 333282#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 333292#L478 assume !(1 == ~t4_pc~0); 333293#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 333974#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 333233#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 333234#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 333195#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 333196#L497 assume !(1 == ~t5_pc~0); 333244#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 333245#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 333839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 333970#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 334060#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 334061#L516 assume !(1 == ~t6_pc~0); 333987#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 333787#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 333470#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 333337#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 333338#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 333775#L535 assume !(1 == ~t7_pc~0); 333776#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 333854#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 333855#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 333891#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 333880#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 333881#L554 assume !(1 == ~t8_pc~0); 333118#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 333119#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 333912#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 333423#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 333424#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 333105#L931 assume !(1 == ~M_E~0); 333106#L931-2 assume !(1 == ~T1_E~0); 334087#L936-1 assume !(1 == ~T2_E~0); 334128#L941-1 assume !(1 == ~T3_E~0); 333598#L946-1 assume !(1 == ~T4_E~0); 333599#L951-1 assume !(1 == ~T5_E~0); 333353#L956-1 assume !(1 == ~T6_E~0); 333354#L961-1 assume !(1 == ~T7_E~0); 333757#L966-1 assume !(1 == ~T8_E~0); 333758#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 333883#L976-1 assume !(1 == ~E_2~0); 333844#L981-1 assume !(1 == ~E_3~0); 333603#L986-1 assume !(1 == ~E_4~0); 333380#L991-1 assume !(1 == ~E_5~0); 333381#L996-1 assume !(1 == ~E_6~0); 334102#L1001-1 assume !(1 == ~E_7~0); 333809#L1006-1 assume !(1 == ~E_8~0); 333810#L1011-1 assume { :end_inline_reset_delta_events } true; 334066#L1272-2 [2024-10-31 22:18:45,246 INFO L747 eck$LassoCheckResult]: Loop: 334066#L1272-2 assume !false; 338009#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 337988#L813-1 assume !false; 337974#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 337935#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 337911#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 337903#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 337895#L696 assume !(0 != eval_~tmp~0#1); 337896#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 353895#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 353891#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 353887#L838-5 assume !(0 == ~T1_E~0); 353883#L843-3 assume !(0 == ~T2_E~0); 353555#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 353554#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 353553#L858-3 assume !(0 == ~T5_E~0); 353551#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 353550#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 353549#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 353548#L878-3 assume !(0 == ~E_1~0); 353547#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 353545#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 353543#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 353541#L898-3 assume !(0 == ~E_5~0); 353539#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 353536#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 353534#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 353211#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 353210#L402-27 assume !(1 == ~m_pc~0); 353209#L402-29 is_master_triggered_~__retres1~0#1 := 0; 353207#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 353206#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 353205#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 353204#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 353202#L421-27 assume !(1 == ~t1_pc~0); 353200#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 353199#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 353198#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 353197#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 353195#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 353194#L440-27 assume !(1 == ~t2_pc~0); 353193#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 353192#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 353191#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 353189#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 353187#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 353184#L459-27 assume !(1 == ~t3_pc~0); 353180#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 353178#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 353176#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 353174#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 353171#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 353169#L478-27 assume !(1 == ~t4_pc~0); 353167#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 353165#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 353163#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 353161#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 353159#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 353157#L497-27 assume !(1 == ~t5_pc~0); 353155#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 353152#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 353150#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 353148#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 353146#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 353143#L516-27 assume !(1 == ~t6_pc~0); 353141#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 353139#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 353136#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 353134#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 353132#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 353129#L535-27 assume !(1 == ~t7_pc~0); 353127#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 353124#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 353122#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 353120#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 353118#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 353115#L554-27 assume !(1 == ~t8_pc~0); 353113#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 353111#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 353109#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 353107#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 353105#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 353103#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 353101#L931-5 assume !(1 == ~T1_E~0); 353099#L936-3 assume !(1 == ~T2_E~0); 353097#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 338828#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 338403#L951-3 assume !(1 == ~T5_E~0); 338402#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 338401#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 338399#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 338398#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 338397#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 338396#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 338391#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 338387#L991-3 assume !(1 == ~E_5~0); 338383#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 338377#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 338372#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 338370#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 338159#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 338146#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 338133#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 338125#L1291 assume !(0 == start_simulation_~tmp~3#1); 338117#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 338040#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 338030#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 338028#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 338025#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 338023#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 338021#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 338019#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 334066#L1272-2 [2024-10-31 22:18:45,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:45,248 INFO L85 PathProgramCache]: Analyzing trace with hash -2130838531, now seen corresponding path program 1 times [2024-10-31 22:18:45,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:45,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746388713] [2024-10-31 22:18:45,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:45,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:45,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:45,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:45,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:45,351 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746388713] [2024-10-31 22:18:45,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746388713] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:45,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:45,352 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:45,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770119153] [2024-10-31 22:18:45,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:45,353 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:45,353 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:45,353 INFO L85 PathProgramCache]: Analyzing trace with hash 654310282, now seen corresponding path program 1 times [2024-10-31 22:18:45,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:45,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535872417] [2024-10-31 22:18:45,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:45,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:45,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:45,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:45,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:45,435 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535872417] [2024-10-31 22:18:45,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535872417] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:45,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:45,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:45,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992160042] [2024-10-31 22:18:45,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:45,438 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:45,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:45,438 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:45,438 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:45,439 INFO L87 Difference]: Start difference. First operand 22079 states and 31132 transitions. cyclomatic complexity: 9085 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:45,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:45,832 INFO L93 Difference]: Finished difference Result 45574 states and 64007 transitions. [2024-10-31 22:18:45,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45574 states and 64007 transitions. [2024-10-31 22:18:46,100 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 45056 [2024-10-31 22:18:46,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45574 states to 45574 states and 64007 transitions. [2024-10-31 22:18:46,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45574 [2024-10-31 22:18:46,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45574 [2024-10-31 22:18:46,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45574 states and 64007 transitions. [2024-10-31 22:18:46,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:46,731 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45574 states and 64007 transitions. [2024-10-31 22:18:46,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45574 states and 64007 transitions. [2024-10-31 22:18:47,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45574 to 24766. [2024-10-31 22:18:47,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24766 states, 24766 states have (on average 1.4045061778244368) internal successors, (34784), 24765 states have internal predecessors, (34784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:47,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24766 states to 24766 states and 34784 transitions. [2024-10-31 22:18:47,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24766 states and 34784 transitions. [2024-10-31 22:18:47,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:47,204 INFO L425 stractBuchiCegarLoop]: Abstraction has 24766 states and 34784 transitions. [2024-10-31 22:18:47,204 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-31 22:18:47,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24766 states and 34784 transitions. [2024-10-31 22:18:47,292 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24448 [2024-10-31 22:18:47,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:47,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:47,294 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:47,295 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:47,295 INFO L745 eck$LassoCheckResult]: Stem: 401011#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 401012#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 401718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 401719#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 401721#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 401131#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 401132#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 401714#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 401703#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 401209#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 401210#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 401463#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 401464#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 401296#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 401297#L838 assume !(0 == ~M_E~0); 401472#L838-2 assume !(0 == ~T1_E~0); 400804#L843-1 assume !(0 == ~T2_E~0); 400805#L848-1 assume !(0 == ~T3_E~0); 400926#L853-1 assume !(0 == ~T4_E~0); 401283#L858-1 assume !(0 == ~T5_E~0); 400759#L863-1 assume !(0 == ~T6_E~0); 400760#L868-1 assume !(0 == ~T7_E~0); 401772#L873-1 assume !(0 == ~T8_E~0); 401768#L878-1 assume 0 == ~E_1~0;~E_1~0 := 1; 401769#L883-1 assume !(0 == ~E_2~0); 401791#L888-1 assume !(0 == ~E_3~0); 401792#L893-1 assume !(0 == ~E_4~0); 401793#L898-1 assume !(0 == ~E_5~0); 401794#L903-1 assume !(0 == ~E_6~0); 401845#L908-1 assume !(0 == ~E_7~0); 401872#L913-1 assume !(0 == ~E_8~0); 401871#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 401589#L402 assume !(1 == ~m_pc~0); 401590#L402-2 is_master_triggered_~__retres1~0#1 := 0; 400954#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 400955#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 401870#L1035 assume !(0 != activate_threads_~tmp~1#1); 401270#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 401271#L421 assume !(1 == ~t1_pc~0); 401773#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 401774#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 401869#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 401325#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 401326#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 401841#L440 assume !(1 == ~t2_pc~0); 401842#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 400964#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 400965#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 401808#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 401809#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 401167#L459 assume !(1 == ~t3_pc~0); 401168#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 401867#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 401865#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 401863#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 401862#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 400958#L478 assume !(1 == ~t4_pc~0); 400959#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 401712#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 401713#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 401141#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 401142#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 401484#L497 assume !(1 == ~t5_pc~0); 401485#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 401512#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 401513#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 401786#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 401787#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 401831#L516 assume !(1 == ~t6_pc~0); 401832#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 401461#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 401462#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 401861#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 401860#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 401449#L535 assume !(1 == ~t7_pc~0); 401450#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 401859#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 401825#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 401565#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 401555#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 401556#L554 assume !(1 == ~t8_pc~0); 400781#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 400782#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 401856#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 401095#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 401096#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 400769#L931 assume !(1 == ~M_E~0); 400770#L931-2 assume !(1 == ~T1_E~0); 401803#L936-1 assume !(1 == ~T2_E~0); 401804#L941-1 assume !(1 == ~T3_E~0); 401838#L946-1 assume !(1 == ~T4_E~0); 401737#L951-1 assume !(1 == ~T5_E~0); 401020#L956-1 assume !(1 == ~T6_E~0); 401021#L961-1 assume !(1 == ~T7_E~0); 401833#L966-1 assume !(1 == ~T8_E~0); 401850#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 401558#L976-1 assume !(1 == ~E_2~0); 401517#L981-1 assume !(1 == ~E_3~0); 401276#L986-1 assume !(1 == ~E_4~0); 401048#L991-1 assume !(1 == ~E_5~0); 401049#L996-1 assume !(1 == ~E_6~0); 401779#L1001-1 assume !(1 == ~E_7~0); 401482#L1006-1 assume !(1 == ~E_8~0); 401483#L1011-1 assume { :end_inline_reset_delta_events } true; 401738#L1272-2 [2024-10-31 22:18:47,296 INFO L747 eck$LassoCheckResult]: Loop: 401738#L1272-2 assume !false; 408848#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 408845#L813-1 assume !false; 408841#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 407866#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 407857#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 407855#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 407852#L696 assume !(0 != eval_~tmp~0#1); 407853#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 409280#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 409194#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 409190#L838-5 assume !(0 == ~T1_E~0); 409186#L843-3 assume !(0 == ~T2_E~0); 409182#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 409178#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 409174#L858-3 assume !(0 == ~T5_E~0); 409170#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 409166#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 409162#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 409160#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 409159#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 409158#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 409157#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 409156#L898-3 assume !(0 == ~E_5~0); 409155#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 409154#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 409153#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 409152#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 409151#L402-27 assume !(1 == ~m_pc~0); 409150#L402-29 is_master_triggered_~__retres1~0#1 := 0; 409148#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 409147#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 409146#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 409145#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 409144#L421-27 assume !(1 == ~t1_pc~0); 409143#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 409142#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 409141#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 409140#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 409139#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 409138#L440-27 assume !(1 == ~t2_pc~0); 409137#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 409136#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 409135#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 409134#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 409133#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 409132#L459-27 assume 1 == ~t3_pc~0; 409130#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 409128#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 409126#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 409124#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 409123#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 409122#L478-27 assume !(1 == ~t4_pc~0); 409121#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 409120#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 409119#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 409118#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 409117#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 409116#L497-27 assume 1 == ~t5_pc~0; 409114#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 409113#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 409112#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 409111#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 409110#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 409109#L516-27 assume !(1 == ~t6_pc~0); 409108#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 409107#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 409106#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 409105#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 409104#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 409103#L535-27 assume !(1 == ~t7_pc~0); 409102#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 409100#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 409099#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 409098#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 409097#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 409096#L554-27 assume !(1 == ~t8_pc~0); 409095#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 409094#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 409093#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 409092#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 409091#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 409090#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 409089#L931-5 assume !(1 == ~T1_E~0); 409088#L936-3 assume !(1 == ~T2_E~0); 409087#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 409086#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 409085#L951-3 assume !(1 == ~T5_E~0); 409084#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 409083#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 409082#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 409080#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 409077#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 409075#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 409062#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 409058#L991-3 assume !(1 == ~E_5~0); 409054#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 409049#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 409046#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 409044#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 408965#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 408954#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 408951#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 408946#L1291 assume !(0 == start_simulation_~tmp~3#1); 408943#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 408899#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 408886#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 408882#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 408876#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 408872#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 408867#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 408861#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 401738#L1272-2 [2024-10-31 22:18:47,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:47,296 INFO L85 PathProgramCache]: Analyzing trace with hash -1073000453, now seen corresponding path program 1 times [2024-10-31 22:18:47,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:47,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37343607] [2024-10-31 22:18:47,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:47,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:47,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:47,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:47,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:47,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37343607] [2024-10-31 22:18:47,377 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37343607] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:47,377 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:47,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:47,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879752742] [2024-10-31 22:18:47,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:47,378 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 22:18:47,378 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:47,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1933720332, now seen corresponding path program 1 times [2024-10-31 22:18:47,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:47,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335449920] [2024-10-31 22:18:47,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:47,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:47,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:47,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:47,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:47,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335449920] [2024-10-31 22:18:47,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335449920] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:47,425 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:47,425 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:47,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723808239] [2024-10-31 22:18:47,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:47,426 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:47,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:47,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 22:18:47,426 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 22:18:47,426 INFO L87 Difference]: Start difference. First operand 24766 states and 34784 transitions. cyclomatic complexity: 10050 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:47,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:47,711 INFO L93 Difference]: Finished difference Result 41983 states and 58906 transitions. [2024-10-31 22:18:47,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41983 states and 58906 transitions. [2024-10-31 22:18:48,170 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41552 [2024-10-31 22:18:48,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41983 states to 41983 states and 58906 transitions. [2024-10-31 22:18:48,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41983 [2024-10-31 22:18:48,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41983 [2024-10-31 22:18:48,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41983 states and 58906 transitions. [2024-10-31 22:18:48,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:48,349 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41983 states and 58906 transitions. [2024-10-31 22:18:48,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41983 states and 58906 transitions. [2024-10-31 22:18:48,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41983 to 22079. [2024-10-31 22:18:48,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.4001539924815436) internal successors, (30914), 22078 states have internal predecessors, (30914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:48,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 30914 transitions. [2024-10-31 22:18:48,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 30914 transitions. [2024-10-31 22:18:48,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 22:18:48,688 INFO L425 stractBuchiCegarLoop]: Abstraction has 22079 states and 30914 transitions. [2024-10-31 22:18:48,688 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-10-31 22:18:48,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 30914 transitions. [2024-10-31 22:18:48,754 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2024-10-31 22:18:48,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:48,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:48,756 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:48,756 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:48,756 INFO L745 eck$LassoCheckResult]: Stem: 467765#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 467766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 468492#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 468493#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 468495#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 467883#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 467884#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 468490#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 468479#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 467969#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 467970#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 468227#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 468228#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 468059#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 468060#L838 assume !(0 == ~M_E~0); 468240#L838-2 assume !(0 == ~T1_E~0); 467563#L843-1 assume !(0 == ~T2_E~0); 467564#L848-1 assume !(0 == ~T3_E~0); 467682#L853-1 assume !(0 == ~T4_E~0); 468048#L858-1 assume !(0 == ~T5_E~0); 467518#L863-1 assume !(0 == ~T6_E~0); 467519#L868-1 assume !(0 == ~T7_E~0); 468544#L873-1 assume !(0 == ~T8_E~0); 468542#L878-1 assume !(0 == ~E_1~0); 468524#L883-1 assume !(0 == ~E_2~0); 468525#L888-1 assume !(0 == ~E_3~0); 468195#L893-1 assume !(0 == ~E_4~0); 468196#L898-1 assume !(0 == ~E_5~0); 468570#L903-1 assume !(0 == ~E_6~0); 468522#L908-1 assume !(0 == ~E_7~0); 468345#L913-1 assume !(0 == ~E_8~0); 467576#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 467577#L402 assume !(1 == ~m_pc~0); 467790#L402-2 is_master_triggered_~__retres1~0#1 := 0; 467709#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 467710#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 467977#L1035 assume !(0 != activate_threads_~tmp~1#1); 467978#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 468034#L421 assume !(1 == ~t1_pc~0); 468516#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 468547#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 467578#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 467579#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 468089#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 468563#L440 assume !(1 == ~t2_pc~0); 468617#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 467719#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 467720#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 467910#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 468363#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 467921#L459 assume !(1 == ~t3_pc~0); 467922#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 468510#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 467538#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 467539#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 467703#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 467713#L478 assume !(1 == ~t4_pc~0); 467714#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 468415#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 467654#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 467655#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 467619#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 467620#L497 assume !(1 == ~t5_pc~0); 467665#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 467666#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 468284#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 468411#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 468504#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 468505#L516 assume !(1 == ~t6_pc~0); 468428#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 468226#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 467893#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 467759#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 467760#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 468215#L535 assume !(1 == ~t7_pc~0); 468216#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 468299#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 468300#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 468337#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 468327#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 468328#L554 assume !(1 == ~t8_pc~0); 467540#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 467541#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 468355#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 467849#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 467850#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 467528#L931 assume !(1 == ~M_E~0); 467529#L931-2 assume !(1 == ~T1_E~0); 468537#L936-1 assume !(1 == ~T2_E~0); 468583#L941-1 assume !(1 == ~T3_E~0); 468035#L946-1 assume !(1 == ~T4_E~0); 468036#L951-1 assume !(1 == ~T5_E~0); 467774#L956-1 assume !(1 == ~T6_E~0); 467775#L961-1 assume !(1 == ~T7_E~0); 468197#L966-1 assume !(1 == ~T8_E~0); 468198#L971-1 assume !(1 == ~E_1~0); 468330#L976-1 assume !(1 == ~E_2~0); 468289#L981-1 assume !(1 == ~E_3~0); 468039#L986-1 assume !(1 == ~E_4~0); 467802#L991-1 assume !(1 == ~E_5~0); 467803#L996-1 assume !(1 == ~E_6~0); 468554#L1001-1 assume !(1 == ~E_7~0); 468252#L1006-1 assume !(1 == ~E_8~0); 468253#L1011-1 assume { :end_inline_reset_delta_events } true; 468514#L1272-2 [2024-10-31 22:18:48,757 INFO L747 eck$LassoCheckResult]: Loop: 468514#L1272-2 assume !false; 475412#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 475411#L813-1 assume !false; 475410#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 475405#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 475396#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 475379#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 475374#L696 assume !(0 != eval_~tmp~0#1); 475375#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 476511#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 476504#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 476500#L838-5 assume !(0 == ~T1_E~0); 476495#L843-3 assume !(0 == ~T2_E~0); 476489#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 476484#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 476478#L858-3 assume !(0 == ~T5_E~0); 476473#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 476468#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 476463#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 476457#L878-3 assume !(0 == ~E_1~0); 476451#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 476446#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 476441#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 476436#L898-3 assume !(0 == ~E_5~0); 476431#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 476425#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 476420#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 476414#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475781#L402-27 assume !(1 == ~m_pc~0); 475778#L402-29 is_master_triggered_~__retres1~0#1 := 0; 475775#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 475773#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 475771#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 475769#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475765#L421-27 assume !(1 == ~t1_pc~0); 475763#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 475761#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475759#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 475756#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 475754#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 475752#L440-27 assume !(1 == ~t2_pc~0); 475750#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 475748#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 475746#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 475744#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 475742#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 475740#L459-27 assume !(1 == ~t3_pc~0); 475735#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 475733#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 475731#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 475729#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 475726#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 475724#L478-27 assume !(1 == ~t4_pc~0); 475722#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 475720#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 475718#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 475716#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 475714#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475712#L497-27 assume !(1 == ~t5_pc~0); 475709#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 475706#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 475704#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 475702#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 475700#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 475698#L516-27 assume !(1 == ~t6_pc~0); 475695#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 475693#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 475691#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 475689#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 475687#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 475686#L535-27 assume !(1 == ~t7_pc~0); 475685#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 475680#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 475678#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 475676#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 475675#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 475672#L554-27 assume !(1 == ~t8_pc~0); 475671#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 475670#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 475667#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 475663#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 475659#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 475654#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 475652#L931-5 assume !(1 == ~T1_E~0); 475650#L936-3 assume !(1 == ~T2_E~0); 475649#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 475648#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 475647#L951-3 assume !(1 == ~T5_E~0); 475637#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 475635#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 475633#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 475630#L971-3 assume !(1 == ~E_1~0); 475626#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 475622#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 475618#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 475614#L991-3 assume !(1 == ~E_5~0); 475611#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 475608#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 475607#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 475606#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 475493#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 475484#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 475482#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 475479#L1291 assume !(0 == start_simulation_~tmp~3#1); 475476#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 475448#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 475438#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 475436#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 475434#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 475433#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 475432#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 475428#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 468514#L1272-2 [2024-10-31 22:18:48,757 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:48,758 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 1 times [2024-10-31 22:18:48,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:48,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1620724409] [2024-10-31 22:18:48,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:48,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:48,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:48,774 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:48,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:48,847 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:48,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:48,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1077012108, now seen corresponding path program 1 times [2024-10-31 22:18:48,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:48,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024750986] [2024-10-31 22:18:48,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:48,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:48,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:48,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:48,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:48,921 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024750986] [2024-10-31 22:18:48,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024750986] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:48,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:48,921 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:48,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [584884249] [2024-10-31 22:18:48,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:48,922 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:48,922 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:48,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:18:48,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:18:48,923 INFO L87 Difference]: Start difference. First operand 22079 states and 30914 transitions. cyclomatic complexity: 8867 Second operand has 5 states, 5 states have (on average 22.4) internal successors, (112), 5 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:49,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:49,107 INFO L93 Difference]: Finished difference Result 22303 states and 31138 transitions. [2024-10-31 22:18:49,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22303 states and 31138 transitions. [2024-10-31 22:18:49,199 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22064 [2024-10-31 22:18:49,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22303 states to 22303 states and 31138 transitions. [2024-10-31 22:18:49,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22303 [2024-10-31 22:18:49,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22303 [2024-10-31 22:18:49,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22303 states and 31138 transitions. [2024-10-31 22:18:49,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:49,528 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22303 states and 31138 transitions. [2024-10-31 22:18:49,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22303 states and 31138 transitions. [2024-10-31 22:18:49,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22303 to 22175. [2024-10-31 22:18:49,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22175 states, 22175 states have (on average 1.3984216459977452) internal successors, (31010), 22174 states have internal predecessors, (31010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:49,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22175 states to 22175 states and 31010 transitions. [2024-10-31 22:18:49,789 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22175 states and 31010 transitions. [2024-10-31 22:18:49,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 22:18:49,790 INFO L425 stractBuchiCegarLoop]: Abstraction has 22175 states and 31010 transitions. [2024-10-31 22:18:49,790 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-10-31 22:18:49,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22175 states and 31010 transitions. [2024-10-31 22:18:49,862 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21936 [2024-10-31 22:18:49,863 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:49,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:49,865 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:49,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:49,866 INFO L745 eck$LassoCheckResult]: Stem: 512158#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 512159#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 512871#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 512872#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 512874#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 512274#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 512275#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 512869#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 512859#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 512351#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 512352#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 512608#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 512609#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 512439#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 512440#L838 assume !(0 == ~M_E~0); 512619#L838-2 assume !(0 == ~T1_E~0); 511954#L843-1 assume !(0 == ~T2_E~0); 511955#L848-1 assume !(0 == ~T3_E~0); 512075#L853-1 assume !(0 == ~T4_E~0); 512428#L858-1 assume !(0 == ~T5_E~0); 511910#L863-1 assume !(0 == ~T6_E~0); 511911#L868-1 assume !(0 == ~T7_E~0); 512924#L873-1 assume !(0 == ~T8_E~0); 512921#L878-1 assume !(0 == ~E_1~0); 512903#L883-1 assume !(0 == ~E_2~0); 512904#L888-1 assume !(0 == ~E_3~0); 512577#L893-1 assume !(0 == ~E_4~0); 512578#L898-1 assume !(0 == ~E_5~0); 512943#L903-1 assume !(0 == ~E_6~0); 512900#L908-1 assume !(0 == ~E_7~0); 512724#L913-1 assume !(0 == ~E_8~0); 511968#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 511969#L402 assume !(1 == ~m_pc~0); 512185#L402-2 is_master_triggered_~__retres1~0#1 := 0; 512100#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 512101#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 512357#L1035 assume !(0 != activate_threads_~tmp~1#1); 512358#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 512413#L421 assume !(1 == ~t1_pc~0); 512892#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 512928#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 511970#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 511971#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 512472#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 512939#L440 assume !(1 == ~t2_pc~0); 512993#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 512111#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 512112#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 512300#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 512747#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 512307#L459 assume !(1 == ~t3_pc~0); 512308#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 512889#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 511928#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 511929#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 512094#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 512104#L478 assume !(1 == ~t4_pc~0); 512105#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 512799#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 512046#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 512047#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 512010#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 512011#L497 assume !(1 == ~t5_pc~0); 512057#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 512058#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 512657#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 512793#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 512881#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 512882#L516 assume !(1 == ~t6_pc~0); 512818#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 512607#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 512284#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 512152#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 512153#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 512595#L535 assume !(1 == ~t7_pc~0); 512596#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 512672#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 512673#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 512714#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 512705#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 512706#L554 assume !(1 == ~t8_pc~0); 511930#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 511931#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 512738#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 512240#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 512241#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 511918#L931 assume !(1 == ~M_E~0); 511919#L931-2 assume !(1 == ~T1_E~0); 512914#L936-1 assume !(1 == ~T2_E~0); 512957#L941-1 assume !(1 == ~T3_E~0); 512414#L946-1 assume !(1 == ~T4_E~0); 512415#L951-1 assume !(1 == ~T5_E~0); 512167#L956-1 assume !(1 == ~T6_E~0); 512168#L961-1 assume !(1 == ~T7_E~0); 512579#L966-1 assume !(1 == ~T8_E~0); 512580#L971-1 assume !(1 == ~E_1~0); 512708#L976-1 assume !(1 == ~E_2~0); 512662#L981-1 assume !(1 == ~E_3~0); 512418#L986-1 assume !(1 == ~E_4~0); 512194#L991-1 assume !(1 == ~E_5~0); 512195#L996-1 assume !(1 == ~E_6~0); 512932#L1001-1 assume !(1 == ~E_7~0); 512630#L1006-1 assume !(1 == ~E_8~0); 512631#L1011-1 assume { :end_inline_reset_delta_events } true; 512890#L1272-2 [2024-10-31 22:18:49,867 INFO L747 eck$LassoCheckResult]: Loop: 512890#L1272-2 assume !false; 515692#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 515690#L813-1 assume !false; 515688#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 515682#L634 assume !(0 == ~m_st~0); 515683#L638 assume !(0 == ~t1_st~0); 515678#L642 assume !(0 == ~t2_st~0); 515679#L646 assume !(0 == ~t3_st~0); 515681#L650 assume !(0 == ~t4_st~0); 515674#L654 assume !(0 == ~t5_st~0); 515675#L658 assume !(0 == ~t6_st~0); 515680#L662 assume !(0 == ~t7_st~0); 515676#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 515677#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 517166#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 517164#L696 assume !(0 != eval_~tmp~0#1); 517162#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 517160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 517158#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 517156#L838-5 assume !(0 == ~T1_E~0); 517154#L843-3 assume !(0 == ~T2_E~0); 517152#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 517150#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 517147#L858-3 assume !(0 == ~T5_E~0); 517145#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 517143#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 517141#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 517139#L878-3 assume !(0 == ~E_1~0); 517136#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 517134#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 517132#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 517130#L898-3 assume !(0 == ~E_5~0); 517128#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 517126#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 517124#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 517122#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 517120#L402-27 assume !(1 == ~m_pc~0); 517118#L402-29 is_master_triggered_~__retres1~0#1 := 0; 517115#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 517113#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 517109#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 517107#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 517105#L421-27 assume !(1 == ~t1_pc~0); 517103#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 517100#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 517098#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 517096#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 517093#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 517091#L440-27 assume !(1 == ~t2_pc~0); 517089#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 517087#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 517085#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 517083#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 517080#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 517078#L459-27 assume 1 == ~t3_pc~0; 517076#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 517077#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 517183#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 517067#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 517065#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 517063#L478-27 assume !(1 == ~t4_pc~0); 517061#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 517059#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 517057#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 517055#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 517052#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 517050#L497-27 assume 1 == ~t5_pc~0; 517047#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 517045#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 517043#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 517041#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 517038#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 517036#L516-27 assume !(1 == ~t6_pc~0); 517034#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 517032#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 517030#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 517028#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 517026#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 517024#L535-27 assume !(1 == ~t7_pc~0); 517022#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 517019#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 517017#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 517015#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 517013#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 517011#L554-27 assume !(1 == ~t8_pc~0); 517009#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 517007#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 517005#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 517003#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 517001#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516999#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 516997#L931-5 assume !(1 == ~T1_E~0); 516995#L936-3 assume !(1 == ~T2_E~0); 516993#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 516992#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 516991#L951-3 assume !(1 == ~T5_E~0); 516990#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 516980#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 516978#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 516976#L971-3 assume !(1 == ~E_1~0); 516972#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 516970#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 516969#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 516968#L991-3 assume !(1 == ~E_5~0); 516967#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 516966#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 516965#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 516964#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 516962#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 516840#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 516056#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 516053#L1291 assume !(0 == start_simulation_~tmp~3#1); 516051#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 516050#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 515986#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 515981#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 515979#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 515977#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 515975#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 515974#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 512890#L1272-2 [2024-10-31 22:18:49,867 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:49,867 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 2 times [2024-10-31 22:18:49,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:49,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334581912] [2024-10-31 22:18:49,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:49,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:49,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:49,884 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:49,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:49,934 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:49,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:49,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1342151226, now seen corresponding path program 1 times [2024-10-31 22:18:49,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:49,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605472916] [2024-10-31 22:18:49,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:49,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:49,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:49,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:49,983 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:49,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [605472916] [2024-10-31 22:18:49,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [605472916] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:49,984 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:49,984 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 22:18:49,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268163256] [2024-10-31 22:18:49,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:49,985 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:49,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:49,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 22:18:49,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 22:18:49,986 INFO L87 Difference]: Start difference. First operand 22175 states and 31010 transitions. cyclomatic complexity: 8867 Second operand has 3 states, 3 states have (on average 40.0) internal successors, (120), 3 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:50,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:50,242 INFO L93 Difference]: Finished difference Result 40724 states and 56454 transitions. [2024-10-31 22:18:50,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40724 states and 56454 transitions. [2024-10-31 22:18:50,420 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40320 [2024-10-31 22:18:50,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40724 states to 40724 states and 56454 transitions. [2024-10-31 22:18:50,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40724 [2024-10-31 22:18:50,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40724 [2024-10-31 22:18:50,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40724 states and 56454 transitions. [2024-10-31 22:18:50,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:50,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40724 states and 56454 transitions. [2024-10-31 22:18:50,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40724 states and 56454 transitions. [2024-10-31 22:18:51,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40724 to 40708. [2024-10-31 22:18:51,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40708 states, 40708 states have (on average 1.3864105335560577) internal successors, (56438), 40707 states have internal predecessors, (56438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:51,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40708 states to 40708 states and 56438 transitions. [2024-10-31 22:18:51,579 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40708 states and 56438 transitions. [2024-10-31 22:18:51,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 22:18:51,580 INFO L425 stractBuchiCegarLoop]: Abstraction has 40708 states and 56438 transitions. [2024-10-31 22:18:51,580 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-10-31 22:18:51,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40708 states and 56438 transitions. [2024-10-31 22:18:51,818 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40304 [2024-10-31 22:18:51,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 22:18:51,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 22:18:51,827 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:51,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 22:18:51,834 INFO L745 eck$LassoCheckResult]: Stem: 575061#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 575062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 575802#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 575803#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 575805#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 575180#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 575181#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 575798#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 575788#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 575266#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 575267#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 575525#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 575526#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 575356#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 575357#L838 assume !(0 == ~M_E~0); 575534#L838-2 assume !(0 == ~T1_E~0); 574858#L843-1 assume !(0 == ~T2_E~0); 574859#L848-1 assume !(0 == ~T3_E~0); 574977#L853-1 assume !(0 == ~T4_E~0); 575343#L858-1 assume !(0 == ~T5_E~0); 574813#L863-1 assume !(0 == ~T6_E~0); 574814#L868-1 assume !(0 == ~T7_E~0); 575863#L873-1 assume !(0 == ~T8_E~0); 575860#L878-1 assume !(0 == ~E_1~0); 575834#L883-1 assume !(0 == ~E_2~0); 575835#L888-1 assume !(0 == ~E_3~0); 575489#L893-1 assume !(0 == ~E_4~0); 575490#L898-1 assume !(0 == ~E_5~0); 575880#L903-1 assume !(0 == ~E_6~0); 575832#L908-1 assume !(0 == ~E_7~0); 575644#L913-1 assume !(0 == ~E_8~0); 574870#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 574871#L402 assume !(1 == ~m_pc~0); 575084#L402-2 is_master_triggered_~__retres1~0#1 := 0; 575005#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 575006#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 575273#L1035 assume !(0 != activate_threads_~tmp~1#1); 575274#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 575329#L421 assume !(1 == ~t1_pc~0); 575827#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 575865#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 574873#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 574874#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 575385#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 575875#L440 assume !(1 == ~t2_pc~0); 575942#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 575015#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 575016#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 575208#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 575665#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 575214#L459 assume !(1 == ~t3_pc~0); 575215#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 575822#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 575873#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 574998#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 574999#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 575009#L478 assume !(1 == ~t4_pc~0); 575010#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 575724#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 574949#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 574950#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 574911#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 574912#L497 assume !(1 == ~t5_pc~0); 574960#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 575448#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 575719#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 575720#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 575814#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 575815#L516 assume !(1 == ~t6_pc~0); 575737#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 575738#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 575190#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 575191#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 575597#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 575598#L535 assume !(1 == ~t7_pc~0); 575769#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 575768#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 575923#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 575635#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 575624#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 575625#L554 assume !(1 == ~t8_pc~0); 574835#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 574836#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 575963#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 575141#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 575142#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 574823#L931 assume !(1 == ~M_E~0); 574824#L931-2 assume !(1 == ~T1_E~0); 575892#L936-1 assume !(1 == ~T2_E~0); 575893#L941-1 assume !(1 == ~T3_E~0); 575330#L946-1 assume !(1 == ~T4_E~0); 575331#L951-1 assume !(1 == ~T5_E~0); 575960#L956-1 assume !(1 == ~T6_E~0); 575932#L961-1 assume !(1 == ~T7_E~0); 575933#L966-1 assume !(1 == ~T8_E~0); 575959#L971-1 assume !(1 == ~E_1~0); 575908#L976-1 assume !(1 == ~E_2~0); 575583#L981-1 assume !(1 == ~E_3~0); 575334#L986-1 assume !(1 == ~E_4~0); 575335#L991-1 assume !(1 == ~E_5~0); 575098#L996-1 assume !(1 == ~E_6~0); 575869#L1001-1 assume !(1 == ~E_7~0); 575547#L1006-1 assume !(1 == ~E_8~0); 575548#L1011-1 assume { :end_inline_reset_delta_events } true; 575825#L1272-2 [2024-10-31 22:18:51,836 INFO L747 eck$LassoCheckResult]: Loop: 575825#L1272-2 assume !false; 602177#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 598148#L813-1 assume !false; 602176#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 602174#L634 assume !(0 == ~m_st~0); 602175#L638 assume !(0 == ~t1_st~0); 602170#L642 assume !(0 == ~t2_st~0); 602171#L646 assume !(0 == ~t3_st~0); 602173#L650 assume !(0 == ~t4_st~0); 602166#L654 assume !(0 == ~t5_st~0); 602167#L658 assume !(0 == ~t6_st~0); 602172#L662 assume !(0 == ~t7_st~0); 602168#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 602169#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 602113#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 602114#L696 assume !(0 != eval_~tmp~0#1); 602516#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 602514#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 602512#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 602510#L838-5 assume !(0 == ~T1_E~0); 602508#L843-3 assume !(0 == ~T2_E~0); 602506#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 602504#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 602502#L858-3 assume !(0 == ~T5_E~0); 602500#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 602498#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 602496#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 602494#L878-3 assume !(0 == ~E_1~0); 602492#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 602490#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 602488#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 602486#L898-3 assume !(0 == ~E_5~0); 602484#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 602482#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 602480#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 602478#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 602476#L402-27 assume !(1 == ~m_pc~0); 602473#L402-29 is_master_triggered_~__retres1~0#1 := 0; 602470#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 602468#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 602466#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 602463#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 602459#L421-27 assume !(1 == ~t1_pc~0); 602456#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 602453#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 602450#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 602447#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 602444#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 602441#L440-27 assume !(1 == ~t2_pc~0); 602438#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 602435#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 602432#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 602429#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 602426#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 602423#L459-27 assume !(1 == ~t3_pc~0); 602419#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 602414#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 602409#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 602404#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 602400#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 602396#L478-27 assume !(1 == ~t4_pc~0); 602392#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 602388#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 602384#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 602381#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 602378#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 602374#L497-27 assume !(1 == ~t5_pc~0); 602369#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 602366#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602363#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 602360#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 602357#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 602353#L516-27 assume !(1 == ~t6_pc~0); 602349#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 602345#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 602341#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 602337#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 602333#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 602329#L535-27 assume 1 == ~t7_pc~0; 602323#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 602319#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 602315#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 602311#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 602307#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 602301#L554-27 assume !(1 == ~t8_pc~0); 602297#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 602293#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 602289#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 602285#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 602281#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 602277#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 602273#L931-5 assume !(1 == ~T1_E~0); 602269#L936-3 assume !(1 == ~T2_E~0); 602265#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 602261#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 602257#L951-3 assume !(1 == ~T5_E~0); 602253#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 602249#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 602245#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 602241#L971-3 assume !(1 == ~E_1~0); 602237#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 602233#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 602229#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 602225#L991-3 assume !(1 == ~E_5~0); 602222#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 602219#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 602216#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 602213#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 602209#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 602200#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 602198#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 602195#L1291 assume !(0 == start_simulation_~tmp~3#1); 602193#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 602192#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 602183#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 602182#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 602181#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 602180#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 602179#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 602178#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 575825#L1272-2 [2024-10-31 22:18:51,840 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:51,841 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 3 times [2024-10-31 22:18:51,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:51,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203751136] [2024-10-31 22:18:51,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:51,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:51,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:51,883 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-10-31 22:18:51,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-10-31 22:18:51,940 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-10-31 22:18:51,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 22:18:51,942 INFO L85 PathProgramCache]: Analyzing trace with hash -1193202729, now seen corresponding path program 1 times [2024-10-31 22:18:51,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 22:18:51,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075686862] [2024-10-31 22:18:51,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 22:18:51,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 22:18:51,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 22:18:52,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 22:18:52,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 22:18:52,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075686862] [2024-10-31 22:18:52,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075686862] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 22:18:52,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 22:18:52,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 22:18:52,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958768616] [2024-10-31 22:18:52,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 22:18:52,078 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 22:18:52,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 22:18:52,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 22:18:52,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 22:18:52,079 INFO L87 Difference]: Start difference. First operand 40708 states and 56438 transitions. cyclomatic complexity: 15762 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 22:18:52,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 22:18:52,543 INFO L93 Difference]: Finished difference Result 42103 states and 57833 transitions. [2024-10-31 22:18:52,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42103 states and 57833 transitions. [2024-10-31 22:18:52,732 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41696 [2024-10-31 22:18:52,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42103 states to 42103 states and 57833 transitions. [2024-10-31 22:18:52,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42103 [2024-10-31 22:18:52,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42103 [2024-10-31 22:18:52,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42103 states and 57833 transitions. [2024-10-31 22:18:52,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 22:18:52,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42103 states and 57833 transitions.